1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 17 #include "bnxt.h" 18 #include "bnxt_filter.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_irq.h" 21 #include "bnxt_ring.h" 22 #include "bnxt_rxq.h" 23 #include "bnxt_rxr.h" 24 #include "bnxt_stats.h" 25 #include "bnxt_txq.h" 26 #include "bnxt_txr.h" 27 #include "bnxt_vnic.h" 28 #include "hsi_struct_def_dpdk.h" 29 #include "bnxt_nvm_defs.h" 30 31 #define DRV_MODULE_NAME "bnxt" 32 static const char bnxt_version[] = 33 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 34 int bnxt_logtype_driver; 35 36 /* 37 * The set of PCI devices this driver supports 38 */ 39 static const struct rte_pci_id bnxt_pci_id_map[] = { 40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 93 { .vendor_id = 0, /* sentinel */ }, 94 }; 95 96 #define BNXT_ETH_RSS_SUPPORT ( \ 97 ETH_RSS_IPV4 | \ 98 ETH_RSS_NONFRAG_IPV4_TCP | \ 99 ETH_RSS_NONFRAG_IPV4_UDP | \ 100 ETH_RSS_IPV6 | \ 101 ETH_RSS_NONFRAG_IPV6_TCP | \ 102 ETH_RSS_NONFRAG_IPV6_UDP) 103 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 105 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 106 DEV_TX_OFFLOAD_TCP_CKSUM | \ 107 DEV_TX_OFFLOAD_UDP_CKSUM | \ 108 DEV_TX_OFFLOAD_TCP_TSO | \ 109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 114 DEV_TX_OFFLOAD_QINQ_INSERT | \ 115 DEV_TX_OFFLOAD_MULTI_SEGS) 116 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 118 DEV_RX_OFFLOAD_VLAN_STRIP | \ 119 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 120 DEV_RX_OFFLOAD_UDP_CKSUM | \ 121 DEV_RX_OFFLOAD_TCP_CKSUM | \ 122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 123 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 124 DEV_RX_OFFLOAD_KEEP_CRC | \ 125 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 126 DEV_RX_OFFLOAD_TCP_LRO | \ 127 DEV_RX_OFFLOAD_SCATTER | \ 128 DEV_RX_OFFLOAD_RSS_HASH) 129 130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 132 static const char *const bnxt_dev_args[] = { 133 BNXT_DEVARG_TRUFLOW, 134 BNXT_DEVARG_FLOW_XSTAT, 135 NULL 136 }; 137 138 /* 139 * truflow == false to disable the feature 140 * truflow == true to enable the feature 141 */ 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 143 144 /* 145 * flow_xstat == false to disable the feature 146 * flow_xstat == true to enable the feature 147 */ 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 149 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 156 static int bnxt_restore_vlan_filters(struct bnxt *bp); 157 static void bnxt_dev_recover(void *arg); 158 static void bnxt_free_error_recovery_info(struct bnxt *bp); 159 160 int is_bnxt_in_error(struct bnxt *bp) 161 { 162 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 163 return -EIO; 164 if (bp->flags & BNXT_FLAG_FW_RESET) 165 return -EBUSY; 166 167 return 0; 168 } 169 170 /***********************/ 171 172 /* 173 * High level utility functions 174 */ 175 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 177 { 178 if (!BNXT_CHIP_THOR(bp)) 179 return 1; 180 181 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 182 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 183 BNXT_RSS_ENTRIES_PER_CTX_THOR; 184 } 185 186 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 187 { 188 if (!BNXT_CHIP_THOR(bp)) 189 return HW_HASH_INDEX_SIZE; 190 191 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 192 } 193 194 static void bnxt_free_pf_info(struct bnxt *bp) 195 { 196 rte_free(bp->pf); 197 } 198 199 static void bnxt_free_link_info(struct bnxt *bp) 200 { 201 rte_free(bp->link_info); 202 } 203 204 static void bnxt_free_leds_info(struct bnxt *bp) 205 { 206 rte_free(bp->leds); 207 bp->leds = NULL; 208 } 209 210 static void bnxt_free_flow_stats_info(struct bnxt *bp) 211 { 212 rte_free(bp->flow_stat); 213 bp->flow_stat = NULL; 214 } 215 216 static void bnxt_free_cos_queues(struct bnxt *bp) 217 { 218 rte_free(bp->rx_cos_queue); 219 rte_free(bp->tx_cos_queue); 220 } 221 222 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 223 { 224 bnxt_free_filter_mem(bp); 225 bnxt_free_vnic_attributes(bp); 226 bnxt_free_vnic_mem(bp); 227 228 /* tx/rx rings are configured as part of *_queue_setup callbacks. 229 * If the number of rings change across fw update, 230 * we don't have much choice except to warn the user. 231 */ 232 if (!reconfig) { 233 bnxt_free_stats(bp); 234 bnxt_free_tx_rings(bp); 235 bnxt_free_rx_rings(bp); 236 } 237 bnxt_free_async_cp_ring(bp); 238 bnxt_free_rxtx_nq_ring(bp); 239 240 rte_free(bp->grp_info); 241 bp->grp_info = NULL; 242 } 243 244 static int bnxt_alloc_pf_info(struct bnxt *bp) 245 { 246 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 247 if (bp->pf == NULL) 248 return -ENOMEM; 249 250 return 0; 251 } 252 253 static int bnxt_alloc_link_info(struct bnxt *bp) 254 { 255 bp->link_info = 256 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 257 if (bp->link_info == NULL) 258 return -ENOMEM; 259 260 return 0; 261 } 262 263 static int bnxt_alloc_leds_info(struct bnxt *bp) 264 { 265 bp->leds = rte_zmalloc("bnxt_leds", 266 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 267 0); 268 if (bp->leds == NULL) 269 return -ENOMEM; 270 271 return 0; 272 } 273 274 static int bnxt_alloc_cos_queues(struct bnxt *bp) 275 { 276 bp->rx_cos_queue = 277 rte_zmalloc("bnxt_rx_cosq", 278 BNXT_COS_QUEUE_COUNT * 279 sizeof(struct bnxt_cos_queue_info), 280 0); 281 if (bp->rx_cos_queue == NULL) 282 return -ENOMEM; 283 284 bp->tx_cos_queue = 285 rte_zmalloc("bnxt_tx_cosq", 286 BNXT_COS_QUEUE_COUNT * 287 sizeof(struct bnxt_cos_queue_info), 288 0); 289 if (bp->tx_cos_queue == NULL) 290 return -ENOMEM; 291 292 return 0; 293 } 294 295 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 296 { 297 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 298 sizeof(struct bnxt_flow_stat_info), 0); 299 if (bp->flow_stat == NULL) 300 return -ENOMEM; 301 302 return 0; 303 } 304 305 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 306 { 307 int rc; 308 309 rc = bnxt_alloc_ring_grps(bp); 310 if (rc) 311 goto alloc_mem_err; 312 313 rc = bnxt_alloc_async_ring_struct(bp); 314 if (rc) 315 goto alloc_mem_err; 316 317 rc = bnxt_alloc_vnic_mem(bp); 318 if (rc) 319 goto alloc_mem_err; 320 321 rc = bnxt_alloc_vnic_attributes(bp); 322 if (rc) 323 goto alloc_mem_err; 324 325 rc = bnxt_alloc_filter_mem(bp); 326 if (rc) 327 goto alloc_mem_err; 328 329 rc = bnxt_alloc_async_cp_ring(bp); 330 if (rc) 331 goto alloc_mem_err; 332 333 rc = bnxt_alloc_rxtx_nq_ring(bp); 334 if (rc) 335 goto alloc_mem_err; 336 337 if (BNXT_FLOW_XSTATS_EN(bp)) { 338 rc = bnxt_alloc_flow_stats_info(bp); 339 if (rc) 340 goto alloc_mem_err; 341 } 342 343 return 0; 344 345 alloc_mem_err: 346 bnxt_free_mem(bp, reconfig); 347 return rc; 348 } 349 350 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 351 { 352 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 353 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 354 uint64_t rx_offloads = dev_conf->rxmode.offloads; 355 struct bnxt_rx_queue *rxq; 356 unsigned int j; 357 int rc; 358 359 rc = bnxt_vnic_grp_alloc(bp, vnic); 360 if (rc) 361 goto err_out; 362 363 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 364 vnic_id, vnic, vnic->fw_grp_ids); 365 366 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 367 if (rc) 368 goto err_out; 369 370 /* Alloc RSS context only if RSS mode is enabled */ 371 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 372 int j, nr_ctxs = bnxt_rss_ctxts(bp); 373 374 rc = 0; 375 for (j = 0; j < nr_ctxs; j++) { 376 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 377 if (rc) 378 break; 379 } 380 if (rc) { 381 PMD_DRV_LOG(ERR, 382 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 383 vnic_id, j, rc); 384 goto err_out; 385 } 386 vnic->num_lb_ctxts = nr_ctxs; 387 } 388 389 /* 390 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 391 * setting is not available at this time, it will not be 392 * configured correctly in the CFA. 393 */ 394 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 395 vnic->vlan_strip = true; 396 else 397 vnic->vlan_strip = false; 398 399 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 400 if (rc) 401 goto err_out; 402 403 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 404 if (rc) 405 goto err_out; 406 407 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 408 rxq = bp->eth_dev->data->rx_queues[j]; 409 410 PMD_DRV_LOG(DEBUG, 411 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 412 j, rxq->vnic, rxq->vnic->fw_grp_ids); 413 414 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 415 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 416 else 417 vnic->rx_queue_cnt++; 418 } 419 420 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 421 422 rc = bnxt_vnic_rss_configure(bp, vnic); 423 if (rc) 424 goto err_out; 425 426 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 427 428 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 429 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 430 else 431 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 432 433 return 0; 434 err_out: 435 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 436 vnic_id, rc); 437 return rc; 438 } 439 440 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 441 { 442 int rc = 0; 443 444 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 445 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 446 if (rc) 447 return rc; 448 449 PMD_DRV_LOG(DEBUG, 450 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 451 " rx_fc_in_tbl.ctx_id = %d\n", 452 bp->flow_stat->rx_fc_in_tbl.va, 453 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 454 bp->flow_stat->rx_fc_in_tbl.ctx_id); 455 456 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 457 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 458 if (rc) 459 return rc; 460 461 PMD_DRV_LOG(DEBUG, 462 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 463 " rx_fc_out_tbl.ctx_id = %d\n", 464 bp->flow_stat->rx_fc_out_tbl.va, 465 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 466 bp->flow_stat->rx_fc_out_tbl.ctx_id); 467 468 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 469 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 470 if (rc) 471 return rc; 472 473 PMD_DRV_LOG(DEBUG, 474 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 475 " tx_fc_in_tbl.ctx_id = %d\n", 476 bp->flow_stat->tx_fc_in_tbl.va, 477 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 478 bp->flow_stat->tx_fc_in_tbl.ctx_id); 479 480 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 481 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 482 if (rc) 483 return rc; 484 485 PMD_DRV_LOG(DEBUG, 486 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 487 " tx_fc_out_tbl.ctx_id = %d\n", 488 bp->flow_stat->tx_fc_out_tbl.va, 489 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 490 bp->flow_stat->tx_fc_out_tbl.ctx_id); 491 492 memset(bp->flow_stat->rx_fc_out_tbl.va, 493 0, 494 bp->flow_stat->rx_fc_out_tbl.size); 495 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 496 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 497 bp->flow_stat->rx_fc_out_tbl.ctx_id, 498 bp->flow_stat->max_fc, 499 true); 500 if (rc) 501 return rc; 502 503 memset(bp->flow_stat->tx_fc_out_tbl.va, 504 0, 505 bp->flow_stat->tx_fc_out_tbl.size); 506 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 507 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 508 bp->flow_stat->tx_fc_out_tbl.ctx_id, 509 bp->flow_stat->max_fc, 510 true); 511 512 return rc; 513 } 514 515 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 516 struct bnxt_ctx_mem_buf_info *ctx) 517 { 518 if (!ctx) 519 return -EINVAL; 520 521 ctx->va = rte_zmalloc(type, size, 0); 522 if (ctx->va == NULL) 523 return -ENOMEM; 524 rte_mem_lock_page(ctx->va); 525 ctx->size = size; 526 ctx->dma = rte_mem_virt2iova(ctx->va); 527 if (ctx->dma == RTE_BAD_IOVA) 528 return -ENOMEM; 529 530 return 0; 531 } 532 533 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 534 { 535 struct rte_pci_device *pdev = bp->pdev; 536 char type[RTE_MEMZONE_NAMESIZE]; 537 uint16_t max_fc; 538 int rc = 0; 539 540 max_fc = bp->flow_stat->max_fc; 541 542 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 543 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 544 /* 4 bytes for each counter-id */ 545 rc = bnxt_alloc_ctx_mem_buf(type, 546 max_fc * 4, 547 &bp->flow_stat->rx_fc_in_tbl); 548 if (rc) 549 return rc; 550 551 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 552 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 553 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 554 rc = bnxt_alloc_ctx_mem_buf(type, 555 max_fc * 16, 556 &bp->flow_stat->rx_fc_out_tbl); 557 if (rc) 558 return rc; 559 560 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 561 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 562 /* 4 bytes for each counter-id */ 563 rc = bnxt_alloc_ctx_mem_buf(type, 564 max_fc * 4, 565 &bp->flow_stat->tx_fc_in_tbl); 566 if (rc) 567 return rc; 568 569 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 570 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 571 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 572 rc = bnxt_alloc_ctx_mem_buf(type, 573 max_fc * 16, 574 &bp->flow_stat->tx_fc_out_tbl); 575 if (rc) 576 return rc; 577 578 rc = bnxt_register_fc_ctx_mem(bp); 579 580 return rc; 581 } 582 583 static int bnxt_init_ctx_mem(struct bnxt *bp) 584 { 585 int rc = 0; 586 587 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 588 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 589 !BNXT_FLOW_XSTATS_EN(bp)) 590 return 0; 591 592 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 593 if (rc) 594 return rc; 595 596 rc = bnxt_init_fc_ctx_mem(bp); 597 598 return rc; 599 } 600 601 static int bnxt_init_chip(struct bnxt *bp) 602 { 603 struct rte_eth_link new; 604 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 605 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 606 uint32_t intr_vector = 0; 607 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 608 uint32_t vec = BNXT_MISC_VEC_ID; 609 unsigned int i, j; 610 int rc; 611 612 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 613 bp->eth_dev->data->dev_conf.rxmode.offloads |= 614 DEV_RX_OFFLOAD_JUMBO_FRAME; 615 bp->flags |= BNXT_FLAG_JUMBO; 616 } else { 617 bp->eth_dev->data->dev_conf.rxmode.offloads &= 618 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 619 bp->flags &= ~BNXT_FLAG_JUMBO; 620 } 621 622 /* THOR does not support ring groups. 623 * But we will use the array to save RSS context IDs. 624 */ 625 if (BNXT_CHIP_THOR(bp)) 626 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 627 628 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 629 if (rc) { 630 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 631 goto err_out; 632 } 633 634 rc = bnxt_alloc_hwrm_rings(bp); 635 if (rc) { 636 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 637 goto err_out; 638 } 639 640 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 641 if (rc) { 642 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 643 goto err_out; 644 } 645 646 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 647 goto skip_cosq_cfg; 648 649 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 650 if (bp->rx_cos_queue[i].id != 0xff) { 651 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 652 653 if (!vnic) { 654 PMD_DRV_LOG(ERR, 655 "Num pools more than FW profile\n"); 656 rc = -EINVAL; 657 goto err_out; 658 } 659 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 660 bp->rx_cosq_cnt++; 661 } 662 } 663 664 skip_cosq_cfg: 665 rc = bnxt_mq_rx_configure(bp); 666 if (rc) { 667 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 668 goto err_out; 669 } 670 671 /* VNIC configuration */ 672 for (i = 0; i < bp->nr_vnics; i++) { 673 rc = bnxt_setup_one_vnic(bp, i); 674 if (rc) 675 goto err_out; 676 } 677 678 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 679 if (rc) { 680 PMD_DRV_LOG(ERR, 681 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 682 goto err_out; 683 } 684 685 /* check and configure queue intr-vector mapping */ 686 if ((rte_intr_cap_multiple(intr_handle) || 687 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 688 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 689 intr_vector = bp->eth_dev->data->nb_rx_queues; 690 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 691 if (intr_vector > bp->rx_cp_nr_rings) { 692 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 693 bp->rx_cp_nr_rings); 694 return -ENOTSUP; 695 } 696 rc = rte_intr_efd_enable(intr_handle, intr_vector); 697 if (rc) 698 return rc; 699 } 700 701 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 702 intr_handle->intr_vec = 703 rte_zmalloc("intr_vec", 704 bp->eth_dev->data->nb_rx_queues * 705 sizeof(int), 0); 706 if (intr_handle->intr_vec == NULL) { 707 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 708 " intr_vec", bp->eth_dev->data->nb_rx_queues); 709 rc = -ENOMEM; 710 goto err_disable; 711 } 712 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 713 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 714 intr_handle->intr_vec, intr_handle->nb_efd, 715 intr_handle->max_intr); 716 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 717 queue_id++) { 718 intr_handle->intr_vec[queue_id] = 719 vec + BNXT_RX_VEC_START; 720 if (vec < base + intr_handle->nb_efd - 1) 721 vec++; 722 } 723 } 724 725 /* enable uio/vfio intr/eventfd mapping */ 726 rc = rte_intr_enable(intr_handle); 727 #ifndef RTE_EXEC_ENV_FREEBSD 728 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 729 if (rc) 730 goto err_free; 731 #endif 732 733 rc = bnxt_get_hwrm_link_config(bp, &new); 734 if (rc) { 735 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 736 goto err_free; 737 } 738 739 if (!bp->link_info->link_up) { 740 rc = bnxt_set_hwrm_link_config(bp, true); 741 if (rc) { 742 PMD_DRV_LOG(ERR, 743 "HWRM link config failure rc: %x\n", rc); 744 goto err_free; 745 } 746 } 747 bnxt_print_link_info(bp->eth_dev); 748 749 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 750 if (!bp->mark_table) 751 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 752 753 return 0; 754 755 err_free: 756 rte_free(intr_handle->intr_vec); 757 err_disable: 758 rte_intr_efd_disable(intr_handle); 759 err_out: 760 /* Some of the error status returned by FW may not be from errno.h */ 761 if (rc > 0) 762 rc = -EIO; 763 764 return rc; 765 } 766 767 static int bnxt_shutdown_nic(struct bnxt *bp) 768 { 769 bnxt_free_all_hwrm_resources(bp); 770 bnxt_free_all_filters(bp); 771 bnxt_free_all_vnics(bp); 772 return 0; 773 } 774 775 /* 776 * Device configuration and status function 777 */ 778 779 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 780 { 781 uint32_t link_speed = bp->link_info->support_speeds; 782 uint32_t speed_capa = 0; 783 784 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 785 speed_capa |= ETH_LINK_SPEED_100M; 786 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 787 speed_capa |= ETH_LINK_SPEED_100M_HD; 788 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 789 speed_capa |= ETH_LINK_SPEED_1G; 790 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 791 speed_capa |= ETH_LINK_SPEED_2_5G; 792 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 793 speed_capa |= ETH_LINK_SPEED_10G; 794 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 795 speed_capa |= ETH_LINK_SPEED_20G; 796 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 797 speed_capa |= ETH_LINK_SPEED_25G; 798 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 799 speed_capa |= ETH_LINK_SPEED_40G; 800 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 801 speed_capa |= ETH_LINK_SPEED_50G; 802 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 803 speed_capa |= ETH_LINK_SPEED_100G; 804 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB) 805 speed_capa |= ETH_LINK_SPEED_200G; 806 807 if (bp->link_info->auto_mode == 808 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 809 speed_capa |= ETH_LINK_SPEED_FIXED; 810 else 811 speed_capa |= ETH_LINK_SPEED_AUTONEG; 812 813 return speed_capa; 814 } 815 816 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 817 struct rte_eth_dev_info *dev_info) 818 { 819 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 820 struct bnxt *bp = eth_dev->data->dev_private; 821 uint16_t max_vnics, i, j, vpool, vrxq; 822 unsigned int max_rx_rings; 823 int rc; 824 825 rc = is_bnxt_in_error(bp); 826 if (rc) 827 return rc; 828 829 /* MAC Specifics */ 830 dev_info->max_mac_addrs = bp->max_l2_ctx; 831 dev_info->max_hash_mac_addrs = 0; 832 833 /* PF/VF specifics */ 834 if (BNXT_PF(bp)) 835 dev_info->max_vfs = pdev->max_vfs; 836 837 max_rx_rings = BNXT_MAX_RINGS(bp); 838 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 839 dev_info->max_rx_queues = max_rx_rings; 840 dev_info->max_tx_queues = max_rx_rings; 841 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 842 dev_info->hash_key_size = 40; 843 max_vnics = bp->max_vnics; 844 845 /* MTU specifics */ 846 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 847 dev_info->max_mtu = BNXT_MAX_MTU; 848 849 /* Fast path specifics */ 850 dev_info->min_rx_bufsize = 1; 851 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 852 853 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 854 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 855 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 856 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 857 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 858 859 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 860 861 /* *INDENT-OFF* */ 862 dev_info->default_rxconf = (struct rte_eth_rxconf) { 863 .rx_thresh = { 864 .pthresh = 8, 865 .hthresh = 8, 866 .wthresh = 0, 867 }, 868 .rx_free_thresh = 32, 869 /* If no descriptors available, pkts are dropped by default */ 870 .rx_drop_en = 1, 871 }; 872 873 dev_info->default_txconf = (struct rte_eth_txconf) { 874 .tx_thresh = { 875 .pthresh = 32, 876 .hthresh = 0, 877 .wthresh = 0, 878 }, 879 .tx_free_thresh = 32, 880 .tx_rs_thresh = 32, 881 }; 882 eth_dev->data->dev_conf.intr_conf.lsc = 1; 883 884 eth_dev->data->dev_conf.intr_conf.rxq = 1; 885 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 886 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 887 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 888 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 889 890 /* *INDENT-ON* */ 891 892 /* 893 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 894 * need further investigation. 895 */ 896 897 /* VMDq resources */ 898 vpool = 64; /* ETH_64_POOLS */ 899 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 900 for (i = 0; i < 4; vpool >>= 1, i++) { 901 if (max_vnics > vpool) { 902 for (j = 0; j < 5; vrxq >>= 1, j++) { 903 if (dev_info->max_rx_queues > vrxq) { 904 if (vpool > vrxq) 905 vpool = vrxq; 906 goto found; 907 } 908 } 909 /* Not enough resources to support VMDq */ 910 break; 911 } 912 } 913 /* Not enough resources to support VMDq */ 914 vpool = 0; 915 vrxq = 0; 916 found: 917 dev_info->max_vmdq_pools = vpool; 918 dev_info->vmdq_queue_num = vrxq; 919 920 dev_info->vmdq_pool_base = 0; 921 dev_info->vmdq_queue_base = 0; 922 923 return 0; 924 } 925 926 /* Configure the device based on the configuration provided */ 927 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 928 { 929 struct bnxt *bp = eth_dev->data->dev_private; 930 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 931 int rc; 932 933 bp->rx_queues = (void *)eth_dev->data->rx_queues; 934 bp->tx_queues = (void *)eth_dev->data->tx_queues; 935 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 936 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 937 938 rc = is_bnxt_in_error(bp); 939 if (rc) 940 return rc; 941 942 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 943 rc = bnxt_hwrm_check_vf_rings(bp); 944 if (rc) { 945 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 946 return -ENOSPC; 947 } 948 949 /* If a resource has already been allocated - in this case 950 * it is the async completion ring, free it. Reallocate it after 951 * resource reservation. This will ensure the resource counts 952 * are calculated correctly. 953 */ 954 955 pthread_mutex_lock(&bp->def_cp_lock); 956 957 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 958 bnxt_disable_int(bp); 959 bnxt_free_cp_ring(bp, bp->async_cp_ring); 960 } 961 962 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 963 if (rc) { 964 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 965 pthread_mutex_unlock(&bp->def_cp_lock); 966 return -ENOSPC; 967 } 968 969 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 970 rc = bnxt_alloc_async_cp_ring(bp); 971 if (rc) { 972 pthread_mutex_unlock(&bp->def_cp_lock); 973 return rc; 974 } 975 bnxt_enable_int(bp); 976 } 977 978 pthread_mutex_unlock(&bp->def_cp_lock); 979 } else { 980 /* legacy driver needs to get updated values */ 981 rc = bnxt_hwrm_func_qcaps(bp); 982 if (rc) { 983 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 984 return rc; 985 } 986 } 987 988 /* Inherit new configurations */ 989 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 990 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 991 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 992 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 993 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 994 bp->max_stat_ctx) 995 goto resource_error; 996 997 if (BNXT_HAS_RING_GRPS(bp) && 998 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 999 goto resource_error; 1000 1001 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1002 bp->max_vnics < eth_dev->data->nb_rx_queues) 1003 goto resource_error; 1004 1005 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1006 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1007 1008 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1009 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1010 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1011 1012 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1013 eth_dev->data->mtu = 1014 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1015 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1016 BNXT_NUM_VLANS; 1017 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1018 } 1019 return 0; 1020 1021 resource_error: 1022 PMD_DRV_LOG(ERR, 1023 "Insufficient resources to support requested config\n"); 1024 PMD_DRV_LOG(ERR, 1025 "Num Queues Requested: Tx %d, Rx %d\n", 1026 eth_dev->data->nb_tx_queues, 1027 eth_dev->data->nb_rx_queues); 1028 PMD_DRV_LOG(ERR, 1029 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1030 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1031 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1032 return -ENOSPC; 1033 } 1034 1035 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1036 { 1037 struct rte_eth_link *link = ð_dev->data->dev_link; 1038 1039 if (link->link_status) 1040 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1041 eth_dev->data->port_id, 1042 (uint32_t)link->link_speed, 1043 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1044 ("full-duplex") : ("half-duplex\n")); 1045 else 1046 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1047 eth_dev->data->port_id); 1048 } 1049 1050 /* 1051 * Determine whether the current configuration requires support for scattered 1052 * receive; return 1 if scattered receive is required and 0 if not. 1053 */ 1054 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1055 { 1056 uint16_t buf_size; 1057 int i; 1058 1059 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1060 return 1; 1061 1062 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1063 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1064 1065 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1066 RTE_PKTMBUF_HEADROOM); 1067 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1068 return 1; 1069 } 1070 return 0; 1071 } 1072 1073 static eth_rx_burst_t 1074 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1075 { 1076 struct bnxt *bp = eth_dev->data->dev_private; 1077 1078 #ifdef RTE_ARCH_X86 1079 #ifndef RTE_LIBRTE_IEEE1588 1080 /* 1081 * Vector mode receive can be enabled only if scatter rx is not 1082 * in use and rx offloads are limited to VLAN stripping and 1083 * CRC stripping. 1084 */ 1085 if (!eth_dev->data->scattered_rx && 1086 !(eth_dev->data->dev_conf.rxmode.offloads & 1087 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1088 DEV_RX_OFFLOAD_KEEP_CRC | 1089 DEV_RX_OFFLOAD_JUMBO_FRAME | 1090 DEV_RX_OFFLOAD_IPV4_CKSUM | 1091 DEV_RX_OFFLOAD_UDP_CKSUM | 1092 DEV_RX_OFFLOAD_TCP_CKSUM | 1093 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1094 DEV_RX_OFFLOAD_RSS_HASH | 1095 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1096 !BNXT_TRUFLOW_EN(bp)) { 1097 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1098 eth_dev->data->port_id); 1099 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1100 return bnxt_recv_pkts_vec; 1101 } 1102 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1103 eth_dev->data->port_id); 1104 PMD_DRV_LOG(INFO, 1105 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1106 eth_dev->data->port_id, 1107 eth_dev->data->scattered_rx, 1108 eth_dev->data->dev_conf.rxmode.offloads); 1109 #endif 1110 #endif 1111 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1112 return bnxt_recv_pkts; 1113 } 1114 1115 static eth_tx_burst_t 1116 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 1117 { 1118 #ifdef RTE_ARCH_X86 1119 #ifndef RTE_LIBRTE_IEEE1588 1120 /* 1121 * Vector mode transmit can be enabled only if not using scatter rx 1122 * or tx offloads. 1123 */ 1124 if (!eth_dev->data->scattered_rx && 1125 !eth_dev->data->dev_conf.txmode.offloads) { 1126 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1127 eth_dev->data->port_id); 1128 return bnxt_xmit_pkts_vec; 1129 } 1130 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1131 eth_dev->data->port_id); 1132 PMD_DRV_LOG(INFO, 1133 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1134 eth_dev->data->port_id, 1135 eth_dev->data->scattered_rx, 1136 eth_dev->data->dev_conf.txmode.offloads); 1137 #endif 1138 #endif 1139 return bnxt_xmit_pkts; 1140 } 1141 1142 static int bnxt_handle_if_change_status(struct bnxt *bp) 1143 { 1144 int rc; 1145 1146 /* Since fw has undergone a reset and lost all contexts, 1147 * set fatal flag to not issue hwrm during cleanup 1148 */ 1149 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1150 bnxt_uninit_resources(bp, true); 1151 1152 /* clear fatal flag so that re-init happens */ 1153 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1154 rc = bnxt_init_resources(bp, true); 1155 1156 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1157 1158 return rc; 1159 } 1160 1161 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1162 { 1163 struct bnxt *bp = eth_dev->data->dev_private; 1164 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1165 int vlan_mask = 0; 1166 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1167 1168 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1169 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1170 return -EINVAL; 1171 } 1172 1173 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 1174 PMD_DRV_LOG(ERR, 1175 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1176 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1177 } 1178 1179 do { 1180 rc = bnxt_hwrm_if_change(bp, true); 1181 if (rc == 0 || rc != -EAGAIN) 1182 break; 1183 1184 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1185 } while (retry_cnt--); 1186 1187 if (rc) 1188 return rc; 1189 1190 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1191 rc = bnxt_handle_if_change_status(bp); 1192 if (rc) 1193 return rc; 1194 } 1195 1196 bnxt_enable_int(bp); 1197 1198 rc = bnxt_init_chip(bp); 1199 if (rc) 1200 goto error; 1201 1202 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1203 eth_dev->data->dev_started = 1; 1204 1205 bnxt_link_update(eth_dev, 1, ETH_LINK_UP); 1206 1207 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1208 vlan_mask |= ETH_VLAN_FILTER_MASK; 1209 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1210 vlan_mask |= ETH_VLAN_STRIP_MASK; 1211 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1212 if (rc) 1213 goto error; 1214 1215 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1216 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1217 1218 pthread_mutex_lock(&bp->def_cp_lock); 1219 bnxt_schedule_fw_health_check(bp); 1220 pthread_mutex_unlock(&bp->def_cp_lock); 1221 1222 if (BNXT_TRUFLOW_EN(bp)) 1223 bnxt_ulp_init(bp); 1224 1225 return 0; 1226 1227 error: 1228 bnxt_shutdown_nic(bp); 1229 bnxt_free_tx_mbufs(bp); 1230 bnxt_free_rx_mbufs(bp); 1231 bnxt_hwrm_if_change(bp, false); 1232 eth_dev->data->dev_started = 0; 1233 return rc; 1234 } 1235 1236 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1237 { 1238 struct bnxt *bp = eth_dev->data->dev_private; 1239 int rc = 0; 1240 1241 if (!bp->link_info->link_up) 1242 rc = bnxt_set_hwrm_link_config(bp, true); 1243 if (!rc) 1244 eth_dev->data->dev_link.link_status = 1; 1245 1246 bnxt_print_link_info(eth_dev); 1247 return rc; 1248 } 1249 1250 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1251 { 1252 struct bnxt *bp = eth_dev->data->dev_private; 1253 1254 eth_dev->data->dev_link.link_status = 0; 1255 bnxt_set_hwrm_link_config(bp, false); 1256 bp->link_info->link_up = 0; 1257 1258 return 0; 1259 } 1260 1261 /* Unload the driver, release resources */ 1262 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1263 { 1264 struct bnxt *bp = eth_dev->data->dev_private; 1265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1266 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1267 1268 if (BNXT_TRUFLOW_EN(bp)) 1269 bnxt_ulp_deinit(bp); 1270 1271 eth_dev->data->dev_started = 0; 1272 /* Prevent crashes when queues are still in use */ 1273 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1274 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1275 1276 bnxt_disable_int(bp); 1277 1278 /* disable uio/vfio intr/eventfd mapping */ 1279 rte_intr_disable(intr_handle); 1280 1281 bnxt_cancel_fw_health_check(bp); 1282 1283 bnxt_dev_set_link_down_op(eth_dev); 1284 1285 /* Wait for link to be reset and the async notification to process. 1286 * During reset recovery, there is no need to wait and 1287 * VF/NPAR functions do not have privilege to change PHY config. 1288 */ 1289 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp)) 1290 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN); 1291 1292 /* Clean queue intr-vector mapping */ 1293 rte_intr_efd_disable(intr_handle); 1294 if (intr_handle->intr_vec != NULL) { 1295 rte_free(intr_handle->intr_vec); 1296 intr_handle->intr_vec = NULL; 1297 } 1298 1299 bnxt_hwrm_port_clr_stats(bp); 1300 bnxt_free_tx_mbufs(bp); 1301 bnxt_free_rx_mbufs(bp); 1302 /* Process any remaining notifications in default completion queue */ 1303 bnxt_int_handler(eth_dev); 1304 bnxt_shutdown_nic(bp); 1305 bnxt_hwrm_if_change(bp, false); 1306 1307 rte_free(bp->mark_table); 1308 bp->mark_table = NULL; 1309 1310 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1311 bp->rx_cosq_cnt = 0; 1312 /* All filters are deleted on a port stop. */ 1313 if (BNXT_FLOW_XSTATS_EN(bp)) 1314 bp->flow_stat->flow_count = 0; 1315 } 1316 1317 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1318 { 1319 struct bnxt *bp = eth_dev->data->dev_private; 1320 1321 /* cancel the recovery handler before remove dev */ 1322 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1323 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1324 bnxt_cancel_fc_thread(bp); 1325 1326 if (eth_dev->data->dev_started) 1327 bnxt_dev_stop_op(eth_dev); 1328 1329 bnxt_uninit_resources(bp, false); 1330 1331 bnxt_free_leds_info(bp); 1332 bnxt_free_cos_queues(bp); 1333 bnxt_free_link_info(bp); 1334 bnxt_free_pf_info(bp); 1335 1336 eth_dev->dev_ops = NULL; 1337 eth_dev->rx_pkt_burst = NULL; 1338 eth_dev->tx_pkt_burst = NULL; 1339 1340 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1341 bp->tx_mem_zone = NULL; 1342 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1343 bp->rx_mem_zone = NULL; 1344 1345 rte_free(bp->pf->vf_info); 1346 bp->pf->vf_info = NULL; 1347 1348 rte_free(bp->grp_info); 1349 bp->grp_info = NULL; 1350 } 1351 1352 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1353 uint32_t index) 1354 { 1355 struct bnxt *bp = eth_dev->data->dev_private; 1356 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1357 struct bnxt_vnic_info *vnic; 1358 struct bnxt_filter_info *filter, *temp_filter; 1359 uint32_t i; 1360 1361 if (is_bnxt_in_error(bp)) 1362 return; 1363 1364 /* 1365 * Loop through all VNICs from the specified filter flow pools to 1366 * remove the corresponding MAC addr filter 1367 */ 1368 for (i = 0; i < bp->nr_vnics; i++) { 1369 if (!(pool_mask & (1ULL << i))) 1370 continue; 1371 1372 vnic = &bp->vnic_info[i]; 1373 filter = STAILQ_FIRST(&vnic->filter); 1374 while (filter) { 1375 temp_filter = STAILQ_NEXT(filter, next); 1376 if (filter->mac_index == index) { 1377 STAILQ_REMOVE(&vnic->filter, filter, 1378 bnxt_filter_info, next); 1379 bnxt_hwrm_clear_l2_filter(bp, filter); 1380 bnxt_free_filter(bp, filter); 1381 } 1382 filter = temp_filter; 1383 } 1384 } 1385 } 1386 1387 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1388 struct rte_ether_addr *mac_addr, uint32_t index, 1389 uint32_t pool) 1390 { 1391 struct bnxt_filter_info *filter; 1392 int rc = 0; 1393 1394 /* Attach requested MAC address to the new l2_filter */ 1395 STAILQ_FOREACH(filter, &vnic->filter, next) { 1396 if (filter->mac_index == index) { 1397 PMD_DRV_LOG(DEBUG, 1398 "MAC addr already existed for pool %d\n", 1399 pool); 1400 return 0; 1401 } 1402 } 1403 1404 filter = bnxt_alloc_filter(bp); 1405 if (!filter) { 1406 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1407 return -ENODEV; 1408 } 1409 1410 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1411 * if the MAC that's been programmed now is a different one, then, 1412 * copy that addr to filter->l2_addr 1413 */ 1414 if (mac_addr) 1415 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1416 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1417 1418 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1419 if (!rc) { 1420 filter->mac_index = index; 1421 if (filter->mac_index == 0) 1422 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1423 else 1424 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1425 } else { 1426 bnxt_free_filter(bp, filter); 1427 } 1428 1429 return rc; 1430 } 1431 1432 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1433 struct rte_ether_addr *mac_addr, 1434 uint32_t index, uint32_t pool) 1435 { 1436 struct bnxt *bp = eth_dev->data->dev_private; 1437 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1438 int rc = 0; 1439 1440 rc = is_bnxt_in_error(bp); 1441 if (rc) 1442 return rc; 1443 1444 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1445 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1446 return -ENOTSUP; 1447 } 1448 1449 if (!vnic) { 1450 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1451 return -EINVAL; 1452 } 1453 1454 /* Filter settings will get applied when port is started */ 1455 if (!eth_dev->data->dev_started) 1456 return 0; 1457 1458 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1459 1460 return rc; 1461 } 1462 1463 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1464 bool exp_link_status) 1465 { 1466 int rc = 0; 1467 struct bnxt *bp = eth_dev->data->dev_private; 1468 struct rte_eth_link new; 1469 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT : 1470 BNXT_LINK_DOWN_WAIT_CNT; 1471 1472 rc = is_bnxt_in_error(bp); 1473 if (rc) 1474 return rc; 1475 1476 memset(&new, 0, sizeof(new)); 1477 do { 1478 /* Retrieve link info from hardware */ 1479 rc = bnxt_get_hwrm_link_config(bp, &new); 1480 if (rc) { 1481 new.link_speed = ETH_LINK_SPEED_100M; 1482 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1483 PMD_DRV_LOG(ERR, 1484 "Failed to retrieve link rc = 0x%x!\n", rc); 1485 goto out; 1486 } 1487 1488 if (!wait_to_complete || new.link_status == exp_link_status) 1489 break; 1490 1491 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1492 } while (cnt--); 1493 1494 out: 1495 /* Timed out or success */ 1496 if (new.link_status != eth_dev->data->dev_link.link_status || 1497 new.link_speed != eth_dev->data->dev_link.link_speed) { 1498 rte_eth_linkstatus_set(eth_dev, &new); 1499 1500 _rte_eth_dev_callback_process(eth_dev, 1501 RTE_ETH_EVENT_INTR_LSC, 1502 NULL); 1503 1504 bnxt_print_link_info(eth_dev); 1505 } 1506 1507 return rc; 1508 } 1509 1510 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1511 int wait_to_complete) 1512 { 1513 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP); 1514 } 1515 1516 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1517 { 1518 struct bnxt *bp = eth_dev->data->dev_private; 1519 struct bnxt_vnic_info *vnic; 1520 uint32_t old_flags; 1521 int rc; 1522 1523 rc = is_bnxt_in_error(bp); 1524 if (rc) 1525 return rc; 1526 1527 /* Filter settings will get applied when port is started */ 1528 if (!eth_dev->data->dev_started) 1529 return 0; 1530 1531 if (bp->vnic_info == NULL) 1532 return 0; 1533 1534 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1535 1536 old_flags = vnic->flags; 1537 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1538 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1539 if (rc != 0) 1540 vnic->flags = old_flags; 1541 1542 return rc; 1543 } 1544 1545 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1546 { 1547 struct bnxt *bp = eth_dev->data->dev_private; 1548 struct bnxt_vnic_info *vnic; 1549 uint32_t old_flags; 1550 int rc; 1551 1552 rc = is_bnxt_in_error(bp); 1553 if (rc) 1554 return rc; 1555 1556 /* Filter settings will get applied when port is started */ 1557 if (!eth_dev->data->dev_started) 1558 return 0; 1559 1560 if (bp->vnic_info == NULL) 1561 return 0; 1562 1563 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1564 1565 old_flags = vnic->flags; 1566 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1567 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1568 if (rc != 0) 1569 vnic->flags = old_flags; 1570 1571 return rc; 1572 } 1573 1574 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1575 { 1576 struct bnxt *bp = eth_dev->data->dev_private; 1577 struct bnxt_vnic_info *vnic; 1578 uint32_t old_flags; 1579 int rc; 1580 1581 rc = is_bnxt_in_error(bp); 1582 if (rc) 1583 return rc; 1584 1585 /* Filter settings will get applied when port is started */ 1586 if (!eth_dev->data->dev_started) 1587 return 0; 1588 1589 if (bp->vnic_info == NULL) 1590 return 0; 1591 1592 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1593 1594 old_flags = vnic->flags; 1595 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1596 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1597 if (rc != 0) 1598 vnic->flags = old_flags; 1599 1600 return rc; 1601 } 1602 1603 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1604 { 1605 struct bnxt *bp = eth_dev->data->dev_private; 1606 struct bnxt_vnic_info *vnic; 1607 uint32_t old_flags; 1608 int rc; 1609 1610 rc = is_bnxt_in_error(bp); 1611 if (rc) 1612 return rc; 1613 1614 /* Filter settings will get applied when port is started */ 1615 if (!eth_dev->data->dev_started) 1616 return 0; 1617 1618 if (bp->vnic_info == NULL) 1619 return 0; 1620 1621 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1622 1623 old_flags = vnic->flags; 1624 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1625 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1626 if (rc != 0) 1627 vnic->flags = old_flags; 1628 1629 return rc; 1630 } 1631 1632 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1633 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1634 { 1635 if (qid >= bp->rx_nr_rings) 1636 return NULL; 1637 1638 return bp->eth_dev->data->rx_queues[qid]; 1639 } 1640 1641 /* Return rxq corresponding to a given rss table ring/group ID. */ 1642 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1643 { 1644 struct bnxt_rx_queue *rxq; 1645 unsigned int i; 1646 1647 if (!BNXT_HAS_RING_GRPS(bp)) { 1648 for (i = 0; i < bp->rx_nr_rings; i++) { 1649 rxq = bp->eth_dev->data->rx_queues[i]; 1650 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1651 return rxq->index; 1652 } 1653 } else { 1654 for (i = 0; i < bp->rx_nr_rings; i++) { 1655 if (bp->grp_info[i].fw_grp_id == fwr) 1656 return i; 1657 } 1658 } 1659 1660 return INVALID_HW_RING_ID; 1661 } 1662 1663 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1664 struct rte_eth_rss_reta_entry64 *reta_conf, 1665 uint16_t reta_size) 1666 { 1667 struct bnxt *bp = eth_dev->data->dev_private; 1668 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1669 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1670 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1671 uint16_t idx, sft; 1672 int i, rc; 1673 1674 rc = is_bnxt_in_error(bp); 1675 if (rc) 1676 return rc; 1677 1678 if (!vnic->rss_table) 1679 return -EINVAL; 1680 1681 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1682 return -EINVAL; 1683 1684 if (reta_size != tbl_size) { 1685 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1686 "(%d) must equal the size supported by the hardware " 1687 "(%d)\n", reta_size, tbl_size); 1688 return -EINVAL; 1689 } 1690 1691 for (i = 0; i < reta_size; i++) { 1692 struct bnxt_rx_queue *rxq; 1693 1694 idx = i / RTE_RETA_GROUP_SIZE; 1695 sft = i % RTE_RETA_GROUP_SIZE; 1696 1697 if (!(reta_conf[idx].mask & (1ULL << sft))) 1698 continue; 1699 1700 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1701 if (!rxq) { 1702 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1703 return -EINVAL; 1704 } 1705 1706 if (BNXT_CHIP_THOR(bp)) { 1707 vnic->rss_table[i * 2] = 1708 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1709 vnic->rss_table[i * 2 + 1] = 1710 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1711 } else { 1712 vnic->rss_table[i] = 1713 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1714 } 1715 } 1716 1717 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1718 return 0; 1719 } 1720 1721 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1722 struct rte_eth_rss_reta_entry64 *reta_conf, 1723 uint16_t reta_size) 1724 { 1725 struct bnxt *bp = eth_dev->data->dev_private; 1726 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1727 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1728 uint16_t idx, sft, i; 1729 int rc; 1730 1731 rc = is_bnxt_in_error(bp); 1732 if (rc) 1733 return rc; 1734 1735 /* Retrieve from the default VNIC */ 1736 if (!vnic) 1737 return -EINVAL; 1738 if (!vnic->rss_table) 1739 return -EINVAL; 1740 1741 if (reta_size != tbl_size) { 1742 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1743 "(%d) must equal the size supported by the hardware " 1744 "(%d)\n", reta_size, tbl_size); 1745 return -EINVAL; 1746 } 1747 1748 for (idx = 0, i = 0; i < reta_size; i++) { 1749 idx = i / RTE_RETA_GROUP_SIZE; 1750 sft = i % RTE_RETA_GROUP_SIZE; 1751 1752 if (reta_conf[idx].mask & (1ULL << sft)) { 1753 uint16_t qid; 1754 1755 if (BNXT_CHIP_THOR(bp)) 1756 qid = bnxt_rss_to_qid(bp, 1757 vnic->rss_table[i * 2]); 1758 else 1759 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1760 1761 if (qid == INVALID_HW_RING_ID) { 1762 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1763 return -EINVAL; 1764 } 1765 reta_conf[idx].reta[sft] = qid; 1766 } 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1773 struct rte_eth_rss_conf *rss_conf) 1774 { 1775 struct bnxt *bp = eth_dev->data->dev_private; 1776 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1777 struct bnxt_vnic_info *vnic; 1778 int rc; 1779 1780 rc = is_bnxt_in_error(bp); 1781 if (rc) 1782 return rc; 1783 1784 /* 1785 * If RSS enablement were different than dev_configure, 1786 * then return -EINVAL 1787 */ 1788 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1789 if (!rss_conf->rss_hf) 1790 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1791 } else { 1792 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1793 return -EINVAL; 1794 } 1795 1796 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1797 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 1798 rss_conf, 1799 sizeof(*rss_conf)); 1800 1801 /* Update the default RSS VNIC(s) */ 1802 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1803 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1804 1805 /* 1806 * If hashkey is not specified, use the previously configured 1807 * hashkey 1808 */ 1809 if (!rss_conf->rss_key) 1810 goto rss_config; 1811 1812 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1813 PMD_DRV_LOG(ERR, 1814 "Invalid hashkey length, should be 16 bytes\n"); 1815 return -EINVAL; 1816 } 1817 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1818 1819 rss_config: 1820 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1821 return 0; 1822 } 1823 1824 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1825 struct rte_eth_rss_conf *rss_conf) 1826 { 1827 struct bnxt *bp = eth_dev->data->dev_private; 1828 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1829 int len, rc; 1830 uint32_t hash_types; 1831 1832 rc = is_bnxt_in_error(bp); 1833 if (rc) 1834 return rc; 1835 1836 /* RSS configuration is the same for all VNICs */ 1837 if (vnic && vnic->rss_hash_key) { 1838 if (rss_conf->rss_key) { 1839 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1840 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1841 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1842 } 1843 1844 hash_types = vnic->hash_type; 1845 rss_conf->rss_hf = 0; 1846 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1847 rss_conf->rss_hf |= ETH_RSS_IPV4; 1848 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1849 } 1850 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1851 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1852 hash_types &= 1853 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1854 } 1855 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1856 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1857 hash_types &= 1858 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1859 } 1860 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1861 rss_conf->rss_hf |= ETH_RSS_IPV6; 1862 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1863 } 1864 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1865 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1866 hash_types &= 1867 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1868 } 1869 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1870 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1871 hash_types &= 1872 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1873 } 1874 if (hash_types) { 1875 PMD_DRV_LOG(ERR, 1876 "Unknown RSS config from firmware (%08x), RSS disabled", 1877 vnic->hash_type); 1878 return -ENOTSUP; 1879 } 1880 } else { 1881 rss_conf->rss_hf = 0; 1882 } 1883 return 0; 1884 } 1885 1886 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1887 struct rte_eth_fc_conf *fc_conf) 1888 { 1889 struct bnxt *bp = dev->data->dev_private; 1890 struct rte_eth_link link_info; 1891 int rc; 1892 1893 rc = is_bnxt_in_error(bp); 1894 if (rc) 1895 return rc; 1896 1897 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1898 if (rc) 1899 return rc; 1900 1901 memset(fc_conf, 0, sizeof(*fc_conf)); 1902 if (bp->link_info->auto_pause) 1903 fc_conf->autoneg = 1; 1904 switch (bp->link_info->pause) { 1905 case 0: 1906 fc_conf->mode = RTE_FC_NONE; 1907 break; 1908 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1909 fc_conf->mode = RTE_FC_TX_PAUSE; 1910 break; 1911 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1912 fc_conf->mode = RTE_FC_RX_PAUSE; 1913 break; 1914 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1915 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1916 fc_conf->mode = RTE_FC_FULL; 1917 break; 1918 } 1919 return 0; 1920 } 1921 1922 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1923 struct rte_eth_fc_conf *fc_conf) 1924 { 1925 struct bnxt *bp = dev->data->dev_private; 1926 int rc; 1927 1928 rc = is_bnxt_in_error(bp); 1929 if (rc) 1930 return rc; 1931 1932 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1933 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1934 return -ENOTSUP; 1935 } 1936 1937 switch (fc_conf->mode) { 1938 case RTE_FC_NONE: 1939 bp->link_info->auto_pause = 0; 1940 bp->link_info->force_pause = 0; 1941 break; 1942 case RTE_FC_RX_PAUSE: 1943 if (fc_conf->autoneg) { 1944 bp->link_info->auto_pause = 1945 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1946 bp->link_info->force_pause = 0; 1947 } else { 1948 bp->link_info->auto_pause = 0; 1949 bp->link_info->force_pause = 1950 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1951 } 1952 break; 1953 case RTE_FC_TX_PAUSE: 1954 if (fc_conf->autoneg) { 1955 bp->link_info->auto_pause = 1956 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1957 bp->link_info->force_pause = 0; 1958 } else { 1959 bp->link_info->auto_pause = 0; 1960 bp->link_info->force_pause = 1961 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1962 } 1963 break; 1964 case RTE_FC_FULL: 1965 if (fc_conf->autoneg) { 1966 bp->link_info->auto_pause = 1967 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1968 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1969 bp->link_info->force_pause = 0; 1970 } else { 1971 bp->link_info->auto_pause = 0; 1972 bp->link_info->force_pause = 1973 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1974 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1975 } 1976 break; 1977 } 1978 return bnxt_set_hwrm_link_config(bp, true); 1979 } 1980 1981 /* Add UDP tunneling port */ 1982 static int 1983 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1984 struct rte_eth_udp_tunnel *udp_tunnel) 1985 { 1986 struct bnxt *bp = eth_dev->data->dev_private; 1987 uint16_t tunnel_type = 0; 1988 int rc = 0; 1989 1990 rc = is_bnxt_in_error(bp); 1991 if (rc) 1992 return rc; 1993 1994 switch (udp_tunnel->prot_type) { 1995 case RTE_TUNNEL_TYPE_VXLAN: 1996 if (bp->vxlan_port_cnt) { 1997 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1998 udp_tunnel->udp_port); 1999 if (bp->vxlan_port != udp_tunnel->udp_port) { 2000 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2001 return -ENOSPC; 2002 } 2003 bp->vxlan_port_cnt++; 2004 return 0; 2005 } 2006 tunnel_type = 2007 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2008 bp->vxlan_port_cnt++; 2009 break; 2010 case RTE_TUNNEL_TYPE_GENEVE: 2011 if (bp->geneve_port_cnt) { 2012 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2013 udp_tunnel->udp_port); 2014 if (bp->geneve_port != udp_tunnel->udp_port) { 2015 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2016 return -ENOSPC; 2017 } 2018 bp->geneve_port_cnt++; 2019 return 0; 2020 } 2021 tunnel_type = 2022 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2023 bp->geneve_port_cnt++; 2024 break; 2025 default: 2026 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2027 return -ENOTSUP; 2028 } 2029 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2030 tunnel_type); 2031 return rc; 2032 } 2033 2034 static int 2035 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2036 struct rte_eth_udp_tunnel *udp_tunnel) 2037 { 2038 struct bnxt *bp = eth_dev->data->dev_private; 2039 uint16_t tunnel_type = 0; 2040 uint16_t port = 0; 2041 int rc = 0; 2042 2043 rc = is_bnxt_in_error(bp); 2044 if (rc) 2045 return rc; 2046 2047 switch (udp_tunnel->prot_type) { 2048 case RTE_TUNNEL_TYPE_VXLAN: 2049 if (!bp->vxlan_port_cnt) { 2050 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2051 return -EINVAL; 2052 } 2053 if (bp->vxlan_port != udp_tunnel->udp_port) { 2054 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2055 udp_tunnel->udp_port, bp->vxlan_port); 2056 return -EINVAL; 2057 } 2058 if (--bp->vxlan_port_cnt) 2059 return 0; 2060 2061 tunnel_type = 2062 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2063 port = bp->vxlan_fw_dst_port_id; 2064 break; 2065 case RTE_TUNNEL_TYPE_GENEVE: 2066 if (!bp->geneve_port_cnt) { 2067 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2068 return -EINVAL; 2069 } 2070 if (bp->geneve_port != udp_tunnel->udp_port) { 2071 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2072 udp_tunnel->udp_port, bp->geneve_port); 2073 return -EINVAL; 2074 } 2075 if (--bp->geneve_port_cnt) 2076 return 0; 2077 2078 tunnel_type = 2079 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2080 port = bp->geneve_fw_dst_port_id; 2081 break; 2082 default: 2083 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2084 return -ENOTSUP; 2085 } 2086 2087 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2088 if (!rc) { 2089 if (tunnel_type == 2090 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 2091 bp->vxlan_port = 0; 2092 if (tunnel_type == 2093 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 2094 bp->geneve_port = 0; 2095 } 2096 return rc; 2097 } 2098 2099 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2100 { 2101 struct bnxt_filter_info *filter; 2102 struct bnxt_vnic_info *vnic; 2103 int rc = 0; 2104 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2105 2106 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2107 filter = STAILQ_FIRST(&vnic->filter); 2108 while (filter) { 2109 /* Search for this matching MAC+VLAN filter */ 2110 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2111 /* Delete the filter */ 2112 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2113 if (rc) 2114 return rc; 2115 STAILQ_REMOVE(&vnic->filter, filter, 2116 bnxt_filter_info, next); 2117 bnxt_free_filter(bp, filter); 2118 PMD_DRV_LOG(INFO, 2119 "Deleted vlan filter for %d\n", 2120 vlan_id); 2121 return 0; 2122 } 2123 filter = STAILQ_NEXT(filter, next); 2124 } 2125 return -ENOENT; 2126 } 2127 2128 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2129 { 2130 struct bnxt_filter_info *filter; 2131 struct bnxt_vnic_info *vnic; 2132 int rc = 0; 2133 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2134 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2135 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2136 2137 /* Implementation notes on the use of VNIC in this command: 2138 * 2139 * By default, these filters belong to default vnic for the function. 2140 * Once these filters are set up, only destination VNIC can be modified. 2141 * If the destination VNIC is not specified in this command, 2142 * then the HWRM shall only create an l2 context id. 2143 */ 2144 2145 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2146 filter = STAILQ_FIRST(&vnic->filter); 2147 /* Check if the VLAN has already been added */ 2148 while (filter) { 2149 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2150 return -EEXIST; 2151 2152 filter = STAILQ_NEXT(filter, next); 2153 } 2154 2155 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2156 * command to create MAC+VLAN filter with the right flags, enables set. 2157 */ 2158 filter = bnxt_alloc_filter(bp); 2159 if (!filter) { 2160 PMD_DRV_LOG(ERR, 2161 "MAC/VLAN filter alloc failed\n"); 2162 return -ENOMEM; 2163 } 2164 /* MAC + VLAN ID filter */ 2165 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2166 * untagged packets are received 2167 * 2168 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2169 * packets and only the programmed vlan's packets are received 2170 */ 2171 filter->l2_ivlan = vlan_id; 2172 filter->l2_ivlan_mask = 0x0FFF; 2173 filter->enables |= en; 2174 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2175 2176 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2177 if (rc) { 2178 /* Free the newly allocated filter as we were 2179 * not able to create the filter in hardware. 2180 */ 2181 bnxt_free_filter(bp, filter); 2182 return rc; 2183 } 2184 2185 filter->mac_index = 0; 2186 /* Add this new filter to the list */ 2187 if (vlan_id == 0) 2188 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2189 else 2190 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2191 2192 PMD_DRV_LOG(INFO, 2193 "Added Vlan filter for %d\n", vlan_id); 2194 return rc; 2195 } 2196 2197 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2198 uint16_t vlan_id, int on) 2199 { 2200 struct bnxt *bp = eth_dev->data->dev_private; 2201 int rc; 2202 2203 rc = is_bnxt_in_error(bp); 2204 if (rc) 2205 return rc; 2206 2207 if (!eth_dev->data->dev_started) { 2208 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2209 return -EINVAL; 2210 } 2211 2212 /* These operations apply to ALL existing MAC/VLAN filters */ 2213 if (on) 2214 return bnxt_add_vlan_filter(bp, vlan_id); 2215 else 2216 return bnxt_del_vlan_filter(bp, vlan_id); 2217 } 2218 2219 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2220 struct bnxt_vnic_info *vnic) 2221 { 2222 struct bnxt_filter_info *filter; 2223 int rc; 2224 2225 filter = STAILQ_FIRST(&vnic->filter); 2226 while (filter) { 2227 if (filter->mac_index == 0 && 2228 !memcmp(filter->l2_addr, bp->mac_addr, 2229 RTE_ETHER_ADDR_LEN)) { 2230 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2231 if (!rc) { 2232 STAILQ_REMOVE(&vnic->filter, filter, 2233 bnxt_filter_info, next); 2234 bnxt_free_filter(bp, filter); 2235 } 2236 return rc; 2237 } 2238 filter = STAILQ_NEXT(filter, next); 2239 } 2240 return 0; 2241 } 2242 2243 static int 2244 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2245 { 2246 struct bnxt_vnic_info *vnic; 2247 unsigned int i; 2248 int rc; 2249 2250 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2251 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2252 /* Remove any VLAN filters programmed */ 2253 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2254 bnxt_del_vlan_filter(bp, i); 2255 2256 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2257 if (rc) 2258 return rc; 2259 } else { 2260 /* Default filter will allow packets that match the 2261 * dest mac. So, it has to be deleted, otherwise, we 2262 * will endup receiving vlan packets for which the 2263 * filter is not programmed, when hw-vlan-filter 2264 * configuration is ON 2265 */ 2266 bnxt_del_dflt_mac_filter(bp, vnic); 2267 /* This filter will allow only untagged packets */ 2268 bnxt_add_vlan_filter(bp, 0); 2269 } 2270 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2271 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2272 2273 return 0; 2274 } 2275 2276 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2277 { 2278 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2279 unsigned int i; 2280 int rc; 2281 2282 /* Destroy vnic filters and vnic */ 2283 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2284 DEV_RX_OFFLOAD_VLAN_FILTER) { 2285 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2286 bnxt_del_vlan_filter(bp, i); 2287 } 2288 bnxt_del_dflt_mac_filter(bp, vnic); 2289 2290 rc = bnxt_hwrm_vnic_free(bp, vnic); 2291 if (rc) 2292 return rc; 2293 2294 rte_free(vnic->fw_grp_ids); 2295 vnic->fw_grp_ids = NULL; 2296 2297 vnic->rx_queue_cnt = 0; 2298 2299 return 0; 2300 } 2301 2302 static int 2303 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2304 { 2305 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2306 int rc; 2307 2308 /* Destroy, recreate and reconfigure the default vnic */ 2309 rc = bnxt_free_one_vnic(bp, 0); 2310 if (rc) 2311 return rc; 2312 2313 /* default vnic 0 */ 2314 rc = bnxt_setup_one_vnic(bp, 0); 2315 if (rc) 2316 return rc; 2317 2318 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2319 DEV_RX_OFFLOAD_VLAN_FILTER) { 2320 rc = bnxt_add_vlan_filter(bp, 0); 2321 if (rc) 2322 return rc; 2323 rc = bnxt_restore_vlan_filters(bp); 2324 if (rc) 2325 return rc; 2326 } else { 2327 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2328 if (rc) 2329 return rc; 2330 } 2331 2332 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2333 if (rc) 2334 return rc; 2335 2336 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2337 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2338 2339 return rc; 2340 } 2341 2342 static int 2343 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2344 { 2345 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2346 struct bnxt *bp = dev->data->dev_private; 2347 int rc; 2348 2349 rc = is_bnxt_in_error(bp); 2350 if (rc) 2351 return rc; 2352 2353 /* Filter settings will get applied when port is started */ 2354 if (!dev->data->dev_started) 2355 return 0; 2356 2357 if (mask & ETH_VLAN_FILTER_MASK) { 2358 /* Enable or disable VLAN filtering */ 2359 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2360 if (rc) 2361 return rc; 2362 } 2363 2364 if (mask & ETH_VLAN_STRIP_MASK) { 2365 /* Enable or disable VLAN stripping */ 2366 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2367 if (rc) 2368 return rc; 2369 } 2370 2371 if (mask & ETH_VLAN_EXTEND_MASK) { 2372 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2373 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2374 else 2375 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2376 } 2377 2378 return 0; 2379 } 2380 2381 static int 2382 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2383 uint16_t tpid) 2384 { 2385 struct bnxt *bp = dev->data->dev_private; 2386 int qinq = dev->data->dev_conf.rxmode.offloads & 2387 DEV_RX_OFFLOAD_VLAN_EXTEND; 2388 2389 if (vlan_type != ETH_VLAN_TYPE_INNER && 2390 vlan_type != ETH_VLAN_TYPE_OUTER) { 2391 PMD_DRV_LOG(ERR, 2392 "Unsupported vlan type."); 2393 return -EINVAL; 2394 } 2395 if (!qinq) { 2396 PMD_DRV_LOG(ERR, 2397 "QinQ not enabled. Needs to be ON as we can " 2398 "accelerate only outer vlan\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2403 switch (tpid) { 2404 case RTE_ETHER_TYPE_QINQ: 2405 bp->outer_tpid_bd = 2406 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2407 break; 2408 case RTE_ETHER_TYPE_VLAN: 2409 bp->outer_tpid_bd = 2410 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2411 break; 2412 case 0x9100: 2413 bp->outer_tpid_bd = 2414 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2415 break; 2416 case 0x9200: 2417 bp->outer_tpid_bd = 2418 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2419 break; 2420 case 0x9300: 2421 bp->outer_tpid_bd = 2422 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2423 break; 2424 default: 2425 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2426 return -EINVAL; 2427 } 2428 bp->outer_tpid_bd |= tpid; 2429 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2430 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2431 PMD_DRV_LOG(ERR, 2432 "Can accelerate only outer vlan in QinQ\n"); 2433 return -EINVAL; 2434 } 2435 2436 return 0; 2437 } 2438 2439 static int 2440 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2441 struct rte_ether_addr *addr) 2442 { 2443 struct bnxt *bp = dev->data->dev_private; 2444 /* Default Filter is tied to VNIC 0 */ 2445 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2446 int rc; 2447 2448 rc = is_bnxt_in_error(bp); 2449 if (rc) 2450 return rc; 2451 2452 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2453 return -EPERM; 2454 2455 if (rte_is_zero_ether_addr(addr)) 2456 return -EINVAL; 2457 2458 /* Filter settings will get applied when port is started */ 2459 if (!dev->data->dev_started) 2460 return 0; 2461 2462 /* Check if the requested MAC is already added */ 2463 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2464 return 0; 2465 2466 /* Destroy filter and re-create it */ 2467 bnxt_del_dflt_mac_filter(bp, vnic); 2468 2469 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2470 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2471 /* This filter will allow only untagged packets */ 2472 rc = bnxt_add_vlan_filter(bp, 0); 2473 } else { 2474 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2475 } 2476 2477 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2478 return rc; 2479 } 2480 2481 static int 2482 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2483 struct rte_ether_addr *mc_addr_set, 2484 uint32_t nb_mc_addr) 2485 { 2486 struct bnxt *bp = eth_dev->data->dev_private; 2487 char *mc_addr_list = (char *)mc_addr_set; 2488 struct bnxt_vnic_info *vnic; 2489 uint32_t off = 0, i = 0; 2490 int rc; 2491 2492 rc = is_bnxt_in_error(bp); 2493 if (rc) 2494 return rc; 2495 2496 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2497 2498 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2499 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2500 goto allmulti; 2501 } 2502 2503 /* TODO Check for Duplicate mcast addresses */ 2504 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2505 for (i = 0; i < nb_mc_addr; i++) { 2506 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2507 RTE_ETHER_ADDR_LEN); 2508 off += RTE_ETHER_ADDR_LEN; 2509 } 2510 2511 vnic->mc_addr_cnt = i; 2512 if (vnic->mc_addr_cnt) 2513 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2514 else 2515 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2516 2517 allmulti: 2518 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2519 } 2520 2521 static int 2522 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2523 { 2524 struct bnxt *bp = dev->data->dev_private; 2525 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2526 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2527 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2528 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2529 int ret; 2530 2531 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2532 fw_major, fw_minor, fw_updt, fw_rsvd); 2533 2534 ret += 1; /* add the size of '\0' */ 2535 if (fw_size < (uint32_t)ret) 2536 return ret; 2537 else 2538 return 0; 2539 } 2540 2541 static void 2542 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2543 struct rte_eth_rxq_info *qinfo) 2544 { 2545 struct bnxt *bp = dev->data->dev_private; 2546 struct bnxt_rx_queue *rxq; 2547 2548 if (is_bnxt_in_error(bp)) 2549 return; 2550 2551 rxq = dev->data->rx_queues[queue_id]; 2552 2553 qinfo->mp = rxq->mb_pool; 2554 qinfo->scattered_rx = dev->data->scattered_rx; 2555 qinfo->nb_desc = rxq->nb_rx_desc; 2556 2557 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2558 qinfo->conf.rx_drop_en = 0; 2559 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2560 } 2561 2562 static void 2563 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2564 struct rte_eth_txq_info *qinfo) 2565 { 2566 struct bnxt *bp = dev->data->dev_private; 2567 struct bnxt_tx_queue *txq; 2568 2569 if (is_bnxt_in_error(bp)) 2570 return; 2571 2572 txq = dev->data->tx_queues[queue_id]; 2573 2574 qinfo->nb_desc = txq->nb_tx_desc; 2575 2576 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2577 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2578 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2579 2580 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2581 qinfo->conf.tx_rs_thresh = 0; 2582 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2583 } 2584 2585 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2586 { 2587 struct bnxt *bp = eth_dev->data->dev_private; 2588 uint32_t new_pkt_size; 2589 uint32_t rc = 0; 2590 uint32_t i; 2591 2592 rc = is_bnxt_in_error(bp); 2593 if (rc) 2594 return rc; 2595 2596 /* Exit if receive queues are not configured yet */ 2597 if (!eth_dev->data->nb_rx_queues) 2598 return rc; 2599 2600 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2601 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2602 2603 #ifdef RTE_ARCH_X86 2604 /* 2605 * If vector-mode tx/rx is active, disallow any MTU change that would 2606 * require scattered receive support. 2607 */ 2608 if (eth_dev->data->dev_started && 2609 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 2610 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 2611 (new_pkt_size > 2612 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2613 PMD_DRV_LOG(ERR, 2614 "MTU change would require scattered rx support. "); 2615 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2616 return -EINVAL; 2617 } 2618 #endif 2619 2620 if (new_mtu > RTE_ETHER_MTU) { 2621 bp->flags |= BNXT_FLAG_JUMBO; 2622 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2623 DEV_RX_OFFLOAD_JUMBO_FRAME; 2624 } else { 2625 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2626 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2627 bp->flags &= ~BNXT_FLAG_JUMBO; 2628 } 2629 2630 /* Is there a change in mtu setting? */ 2631 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2632 return rc; 2633 2634 for (i = 0; i < bp->nr_vnics; i++) { 2635 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2636 uint16_t size = 0; 2637 2638 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2639 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2640 if (rc) 2641 break; 2642 2643 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2644 size -= RTE_PKTMBUF_HEADROOM; 2645 2646 if (size < new_mtu) { 2647 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2648 if (rc) 2649 return rc; 2650 } 2651 } 2652 2653 if (!rc) 2654 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2655 2656 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2657 2658 return rc; 2659 } 2660 2661 static int 2662 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2663 { 2664 struct bnxt *bp = dev->data->dev_private; 2665 uint16_t vlan = bp->vlan; 2666 int rc; 2667 2668 rc = is_bnxt_in_error(bp); 2669 if (rc) 2670 return rc; 2671 2672 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2673 PMD_DRV_LOG(ERR, 2674 "PVID cannot be modified for this function\n"); 2675 return -ENOTSUP; 2676 } 2677 bp->vlan = on ? pvid : 0; 2678 2679 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2680 if (rc) 2681 bp->vlan = vlan; 2682 return rc; 2683 } 2684 2685 static int 2686 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2687 { 2688 struct bnxt *bp = dev->data->dev_private; 2689 int rc; 2690 2691 rc = is_bnxt_in_error(bp); 2692 if (rc) 2693 return rc; 2694 2695 return bnxt_hwrm_port_led_cfg(bp, true); 2696 } 2697 2698 static int 2699 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2700 { 2701 struct bnxt *bp = dev->data->dev_private; 2702 int rc; 2703 2704 rc = is_bnxt_in_error(bp); 2705 if (rc) 2706 return rc; 2707 2708 return bnxt_hwrm_port_led_cfg(bp, false); 2709 } 2710 2711 static uint32_t 2712 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2713 { 2714 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2715 uint32_t desc = 0, raw_cons = 0, cons; 2716 struct bnxt_cp_ring_info *cpr; 2717 struct bnxt_rx_queue *rxq; 2718 struct rx_pkt_cmpl *rxcmp; 2719 int rc; 2720 2721 rc = is_bnxt_in_error(bp); 2722 if (rc) 2723 return rc; 2724 2725 rxq = dev->data->rx_queues[rx_queue_id]; 2726 cpr = rxq->cp_ring; 2727 raw_cons = cpr->cp_raw_cons; 2728 2729 while (1) { 2730 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2731 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2732 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2733 2734 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2735 break; 2736 } else { 2737 raw_cons++; 2738 desc++; 2739 } 2740 } 2741 2742 return desc; 2743 } 2744 2745 static int 2746 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2747 { 2748 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2749 struct bnxt_rx_ring_info *rxr; 2750 struct bnxt_cp_ring_info *cpr; 2751 struct bnxt_sw_rx_bd *rx_buf; 2752 struct rx_pkt_cmpl *rxcmp; 2753 uint32_t cons, cp_cons; 2754 int rc; 2755 2756 if (!rxq) 2757 return -EINVAL; 2758 2759 rc = is_bnxt_in_error(rxq->bp); 2760 if (rc) 2761 return rc; 2762 2763 cpr = rxq->cp_ring; 2764 rxr = rxq->rx_ring; 2765 2766 if (offset >= rxq->nb_rx_desc) 2767 return -EINVAL; 2768 2769 cons = RING_CMP(cpr->cp_ring_struct, offset); 2770 cp_cons = cpr->cp_raw_cons; 2771 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2772 2773 if (cons > cp_cons) { 2774 if (CMPL_VALID(rxcmp, cpr->valid)) 2775 return RTE_ETH_RX_DESC_DONE; 2776 } else { 2777 if (CMPL_VALID(rxcmp, !cpr->valid)) 2778 return RTE_ETH_RX_DESC_DONE; 2779 } 2780 rx_buf = &rxr->rx_buf_ring[cons]; 2781 if (rx_buf->mbuf == NULL) 2782 return RTE_ETH_RX_DESC_UNAVAIL; 2783 2784 2785 return RTE_ETH_RX_DESC_AVAIL; 2786 } 2787 2788 static int 2789 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2790 { 2791 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2792 struct bnxt_tx_ring_info *txr; 2793 struct bnxt_cp_ring_info *cpr; 2794 struct bnxt_sw_tx_bd *tx_buf; 2795 struct tx_pkt_cmpl *txcmp; 2796 uint32_t cons, cp_cons; 2797 int rc; 2798 2799 if (!txq) 2800 return -EINVAL; 2801 2802 rc = is_bnxt_in_error(txq->bp); 2803 if (rc) 2804 return rc; 2805 2806 cpr = txq->cp_ring; 2807 txr = txq->tx_ring; 2808 2809 if (offset >= txq->nb_tx_desc) 2810 return -EINVAL; 2811 2812 cons = RING_CMP(cpr->cp_ring_struct, offset); 2813 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2814 cp_cons = cpr->cp_raw_cons; 2815 2816 if (cons > cp_cons) { 2817 if (CMPL_VALID(txcmp, cpr->valid)) 2818 return RTE_ETH_TX_DESC_UNAVAIL; 2819 } else { 2820 if (CMPL_VALID(txcmp, !cpr->valid)) 2821 return RTE_ETH_TX_DESC_UNAVAIL; 2822 } 2823 tx_buf = &txr->tx_buf_ring[cons]; 2824 if (tx_buf->mbuf == NULL) 2825 return RTE_ETH_TX_DESC_DONE; 2826 2827 return RTE_ETH_TX_DESC_FULL; 2828 } 2829 2830 static struct bnxt_filter_info * 2831 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2832 struct rte_eth_ethertype_filter *efilter, 2833 struct bnxt_vnic_info *vnic0, 2834 struct bnxt_vnic_info *vnic, 2835 int *ret) 2836 { 2837 struct bnxt_filter_info *mfilter = NULL; 2838 int match = 0; 2839 *ret = 0; 2840 2841 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2842 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2843 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2844 " ethertype filter.", efilter->ether_type); 2845 *ret = -EINVAL; 2846 goto exit; 2847 } 2848 if (efilter->queue >= bp->rx_nr_rings) { 2849 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2850 *ret = -EINVAL; 2851 goto exit; 2852 } 2853 2854 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2855 vnic = &bp->vnic_info[efilter->queue]; 2856 if (vnic == NULL) { 2857 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2858 *ret = -EINVAL; 2859 goto exit; 2860 } 2861 2862 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2863 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2864 if ((!memcmp(efilter->mac_addr.addr_bytes, 2865 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2866 mfilter->flags == 2867 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2868 mfilter->ethertype == efilter->ether_type)) { 2869 match = 1; 2870 break; 2871 } 2872 } 2873 } else { 2874 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2875 if ((!memcmp(efilter->mac_addr.addr_bytes, 2876 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2877 mfilter->ethertype == efilter->ether_type && 2878 mfilter->flags == 2879 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2880 match = 1; 2881 break; 2882 } 2883 } 2884 2885 if (match) 2886 *ret = -EEXIST; 2887 2888 exit: 2889 return mfilter; 2890 } 2891 2892 static int 2893 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2894 enum rte_filter_op filter_op, 2895 void *arg) 2896 { 2897 struct bnxt *bp = dev->data->dev_private; 2898 struct rte_eth_ethertype_filter *efilter = 2899 (struct rte_eth_ethertype_filter *)arg; 2900 struct bnxt_filter_info *bfilter, *filter1; 2901 struct bnxt_vnic_info *vnic, *vnic0; 2902 int ret; 2903 2904 if (filter_op == RTE_ETH_FILTER_NOP) 2905 return 0; 2906 2907 if (arg == NULL) { 2908 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2909 filter_op); 2910 return -EINVAL; 2911 } 2912 2913 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2914 vnic = &bp->vnic_info[efilter->queue]; 2915 2916 switch (filter_op) { 2917 case RTE_ETH_FILTER_ADD: 2918 bnxt_match_and_validate_ether_filter(bp, efilter, 2919 vnic0, vnic, &ret); 2920 if (ret < 0) 2921 return ret; 2922 2923 bfilter = bnxt_get_unused_filter(bp); 2924 if (bfilter == NULL) { 2925 PMD_DRV_LOG(ERR, 2926 "Not enough resources for a new filter.\n"); 2927 return -ENOMEM; 2928 } 2929 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2930 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 2931 RTE_ETHER_ADDR_LEN); 2932 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 2933 RTE_ETHER_ADDR_LEN); 2934 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2935 bfilter->ethertype = efilter->ether_type; 2936 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2937 2938 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 2939 if (filter1 == NULL) { 2940 ret = -EINVAL; 2941 goto cleanup; 2942 } 2943 bfilter->enables |= 2944 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2945 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2946 2947 bfilter->dst_id = vnic->fw_vnic_id; 2948 2949 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2950 bfilter->flags = 2951 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2952 } 2953 2954 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2955 if (ret) 2956 goto cleanup; 2957 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2958 break; 2959 case RTE_ETH_FILTER_DELETE: 2960 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 2961 vnic0, vnic, &ret); 2962 if (ret == -EEXIST) { 2963 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 2964 2965 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 2966 next); 2967 bnxt_free_filter(bp, filter1); 2968 } else if (ret == 0) { 2969 PMD_DRV_LOG(ERR, "No matching filter found\n"); 2970 } 2971 break; 2972 default: 2973 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2974 ret = -EINVAL; 2975 goto error; 2976 } 2977 return ret; 2978 cleanup: 2979 bnxt_free_filter(bp, bfilter); 2980 error: 2981 return ret; 2982 } 2983 2984 static inline int 2985 parse_ntuple_filter(struct bnxt *bp, 2986 struct rte_eth_ntuple_filter *nfilter, 2987 struct bnxt_filter_info *bfilter) 2988 { 2989 uint32_t en = 0; 2990 2991 if (nfilter->queue >= bp->rx_nr_rings) { 2992 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 2993 return -EINVAL; 2994 } 2995 2996 switch (nfilter->dst_port_mask) { 2997 case UINT16_MAX: 2998 bfilter->dst_port_mask = -1; 2999 bfilter->dst_port = nfilter->dst_port; 3000 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 3001 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3002 break; 3003 default: 3004 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 3005 return -EINVAL; 3006 } 3007 3008 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3009 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3010 3011 switch (nfilter->proto_mask) { 3012 case UINT8_MAX: 3013 if (nfilter->proto == 17) /* IPPROTO_UDP */ 3014 bfilter->ip_protocol = 17; 3015 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 3016 bfilter->ip_protocol = 6; 3017 else 3018 return -EINVAL; 3019 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3020 break; 3021 default: 3022 PMD_DRV_LOG(ERR, "invalid protocol mask."); 3023 return -EINVAL; 3024 } 3025 3026 switch (nfilter->dst_ip_mask) { 3027 case UINT32_MAX: 3028 bfilter->dst_ipaddr_mask[0] = -1; 3029 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 3030 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 3031 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3032 break; 3033 default: 3034 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3035 return -EINVAL; 3036 } 3037 3038 switch (nfilter->src_ip_mask) { 3039 case UINT32_MAX: 3040 bfilter->src_ipaddr_mask[0] = -1; 3041 bfilter->src_ipaddr[0] = nfilter->src_ip; 3042 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 3043 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3044 break; 3045 default: 3046 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 3047 return -EINVAL; 3048 } 3049 3050 switch (nfilter->src_port_mask) { 3051 case UINT16_MAX: 3052 bfilter->src_port_mask = -1; 3053 bfilter->src_port = nfilter->src_port; 3054 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 3055 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3056 break; 3057 default: 3058 PMD_DRV_LOG(ERR, "invalid src_port mask."); 3059 return -EINVAL; 3060 } 3061 3062 bfilter->enables = en; 3063 return 0; 3064 } 3065 3066 static struct bnxt_filter_info* 3067 bnxt_match_ntuple_filter(struct bnxt *bp, 3068 struct bnxt_filter_info *bfilter, 3069 struct bnxt_vnic_info **mvnic) 3070 { 3071 struct bnxt_filter_info *mfilter = NULL; 3072 int i; 3073 3074 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3075 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3076 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 3077 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 3078 bfilter->src_ipaddr_mask[0] == 3079 mfilter->src_ipaddr_mask[0] && 3080 bfilter->src_port == mfilter->src_port && 3081 bfilter->src_port_mask == mfilter->src_port_mask && 3082 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 3083 bfilter->dst_ipaddr_mask[0] == 3084 mfilter->dst_ipaddr_mask[0] && 3085 bfilter->dst_port == mfilter->dst_port && 3086 bfilter->dst_port_mask == mfilter->dst_port_mask && 3087 bfilter->flags == mfilter->flags && 3088 bfilter->enables == mfilter->enables) { 3089 if (mvnic) 3090 *mvnic = vnic; 3091 return mfilter; 3092 } 3093 } 3094 } 3095 return NULL; 3096 } 3097 3098 static int 3099 bnxt_cfg_ntuple_filter(struct bnxt *bp, 3100 struct rte_eth_ntuple_filter *nfilter, 3101 enum rte_filter_op filter_op) 3102 { 3103 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 3104 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 3105 int ret; 3106 3107 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 3108 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 3109 return -EINVAL; 3110 } 3111 3112 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 3113 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 3114 return -EINVAL; 3115 } 3116 3117 bfilter = bnxt_get_unused_filter(bp); 3118 if (bfilter == NULL) { 3119 PMD_DRV_LOG(ERR, 3120 "Not enough resources for a new filter.\n"); 3121 return -ENOMEM; 3122 } 3123 ret = parse_ntuple_filter(bp, nfilter, bfilter); 3124 if (ret < 0) 3125 goto free_filter; 3126 3127 vnic = &bp->vnic_info[nfilter->queue]; 3128 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3129 filter1 = STAILQ_FIRST(&vnic0->filter); 3130 if (filter1 == NULL) { 3131 ret = -EINVAL; 3132 goto free_filter; 3133 } 3134 3135 bfilter->dst_id = vnic->fw_vnic_id; 3136 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3137 bfilter->enables |= 3138 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3139 bfilter->ethertype = 0x800; 3140 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3141 3142 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 3143 3144 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 3145 bfilter->dst_id == mfilter->dst_id) { 3146 PMD_DRV_LOG(ERR, "filter exists.\n"); 3147 ret = -EEXIST; 3148 goto free_filter; 3149 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 3150 bfilter->dst_id != mfilter->dst_id) { 3151 mfilter->dst_id = vnic->fw_vnic_id; 3152 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 3153 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 3154 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 3155 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 3156 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 3157 goto free_filter; 3158 } 3159 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3160 PMD_DRV_LOG(ERR, "filter doesn't exist."); 3161 ret = -ENOENT; 3162 goto free_filter; 3163 } 3164 3165 if (filter_op == RTE_ETH_FILTER_ADD) { 3166 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3167 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 3168 if (ret) 3169 goto free_filter; 3170 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 3171 } else { 3172 if (mfilter == NULL) { 3173 /* This should not happen. But for Coverity! */ 3174 ret = -ENOENT; 3175 goto free_filter; 3176 } 3177 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 3178 3179 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 3180 bnxt_free_filter(bp, mfilter); 3181 bnxt_free_filter(bp, bfilter); 3182 } 3183 3184 return 0; 3185 free_filter: 3186 bnxt_free_filter(bp, bfilter); 3187 return ret; 3188 } 3189 3190 static int 3191 bnxt_ntuple_filter(struct rte_eth_dev *dev, 3192 enum rte_filter_op filter_op, 3193 void *arg) 3194 { 3195 struct bnxt *bp = dev->data->dev_private; 3196 int ret; 3197 3198 if (filter_op == RTE_ETH_FILTER_NOP) 3199 return 0; 3200 3201 if (arg == NULL) { 3202 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 3203 filter_op); 3204 return -EINVAL; 3205 } 3206 3207 switch (filter_op) { 3208 case RTE_ETH_FILTER_ADD: 3209 ret = bnxt_cfg_ntuple_filter(bp, 3210 (struct rte_eth_ntuple_filter *)arg, 3211 filter_op); 3212 break; 3213 case RTE_ETH_FILTER_DELETE: 3214 ret = bnxt_cfg_ntuple_filter(bp, 3215 (struct rte_eth_ntuple_filter *)arg, 3216 filter_op); 3217 break; 3218 default: 3219 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 3220 ret = -EINVAL; 3221 break; 3222 } 3223 return ret; 3224 } 3225 3226 static int 3227 bnxt_parse_fdir_filter(struct bnxt *bp, 3228 struct rte_eth_fdir_filter *fdir, 3229 struct bnxt_filter_info *filter) 3230 { 3231 enum rte_fdir_mode fdir_mode = 3232 bp->eth_dev->data->dev_conf.fdir_conf.mode; 3233 struct bnxt_vnic_info *vnic0, *vnic; 3234 struct bnxt_filter_info *filter1; 3235 uint32_t en = 0; 3236 int i; 3237 3238 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 3239 return -EINVAL; 3240 3241 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 3242 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 3243 3244 switch (fdir->input.flow_type) { 3245 case RTE_ETH_FLOW_IPV4: 3246 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3247 /* FALLTHROUGH */ 3248 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 3249 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3250 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 3251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3252 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 3253 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3254 filter->ip_addr_type = 3255 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3256 filter->src_ipaddr_mask[0] = 0xffffffff; 3257 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3258 filter->dst_ipaddr_mask[0] = 0xffffffff; 3259 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3260 filter->ethertype = 0x800; 3261 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3262 break; 3263 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3264 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 3265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3266 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 3267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3268 filter->dst_port_mask = 0xffff; 3269 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3270 filter->src_port_mask = 0xffff; 3271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3272 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 3273 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3274 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 3275 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3276 filter->ip_protocol = 6; 3277 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3278 filter->ip_addr_type = 3279 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3280 filter->src_ipaddr_mask[0] = 0xffffffff; 3281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3282 filter->dst_ipaddr_mask[0] = 0xffffffff; 3283 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3284 filter->ethertype = 0x800; 3285 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3286 break; 3287 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3288 filter->src_port = fdir->input.flow.udp4_flow.src_port; 3289 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3290 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 3291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3292 filter->dst_port_mask = 0xffff; 3293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3294 filter->src_port_mask = 0xffff; 3295 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3296 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 3297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3298 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 3299 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3300 filter->ip_protocol = 17; 3301 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3302 filter->ip_addr_type = 3303 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3304 filter->src_ipaddr_mask[0] = 0xffffffff; 3305 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3306 filter->dst_ipaddr_mask[0] = 0xffffffff; 3307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3308 filter->ethertype = 0x800; 3309 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3310 break; 3311 case RTE_ETH_FLOW_IPV6: 3312 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3313 /* FALLTHROUGH */ 3314 filter->ip_addr_type = 3315 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3316 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 3317 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3318 rte_memcpy(filter->src_ipaddr, 3319 fdir->input.flow.ipv6_flow.src_ip, 16); 3320 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3321 rte_memcpy(filter->dst_ipaddr, 3322 fdir->input.flow.ipv6_flow.dst_ip, 16); 3323 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3324 memset(filter->dst_ipaddr_mask, 0xff, 16); 3325 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3326 memset(filter->src_ipaddr_mask, 0xff, 16); 3327 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3328 filter->ethertype = 0x86dd; 3329 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3330 break; 3331 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3332 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 3333 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3334 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 3335 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3336 filter->dst_port_mask = 0xffff; 3337 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3338 filter->src_port_mask = 0xffff; 3339 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3340 filter->ip_addr_type = 3341 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3342 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 3343 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3344 rte_memcpy(filter->src_ipaddr, 3345 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 3346 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3347 rte_memcpy(filter->dst_ipaddr, 3348 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 3349 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3350 memset(filter->dst_ipaddr_mask, 0xff, 16); 3351 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3352 memset(filter->src_ipaddr_mask, 0xff, 16); 3353 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3354 filter->ethertype = 0x86dd; 3355 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3356 break; 3357 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3358 filter->src_port = fdir->input.flow.udp6_flow.src_port; 3359 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3360 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3362 filter->dst_port_mask = 0xffff; 3363 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3364 filter->src_port_mask = 0xffff; 3365 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3366 filter->ip_addr_type = 3367 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3368 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 3369 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3370 rte_memcpy(filter->src_ipaddr, 3371 fdir->input.flow.udp6_flow.ip.src_ip, 16); 3372 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3373 rte_memcpy(filter->dst_ipaddr, 3374 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 3375 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3376 memset(filter->dst_ipaddr_mask, 0xff, 16); 3377 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3378 memset(filter->src_ipaddr_mask, 0xff, 16); 3379 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3380 filter->ethertype = 0x86dd; 3381 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3382 break; 3383 case RTE_ETH_FLOW_L2_PAYLOAD: 3384 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 3385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3386 break; 3387 case RTE_ETH_FLOW_VXLAN: 3388 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3389 return -EINVAL; 3390 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3391 filter->tunnel_type = 3392 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 3393 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3394 break; 3395 case RTE_ETH_FLOW_NVGRE: 3396 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3397 return -EINVAL; 3398 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3399 filter->tunnel_type = 3400 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 3401 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3402 break; 3403 case RTE_ETH_FLOW_UNKNOWN: 3404 case RTE_ETH_FLOW_RAW: 3405 case RTE_ETH_FLOW_FRAG_IPV4: 3406 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 3407 case RTE_ETH_FLOW_FRAG_IPV6: 3408 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 3409 case RTE_ETH_FLOW_IPV6_EX: 3410 case RTE_ETH_FLOW_IPV6_TCP_EX: 3411 case RTE_ETH_FLOW_IPV6_UDP_EX: 3412 case RTE_ETH_FLOW_GENEVE: 3413 /* FALLTHROUGH */ 3414 default: 3415 return -EINVAL; 3416 } 3417 3418 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3419 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3420 if (vnic == NULL) { 3421 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 3422 return -EINVAL; 3423 } 3424 3425 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3426 rte_memcpy(filter->dst_macaddr, 3427 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 3428 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 3429 } 3430 3431 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 3432 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 3433 filter1 = STAILQ_FIRST(&vnic0->filter); 3434 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 3435 } else { 3436 filter->dst_id = vnic->fw_vnic_id; 3437 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3438 if (filter->dst_macaddr[i] == 0x00) 3439 filter1 = STAILQ_FIRST(&vnic0->filter); 3440 else 3441 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 3442 } 3443 3444 if (filter1 == NULL) 3445 return -EINVAL; 3446 3447 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3448 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3449 3450 filter->enables = en; 3451 3452 return 0; 3453 } 3454 3455 static struct bnxt_filter_info * 3456 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 3457 struct bnxt_vnic_info **mvnic) 3458 { 3459 struct bnxt_filter_info *mf = NULL; 3460 int i; 3461 3462 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3463 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3464 3465 STAILQ_FOREACH(mf, &vnic->filter, next) { 3466 if (mf->filter_type == nf->filter_type && 3467 mf->flags == nf->flags && 3468 mf->src_port == nf->src_port && 3469 mf->src_port_mask == nf->src_port_mask && 3470 mf->dst_port == nf->dst_port && 3471 mf->dst_port_mask == nf->dst_port_mask && 3472 mf->ip_protocol == nf->ip_protocol && 3473 mf->ip_addr_type == nf->ip_addr_type && 3474 mf->ethertype == nf->ethertype && 3475 mf->vni == nf->vni && 3476 mf->tunnel_type == nf->tunnel_type && 3477 mf->l2_ovlan == nf->l2_ovlan && 3478 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 3479 mf->l2_ivlan == nf->l2_ivlan && 3480 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 3481 !memcmp(mf->l2_addr, nf->l2_addr, 3482 RTE_ETHER_ADDR_LEN) && 3483 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 3484 RTE_ETHER_ADDR_LEN) && 3485 !memcmp(mf->src_macaddr, nf->src_macaddr, 3486 RTE_ETHER_ADDR_LEN) && 3487 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 3488 RTE_ETHER_ADDR_LEN) && 3489 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 3490 sizeof(nf->src_ipaddr)) && 3491 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 3492 sizeof(nf->src_ipaddr_mask)) && 3493 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 3494 sizeof(nf->dst_ipaddr)) && 3495 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 3496 sizeof(nf->dst_ipaddr_mask))) { 3497 if (mvnic) 3498 *mvnic = vnic; 3499 return mf; 3500 } 3501 } 3502 } 3503 return NULL; 3504 } 3505 3506 static int 3507 bnxt_fdir_filter(struct rte_eth_dev *dev, 3508 enum rte_filter_op filter_op, 3509 void *arg) 3510 { 3511 struct bnxt *bp = dev->data->dev_private; 3512 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 3513 struct bnxt_filter_info *filter, *match; 3514 struct bnxt_vnic_info *vnic, *mvnic; 3515 int ret = 0, i; 3516 3517 if (filter_op == RTE_ETH_FILTER_NOP) 3518 return 0; 3519 3520 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 3521 return -EINVAL; 3522 3523 switch (filter_op) { 3524 case RTE_ETH_FILTER_ADD: 3525 case RTE_ETH_FILTER_DELETE: 3526 /* FALLTHROUGH */ 3527 filter = bnxt_get_unused_filter(bp); 3528 if (filter == NULL) { 3529 PMD_DRV_LOG(ERR, 3530 "Not enough resources for a new flow.\n"); 3531 return -ENOMEM; 3532 } 3533 3534 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 3535 if (ret != 0) 3536 goto free_filter; 3537 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3538 3539 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3540 vnic = &bp->vnic_info[0]; 3541 else 3542 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3543 3544 match = bnxt_match_fdir(bp, filter, &mvnic); 3545 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 3546 if (match->dst_id == vnic->fw_vnic_id) { 3547 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 3548 ret = -EEXIST; 3549 goto free_filter; 3550 } else { 3551 match->dst_id = vnic->fw_vnic_id; 3552 ret = bnxt_hwrm_set_ntuple_filter(bp, 3553 match->dst_id, 3554 match); 3555 STAILQ_REMOVE(&mvnic->filter, match, 3556 bnxt_filter_info, next); 3557 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 3558 PMD_DRV_LOG(ERR, 3559 "Filter with matching pattern exist\n"); 3560 PMD_DRV_LOG(ERR, 3561 "Updated it to new destination q\n"); 3562 goto free_filter; 3563 } 3564 } 3565 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3566 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 3567 ret = -ENOENT; 3568 goto free_filter; 3569 } 3570 3571 if (filter_op == RTE_ETH_FILTER_ADD) { 3572 ret = bnxt_hwrm_set_ntuple_filter(bp, 3573 filter->dst_id, 3574 filter); 3575 if (ret) 3576 goto free_filter; 3577 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 3578 } else { 3579 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 3580 STAILQ_REMOVE(&vnic->filter, match, 3581 bnxt_filter_info, next); 3582 bnxt_free_filter(bp, match); 3583 bnxt_free_filter(bp, filter); 3584 } 3585 break; 3586 case RTE_ETH_FILTER_FLUSH: 3587 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3588 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3589 3590 STAILQ_FOREACH(filter, &vnic->filter, next) { 3591 if (filter->filter_type == 3592 HWRM_CFA_NTUPLE_FILTER) { 3593 ret = 3594 bnxt_hwrm_clear_ntuple_filter(bp, 3595 filter); 3596 STAILQ_REMOVE(&vnic->filter, filter, 3597 bnxt_filter_info, next); 3598 } 3599 } 3600 } 3601 return ret; 3602 case RTE_ETH_FILTER_UPDATE: 3603 case RTE_ETH_FILTER_STATS: 3604 case RTE_ETH_FILTER_INFO: 3605 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 3606 break; 3607 default: 3608 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 3609 ret = -EINVAL; 3610 break; 3611 } 3612 return ret; 3613 3614 free_filter: 3615 bnxt_free_filter(bp, filter); 3616 return ret; 3617 } 3618 3619 static int 3620 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3621 enum rte_filter_type filter_type, 3622 enum rte_filter_op filter_op, void *arg) 3623 { 3624 struct bnxt *bp = dev->data->dev_private; 3625 int ret = 0; 3626 3627 ret = is_bnxt_in_error(dev->data->dev_private); 3628 if (ret) 3629 return ret; 3630 3631 switch (filter_type) { 3632 case RTE_ETH_FILTER_TUNNEL: 3633 PMD_DRV_LOG(ERR, 3634 "filter type: %d: To be implemented\n", filter_type); 3635 break; 3636 case RTE_ETH_FILTER_FDIR: 3637 ret = bnxt_fdir_filter(dev, filter_op, arg); 3638 break; 3639 case RTE_ETH_FILTER_NTUPLE: 3640 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3641 break; 3642 case RTE_ETH_FILTER_ETHERTYPE: 3643 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3644 break; 3645 case RTE_ETH_FILTER_GENERIC: 3646 if (filter_op != RTE_ETH_FILTER_GET) 3647 return -EINVAL; 3648 if (BNXT_TRUFLOW_EN(bp)) 3649 *(const void **)arg = &bnxt_ulp_rte_flow_ops; 3650 else 3651 *(const void **)arg = &bnxt_flow_ops; 3652 break; 3653 default: 3654 PMD_DRV_LOG(ERR, 3655 "Filter type (%d) not supported", filter_type); 3656 ret = -EINVAL; 3657 break; 3658 } 3659 return ret; 3660 } 3661 3662 static const uint32_t * 3663 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3664 { 3665 static const uint32_t ptypes[] = { 3666 RTE_PTYPE_L2_ETHER_VLAN, 3667 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3668 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3669 RTE_PTYPE_L4_ICMP, 3670 RTE_PTYPE_L4_TCP, 3671 RTE_PTYPE_L4_UDP, 3672 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3673 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3674 RTE_PTYPE_INNER_L4_ICMP, 3675 RTE_PTYPE_INNER_L4_TCP, 3676 RTE_PTYPE_INNER_L4_UDP, 3677 RTE_PTYPE_UNKNOWN 3678 }; 3679 3680 if (!dev->rx_pkt_burst) 3681 return NULL; 3682 3683 return ptypes; 3684 } 3685 3686 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3687 int reg_win) 3688 { 3689 uint32_t reg_base = *reg_arr & 0xfffff000; 3690 uint32_t win_off; 3691 int i; 3692 3693 for (i = 0; i < count; i++) { 3694 if ((reg_arr[i] & 0xfffff000) != reg_base) 3695 return -ERANGE; 3696 } 3697 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3698 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3699 return 0; 3700 } 3701 3702 static int bnxt_map_ptp_regs(struct bnxt *bp) 3703 { 3704 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3705 uint32_t *reg_arr; 3706 int rc, i; 3707 3708 reg_arr = ptp->rx_regs; 3709 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3710 if (rc) 3711 return rc; 3712 3713 reg_arr = ptp->tx_regs; 3714 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3715 if (rc) 3716 return rc; 3717 3718 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3719 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3720 3721 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3722 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3723 3724 return 0; 3725 } 3726 3727 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3728 { 3729 rte_write32(0, (uint8_t *)bp->bar0 + 3730 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3731 rte_write32(0, (uint8_t *)bp->bar0 + 3732 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3733 } 3734 3735 static uint64_t bnxt_cc_read(struct bnxt *bp) 3736 { 3737 uint64_t ns; 3738 3739 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3740 BNXT_GRCPF_REG_SYNC_TIME)); 3741 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3742 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3743 return ns; 3744 } 3745 3746 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3747 { 3748 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3749 uint32_t fifo; 3750 3751 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3752 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3753 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3754 return -EAGAIN; 3755 3756 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3757 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3758 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3759 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3760 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3761 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3762 3763 return 0; 3764 } 3765 3766 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3767 { 3768 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3769 struct bnxt_pf_info *pf = bp->pf; 3770 uint16_t port_id; 3771 uint32_t fifo; 3772 3773 if (!ptp) 3774 return -ENODEV; 3775 3776 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3777 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3778 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3779 return -EAGAIN; 3780 3781 port_id = pf->port_id; 3782 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3783 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3784 3785 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3786 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3787 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3788 /* bnxt_clr_rx_ts(bp); TBD */ 3789 return -EBUSY; 3790 } 3791 3792 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3793 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3794 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3795 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3796 3797 return 0; 3798 } 3799 3800 static int 3801 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3802 { 3803 uint64_t ns; 3804 struct bnxt *bp = dev->data->dev_private; 3805 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3806 3807 if (!ptp) 3808 return 0; 3809 3810 ns = rte_timespec_to_ns(ts); 3811 /* Set the timecounters to a new value. */ 3812 ptp->tc.nsec = ns; 3813 3814 return 0; 3815 } 3816 3817 static int 3818 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3819 { 3820 struct bnxt *bp = dev->data->dev_private; 3821 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3822 uint64_t ns, systime_cycles = 0; 3823 int rc = 0; 3824 3825 if (!ptp) 3826 return 0; 3827 3828 if (BNXT_CHIP_THOR(bp)) 3829 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3830 &systime_cycles); 3831 else 3832 systime_cycles = bnxt_cc_read(bp); 3833 3834 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3835 *ts = rte_ns_to_timespec(ns); 3836 3837 return rc; 3838 } 3839 static int 3840 bnxt_timesync_enable(struct rte_eth_dev *dev) 3841 { 3842 struct bnxt *bp = dev->data->dev_private; 3843 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3844 uint32_t shift = 0; 3845 int rc; 3846 3847 if (!ptp) 3848 return 0; 3849 3850 ptp->rx_filter = 1; 3851 ptp->tx_tstamp_en = 1; 3852 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3853 3854 rc = bnxt_hwrm_ptp_cfg(bp); 3855 if (rc) 3856 return rc; 3857 3858 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3859 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3860 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3861 3862 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3863 ptp->tc.cc_shift = shift; 3864 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3865 3866 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3867 ptp->rx_tstamp_tc.cc_shift = shift; 3868 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3869 3870 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3871 ptp->tx_tstamp_tc.cc_shift = shift; 3872 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3873 3874 if (!BNXT_CHIP_THOR(bp)) 3875 bnxt_map_ptp_regs(bp); 3876 3877 return 0; 3878 } 3879 3880 static int 3881 bnxt_timesync_disable(struct rte_eth_dev *dev) 3882 { 3883 struct bnxt *bp = dev->data->dev_private; 3884 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3885 3886 if (!ptp) 3887 return 0; 3888 3889 ptp->rx_filter = 0; 3890 ptp->tx_tstamp_en = 0; 3891 ptp->rxctl = 0; 3892 3893 bnxt_hwrm_ptp_cfg(bp); 3894 3895 if (!BNXT_CHIP_THOR(bp)) 3896 bnxt_unmap_ptp_regs(bp); 3897 3898 return 0; 3899 } 3900 3901 static int 3902 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3903 struct timespec *timestamp, 3904 uint32_t flags __rte_unused) 3905 { 3906 struct bnxt *bp = dev->data->dev_private; 3907 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3908 uint64_t rx_tstamp_cycles = 0; 3909 uint64_t ns; 3910 3911 if (!ptp) 3912 return 0; 3913 3914 if (BNXT_CHIP_THOR(bp)) 3915 rx_tstamp_cycles = ptp->rx_timestamp; 3916 else 3917 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3918 3919 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3920 *timestamp = rte_ns_to_timespec(ns); 3921 return 0; 3922 } 3923 3924 static int 3925 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3926 struct timespec *timestamp) 3927 { 3928 struct bnxt *bp = dev->data->dev_private; 3929 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3930 uint64_t tx_tstamp_cycles = 0; 3931 uint64_t ns; 3932 int rc = 0; 3933 3934 if (!ptp) 3935 return 0; 3936 3937 if (BNXT_CHIP_THOR(bp)) 3938 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3939 &tx_tstamp_cycles); 3940 else 3941 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3942 3943 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3944 *timestamp = rte_ns_to_timespec(ns); 3945 3946 return rc; 3947 } 3948 3949 static int 3950 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3951 { 3952 struct bnxt *bp = dev->data->dev_private; 3953 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3954 3955 if (!ptp) 3956 return 0; 3957 3958 ptp->tc.nsec += delta; 3959 3960 return 0; 3961 } 3962 3963 static int 3964 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3965 { 3966 struct bnxt *bp = dev->data->dev_private; 3967 int rc; 3968 uint32_t dir_entries; 3969 uint32_t entry_length; 3970 3971 rc = is_bnxt_in_error(bp); 3972 if (rc) 3973 return rc; 3974 3975 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3976 bp->pdev->addr.domain, bp->pdev->addr.bus, 3977 bp->pdev->addr.devid, bp->pdev->addr.function); 3978 3979 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3980 if (rc != 0) 3981 return rc; 3982 3983 return dir_entries * entry_length; 3984 } 3985 3986 static int 3987 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3988 struct rte_dev_eeprom_info *in_eeprom) 3989 { 3990 struct bnxt *bp = dev->data->dev_private; 3991 uint32_t index; 3992 uint32_t offset; 3993 int rc; 3994 3995 rc = is_bnxt_in_error(bp); 3996 if (rc) 3997 return rc; 3998 3999 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 4000 bp->pdev->addr.domain, bp->pdev->addr.bus, 4001 bp->pdev->addr.devid, bp->pdev->addr.function, 4002 in_eeprom->offset, in_eeprom->length); 4003 4004 if (in_eeprom->offset == 0) /* special offset value to get directory */ 4005 return bnxt_get_nvram_directory(bp, in_eeprom->length, 4006 in_eeprom->data); 4007 4008 index = in_eeprom->offset >> 24; 4009 offset = in_eeprom->offset & 0xffffff; 4010 4011 if (index != 0) 4012 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 4013 in_eeprom->length, in_eeprom->data); 4014 4015 return 0; 4016 } 4017 4018 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 4019 { 4020 switch (dir_type) { 4021 case BNX_DIR_TYPE_CHIMP_PATCH: 4022 case BNX_DIR_TYPE_BOOTCODE: 4023 case BNX_DIR_TYPE_BOOTCODE_2: 4024 case BNX_DIR_TYPE_APE_FW: 4025 case BNX_DIR_TYPE_APE_PATCH: 4026 case BNX_DIR_TYPE_KONG_FW: 4027 case BNX_DIR_TYPE_KONG_PATCH: 4028 case BNX_DIR_TYPE_BONO_FW: 4029 case BNX_DIR_TYPE_BONO_PATCH: 4030 /* FALLTHROUGH */ 4031 return true; 4032 } 4033 4034 return false; 4035 } 4036 4037 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 4038 { 4039 switch (dir_type) { 4040 case BNX_DIR_TYPE_AVS: 4041 case BNX_DIR_TYPE_EXP_ROM_MBA: 4042 case BNX_DIR_TYPE_PCIE: 4043 case BNX_DIR_TYPE_TSCF_UCODE: 4044 case BNX_DIR_TYPE_EXT_PHY: 4045 case BNX_DIR_TYPE_CCM: 4046 case BNX_DIR_TYPE_ISCSI_BOOT: 4047 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 4048 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 4049 /* FALLTHROUGH */ 4050 return true; 4051 } 4052 4053 return false; 4054 } 4055 4056 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 4057 { 4058 return bnxt_dir_type_is_ape_bin_format(dir_type) || 4059 bnxt_dir_type_is_other_exec_format(dir_type); 4060 } 4061 4062 static int 4063 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 4064 struct rte_dev_eeprom_info *in_eeprom) 4065 { 4066 struct bnxt *bp = dev->data->dev_private; 4067 uint8_t index, dir_op; 4068 uint16_t type, ext, ordinal, attr; 4069 int rc; 4070 4071 rc = is_bnxt_in_error(bp); 4072 if (rc) 4073 return rc; 4074 4075 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 4076 bp->pdev->addr.domain, bp->pdev->addr.bus, 4077 bp->pdev->addr.devid, bp->pdev->addr.function, 4078 in_eeprom->offset, in_eeprom->length); 4079 4080 if (!BNXT_PF(bp)) { 4081 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 4082 return -EINVAL; 4083 } 4084 4085 type = in_eeprom->magic >> 16; 4086 4087 if (type == 0xffff) { /* special value for directory operations */ 4088 index = in_eeprom->magic & 0xff; 4089 dir_op = in_eeprom->magic >> 8; 4090 if (index == 0) 4091 return -EINVAL; 4092 switch (dir_op) { 4093 case 0x0e: /* erase */ 4094 if (in_eeprom->offset != ~in_eeprom->magic) 4095 return -EINVAL; 4096 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 4097 default: 4098 return -EINVAL; 4099 } 4100 } 4101 4102 /* Create or re-write an NVM item: */ 4103 if (bnxt_dir_type_is_executable(type) == true) 4104 return -EOPNOTSUPP; 4105 ext = in_eeprom->magic & 0xffff; 4106 ordinal = in_eeprom->offset >> 16; 4107 attr = in_eeprom->offset & 0xffff; 4108 4109 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 4110 in_eeprom->data, in_eeprom->length); 4111 } 4112 4113 /* 4114 * Initialization 4115 */ 4116 4117 static const struct eth_dev_ops bnxt_dev_ops = { 4118 .dev_infos_get = bnxt_dev_info_get_op, 4119 .dev_close = bnxt_dev_close_op, 4120 .dev_configure = bnxt_dev_configure_op, 4121 .dev_start = bnxt_dev_start_op, 4122 .dev_stop = bnxt_dev_stop_op, 4123 .dev_set_link_up = bnxt_dev_set_link_up_op, 4124 .dev_set_link_down = bnxt_dev_set_link_down_op, 4125 .stats_get = bnxt_stats_get_op, 4126 .stats_reset = bnxt_stats_reset_op, 4127 .rx_queue_setup = bnxt_rx_queue_setup_op, 4128 .rx_queue_release = bnxt_rx_queue_release_op, 4129 .tx_queue_setup = bnxt_tx_queue_setup_op, 4130 .tx_queue_release = bnxt_tx_queue_release_op, 4131 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4132 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4133 .reta_update = bnxt_reta_update_op, 4134 .reta_query = bnxt_reta_query_op, 4135 .rss_hash_update = bnxt_rss_hash_update_op, 4136 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4137 .link_update = bnxt_link_update_op, 4138 .promiscuous_enable = bnxt_promiscuous_enable_op, 4139 .promiscuous_disable = bnxt_promiscuous_disable_op, 4140 .allmulticast_enable = bnxt_allmulticast_enable_op, 4141 .allmulticast_disable = bnxt_allmulticast_disable_op, 4142 .mac_addr_add = bnxt_mac_addr_add_op, 4143 .mac_addr_remove = bnxt_mac_addr_remove_op, 4144 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4145 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4146 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4147 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4148 .vlan_filter_set = bnxt_vlan_filter_set_op, 4149 .vlan_offload_set = bnxt_vlan_offload_set_op, 4150 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4151 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4152 .mtu_set = bnxt_mtu_set_op, 4153 .mac_addr_set = bnxt_set_default_mac_addr_op, 4154 .xstats_get = bnxt_dev_xstats_get_op, 4155 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4156 .xstats_reset = bnxt_dev_xstats_reset_op, 4157 .fw_version_get = bnxt_fw_version_get, 4158 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4159 .rxq_info_get = bnxt_rxq_info_get_op, 4160 .txq_info_get = bnxt_txq_info_get_op, 4161 .dev_led_on = bnxt_dev_led_on_op, 4162 .dev_led_off = bnxt_dev_led_off_op, 4163 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 4164 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 4165 .rx_queue_count = bnxt_rx_queue_count_op, 4166 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 4167 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 4168 .rx_queue_start = bnxt_rx_queue_start, 4169 .rx_queue_stop = bnxt_rx_queue_stop, 4170 .tx_queue_start = bnxt_tx_queue_start, 4171 .tx_queue_stop = bnxt_tx_queue_stop, 4172 .filter_ctrl = bnxt_filter_ctrl_op, 4173 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4174 .get_eeprom_length = bnxt_get_eeprom_length_op, 4175 .get_eeprom = bnxt_get_eeprom_op, 4176 .set_eeprom = bnxt_set_eeprom_op, 4177 .timesync_enable = bnxt_timesync_enable, 4178 .timesync_disable = bnxt_timesync_disable, 4179 .timesync_read_time = bnxt_timesync_read_time, 4180 .timesync_write_time = bnxt_timesync_write_time, 4181 .timesync_adjust_time = bnxt_timesync_adjust_time, 4182 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4183 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4184 }; 4185 4186 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4187 { 4188 uint32_t offset; 4189 4190 /* Only pre-map the reset GRC registers using window 3 */ 4191 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4192 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4193 4194 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4195 4196 return offset; 4197 } 4198 4199 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4200 { 4201 struct bnxt_error_recovery_info *info = bp->recovery_info; 4202 uint32_t reg_base = 0xffffffff; 4203 int i; 4204 4205 /* Only pre-map the monitoring GRC registers using window 2 */ 4206 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4207 uint32_t reg = info->status_regs[i]; 4208 4209 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4210 continue; 4211 4212 if (reg_base == 0xffffffff) 4213 reg_base = reg & 0xfffff000; 4214 if ((reg & 0xfffff000) != reg_base) 4215 return -ERANGE; 4216 4217 /* Use mask 0xffc as the Lower 2 bits indicates 4218 * address space location 4219 */ 4220 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4221 (reg & 0xffc); 4222 } 4223 4224 if (reg_base == 0xffffffff) 4225 return 0; 4226 4227 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4228 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4229 4230 return 0; 4231 } 4232 4233 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4234 { 4235 struct bnxt_error_recovery_info *info = bp->recovery_info; 4236 uint32_t delay = info->delay_after_reset[index]; 4237 uint32_t val = info->reset_reg_val[index]; 4238 uint32_t reg = info->reset_reg[index]; 4239 uint32_t type, offset; 4240 4241 type = BNXT_FW_STATUS_REG_TYPE(reg); 4242 offset = BNXT_FW_STATUS_REG_OFF(reg); 4243 4244 switch (type) { 4245 case BNXT_FW_STATUS_REG_TYPE_CFG: 4246 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4247 break; 4248 case BNXT_FW_STATUS_REG_TYPE_GRC: 4249 offset = bnxt_map_reset_regs(bp, offset); 4250 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4251 break; 4252 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4253 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4254 break; 4255 } 4256 /* wait on a specific interval of time until core reset is complete */ 4257 if (delay) 4258 rte_delay_ms(delay); 4259 } 4260 4261 static void bnxt_dev_cleanup(struct bnxt *bp) 4262 { 4263 bnxt_set_hwrm_link_config(bp, false); 4264 bp->link_info->link_up = 0; 4265 if (bp->eth_dev->data->dev_started) 4266 bnxt_dev_stop_op(bp->eth_dev); 4267 4268 bnxt_uninit_resources(bp, true); 4269 } 4270 4271 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4272 { 4273 struct rte_eth_dev *dev = bp->eth_dev; 4274 struct rte_vlan_filter_conf *vfc; 4275 int vidx, vbit, rc; 4276 uint16_t vlan_id; 4277 4278 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4279 vfc = &dev->data->vlan_filter_conf; 4280 vidx = vlan_id / 64; 4281 vbit = vlan_id % 64; 4282 4283 /* Each bit corresponds to a VLAN id */ 4284 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4285 rc = bnxt_add_vlan_filter(bp, vlan_id); 4286 if (rc) 4287 return rc; 4288 } 4289 } 4290 4291 return 0; 4292 } 4293 4294 static int bnxt_restore_mac_filters(struct bnxt *bp) 4295 { 4296 struct rte_eth_dev *dev = bp->eth_dev; 4297 struct rte_eth_dev_info dev_info; 4298 struct rte_ether_addr *addr; 4299 uint64_t pool_mask; 4300 uint32_t pool = 0; 4301 uint16_t i; 4302 int rc; 4303 4304 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) 4305 return 0; 4306 4307 rc = bnxt_dev_info_get_op(dev, &dev_info); 4308 if (rc) 4309 return rc; 4310 4311 /* replay MAC address configuration */ 4312 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4313 addr = &dev->data->mac_addrs[i]; 4314 4315 /* skip zero address */ 4316 if (rte_is_zero_ether_addr(addr)) 4317 continue; 4318 4319 pool = 0; 4320 pool_mask = dev->data->mac_pool_sel[i]; 4321 4322 do { 4323 if (pool_mask & 1ULL) { 4324 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4325 if (rc) 4326 return rc; 4327 } 4328 pool_mask >>= 1; 4329 pool++; 4330 } while (pool_mask); 4331 } 4332 4333 return 0; 4334 } 4335 4336 static int bnxt_restore_filters(struct bnxt *bp) 4337 { 4338 struct rte_eth_dev *dev = bp->eth_dev; 4339 int ret = 0; 4340 4341 if (dev->data->all_multicast) { 4342 ret = bnxt_allmulticast_enable_op(dev); 4343 if (ret) 4344 return ret; 4345 } 4346 if (dev->data->promiscuous) { 4347 ret = bnxt_promiscuous_enable_op(dev); 4348 if (ret) 4349 return ret; 4350 } 4351 4352 ret = bnxt_restore_mac_filters(bp); 4353 if (ret) 4354 return ret; 4355 4356 ret = bnxt_restore_vlan_filters(bp); 4357 /* TODO restore other filters as well */ 4358 return ret; 4359 } 4360 4361 static void bnxt_dev_recover(void *arg) 4362 { 4363 struct bnxt *bp = arg; 4364 int timeout = bp->fw_reset_max_msecs; 4365 int rc = 0; 4366 4367 /* Clear Error flag so that device re-init should happen */ 4368 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4369 4370 do { 4371 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); 4372 if (rc == 0) 4373 break; 4374 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4375 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4376 } while (rc && timeout); 4377 4378 if (rc) { 4379 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4380 goto err; 4381 } 4382 4383 rc = bnxt_init_resources(bp, true); 4384 if (rc) { 4385 PMD_DRV_LOG(ERR, 4386 "Failed to initialize resources after reset\n"); 4387 goto err; 4388 } 4389 /* clear reset flag as the device is initialized now */ 4390 bp->flags &= ~BNXT_FLAG_FW_RESET; 4391 4392 rc = bnxt_dev_start_op(bp->eth_dev); 4393 if (rc) { 4394 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4395 goto err_start; 4396 } 4397 4398 rc = bnxt_restore_filters(bp); 4399 if (rc) 4400 goto err_start; 4401 4402 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4403 return; 4404 err_start: 4405 bnxt_dev_stop_op(bp->eth_dev); 4406 err: 4407 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4408 bnxt_uninit_resources(bp, false); 4409 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4410 } 4411 4412 void bnxt_dev_reset_and_resume(void *arg) 4413 { 4414 struct bnxt *bp = arg; 4415 int rc; 4416 4417 bnxt_dev_cleanup(bp); 4418 4419 bnxt_wait_for_device_shutdown(bp); 4420 4421 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 4422 bnxt_dev_recover, (void *)bp); 4423 if (rc) 4424 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4425 } 4426 4427 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4428 { 4429 struct bnxt_error_recovery_info *info = bp->recovery_info; 4430 uint32_t reg = info->status_regs[index]; 4431 uint32_t type, offset, val = 0; 4432 4433 type = BNXT_FW_STATUS_REG_TYPE(reg); 4434 offset = BNXT_FW_STATUS_REG_OFF(reg); 4435 4436 switch (type) { 4437 case BNXT_FW_STATUS_REG_TYPE_CFG: 4438 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4439 break; 4440 case BNXT_FW_STATUS_REG_TYPE_GRC: 4441 offset = info->mapped_status_regs[index]; 4442 /* FALLTHROUGH */ 4443 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4444 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4445 offset)); 4446 break; 4447 } 4448 4449 return val; 4450 } 4451 4452 static int bnxt_fw_reset_all(struct bnxt *bp) 4453 { 4454 struct bnxt_error_recovery_info *info = bp->recovery_info; 4455 uint32_t i; 4456 int rc = 0; 4457 4458 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4459 /* Reset through master function driver */ 4460 for (i = 0; i < info->reg_array_cnt; i++) 4461 bnxt_write_fw_reset_reg(bp, i); 4462 /* Wait for time specified by FW after triggering reset */ 4463 rte_delay_ms(info->master_func_wait_period_after_reset); 4464 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4465 /* Reset with the help of Kong processor */ 4466 rc = bnxt_hwrm_fw_reset(bp); 4467 if (rc) 4468 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4469 } 4470 4471 return rc; 4472 } 4473 4474 static void bnxt_fw_reset_cb(void *arg) 4475 { 4476 struct bnxt *bp = arg; 4477 struct bnxt_error_recovery_info *info = bp->recovery_info; 4478 int rc = 0; 4479 4480 /* Only Master function can do FW reset */ 4481 if (bnxt_is_master_func(bp) && 4482 bnxt_is_recovery_enabled(bp)) { 4483 rc = bnxt_fw_reset_all(bp); 4484 if (rc) { 4485 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4486 return; 4487 } 4488 } 4489 4490 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4491 * EXCEPTION_FATAL_ASYNC event to all the functions 4492 * (including MASTER FUNC). After receiving this Async, all the active 4493 * drivers should treat this case as FW initiated recovery 4494 */ 4495 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4496 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4497 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4498 4499 /* To recover from error */ 4500 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4501 (void *)bp); 4502 } 4503 } 4504 4505 /* Driver should poll FW heartbeat, reset_counter with the frequency 4506 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4507 * When the driver detects heartbeat stop or change in reset_counter, 4508 * it has to trigger a reset to recover from the error condition. 4509 * A “master PF” is the function who will have the privilege to 4510 * initiate the chimp reset. The master PF will be elected by the 4511 * firmware and will be notified through async message. 4512 */ 4513 static void bnxt_check_fw_health(void *arg) 4514 { 4515 struct bnxt *bp = arg; 4516 struct bnxt_error_recovery_info *info = bp->recovery_info; 4517 uint32_t val = 0, wait_msec; 4518 4519 if (!info || !bnxt_is_recovery_enabled(bp) || 4520 is_bnxt_in_error(bp)) 4521 return; 4522 4523 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4524 if (val == info->last_heart_beat) 4525 goto reset; 4526 4527 info->last_heart_beat = val; 4528 4529 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4530 if (val != info->last_reset_counter) 4531 goto reset; 4532 4533 info->last_reset_counter = val; 4534 4535 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4536 bnxt_check_fw_health, (void *)bp); 4537 4538 return; 4539 reset: 4540 /* Stop DMA to/from device */ 4541 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4542 bp->flags |= BNXT_FLAG_FW_RESET; 4543 4544 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4545 4546 if (bnxt_is_master_func(bp)) 4547 wait_msec = info->master_func_wait_period; 4548 else 4549 wait_msec = info->normal_func_wait_period; 4550 4551 rte_eal_alarm_set(US_PER_MS * wait_msec, 4552 bnxt_fw_reset_cb, (void *)bp); 4553 } 4554 4555 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4556 { 4557 uint32_t polling_freq; 4558 4559 if (!bnxt_is_recovery_enabled(bp)) 4560 return; 4561 4562 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4563 return; 4564 4565 polling_freq = bp->recovery_info->driver_polling_freq; 4566 4567 rte_eal_alarm_set(US_PER_MS * polling_freq, 4568 bnxt_check_fw_health, (void *)bp); 4569 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4570 } 4571 4572 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4573 { 4574 if (!bnxt_is_recovery_enabled(bp)) 4575 return; 4576 4577 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4578 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4579 } 4580 4581 static bool bnxt_vf_pciid(uint16_t device_id) 4582 { 4583 switch (device_id) { 4584 case BROADCOM_DEV_ID_57304_VF: 4585 case BROADCOM_DEV_ID_57406_VF: 4586 case BROADCOM_DEV_ID_5731X_VF: 4587 case BROADCOM_DEV_ID_5741X_VF: 4588 case BROADCOM_DEV_ID_57414_VF: 4589 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4590 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4591 case BROADCOM_DEV_ID_58802_VF: 4592 case BROADCOM_DEV_ID_57500_VF1: 4593 case BROADCOM_DEV_ID_57500_VF2: 4594 /* FALLTHROUGH */ 4595 return true; 4596 default: 4597 return false; 4598 } 4599 } 4600 4601 static bool bnxt_thor_device(uint16_t device_id) 4602 { 4603 switch (device_id) { 4604 case BROADCOM_DEV_ID_57508: 4605 case BROADCOM_DEV_ID_57504: 4606 case BROADCOM_DEV_ID_57502: 4607 case BROADCOM_DEV_ID_57508_MF1: 4608 case BROADCOM_DEV_ID_57504_MF1: 4609 case BROADCOM_DEV_ID_57502_MF1: 4610 case BROADCOM_DEV_ID_57508_MF2: 4611 case BROADCOM_DEV_ID_57504_MF2: 4612 case BROADCOM_DEV_ID_57502_MF2: 4613 case BROADCOM_DEV_ID_57500_VF1: 4614 case BROADCOM_DEV_ID_57500_VF2: 4615 /* FALLTHROUGH */ 4616 return true; 4617 default: 4618 return false; 4619 } 4620 } 4621 4622 bool bnxt_stratus_device(struct bnxt *bp) 4623 { 4624 uint16_t device_id = bp->pdev->id.device_id; 4625 4626 switch (device_id) { 4627 case BROADCOM_DEV_ID_STRATUS_NIC: 4628 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4629 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4630 /* FALLTHROUGH */ 4631 return true; 4632 default: 4633 return false; 4634 } 4635 } 4636 4637 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4638 { 4639 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4640 struct bnxt *bp = eth_dev->data->dev_private; 4641 4642 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4643 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4644 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4645 if (!bp->bar0 || !bp->doorbell_base) { 4646 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4647 return -ENODEV; 4648 } 4649 4650 bp->eth_dev = eth_dev; 4651 bp->pdev = pci_dev; 4652 4653 return 0; 4654 } 4655 4656 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4657 struct bnxt_ctx_pg_info *ctx_pg, 4658 uint32_t mem_size, 4659 const char *suffix, 4660 uint16_t idx) 4661 { 4662 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4663 const struct rte_memzone *mz = NULL; 4664 char mz_name[RTE_MEMZONE_NAMESIZE]; 4665 rte_iova_t mz_phys_addr; 4666 uint64_t valid_bits = 0; 4667 uint32_t sz; 4668 int i; 4669 4670 if (!mem_size) 4671 return 0; 4672 4673 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4674 BNXT_PAGE_SIZE; 4675 rmem->page_size = BNXT_PAGE_SIZE; 4676 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4677 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4678 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4679 4680 valid_bits = PTU_PTE_VALID; 4681 4682 if (rmem->nr_pages > 1) { 4683 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4684 "bnxt_ctx_pg_tbl%s_%x_%d", 4685 suffix, idx, bp->eth_dev->data->port_id); 4686 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4687 mz = rte_memzone_lookup(mz_name); 4688 if (!mz) { 4689 mz = rte_memzone_reserve_aligned(mz_name, 4690 rmem->nr_pages * 8, 4691 SOCKET_ID_ANY, 4692 RTE_MEMZONE_2MB | 4693 RTE_MEMZONE_SIZE_HINT_ONLY | 4694 RTE_MEMZONE_IOVA_CONTIG, 4695 BNXT_PAGE_SIZE); 4696 if (mz == NULL) 4697 return -ENOMEM; 4698 } 4699 4700 memset(mz->addr, 0, mz->len); 4701 mz_phys_addr = mz->iova; 4702 4703 rmem->pg_tbl = mz->addr; 4704 rmem->pg_tbl_map = mz_phys_addr; 4705 rmem->pg_tbl_mz = mz; 4706 } 4707 4708 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4709 suffix, idx, bp->eth_dev->data->port_id); 4710 mz = rte_memzone_lookup(mz_name); 4711 if (!mz) { 4712 mz = rte_memzone_reserve_aligned(mz_name, 4713 mem_size, 4714 SOCKET_ID_ANY, 4715 RTE_MEMZONE_1GB | 4716 RTE_MEMZONE_SIZE_HINT_ONLY | 4717 RTE_MEMZONE_IOVA_CONTIG, 4718 BNXT_PAGE_SIZE); 4719 if (mz == NULL) 4720 return -ENOMEM; 4721 } 4722 4723 memset(mz->addr, 0, mz->len); 4724 mz_phys_addr = mz->iova; 4725 4726 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4727 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4728 rmem->dma_arr[i] = mz_phys_addr + sz; 4729 4730 if (rmem->nr_pages > 1) { 4731 if (i == rmem->nr_pages - 2 && 4732 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4733 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4734 else if (i == rmem->nr_pages - 1 && 4735 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4736 valid_bits |= PTU_PTE_LAST; 4737 4738 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4739 valid_bits); 4740 } 4741 } 4742 4743 rmem->mz = mz; 4744 if (rmem->vmem_size) 4745 rmem->vmem = (void **)mz->addr; 4746 rmem->dma_arr[0] = mz_phys_addr; 4747 return 0; 4748 } 4749 4750 static void bnxt_free_ctx_mem(struct bnxt *bp) 4751 { 4752 int i; 4753 4754 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4755 return; 4756 4757 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4758 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4759 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4760 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4761 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4762 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4763 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4764 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4765 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4766 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4767 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4768 4769 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4770 if (bp->ctx->tqm_mem[i]) 4771 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4772 } 4773 4774 rte_free(bp->ctx); 4775 bp->ctx = NULL; 4776 } 4777 4778 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4779 4780 #define min_t(type, x, y) ({ \ 4781 type __min1 = (x); \ 4782 type __min2 = (y); \ 4783 __min1 < __min2 ? __min1 : __min2; }) 4784 4785 #define max_t(type, x, y) ({ \ 4786 type __max1 = (x); \ 4787 type __max2 = (y); \ 4788 __max1 > __max2 ? __max1 : __max2; }) 4789 4790 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4791 4792 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4793 { 4794 struct bnxt_ctx_pg_info *ctx_pg; 4795 struct bnxt_ctx_mem_info *ctx; 4796 uint32_t mem_size, ena, entries; 4797 uint32_t entries_sp, min; 4798 int i, rc; 4799 4800 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4801 if (rc) { 4802 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4803 return rc; 4804 } 4805 ctx = bp->ctx; 4806 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4807 return 0; 4808 4809 ctx_pg = &ctx->qp_mem; 4810 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4811 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4812 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4813 if (rc) 4814 return rc; 4815 4816 ctx_pg = &ctx->srq_mem; 4817 ctx_pg->entries = ctx->srq_max_l2_entries; 4818 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4819 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4820 if (rc) 4821 return rc; 4822 4823 ctx_pg = &ctx->cq_mem; 4824 ctx_pg->entries = ctx->cq_max_l2_entries; 4825 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4826 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4827 if (rc) 4828 return rc; 4829 4830 ctx_pg = &ctx->vnic_mem; 4831 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4832 ctx->vnic_max_ring_table_entries; 4833 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4834 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4835 if (rc) 4836 return rc; 4837 4838 ctx_pg = &ctx->stat_mem; 4839 ctx_pg->entries = ctx->stat_max_entries; 4840 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4841 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4842 if (rc) 4843 return rc; 4844 4845 min = ctx->tqm_min_entries_per_ring; 4846 4847 entries_sp = ctx->qp_max_l2_entries + 4848 ctx->vnic_max_vnic_entries + 4849 2 * ctx->qp_min_qp1_entries + min; 4850 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4851 4852 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4853 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4854 entries = clamp_t(uint32_t, entries, min, 4855 ctx->tqm_max_entries_per_ring); 4856 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4857 ctx_pg = ctx->tqm_mem[i]; 4858 ctx_pg->entries = i ? entries : entries_sp; 4859 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4860 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4861 if (rc) 4862 return rc; 4863 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4864 } 4865 4866 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4867 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4868 if (rc) 4869 PMD_DRV_LOG(ERR, 4870 "Failed to configure context mem: rc = %d\n", rc); 4871 else 4872 ctx->flags |= BNXT_CTX_FLAG_INITED; 4873 4874 return rc; 4875 } 4876 4877 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4878 { 4879 struct rte_pci_device *pci_dev = bp->pdev; 4880 char mz_name[RTE_MEMZONE_NAMESIZE]; 4881 const struct rte_memzone *mz = NULL; 4882 uint32_t total_alloc_len; 4883 rte_iova_t mz_phys_addr; 4884 4885 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4886 return 0; 4887 4888 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4889 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4890 pci_dev->addr.bus, pci_dev->addr.devid, 4891 pci_dev->addr.function, "rx_port_stats"); 4892 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4893 mz = rte_memzone_lookup(mz_name); 4894 total_alloc_len = 4895 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4896 sizeof(struct rx_port_stats_ext) + 512); 4897 if (!mz) { 4898 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4899 SOCKET_ID_ANY, 4900 RTE_MEMZONE_2MB | 4901 RTE_MEMZONE_SIZE_HINT_ONLY | 4902 RTE_MEMZONE_IOVA_CONTIG); 4903 if (mz == NULL) 4904 return -ENOMEM; 4905 } 4906 memset(mz->addr, 0, mz->len); 4907 mz_phys_addr = mz->iova; 4908 4909 bp->rx_mem_zone = (const void *)mz; 4910 bp->hw_rx_port_stats = mz->addr; 4911 bp->hw_rx_port_stats_map = mz_phys_addr; 4912 4913 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4914 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4915 pci_dev->addr.bus, pci_dev->addr.devid, 4916 pci_dev->addr.function, "tx_port_stats"); 4917 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4918 mz = rte_memzone_lookup(mz_name); 4919 total_alloc_len = 4920 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4921 sizeof(struct tx_port_stats_ext) + 512); 4922 if (!mz) { 4923 mz = rte_memzone_reserve(mz_name, 4924 total_alloc_len, 4925 SOCKET_ID_ANY, 4926 RTE_MEMZONE_2MB | 4927 RTE_MEMZONE_SIZE_HINT_ONLY | 4928 RTE_MEMZONE_IOVA_CONTIG); 4929 if (mz == NULL) 4930 return -ENOMEM; 4931 } 4932 memset(mz->addr, 0, mz->len); 4933 mz_phys_addr = mz->iova; 4934 4935 bp->tx_mem_zone = (const void *)mz; 4936 bp->hw_tx_port_stats = mz->addr; 4937 bp->hw_tx_port_stats_map = mz_phys_addr; 4938 bp->flags |= BNXT_FLAG_PORT_STATS; 4939 4940 /* Display extended statistics if FW supports it */ 4941 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4942 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4943 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4944 return 0; 4945 4946 bp->hw_rx_port_stats_ext = (void *) 4947 ((uint8_t *)bp->hw_rx_port_stats + 4948 sizeof(struct rx_port_stats)); 4949 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4950 sizeof(struct rx_port_stats); 4951 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4952 4953 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4954 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4955 bp->hw_tx_port_stats_ext = (void *) 4956 ((uint8_t *)bp->hw_tx_port_stats + 4957 sizeof(struct tx_port_stats)); 4958 bp->hw_tx_port_stats_ext_map = 4959 bp->hw_tx_port_stats_map + 4960 sizeof(struct tx_port_stats); 4961 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4962 } 4963 4964 return 0; 4965 } 4966 4967 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4968 { 4969 struct bnxt *bp = eth_dev->data->dev_private; 4970 int rc = 0; 4971 4972 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4973 RTE_ETHER_ADDR_LEN * 4974 bp->max_l2_ctx, 4975 0); 4976 if (eth_dev->data->mac_addrs == NULL) { 4977 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4978 return -ENOMEM; 4979 } 4980 4981 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4982 if (BNXT_PF(bp)) 4983 return -EINVAL; 4984 4985 /* Generate a random MAC address, if none was assigned by PF */ 4986 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4987 bnxt_eth_hw_addr_random(bp->mac_addr); 4988 PMD_DRV_LOG(INFO, 4989 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4990 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4991 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4992 4993 rc = bnxt_hwrm_set_mac(bp); 4994 if (rc) 4995 return rc; 4996 } 4997 4998 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4999 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5000 5001 return rc; 5002 } 5003 5004 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5005 { 5006 int rc = 0; 5007 5008 /* MAC is already configured in FW */ 5009 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5010 return 0; 5011 5012 /* Restore the old MAC configured */ 5013 rc = bnxt_hwrm_set_mac(bp); 5014 if (rc) 5015 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5016 5017 return rc; 5018 } 5019 5020 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5021 { 5022 if (!BNXT_PF(bp)) 5023 return; 5024 5025 #define ALLOW_FUNC(x) \ 5026 { \ 5027 uint32_t arg = (x); \ 5028 bp->pf->vf_req_fwd[((arg) >> 5)] &= \ 5029 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 5030 } 5031 5032 /* Forward all requests if firmware is new enough */ 5033 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 5034 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 5035 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 5036 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd)); 5037 } else { 5038 PMD_DRV_LOG(WARNING, 5039 "Firmware too old for VF mailbox functionality\n"); 5040 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5041 } 5042 5043 /* 5044 * The following are used for driver cleanup. If we disallow these, 5045 * VF drivers can't clean up cleanly. 5046 */ 5047 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 5048 ALLOW_FUNC(HWRM_VNIC_FREE); 5049 ALLOW_FUNC(HWRM_RING_FREE); 5050 ALLOW_FUNC(HWRM_RING_GRP_FREE); 5051 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 5052 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 5053 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 5054 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 5055 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 5056 } 5057 5058 uint16_t 5059 bnxt_get_svif(uint16_t port_id, bool func_svif) 5060 { 5061 struct rte_eth_dev *eth_dev; 5062 struct bnxt *bp; 5063 5064 eth_dev = &rte_eth_devices[port_id]; 5065 bp = eth_dev->data->dev_private; 5066 5067 return func_svif ? bp->func_svif : bp->port_svif; 5068 } 5069 5070 uint16_t 5071 bnxt_get_vnic_id(uint16_t port) 5072 { 5073 struct rte_eth_dev *eth_dev; 5074 struct bnxt_vnic_info *vnic; 5075 struct bnxt *bp; 5076 5077 eth_dev = &rte_eth_devices[port]; 5078 bp = eth_dev->data->dev_private; 5079 5080 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5081 5082 return vnic->fw_vnic_id; 5083 } 5084 5085 uint16_t 5086 bnxt_get_fw_func_id(uint16_t port) 5087 { 5088 struct rte_eth_dev *eth_dev; 5089 struct bnxt *bp; 5090 5091 eth_dev = &rte_eth_devices[port]; 5092 bp = eth_dev->data->dev_private; 5093 5094 return bp->fw_fid; 5095 } 5096 5097 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5098 { 5099 struct bnxt_error_recovery_info *info = bp->recovery_info; 5100 5101 if (info) { 5102 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5103 memset(info, 0, sizeof(*info)); 5104 return; 5105 } 5106 5107 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5108 return; 5109 5110 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5111 sizeof(*info), 0); 5112 if (!info) 5113 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5114 5115 bp->recovery_info = info; 5116 } 5117 5118 static void bnxt_check_fw_status(struct bnxt *bp) 5119 { 5120 uint32_t fw_status; 5121 5122 if (!(bp->recovery_info && 5123 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5124 return; 5125 5126 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5127 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5128 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5129 fw_status); 5130 } 5131 5132 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5133 { 5134 struct bnxt_error_recovery_info *info = bp->recovery_info; 5135 uint32_t status_loc; 5136 uint32_t sig_ver; 5137 5138 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5139 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5140 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5141 BNXT_GRCP_WINDOW_2_BASE + 5142 offsetof(struct hcomm_status, 5143 sig_ver))); 5144 /* If the signature is absent, then FW does not support this feature */ 5145 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5146 HCOMM_STATUS_SIGNATURE_VAL) 5147 return 0; 5148 5149 if (!info) { 5150 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5151 sizeof(*info), 0); 5152 if (!info) 5153 return -ENOMEM; 5154 bp->recovery_info = info; 5155 } else { 5156 memset(info, 0, sizeof(*info)); 5157 } 5158 5159 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5160 BNXT_GRCP_WINDOW_2_BASE + 5161 offsetof(struct hcomm_status, 5162 fw_status_loc))); 5163 5164 /* Only pre-map the FW health status GRC register */ 5165 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5166 return 0; 5167 5168 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5169 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5170 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5171 5172 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5173 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5174 5175 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5176 5177 return 0; 5178 } 5179 5180 static int bnxt_init_fw(struct bnxt *bp) 5181 { 5182 uint16_t mtu; 5183 int rc = 0; 5184 5185 bp->fw_cap = 0; 5186 5187 rc = bnxt_map_hcomm_fw_status_reg(bp); 5188 if (rc) 5189 return rc; 5190 5191 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5192 if (rc) { 5193 bnxt_check_fw_status(bp); 5194 return rc; 5195 } 5196 5197 rc = bnxt_hwrm_func_reset(bp); 5198 if (rc) 5199 return -EIO; 5200 5201 rc = bnxt_hwrm_vnic_qcaps(bp); 5202 if (rc) 5203 return rc; 5204 5205 rc = bnxt_hwrm_queue_qportcfg(bp); 5206 if (rc) 5207 return rc; 5208 5209 /* Get the MAX capabilities for this function. 5210 * This function also allocates context memory for TQM rings and 5211 * informs the firmware about this allocated backing store memory. 5212 */ 5213 rc = bnxt_hwrm_func_qcaps(bp); 5214 if (rc) 5215 return rc; 5216 5217 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5218 if (rc) 5219 return rc; 5220 5221 bnxt_hwrm_port_mac_qcfg(bp); 5222 5223 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5224 if (rc) 5225 return rc; 5226 5227 bnxt_alloc_error_recovery_info(bp); 5228 /* Get the adapter error recovery support info */ 5229 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5230 if (rc) 5231 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5232 5233 bnxt_hwrm_port_led_qcaps(bp); 5234 5235 return 0; 5236 } 5237 5238 static int 5239 bnxt_init_locks(struct bnxt *bp) 5240 { 5241 int err; 5242 5243 err = pthread_mutex_init(&bp->flow_lock, NULL); 5244 if (err) { 5245 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5246 return err; 5247 } 5248 5249 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5250 if (err) 5251 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5252 return err; 5253 } 5254 5255 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5256 { 5257 int rc; 5258 5259 rc = bnxt_init_fw(bp); 5260 if (rc) 5261 return rc; 5262 5263 if (!reconfig_dev) { 5264 rc = bnxt_setup_mac_addr(bp->eth_dev); 5265 if (rc) 5266 return rc; 5267 } else { 5268 rc = bnxt_restore_dflt_mac(bp); 5269 if (rc) 5270 return rc; 5271 } 5272 5273 bnxt_config_vf_req_fwd(bp); 5274 5275 rc = bnxt_hwrm_func_driver_register(bp); 5276 if (rc) { 5277 PMD_DRV_LOG(ERR, "Failed to register driver"); 5278 return -EBUSY; 5279 } 5280 5281 if (BNXT_PF(bp)) { 5282 if (bp->pdev->max_vfs) { 5283 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5284 if (rc) { 5285 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5286 return rc; 5287 } 5288 } else { 5289 rc = bnxt_hwrm_allocate_pf_only(bp); 5290 if (rc) { 5291 PMD_DRV_LOG(ERR, 5292 "Failed to allocate PF resources"); 5293 return rc; 5294 } 5295 } 5296 } 5297 5298 rc = bnxt_alloc_mem(bp, reconfig_dev); 5299 if (rc) 5300 return rc; 5301 5302 rc = bnxt_setup_int(bp); 5303 if (rc) 5304 return rc; 5305 5306 rc = bnxt_request_int(bp); 5307 if (rc) 5308 return rc; 5309 5310 rc = bnxt_init_ctx_mem(bp); 5311 if (rc) { 5312 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5313 return rc; 5314 } 5315 5316 rc = bnxt_init_locks(bp); 5317 if (rc) 5318 return rc; 5319 5320 return 0; 5321 } 5322 5323 static int 5324 bnxt_parse_devarg_truflow(__rte_unused const char *key, 5325 const char *value, void *opaque_arg) 5326 { 5327 struct bnxt *bp = opaque_arg; 5328 unsigned long truflow; 5329 char *end = NULL; 5330 5331 if (!value || !opaque_arg) { 5332 PMD_DRV_LOG(ERR, 5333 "Invalid parameter passed to truflow devargs.\n"); 5334 return -EINVAL; 5335 } 5336 5337 truflow = strtoul(value, &end, 10); 5338 if (end == NULL || *end != '\0' || 5339 (truflow == ULONG_MAX && errno == ERANGE)) { 5340 PMD_DRV_LOG(ERR, 5341 "Invalid parameter passed to truflow devargs.\n"); 5342 return -EINVAL; 5343 } 5344 5345 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 5346 PMD_DRV_LOG(ERR, 5347 "Invalid value passed to truflow devargs.\n"); 5348 return -EINVAL; 5349 } 5350 5351 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 5352 if (BNXT_TRUFLOW_EN(bp)) 5353 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 5354 5355 return 0; 5356 } 5357 5358 static int 5359 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5360 const char *value, void *opaque_arg) 5361 { 5362 struct bnxt *bp = opaque_arg; 5363 unsigned long flow_xstat; 5364 char *end = NULL; 5365 5366 if (!value || !opaque_arg) { 5367 PMD_DRV_LOG(ERR, 5368 "Invalid parameter passed to flow_xstat devarg.\n"); 5369 return -EINVAL; 5370 } 5371 5372 flow_xstat = strtoul(value, &end, 10); 5373 if (end == NULL || *end != '\0' || 5374 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5375 PMD_DRV_LOG(ERR, 5376 "Invalid parameter passed to flow_xstat devarg.\n"); 5377 return -EINVAL; 5378 } 5379 5380 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5381 PMD_DRV_LOG(ERR, 5382 "Invalid value passed to flow_xstat devarg.\n"); 5383 return -EINVAL; 5384 } 5385 5386 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5387 if (BNXT_FLOW_XSTATS_EN(bp)) 5388 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5389 5390 return 0; 5391 } 5392 5393 static void 5394 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5395 { 5396 struct rte_kvargs *kvlist; 5397 5398 if (devargs == NULL) 5399 return; 5400 5401 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5402 if (kvlist == NULL) 5403 return; 5404 5405 /* 5406 * Handler for "truflow" devarg. 5407 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1” 5408 */ 5409 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5410 bnxt_parse_devarg_truflow, bp); 5411 5412 /* 5413 * Handler for "flow_xstat" devarg. 5414 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1” 5415 */ 5416 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5417 bnxt_parse_devarg_flow_xstat, bp); 5418 5419 rte_kvargs_free(kvlist); 5420 } 5421 5422 static int 5423 bnxt_dev_init(struct rte_eth_dev *eth_dev) 5424 { 5425 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5426 static int version_printed; 5427 struct bnxt *bp; 5428 int rc; 5429 5430 if (version_printed++ == 0) 5431 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5432 5433 eth_dev->dev_ops = &bnxt_dev_ops; 5434 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5435 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5436 5437 /* 5438 * For secondary processes, we don't initialise any further 5439 * as primary has already done this work. 5440 */ 5441 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5442 return 0; 5443 5444 rte_eth_copy_pci_info(eth_dev, pci_dev); 5445 5446 bp = eth_dev->data->dev_private; 5447 5448 /* Parse dev arguments passed on when starting the DPDK application. */ 5449 bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5450 5451 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5452 5453 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5454 bp->flags |= BNXT_FLAG_VF; 5455 5456 if (bnxt_thor_device(pci_dev->id.device_id)) 5457 bp->flags |= BNXT_FLAG_THOR_CHIP; 5458 5459 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5460 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5461 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5462 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5463 bp->flags |= BNXT_FLAG_STINGRAY; 5464 5465 rc = bnxt_init_board(eth_dev); 5466 if (rc) { 5467 PMD_DRV_LOG(ERR, 5468 "Failed to initialize board rc: %x\n", rc); 5469 return rc; 5470 } 5471 5472 rc = bnxt_alloc_pf_info(bp); 5473 if (rc) 5474 goto error_free; 5475 5476 rc = bnxt_alloc_link_info(bp); 5477 if (rc) 5478 goto error_free; 5479 5480 rc = bnxt_alloc_hwrm_resources(bp); 5481 if (rc) { 5482 PMD_DRV_LOG(ERR, 5483 "Failed to allocate hwrm resource rc: %x\n", rc); 5484 goto error_free; 5485 } 5486 rc = bnxt_alloc_leds_info(bp); 5487 if (rc) 5488 goto error_free; 5489 5490 rc = bnxt_alloc_cos_queues(bp); 5491 if (rc) 5492 goto error_free; 5493 5494 rc = bnxt_init_resources(bp, false); 5495 if (rc) 5496 goto error_free; 5497 5498 rc = bnxt_alloc_stats_mem(bp); 5499 if (rc) 5500 goto error_free; 5501 5502 /* Pass the information to the rte_eth_dev_close() that it should also 5503 * release the private port resources. 5504 */ 5505 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 5506 5507 PMD_DRV_LOG(INFO, 5508 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5509 pci_dev->mem_resource[0].phys_addr, 5510 pci_dev->mem_resource[0].addr); 5511 5512 return 0; 5513 5514 error_free: 5515 bnxt_dev_uninit(eth_dev); 5516 return rc; 5517 } 5518 5519 5520 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5521 { 5522 if (!ctx) 5523 return; 5524 5525 if (ctx->va) 5526 rte_free(ctx->va); 5527 5528 ctx->va = NULL; 5529 ctx->dma = RTE_BAD_IOVA; 5530 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5531 } 5532 5533 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5534 { 5535 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5536 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5537 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5538 bp->flow_stat->max_fc, 5539 false); 5540 5541 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5542 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5543 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5544 bp->flow_stat->max_fc, 5545 false); 5546 5547 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5548 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5549 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5550 5551 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5552 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5553 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5554 5555 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5556 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5557 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5558 5559 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5560 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5561 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5562 } 5563 5564 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5565 { 5566 bnxt_unregister_fc_ctx_mem(bp); 5567 5568 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5569 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5570 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5571 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5572 } 5573 5574 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5575 { 5576 if (BNXT_FLOW_XSTATS_EN(bp)) 5577 bnxt_uninit_fc_ctx_mem(bp); 5578 } 5579 5580 static void 5581 bnxt_free_error_recovery_info(struct bnxt *bp) 5582 { 5583 rte_free(bp->recovery_info); 5584 bp->recovery_info = NULL; 5585 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5586 } 5587 5588 static void 5589 bnxt_uninit_locks(struct bnxt *bp) 5590 { 5591 pthread_mutex_destroy(&bp->flow_lock); 5592 pthread_mutex_destroy(&bp->def_cp_lock); 5593 } 5594 5595 static int 5596 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5597 { 5598 int rc; 5599 5600 bnxt_free_int(bp); 5601 bnxt_free_mem(bp, reconfig_dev); 5602 bnxt_hwrm_func_buf_unrgtr(bp); 5603 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5604 bp->flags &= ~BNXT_FLAG_REGISTERED; 5605 bnxt_free_ctx_mem(bp); 5606 if (!reconfig_dev) { 5607 bnxt_free_hwrm_resources(bp); 5608 bnxt_free_error_recovery_info(bp); 5609 } 5610 5611 bnxt_uninit_ctx_mem(bp); 5612 5613 bnxt_uninit_locks(bp); 5614 bnxt_free_flow_stats_info(bp); 5615 rte_free(bp->ptp_cfg); 5616 bp->ptp_cfg = NULL; 5617 return rc; 5618 } 5619 5620 static int 5621 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5622 { 5623 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5624 return -EPERM; 5625 5626 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5627 5628 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5629 bnxt_dev_close_op(eth_dev); 5630 5631 return 0; 5632 } 5633 5634 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5635 struct rte_pci_device *pci_dev) 5636 { 5637 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 5638 bnxt_dev_init); 5639 } 5640 5641 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 5642 { 5643 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 5644 return rte_eth_dev_pci_generic_remove(pci_dev, 5645 bnxt_dev_uninit); 5646 else 5647 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 5648 } 5649 5650 static struct rte_pci_driver bnxt_rte_pmd = { 5651 .id_table = bnxt_pci_id_map, 5652 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 5653 .probe = bnxt_pci_probe, 5654 .remove = bnxt_pci_remove, 5655 }; 5656 5657 static bool 5658 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5659 { 5660 if (strcmp(dev->device->driver->name, drv->driver.name)) 5661 return false; 5662 5663 return true; 5664 } 5665 5666 bool is_bnxt_supported(struct rte_eth_dev *dev) 5667 { 5668 return is_device_supported(dev, &bnxt_rte_pmd); 5669 } 5670 5671 RTE_INIT(bnxt_init_log) 5672 { 5673 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 5674 if (bnxt_logtype_driver >= 0) 5675 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 5676 } 5677 5678 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 5679 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 5680 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 5681