1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 16 #include "bnxt.h" 17 #include "bnxt_cpr.h" 18 #include "bnxt_filter.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_irq.h" 21 #include "bnxt_ring.h" 22 #include "bnxt_rxq.h" 23 #include "bnxt_rxr.h" 24 #include "bnxt_stats.h" 25 #include "bnxt_txq.h" 26 #include "bnxt_txr.h" 27 #include "bnxt_vnic.h" 28 #include "hsi_struct_def_dpdk.h" 29 #include "bnxt_nvm_defs.h" 30 #include "bnxt_util.h" 31 32 #define DRV_MODULE_NAME "bnxt" 33 static const char bnxt_version[] = 34 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 35 int bnxt_logtype_driver; 36 37 #define PCI_VENDOR_ID_BROADCOM 0x14E4 38 39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 42 #define BROADCOM_DEV_ID_57414_VF 0x16c1 43 #define BROADCOM_DEV_ID_57301 0x16c8 44 #define BROADCOM_DEV_ID_57302 0x16c9 45 #define BROADCOM_DEV_ID_57304_PF 0x16ca 46 #define BROADCOM_DEV_ID_57304_VF 0x16cb 47 #define BROADCOM_DEV_ID_57417_MF 0x16cc 48 #define BROADCOM_DEV_ID_NS2 0x16cd 49 #define BROADCOM_DEV_ID_57311 0x16ce 50 #define BROADCOM_DEV_ID_57312 0x16cf 51 #define BROADCOM_DEV_ID_57402 0x16d0 52 #define BROADCOM_DEV_ID_57404 0x16d1 53 #define BROADCOM_DEV_ID_57406_PF 0x16d2 54 #define BROADCOM_DEV_ID_57406_VF 0x16d3 55 #define BROADCOM_DEV_ID_57402_MF 0x16d4 56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 57 #define BROADCOM_DEV_ID_57412 0x16d6 58 #define BROADCOM_DEV_ID_57414 0x16d7 59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 62 #define BROADCOM_DEV_ID_57412_MF 0x16de 63 #define BROADCOM_DEV_ID_57314 0x16df 64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 69 #define BROADCOM_DEV_ID_57404_MF 0x16e7 70 #define BROADCOM_DEV_ID_57406_MF 0x16e8 71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 72 #define BROADCOM_DEV_ID_57407_MF 0x16ea 73 #define BROADCOM_DEV_ID_57414_MF 0x16ec 74 #define BROADCOM_DEV_ID_57416_MF 0x16ee 75 #define BROADCOM_DEV_ID_57508 0x1750 76 #define BROADCOM_DEV_ID_57504 0x1751 77 #define BROADCOM_DEV_ID_57502 0x1752 78 #define BROADCOM_DEV_ID_57500_VF1 0x1806 79 #define BROADCOM_DEV_ID_57500_VF2 0x1807 80 #define BROADCOM_DEV_ID_58802 0xd802 81 #define BROADCOM_DEV_ID_58804 0xd804 82 #define BROADCOM_DEV_ID_58808 0x16f0 83 #define BROADCOM_DEV_ID_58802_VF 0xd800 84 85 static const struct rte_pci_id bnxt_pci_id_map[] = { 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 133 { .vendor_id = 0, /* sentinel */ }, 134 }; 135 136 #define BNXT_ETH_RSS_SUPPORT ( \ 137 ETH_RSS_IPV4 | \ 138 ETH_RSS_NONFRAG_IPV4_TCP | \ 139 ETH_RSS_NONFRAG_IPV4_UDP | \ 140 ETH_RSS_IPV6 | \ 141 ETH_RSS_NONFRAG_IPV6_TCP | \ 142 ETH_RSS_NONFRAG_IPV6_UDP) 143 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 145 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 146 DEV_TX_OFFLOAD_TCP_CKSUM | \ 147 DEV_TX_OFFLOAD_UDP_CKSUM | \ 148 DEV_TX_OFFLOAD_TCP_TSO | \ 149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 154 DEV_TX_OFFLOAD_QINQ_INSERT | \ 155 DEV_TX_OFFLOAD_MULTI_SEGS) 156 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 158 DEV_RX_OFFLOAD_VLAN_STRIP | \ 159 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 160 DEV_RX_OFFLOAD_UDP_CKSUM | \ 161 DEV_RX_OFFLOAD_TCP_CKSUM | \ 162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 163 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 164 DEV_RX_OFFLOAD_KEEP_CRC | \ 165 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 166 DEV_RX_OFFLOAD_TCP_LRO | \ 167 DEV_RX_OFFLOAD_SCATTER) 168 169 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 170 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 171 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 172 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 173 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 174 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 175 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 176 177 int is_bnxt_in_error(struct bnxt *bp) 178 { 179 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 180 return -EIO; 181 if (bp->flags & BNXT_FLAG_FW_RESET) 182 return -EBUSY; 183 184 return 0; 185 } 186 187 /***********************/ 188 189 /* 190 * High level utility functions 191 */ 192 193 uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 194 { 195 if (!BNXT_CHIP_THOR(bp)) 196 return 1; 197 198 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 199 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 200 BNXT_RSS_ENTRIES_PER_CTX_THOR; 201 } 202 203 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 204 { 205 if (!BNXT_CHIP_THOR(bp)) 206 return HW_HASH_INDEX_SIZE; 207 208 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 209 } 210 211 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 212 { 213 bnxt_free_filter_mem(bp); 214 bnxt_free_vnic_attributes(bp); 215 bnxt_free_vnic_mem(bp); 216 217 /* tx/rx rings are configured as part of *_queue_setup callbacks. 218 * If the number of rings change across fw update, 219 * we don't have much choice except to warn the user. 220 */ 221 if (!reconfig) { 222 bnxt_free_stats(bp); 223 bnxt_free_tx_rings(bp); 224 bnxt_free_rx_rings(bp); 225 } 226 bnxt_free_async_cp_ring(bp); 227 bnxt_free_rxtx_nq_ring(bp); 228 } 229 230 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 231 { 232 int rc; 233 234 rc = bnxt_alloc_ring_grps(bp); 235 if (rc) 236 goto alloc_mem_err; 237 238 rc = bnxt_alloc_async_ring_struct(bp); 239 if (rc) 240 goto alloc_mem_err; 241 242 rc = bnxt_alloc_vnic_mem(bp); 243 if (rc) 244 goto alloc_mem_err; 245 246 rc = bnxt_alloc_vnic_attributes(bp); 247 if (rc) 248 goto alloc_mem_err; 249 250 rc = bnxt_alloc_filter_mem(bp); 251 if (rc) 252 goto alloc_mem_err; 253 254 rc = bnxt_alloc_async_cp_ring(bp); 255 if (rc) 256 goto alloc_mem_err; 257 258 rc = bnxt_alloc_rxtx_nq_ring(bp); 259 if (rc) 260 goto alloc_mem_err; 261 262 return 0; 263 264 alloc_mem_err: 265 bnxt_free_mem(bp, reconfig); 266 return rc; 267 } 268 269 static int bnxt_init_chip(struct bnxt *bp) 270 { 271 struct bnxt_rx_queue *rxq; 272 struct rte_eth_link new; 273 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 274 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 275 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 276 uint64_t rx_offloads = dev_conf->rxmode.offloads; 277 uint32_t intr_vector = 0; 278 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 279 uint32_t vec = BNXT_MISC_VEC_ID; 280 unsigned int i, j; 281 int rc; 282 283 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 284 bp->eth_dev->data->dev_conf.rxmode.offloads |= 285 DEV_RX_OFFLOAD_JUMBO_FRAME; 286 bp->flags |= BNXT_FLAG_JUMBO; 287 } else { 288 bp->eth_dev->data->dev_conf.rxmode.offloads &= 289 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 290 bp->flags &= ~BNXT_FLAG_JUMBO; 291 } 292 293 /* THOR does not support ring groups. 294 * But we will use the array to save RSS context IDs. 295 */ 296 if (BNXT_CHIP_THOR(bp)) 297 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 298 299 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 300 if (rc) { 301 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 302 goto err_out; 303 } 304 305 rc = bnxt_alloc_hwrm_rings(bp); 306 if (rc) { 307 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 308 goto err_out; 309 } 310 311 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 312 if (rc) { 313 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 314 goto err_out; 315 } 316 317 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 318 goto skip_cosq_cfg; 319 320 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 321 if (bp->rx_cos_queue[i].id != 0xff) { 322 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 323 324 if (!vnic) { 325 PMD_DRV_LOG(ERR, 326 "Num pools more than FW profile\n"); 327 rc = -EINVAL; 328 goto err_out; 329 } 330 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 331 bp->rx_cosq_cnt++; 332 } 333 } 334 335 skip_cosq_cfg: 336 rc = bnxt_mq_rx_configure(bp); 337 if (rc) { 338 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 339 goto err_out; 340 } 341 342 /* VNIC configuration */ 343 for (i = 0; i < bp->nr_vnics; i++) { 344 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 345 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 346 347 rc = bnxt_vnic_grp_alloc(bp, vnic); 348 if (rc) 349 goto err_out; 350 351 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 352 i, vnic, vnic->fw_grp_ids); 353 354 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 355 if (rc) { 356 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 357 i, rc); 358 goto err_out; 359 } 360 361 /* Alloc RSS context only if RSS mode is enabled */ 362 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 363 int j, nr_ctxs = bnxt_rss_ctxts(bp); 364 365 rc = 0; 366 for (j = 0; j < nr_ctxs; j++) { 367 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 368 if (rc) 369 break; 370 } 371 if (rc) { 372 PMD_DRV_LOG(ERR, 373 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 374 i, j, rc); 375 goto err_out; 376 } 377 vnic->num_lb_ctxts = nr_ctxs; 378 } 379 380 /* 381 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 382 * setting is not available at this time, it will not be 383 * configured correctly in the CFA. 384 */ 385 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 386 vnic->vlan_strip = true; 387 else 388 vnic->vlan_strip = false; 389 390 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 391 if (rc) { 392 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 393 i, rc); 394 goto err_out; 395 } 396 397 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 398 if (rc) { 399 PMD_DRV_LOG(ERR, 400 "HWRM vnic %d filter failure rc: %x\n", 401 i, rc); 402 goto err_out; 403 } 404 405 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 406 rxq = bp->eth_dev->data->rx_queues[j]; 407 408 PMD_DRV_LOG(DEBUG, 409 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 410 j, rxq->vnic, rxq->vnic->fw_grp_ids); 411 412 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 413 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 414 } 415 416 rc = bnxt_vnic_rss_configure(bp, vnic); 417 if (rc) { 418 PMD_DRV_LOG(ERR, 419 "HWRM vnic set RSS failure rc: %x\n", rc); 420 goto err_out; 421 } 422 423 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 424 425 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 426 DEV_RX_OFFLOAD_TCP_LRO) 427 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 428 else 429 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 430 } 431 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 432 if (rc) { 433 PMD_DRV_LOG(ERR, 434 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 435 goto err_out; 436 } 437 438 /* check and configure queue intr-vector mapping */ 439 if ((rte_intr_cap_multiple(intr_handle) || 440 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 441 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 442 intr_vector = bp->eth_dev->data->nb_rx_queues; 443 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 444 if (intr_vector > bp->rx_cp_nr_rings) { 445 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 446 bp->rx_cp_nr_rings); 447 return -ENOTSUP; 448 } 449 rc = rte_intr_efd_enable(intr_handle, intr_vector); 450 if (rc) 451 return rc; 452 } 453 454 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 455 intr_handle->intr_vec = 456 rte_zmalloc("intr_vec", 457 bp->eth_dev->data->nb_rx_queues * 458 sizeof(int), 0); 459 if (intr_handle->intr_vec == NULL) { 460 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 461 " intr_vec", bp->eth_dev->data->nb_rx_queues); 462 rc = -ENOMEM; 463 goto err_disable; 464 } 465 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 466 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 467 intr_handle->intr_vec, intr_handle->nb_efd, 468 intr_handle->max_intr); 469 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 470 queue_id++) { 471 intr_handle->intr_vec[queue_id] = 472 vec + BNXT_RX_VEC_START; 473 if (vec < base + intr_handle->nb_efd - 1) 474 vec++; 475 } 476 } 477 478 /* enable uio/vfio intr/eventfd mapping */ 479 rc = rte_intr_enable(intr_handle); 480 if (rc) 481 goto err_free; 482 483 rc = bnxt_get_hwrm_link_config(bp, &new); 484 if (rc) { 485 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 486 goto err_free; 487 } 488 489 if (!bp->link_info.link_up) { 490 rc = bnxt_set_hwrm_link_config(bp, true); 491 if (rc) { 492 PMD_DRV_LOG(ERR, 493 "HWRM link config failure rc: %x\n", rc); 494 goto err_free; 495 } 496 } 497 bnxt_print_link_info(bp->eth_dev); 498 499 return 0; 500 501 err_free: 502 rte_free(intr_handle->intr_vec); 503 err_disable: 504 rte_intr_efd_disable(intr_handle); 505 err_out: 506 /* Some of the error status returned by FW may not be from errno.h */ 507 if (rc > 0) 508 rc = -EIO; 509 510 return rc; 511 } 512 513 static int bnxt_shutdown_nic(struct bnxt *bp) 514 { 515 bnxt_free_all_hwrm_resources(bp); 516 bnxt_free_all_filters(bp); 517 bnxt_free_all_vnics(bp); 518 return 0; 519 } 520 521 static int bnxt_init_nic(struct bnxt *bp) 522 { 523 int rc; 524 525 if (BNXT_HAS_RING_GRPS(bp)) { 526 rc = bnxt_init_ring_grps(bp); 527 if (rc) 528 return rc; 529 } 530 531 bnxt_init_vnics(bp); 532 bnxt_init_filters(bp); 533 534 return 0; 535 } 536 537 /* 538 * Device configuration and status function 539 */ 540 541 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 542 struct rte_eth_dev_info *dev_info) 543 { 544 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 545 struct bnxt *bp = eth_dev->data->dev_private; 546 uint16_t max_vnics, i, j, vpool, vrxq; 547 unsigned int max_rx_rings; 548 int rc; 549 550 rc = is_bnxt_in_error(bp); 551 if (rc) 552 return rc; 553 554 /* MAC Specifics */ 555 dev_info->max_mac_addrs = bp->max_l2_ctx; 556 dev_info->max_hash_mac_addrs = 0; 557 558 /* PF/VF specifics */ 559 if (BNXT_PF(bp)) 560 dev_info->max_vfs = pdev->max_vfs; 561 562 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx); 563 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 564 dev_info->max_rx_queues = max_rx_rings; 565 dev_info->max_tx_queues = max_rx_rings; 566 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 567 dev_info->hash_key_size = 40; 568 max_vnics = bp->max_vnics; 569 570 /* MTU specifics */ 571 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 572 dev_info->max_mtu = BNXT_MAX_MTU; 573 574 /* Fast path specifics */ 575 dev_info->min_rx_bufsize = 1; 576 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 577 578 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 579 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 580 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 581 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 582 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 583 584 /* *INDENT-OFF* */ 585 dev_info->default_rxconf = (struct rte_eth_rxconf) { 586 .rx_thresh = { 587 .pthresh = 8, 588 .hthresh = 8, 589 .wthresh = 0, 590 }, 591 .rx_free_thresh = 32, 592 /* If no descriptors available, pkts are dropped by default */ 593 .rx_drop_en = 1, 594 }; 595 596 dev_info->default_txconf = (struct rte_eth_txconf) { 597 .tx_thresh = { 598 .pthresh = 32, 599 .hthresh = 0, 600 .wthresh = 0, 601 }, 602 .tx_free_thresh = 32, 603 .tx_rs_thresh = 32, 604 }; 605 eth_dev->data->dev_conf.intr_conf.lsc = 1; 606 607 eth_dev->data->dev_conf.intr_conf.rxq = 1; 608 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 609 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 610 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 611 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 612 613 /* *INDENT-ON* */ 614 615 /* 616 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 617 * need further investigation. 618 */ 619 620 /* VMDq resources */ 621 vpool = 64; /* ETH_64_POOLS */ 622 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 623 for (i = 0; i < 4; vpool >>= 1, i++) { 624 if (max_vnics > vpool) { 625 for (j = 0; j < 5; vrxq >>= 1, j++) { 626 if (dev_info->max_rx_queues > vrxq) { 627 if (vpool > vrxq) 628 vpool = vrxq; 629 goto found; 630 } 631 } 632 /* Not enough resources to support VMDq */ 633 break; 634 } 635 } 636 /* Not enough resources to support VMDq */ 637 vpool = 0; 638 vrxq = 0; 639 found: 640 dev_info->max_vmdq_pools = vpool; 641 dev_info->vmdq_queue_num = vrxq; 642 643 dev_info->vmdq_pool_base = 0; 644 dev_info->vmdq_queue_base = 0; 645 646 return 0; 647 } 648 649 /* Configure the device based on the configuration provided */ 650 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 651 { 652 struct bnxt *bp = eth_dev->data->dev_private; 653 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 654 int rc; 655 656 bp->rx_queues = (void *)eth_dev->data->rx_queues; 657 bp->tx_queues = (void *)eth_dev->data->tx_queues; 658 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 659 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 660 661 rc = is_bnxt_in_error(bp); 662 if (rc) 663 return rc; 664 665 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 666 rc = bnxt_hwrm_check_vf_rings(bp); 667 if (rc) { 668 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 669 return -ENOSPC; 670 } 671 672 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 673 if (rc) { 674 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 675 return -ENOSPC; 676 } 677 } else { 678 /* legacy driver needs to get updated values */ 679 rc = bnxt_hwrm_func_qcaps(bp); 680 if (rc) { 681 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 682 return rc; 683 } 684 } 685 686 /* Inherit new configurations */ 687 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 688 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 689 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 690 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 691 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 692 bp->max_stat_ctx) 693 goto resource_error; 694 695 if (BNXT_HAS_RING_GRPS(bp) && 696 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 697 goto resource_error; 698 699 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 700 bp->max_vnics < eth_dev->data->nb_rx_queues) 701 goto resource_error; 702 703 bp->rx_cp_nr_rings = bp->rx_nr_rings; 704 bp->tx_cp_nr_rings = bp->tx_nr_rings; 705 706 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 707 eth_dev->data->mtu = 708 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 709 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 710 BNXT_NUM_VLANS; 711 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 712 } 713 return 0; 714 715 resource_error: 716 PMD_DRV_LOG(ERR, 717 "Insufficient resources to support requested config\n"); 718 PMD_DRV_LOG(ERR, 719 "Num Queues Requested: Tx %d, Rx %d\n", 720 eth_dev->data->nb_tx_queues, 721 eth_dev->data->nb_rx_queues); 722 PMD_DRV_LOG(ERR, 723 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 724 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 725 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 726 return -ENOSPC; 727 } 728 729 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 730 { 731 struct rte_eth_link *link = ð_dev->data->dev_link; 732 733 if (link->link_status) 734 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 735 eth_dev->data->port_id, 736 (uint32_t)link->link_speed, 737 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 738 ("full-duplex") : ("half-duplex\n")); 739 else 740 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 741 eth_dev->data->port_id); 742 } 743 744 /* 745 * Determine whether the current configuration requires support for scattered 746 * receive; return 1 if scattered receive is required and 0 if not. 747 */ 748 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 749 { 750 uint16_t buf_size; 751 int i; 752 753 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 754 return 1; 755 756 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 757 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 758 759 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 760 RTE_PKTMBUF_HEADROOM); 761 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 762 return 1; 763 } 764 return 0; 765 } 766 767 static eth_rx_burst_t 768 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev) 769 { 770 #ifdef RTE_ARCH_X86 771 #ifndef RTE_LIBRTE_IEEE1588 772 /* 773 * Vector mode receive can be enabled only if scatter rx is not 774 * in use and rx offloads are limited to VLAN stripping and 775 * CRC stripping. 776 */ 777 if (!eth_dev->data->scattered_rx && 778 !(eth_dev->data->dev_conf.rxmode.offloads & 779 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 780 DEV_RX_OFFLOAD_KEEP_CRC | 781 DEV_RX_OFFLOAD_JUMBO_FRAME | 782 DEV_RX_OFFLOAD_IPV4_CKSUM | 783 DEV_RX_OFFLOAD_UDP_CKSUM | 784 DEV_RX_OFFLOAD_TCP_CKSUM | 785 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 786 DEV_RX_OFFLOAD_VLAN_FILTER))) { 787 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 788 eth_dev->data->port_id); 789 return bnxt_recv_pkts_vec; 790 } 791 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 792 eth_dev->data->port_id); 793 PMD_DRV_LOG(INFO, 794 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 795 eth_dev->data->port_id, 796 eth_dev->data->scattered_rx, 797 eth_dev->data->dev_conf.rxmode.offloads); 798 #endif 799 #endif 800 return bnxt_recv_pkts; 801 } 802 803 static eth_tx_burst_t 804 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 805 { 806 #ifdef RTE_ARCH_X86 807 #ifndef RTE_LIBRTE_IEEE1588 808 /* 809 * Vector mode transmit can be enabled only if not using scatter rx 810 * or tx offloads. 811 */ 812 if (!eth_dev->data->scattered_rx && 813 !eth_dev->data->dev_conf.txmode.offloads) { 814 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 815 eth_dev->data->port_id); 816 return bnxt_xmit_pkts_vec; 817 } 818 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 819 eth_dev->data->port_id); 820 PMD_DRV_LOG(INFO, 821 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 822 eth_dev->data->port_id, 823 eth_dev->data->scattered_rx, 824 eth_dev->data->dev_conf.txmode.offloads); 825 #endif 826 #endif 827 return bnxt_xmit_pkts; 828 } 829 830 static int bnxt_handle_if_change_status(struct bnxt *bp) 831 { 832 int rc; 833 834 /* Since fw has undergone a reset and lost all contexts, 835 * set fatal flag to not issue hwrm during cleanup 836 */ 837 bp->flags |= BNXT_FLAG_FATAL_ERROR; 838 bnxt_uninit_resources(bp, true); 839 840 /* clear fatal flag so that re-init happens */ 841 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 842 rc = bnxt_init_resources(bp, true); 843 844 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 845 846 return rc; 847 } 848 849 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 850 { 851 struct bnxt *bp = eth_dev->data->dev_private; 852 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 853 int vlan_mask = 0; 854 int rc; 855 856 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 857 PMD_DRV_LOG(ERR, 858 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 859 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 860 } 861 862 bnxt_enable_int(bp); 863 rc = bnxt_hwrm_if_change(bp, 1); 864 if (!rc) { 865 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 866 rc = bnxt_handle_if_change_status(bp); 867 if (rc) 868 return rc; 869 } 870 } 871 872 rc = bnxt_init_chip(bp); 873 if (rc) 874 goto error; 875 876 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 877 878 bnxt_link_update_op(eth_dev, 1); 879 880 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 881 vlan_mask |= ETH_VLAN_FILTER_MASK; 882 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 883 vlan_mask |= ETH_VLAN_STRIP_MASK; 884 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 885 if (rc) 886 goto error; 887 888 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 889 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 890 891 bp->flags |= BNXT_FLAG_INIT_DONE; 892 eth_dev->data->dev_started = 1; 893 bp->dev_stopped = 0; 894 bnxt_schedule_fw_health_check(bp); 895 return 0; 896 897 error: 898 bnxt_hwrm_if_change(bp, 0); 899 bnxt_shutdown_nic(bp); 900 bnxt_free_tx_mbufs(bp); 901 bnxt_free_rx_mbufs(bp); 902 return rc; 903 } 904 905 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 906 { 907 struct bnxt *bp = eth_dev->data->dev_private; 908 int rc = 0; 909 910 if (!bp->link_info.link_up) 911 rc = bnxt_set_hwrm_link_config(bp, true); 912 if (!rc) 913 eth_dev->data->dev_link.link_status = 1; 914 915 bnxt_print_link_info(eth_dev); 916 return 0; 917 } 918 919 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 920 { 921 struct bnxt *bp = eth_dev->data->dev_private; 922 923 eth_dev->data->dev_link.link_status = 0; 924 bnxt_set_hwrm_link_config(bp, false); 925 bp->link_info.link_up = 0; 926 927 return 0; 928 } 929 930 /* Unload the driver, release resources */ 931 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 932 { 933 struct bnxt *bp = eth_dev->data->dev_private; 934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 935 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 936 937 eth_dev->data->dev_started = 0; 938 /* Prevent crashes when queues are still in use */ 939 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 940 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 941 942 bnxt_disable_int(bp); 943 944 /* disable uio/vfio intr/eventfd mapping */ 945 rte_intr_disable(intr_handle); 946 947 bnxt_cancel_fw_health_check(bp); 948 949 bp->flags &= ~BNXT_FLAG_INIT_DONE; 950 if (bp->eth_dev->data->dev_started) { 951 /* TBD: STOP HW queues DMA */ 952 eth_dev->data->dev_link.link_status = 0; 953 } 954 bnxt_dev_set_link_down_op(eth_dev); 955 /* Wait for link to be reset and the async notification to process. */ 956 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2); 957 958 /* Clean queue intr-vector mapping */ 959 rte_intr_efd_disable(intr_handle); 960 if (intr_handle->intr_vec != NULL) { 961 rte_free(intr_handle->intr_vec); 962 intr_handle->intr_vec = NULL; 963 } 964 965 bnxt_hwrm_port_clr_stats(bp); 966 bnxt_free_tx_mbufs(bp); 967 bnxt_free_rx_mbufs(bp); 968 /* Process any remaining notifications in default completion queue */ 969 bnxt_int_handler(eth_dev); 970 bnxt_shutdown_nic(bp); 971 bnxt_hwrm_if_change(bp, 0); 972 bp->dev_stopped = 1; 973 } 974 975 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 976 { 977 struct bnxt *bp = eth_dev->data->dev_private; 978 979 if (bp->dev_stopped == 0) 980 bnxt_dev_stop_op(eth_dev); 981 982 if (eth_dev->data->mac_addrs != NULL) { 983 rte_free(eth_dev->data->mac_addrs); 984 eth_dev->data->mac_addrs = NULL; 985 } 986 if (bp->grp_info != NULL) { 987 rte_free(bp->grp_info); 988 bp->grp_info = NULL; 989 } 990 991 bnxt_dev_uninit(eth_dev); 992 } 993 994 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 995 uint32_t index) 996 { 997 struct bnxt *bp = eth_dev->data->dev_private; 998 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 999 struct bnxt_vnic_info *vnic; 1000 struct bnxt_filter_info *filter, *temp_filter; 1001 uint32_t i; 1002 1003 if (is_bnxt_in_error(bp)) 1004 return; 1005 1006 /* 1007 * Loop through all VNICs from the specified filter flow pools to 1008 * remove the corresponding MAC addr filter 1009 */ 1010 for (i = 0; i < bp->nr_vnics; i++) { 1011 if (!(pool_mask & (1ULL << i))) 1012 continue; 1013 1014 vnic = &bp->vnic_info[i]; 1015 filter = STAILQ_FIRST(&vnic->filter); 1016 while (filter) { 1017 temp_filter = STAILQ_NEXT(filter, next); 1018 if (filter->mac_index == index) { 1019 STAILQ_REMOVE(&vnic->filter, filter, 1020 bnxt_filter_info, next); 1021 bnxt_hwrm_clear_l2_filter(bp, filter); 1022 filter->mac_index = INVALID_MAC_INDEX; 1023 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 1024 STAILQ_INSERT_TAIL(&bp->free_filter_list, 1025 filter, next); 1026 } 1027 filter = temp_filter; 1028 } 1029 } 1030 } 1031 1032 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1033 struct rte_ether_addr *mac_addr, uint32_t index) 1034 { 1035 struct bnxt_filter_info *filter; 1036 int rc = 0; 1037 1038 filter = STAILQ_FIRST(&vnic->filter); 1039 /* During bnxt_mac_addr_add_op, default MAC is 1040 * already programmed, so skip it. But, when 1041 * hw-vlan-filter is turned OFF from ON, default 1042 * MAC filter should be restored 1043 */ 1044 if (filter->dflt) 1045 return 0; 1046 1047 filter = bnxt_alloc_filter(bp); 1048 if (!filter) { 1049 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1050 return -ENODEV; 1051 } 1052 1053 filter->mac_index = index; 1054 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1055 * if the MAC that's been programmed now is a different one, then, 1056 * copy that addr to filter->l2_addr 1057 */ 1058 if (mac_addr) 1059 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1060 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1061 1062 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1063 if (!rc) { 1064 if (filter->mac_index == 0) { 1065 filter->dflt = true; 1066 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1067 } else { 1068 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1069 } 1070 } else { 1071 filter->mac_index = INVALID_MAC_INDEX; 1072 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 1073 bnxt_free_filter(bp, filter); 1074 } 1075 1076 return rc; 1077 } 1078 1079 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1080 struct rte_ether_addr *mac_addr, 1081 uint32_t index, uint32_t pool) 1082 { 1083 struct bnxt *bp = eth_dev->data->dev_private; 1084 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1085 struct bnxt_filter_info *filter; 1086 int rc = 0; 1087 1088 rc = is_bnxt_in_error(bp); 1089 if (rc) 1090 return rc; 1091 1092 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1093 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1094 return -ENOTSUP; 1095 } 1096 1097 if (!vnic) { 1098 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1099 return -EINVAL; 1100 } 1101 /* Attach requested MAC address to the new l2_filter */ 1102 STAILQ_FOREACH(filter, &vnic->filter, next) { 1103 if (filter->mac_index == index) { 1104 PMD_DRV_LOG(ERR, 1105 "MAC addr already existed for pool %d\n", pool); 1106 return 0; 1107 } 1108 } 1109 1110 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index); 1111 1112 return rc; 1113 } 1114 1115 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1116 { 1117 int rc = 0; 1118 struct bnxt *bp = eth_dev->data->dev_private; 1119 struct rte_eth_link new; 1120 unsigned int cnt = BNXT_LINK_WAIT_CNT; 1121 1122 rc = is_bnxt_in_error(bp); 1123 if (rc) 1124 return rc; 1125 1126 memset(&new, 0, sizeof(new)); 1127 do { 1128 /* Retrieve link info from hardware */ 1129 rc = bnxt_get_hwrm_link_config(bp, &new); 1130 if (rc) { 1131 new.link_speed = ETH_LINK_SPEED_100M; 1132 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1133 PMD_DRV_LOG(ERR, 1134 "Failed to retrieve link rc = 0x%x!\n", rc); 1135 goto out; 1136 } 1137 1138 if (!wait_to_complete || new.link_status) 1139 break; 1140 1141 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1142 } while (cnt--); 1143 1144 out: 1145 /* Timed out or success */ 1146 if (new.link_status != eth_dev->data->dev_link.link_status || 1147 new.link_speed != eth_dev->data->dev_link.link_speed) { 1148 rte_eth_linkstatus_set(eth_dev, &new); 1149 1150 _rte_eth_dev_callback_process(eth_dev, 1151 RTE_ETH_EVENT_INTR_LSC, 1152 NULL); 1153 1154 bnxt_print_link_info(eth_dev); 1155 } 1156 1157 return rc; 1158 } 1159 1160 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1161 { 1162 struct bnxt *bp = eth_dev->data->dev_private; 1163 struct bnxt_vnic_info *vnic; 1164 uint32_t old_flags; 1165 int rc; 1166 1167 rc = is_bnxt_in_error(bp); 1168 if (rc) 1169 return rc; 1170 1171 if (bp->vnic_info == NULL) 1172 return 0; 1173 1174 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1175 1176 old_flags = vnic->flags; 1177 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1178 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1179 if (rc != 0) 1180 vnic->flags = old_flags; 1181 1182 return rc; 1183 } 1184 1185 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1186 { 1187 struct bnxt *bp = eth_dev->data->dev_private; 1188 struct bnxt_vnic_info *vnic; 1189 uint32_t old_flags; 1190 int rc; 1191 1192 rc = is_bnxt_in_error(bp); 1193 if (rc) 1194 return rc; 1195 1196 if (bp->vnic_info == NULL) 1197 return 0; 1198 1199 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1200 1201 old_flags = vnic->flags; 1202 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1203 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1204 if (rc != 0) 1205 vnic->flags = old_flags; 1206 1207 return rc; 1208 } 1209 1210 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1211 { 1212 struct bnxt *bp = eth_dev->data->dev_private; 1213 struct bnxt_vnic_info *vnic; 1214 uint32_t old_flags; 1215 int rc; 1216 1217 rc = is_bnxt_in_error(bp); 1218 if (rc) 1219 return rc; 1220 1221 if (bp->vnic_info == NULL) 1222 return 0; 1223 1224 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1225 1226 old_flags = vnic->flags; 1227 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1228 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1229 if (rc != 0) 1230 vnic->flags = old_flags; 1231 1232 return rc; 1233 } 1234 1235 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1236 { 1237 struct bnxt *bp = eth_dev->data->dev_private; 1238 struct bnxt_vnic_info *vnic; 1239 uint32_t old_flags; 1240 int rc; 1241 1242 rc = is_bnxt_in_error(bp); 1243 if (rc) 1244 return rc; 1245 1246 if (bp->vnic_info == NULL) 1247 return 0; 1248 1249 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1250 1251 old_flags = vnic->flags; 1252 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1253 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1254 if (rc != 0) 1255 vnic->flags = old_flags; 1256 1257 return rc; 1258 } 1259 1260 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1261 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1262 { 1263 if (qid >= bp->rx_nr_rings) 1264 return NULL; 1265 1266 return bp->eth_dev->data->rx_queues[qid]; 1267 } 1268 1269 /* Return rxq corresponding to a given rss table ring/group ID. */ 1270 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1271 { 1272 struct bnxt_rx_queue *rxq; 1273 unsigned int i; 1274 1275 if (!BNXT_HAS_RING_GRPS(bp)) { 1276 for (i = 0; i < bp->rx_nr_rings; i++) { 1277 rxq = bp->eth_dev->data->rx_queues[i]; 1278 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1279 return rxq->index; 1280 } 1281 } else { 1282 for (i = 0; i < bp->rx_nr_rings; i++) { 1283 if (bp->grp_info[i].fw_grp_id == fwr) 1284 return i; 1285 } 1286 } 1287 1288 return INVALID_HW_RING_ID; 1289 } 1290 1291 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1292 struct rte_eth_rss_reta_entry64 *reta_conf, 1293 uint16_t reta_size) 1294 { 1295 struct bnxt *bp = eth_dev->data->dev_private; 1296 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1297 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1298 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1299 uint16_t idx, sft; 1300 int i, rc; 1301 1302 rc = is_bnxt_in_error(bp); 1303 if (rc) 1304 return rc; 1305 1306 if (!vnic->rss_table) 1307 return -EINVAL; 1308 1309 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1310 return -EINVAL; 1311 1312 if (reta_size != tbl_size) { 1313 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1314 "(%d) must equal the size supported by the hardware " 1315 "(%d)\n", reta_size, tbl_size); 1316 return -EINVAL; 1317 } 1318 1319 for (i = 0; i < reta_size; i++) { 1320 struct bnxt_rx_queue *rxq; 1321 1322 idx = i / RTE_RETA_GROUP_SIZE; 1323 sft = i % RTE_RETA_GROUP_SIZE; 1324 1325 if (!(reta_conf[idx].mask & (1ULL << sft))) 1326 continue; 1327 1328 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1329 if (!rxq) { 1330 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1331 return -EINVAL; 1332 } 1333 1334 if (BNXT_CHIP_THOR(bp)) { 1335 vnic->rss_table[i * 2] = 1336 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1337 vnic->rss_table[i * 2 + 1] = 1338 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1339 } else { 1340 vnic->rss_table[i] = 1341 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1342 } 1343 1344 vnic->rss_table[i] = 1345 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1346 } 1347 1348 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1349 return 0; 1350 } 1351 1352 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1353 struct rte_eth_rss_reta_entry64 *reta_conf, 1354 uint16_t reta_size) 1355 { 1356 struct bnxt *bp = eth_dev->data->dev_private; 1357 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1358 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1359 uint16_t idx, sft, i; 1360 int rc; 1361 1362 rc = is_bnxt_in_error(bp); 1363 if (rc) 1364 return rc; 1365 1366 /* Retrieve from the default VNIC */ 1367 if (!vnic) 1368 return -EINVAL; 1369 if (!vnic->rss_table) 1370 return -EINVAL; 1371 1372 if (reta_size != tbl_size) { 1373 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1374 "(%d) must equal the size supported by the hardware " 1375 "(%d)\n", reta_size, tbl_size); 1376 return -EINVAL; 1377 } 1378 1379 for (idx = 0, i = 0; i < reta_size; i++) { 1380 idx = i / RTE_RETA_GROUP_SIZE; 1381 sft = i % RTE_RETA_GROUP_SIZE; 1382 1383 if (reta_conf[idx].mask & (1ULL << sft)) { 1384 uint16_t qid; 1385 1386 if (BNXT_CHIP_THOR(bp)) 1387 qid = bnxt_rss_to_qid(bp, 1388 vnic->rss_table[i * 2]); 1389 else 1390 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1391 1392 if (qid == INVALID_HW_RING_ID) { 1393 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1394 return -EINVAL; 1395 } 1396 reta_conf[idx].reta[sft] = qid; 1397 } 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1404 struct rte_eth_rss_conf *rss_conf) 1405 { 1406 struct bnxt *bp = eth_dev->data->dev_private; 1407 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1408 struct bnxt_vnic_info *vnic; 1409 int rc; 1410 1411 rc = is_bnxt_in_error(bp); 1412 if (rc) 1413 return rc; 1414 1415 /* 1416 * If RSS enablement were different than dev_configure, 1417 * then return -EINVAL 1418 */ 1419 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1420 if (!rss_conf->rss_hf) 1421 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1422 } else { 1423 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1424 return -EINVAL; 1425 } 1426 1427 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1428 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 1429 1430 /* Update the default RSS VNIC(s) */ 1431 vnic = &bp->vnic_info[0]; 1432 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1433 1434 /* 1435 * If hashkey is not specified, use the previously configured 1436 * hashkey 1437 */ 1438 if (!rss_conf->rss_key) 1439 goto rss_config; 1440 1441 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1442 PMD_DRV_LOG(ERR, 1443 "Invalid hashkey length, should be 16 bytes\n"); 1444 return -EINVAL; 1445 } 1446 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1447 1448 rss_config: 1449 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1450 return 0; 1451 } 1452 1453 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1454 struct rte_eth_rss_conf *rss_conf) 1455 { 1456 struct bnxt *bp = eth_dev->data->dev_private; 1457 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1458 int len, rc; 1459 uint32_t hash_types; 1460 1461 rc = is_bnxt_in_error(bp); 1462 if (rc) 1463 return rc; 1464 1465 /* RSS configuration is the same for all VNICs */ 1466 if (vnic && vnic->rss_hash_key) { 1467 if (rss_conf->rss_key) { 1468 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1469 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1470 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1471 } 1472 1473 hash_types = vnic->hash_type; 1474 rss_conf->rss_hf = 0; 1475 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1476 rss_conf->rss_hf |= ETH_RSS_IPV4; 1477 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1478 } 1479 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1480 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1481 hash_types &= 1482 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1483 } 1484 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1485 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1486 hash_types &= 1487 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1488 } 1489 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1490 rss_conf->rss_hf |= ETH_RSS_IPV6; 1491 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1492 } 1493 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1494 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1495 hash_types &= 1496 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1497 } 1498 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1499 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1500 hash_types &= 1501 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1502 } 1503 if (hash_types) { 1504 PMD_DRV_LOG(ERR, 1505 "Unknwon RSS config from firmware (%08x), RSS disabled", 1506 vnic->hash_type); 1507 return -ENOTSUP; 1508 } 1509 } else { 1510 rss_conf->rss_hf = 0; 1511 } 1512 return 0; 1513 } 1514 1515 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1516 struct rte_eth_fc_conf *fc_conf) 1517 { 1518 struct bnxt *bp = dev->data->dev_private; 1519 struct rte_eth_link link_info; 1520 int rc; 1521 1522 rc = is_bnxt_in_error(bp); 1523 if (rc) 1524 return rc; 1525 1526 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1527 if (rc) 1528 return rc; 1529 1530 memset(fc_conf, 0, sizeof(*fc_conf)); 1531 if (bp->link_info.auto_pause) 1532 fc_conf->autoneg = 1; 1533 switch (bp->link_info.pause) { 1534 case 0: 1535 fc_conf->mode = RTE_FC_NONE; 1536 break; 1537 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1538 fc_conf->mode = RTE_FC_TX_PAUSE; 1539 break; 1540 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1541 fc_conf->mode = RTE_FC_RX_PAUSE; 1542 break; 1543 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1544 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1545 fc_conf->mode = RTE_FC_FULL; 1546 break; 1547 } 1548 return 0; 1549 } 1550 1551 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1552 struct rte_eth_fc_conf *fc_conf) 1553 { 1554 struct bnxt *bp = dev->data->dev_private; 1555 int rc; 1556 1557 rc = is_bnxt_in_error(bp); 1558 if (rc) 1559 return rc; 1560 1561 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1562 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1563 return -ENOTSUP; 1564 } 1565 1566 switch (fc_conf->mode) { 1567 case RTE_FC_NONE: 1568 bp->link_info.auto_pause = 0; 1569 bp->link_info.force_pause = 0; 1570 break; 1571 case RTE_FC_RX_PAUSE: 1572 if (fc_conf->autoneg) { 1573 bp->link_info.auto_pause = 1574 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1575 bp->link_info.force_pause = 0; 1576 } else { 1577 bp->link_info.auto_pause = 0; 1578 bp->link_info.force_pause = 1579 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1580 } 1581 break; 1582 case RTE_FC_TX_PAUSE: 1583 if (fc_conf->autoneg) { 1584 bp->link_info.auto_pause = 1585 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1586 bp->link_info.force_pause = 0; 1587 } else { 1588 bp->link_info.auto_pause = 0; 1589 bp->link_info.force_pause = 1590 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1591 } 1592 break; 1593 case RTE_FC_FULL: 1594 if (fc_conf->autoneg) { 1595 bp->link_info.auto_pause = 1596 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1597 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1598 bp->link_info.force_pause = 0; 1599 } else { 1600 bp->link_info.auto_pause = 0; 1601 bp->link_info.force_pause = 1602 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1603 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1604 } 1605 break; 1606 } 1607 return bnxt_set_hwrm_link_config(bp, true); 1608 } 1609 1610 /* Add UDP tunneling port */ 1611 static int 1612 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1613 struct rte_eth_udp_tunnel *udp_tunnel) 1614 { 1615 struct bnxt *bp = eth_dev->data->dev_private; 1616 uint16_t tunnel_type = 0; 1617 int rc = 0; 1618 1619 rc = is_bnxt_in_error(bp); 1620 if (rc) 1621 return rc; 1622 1623 switch (udp_tunnel->prot_type) { 1624 case RTE_TUNNEL_TYPE_VXLAN: 1625 if (bp->vxlan_port_cnt) { 1626 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1627 udp_tunnel->udp_port); 1628 if (bp->vxlan_port != udp_tunnel->udp_port) { 1629 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1630 return -ENOSPC; 1631 } 1632 bp->vxlan_port_cnt++; 1633 return 0; 1634 } 1635 tunnel_type = 1636 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1637 bp->vxlan_port_cnt++; 1638 break; 1639 case RTE_TUNNEL_TYPE_GENEVE: 1640 if (bp->geneve_port_cnt) { 1641 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1642 udp_tunnel->udp_port); 1643 if (bp->geneve_port != udp_tunnel->udp_port) { 1644 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1645 return -ENOSPC; 1646 } 1647 bp->geneve_port_cnt++; 1648 return 0; 1649 } 1650 tunnel_type = 1651 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1652 bp->geneve_port_cnt++; 1653 break; 1654 default: 1655 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1656 return -ENOTSUP; 1657 } 1658 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1659 tunnel_type); 1660 return rc; 1661 } 1662 1663 static int 1664 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1665 struct rte_eth_udp_tunnel *udp_tunnel) 1666 { 1667 struct bnxt *bp = eth_dev->data->dev_private; 1668 uint16_t tunnel_type = 0; 1669 uint16_t port = 0; 1670 int rc = 0; 1671 1672 rc = is_bnxt_in_error(bp); 1673 if (rc) 1674 return rc; 1675 1676 switch (udp_tunnel->prot_type) { 1677 case RTE_TUNNEL_TYPE_VXLAN: 1678 if (!bp->vxlan_port_cnt) { 1679 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1680 return -EINVAL; 1681 } 1682 if (bp->vxlan_port != udp_tunnel->udp_port) { 1683 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1684 udp_tunnel->udp_port, bp->vxlan_port); 1685 return -EINVAL; 1686 } 1687 if (--bp->vxlan_port_cnt) 1688 return 0; 1689 1690 tunnel_type = 1691 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1692 port = bp->vxlan_fw_dst_port_id; 1693 break; 1694 case RTE_TUNNEL_TYPE_GENEVE: 1695 if (!bp->geneve_port_cnt) { 1696 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1697 return -EINVAL; 1698 } 1699 if (bp->geneve_port != udp_tunnel->udp_port) { 1700 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1701 udp_tunnel->udp_port, bp->geneve_port); 1702 return -EINVAL; 1703 } 1704 if (--bp->geneve_port_cnt) 1705 return 0; 1706 1707 tunnel_type = 1708 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1709 port = bp->geneve_fw_dst_port_id; 1710 break; 1711 default: 1712 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1713 return -ENOTSUP; 1714 } 1715 1716 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1717 if (!rc) { 1718 if (tunnel_type == 1719 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1720 bp->vxlan_port = 0; 1721 if (tunnel_type == 1722 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1723 bp->geneve_port = 0; 1724 } 1725 return rc; 1726 } 1727 1728 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1729 { 1730 struct bnxt_filter_info *filter; 1731 struct bnxt_vnic_info *vnic; 1732 int rc = 0; 1733 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1734 1735 /* if VLAN exists && VLAN matches vlan_id 1736 * remove the MAC+VLAN filter 1737 * add a new MAC only filter 1738 * else 1739 * VLAN filter doesn't exist, just skip and continue 1740 */ 1741 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1742 filter = STAILQ_FIRST(&vnic->filter); 1743 while (filter) { 1744 /* Search for this matching MAC+VLAN filter */ 1745 if ((filter->enables & chk) && 1746 (filter->l2_ivlan == vlan_id && 1747 filter->l2_ivlan_mask != 0) && 1748 !memcmp(filter->l2_addr, bp->mac_addr, 1749 RTE_ETHER_ADDR_LEN)) { 1750 /* Delete the filter */ 1751 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1752 if (rc) 1753 return rc; 1754 STAILQ_REMOVE(&vnic->filter, filter, 1755 bnxt_filter_info, next); 1756 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next); 1757 1758 PMD_DRV_LOG(INFO, 1759 "Del Vlan filter for %d\n", 1760 vlan_id); 1761 return rc; 1762 } 1763 filter = STAILQ_NEXT(filter, next); 1764 } 1765 return -ENOENT; 1766 } 1767 1768 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1769 { 1770 struct bnxt_filter_info *filter; 1771 struct bnxt_vnic_info *vnic; 1772 int rc = 0; 1773 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1774 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1775 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1776 1777 /* Implementation notes on the use of VNIC in this command: 1778 * 1779 * By default, these filters belong to default vnic for the function. 1780 * Once these filters are set up, only destination VNIC can be modified. 1781 * If the destination VNIC is not specified in this command, 1782 * then the HWRM shall only create an l2 context id. 1783 */ 1784 1785 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1786 filter = STAILQ_FIRST(&vnic->filter); 1787 /* Check if the VLAN has already been added */ 1788 while (filter) { 1789 if ((filter->enables & chk) && 1790 (filter->l2_ivlan == vlan_id && 1791 filter->l2_ivlan_mask == 0x0FFF) && 1792 !memcmp(filter->l2_addr, bp->mac_addr, 1793 RTE_ETHER_ADDR_LEN)) 1794 return -EEXIST; 1795 1796 filter = STAILQ_NEXT(filter, next); 1797 } 1798 1799 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 1800 * command to create MAC+VLAN filter with the right flags, enables set. 1801 */ 1802 filter = bnxt_alloc_filter(bp); 1803 if (!filter) { 1804 PMD_DRV_LOG(ERR, 1805 "MAC/VLAN filter alloc failed\n"); 1806 return -ENOMEM; 1807 } 1808 /* MAC + VLAN ID filter */ 1809 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 1810 * untagged packets are received 1811 * 1812 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 1813 * packets and only the programmed vlan's packets are received 1814 */ 1815 filter->l2_ivlan = vlan_id; 1816 filter->l2_ivlan_mask = 0x0FFF; 1817 filter->enables |= en; 1818 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1819 1820 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1821 if (rc) { 1822 /* Free the newly allocated filter as we were 1823 * not able to create the filter in hardware. 1824 */ 1825 filter->fw_l2_filter_id = UINT64_MAX; 1826 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next); 1827 return rc; 1828 } else { 1829 /* Add this new filter to the list */ 1830 if (vlan_id == 0) { 1831 filter->dflt = true; 1832 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1833 } else { 1834 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1835 } 1836 } 1837 1838 PMD_DRV_LOG(INFO, 1839 "Added Vlan filter for %d\n", vlan_id); 1840 return rc; 1841 } 1842 1843 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1844 uint16_t vlan_id, int on) 1845 { 1846 struct bnxt *bp = eth_dev->data->dev_private; 1847 int rc; 1848 1849 rc = is_bnxt_in_error(bp); 1850 if (rc) 1851 return rc; 1852 1853 /* These operations apply to ALL existing MAC/VLAN filters */ 1854 if (on) 1855 return bnxt_add_vlan_filter(bp, vlan_id); 1856 else 1857 return bnxt_del_vlan_filter(bp, vlan_id); 1858 } 1859 1860 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 1861 struct bnxt_vnic_info *vnic) 1862 { 1863 struct bnxt_filter_info *filter; 1864 int rc; 1865 1866 filter = STAILQ_FIRST(&vnic->filter); 1867 while (filter) { 1868 if (filter->dflt && 1869 !memcmp(filter->l2_addr, bp->mac_addr, 1870 RTE_ETHER_ADDR_LEN)) { 1871 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1872 if (rc) 1873 return rc; 1874 filter->dflt = false; 1875 STAILQ_REMOVE(&vnic->filter, filter, 1876 bnxt_filter_info, next); 1877 STAILQ_INSERT_TAIL(&bp->free_filter_list, 1878 filter, next); 1879 filter->fw_l2_filter_id = -1; 1880 break; 1881 } 1882 filter = STAILQ_NEXT(filter, next); 1883 } 1884 return 0; 1885 } 1886 1887 static int 1888 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1889 { 1890 struct bnxt *bp = dev->data->dev_private; 1891 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1892 struct bnxt_vnic_info *vnic; 1893 unsigned int i; 1894 int rc; 1895 1896 rc = is_bnxt_in_error(bp); 1897 if (rc) 1898 return rc; 1899 1900 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1901 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1902 /* Remove any VLAN filters programmed */ 1903 for (i = 0; i < 4095; i++) 1904 bnxt_del_vlan_filter(bp, i); 1905 1906 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0); 1907 if (rc) 1908 return rc; 1909 } else { 1910 /* Default filter will allow packets that match the 1911 * dest mac. So, it has to be deleted, otherwise, we 1912 * will endup receiving vlan packets for which the 1913 * filter is not programmed, when hw-vlan-filter 1914 * configuration is ON 1915 */ 1916 bnxt_del_dflt_mac_filter(bp, vnic); 1917 /* This filter will allow only untagged packets */ 1918 bnxt_add_vlan_filter(bp, 0); 1919 } 1920 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1921 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1922 1923 if (mask & ETH_VLAN_STRIP_MASK) { 1924 /* Enable or disable VLAN stripping */ 1925 for (i = 0; i < bp->nr_vnics; i++) { 1926 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1927 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1928 vnic->vlan_strip = true; 1929 else 1930 vnic->vlan_strip = false; 1931 bnxt_hwrm_vnic_cfg(bp, vnic); 1932 } 1933 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1934 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1935 } 1936 1937 if (mask & ETH_VLAN_EXTEND_MASK) { 1938 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 1939 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 1940 else 1941 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 1942 } 1943 1944 return 0; 1945 } 1946 1947 static int 1948 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 1949 uint16_t tpid) 1950 { 1951 struct bnxt *bp = dev->data->dev_private; 1952 int qinq = dev->data->dev_conf.rxmode.offloads & 1953 DEV_RX_OFFLOAD_VLAN_EXTEND; 1954 1955 if (vlan_type != ETH_VLAN_TYPE_INNER && 1956 vlan_type != ETH_VLAN_TYPE_OUTER) { 1957 PMD_DRV_LOG(ERR, 1958 "Unsupported vlan type."); 1959 return -EINVAL; 1960 } 1961 if (!qinq) { 1962 PMD_DRV_LOG(ERR, 1963 "QinQ not enabled. Needs to be ON as we can " 1964 "accelerate only outer vlan\n"); 1965 return -EINVAL; 1966 } 1967 1968 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 1969 switch (tpid) { 1970 case RTE_ETHER_TYPE_QINQ: 1971 bp->outer_tpid_bd = 1972 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 1973 break; 1974 case RTE_ETHER_TYPE_VLAN: 1975 bp->outer_tpid_bd = 1976 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 1977 break; 1978 case 0x9100: 1979 bp->outer_tpid_bd = 1980 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 1981 break; 1982 case 0x9200: 1983 bp->outer_tpid_bd = 1984 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 1985 break; 1986 case 0x9300: 1987 bp->outer_tpid_bd = 1988 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 1989 break; 1990 default: 1991 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 1992 return -EINVAL; 1993 } 1994 bp->outer_tpid_bd |= tpid; 1995 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 1996 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 1997 PMD_DRV_LOG(ERR, 1998 "Can accelerate only outer vlan in QinQ\n"); 1999 return -EINVAL; 2000 } 2001 2002 return 0; 2003 } 2004 2005 static int 2006 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2007 struct rte_ether_addr *addr) 2008 { 2009 struct bnxt *bp = dev->data->dev_private; 2010 /* Default Filter is tied to VNIC 0 */ 2011 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 2012 struct bnxt_filter_info *filter; 2013 int rc; 2014 2015 rc = is_bnxt_in_error(bp); 2016 if (rc) 2017 return rc; 2018 2019 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2020 return -EPERM; 2021 2022 if (rte_is_zero_ether_addr(addr)) 2023 return -EINVAL; 2024 2025 STAILQ_FOREACH(filter, &vnic->filter, next) { 2026 /* Default Filter is at Index 0 */ 2027 if (filter->mac_index != 0) 2028 continue; 2029 2030 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN); 2031 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN); 2032 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX | 2033 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2034 filter->enables |= 2035 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 2036 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 2037 2038 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2039 if (rc) { 2040 memcpy(filter->l2_addr, bp->mac_addr, 2041 RTE_ETHER_ADDR_LEN); 2042 return rc; 2043 } 2044 2045 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2046 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2047 return 0; 2048 } 2049 2050 return 0; 2051 } 2052 2053 static int 2054 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2055 struct rte_ether_addr *mc_addr_set, 2056 uint32_t nb_mc_addr) 2057 { 2058 struct bnxt *bp = eth_dev->data->dev_private; 2059 char *mc_addr_list = (char *)mc_addr_set; 2060 struct bnxt_vnic_info *vnic; 2061 uint32_t off = 0, i = 0; 2062 int rc; 2063 2064 rc = is_bnxt_in_error(bp); 2065 if (rc) 2066 return rc; 2067 2068 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2069 2070 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2071 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2072 goto allmulti; 2073 } 2074 2075 /* TODO Check for Duplicate mcast addresses */ 2076 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2077 for (i = 0; i < nb_mc_addr; i++) { 2078 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2079 RTE_ETHER_ADDR_LEN); 2080 off += RTE_ETHER_ADDR_LEN; 2081 } 2082 2083 vnic->mc_addr_cnt = i; 2084 if (vnic->mc_addr_cnt) 2085 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2086 else 2087 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2088 2089 allmulti: 2090 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2091 } 2092 2093 static int 2094 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2095 { 2096 struct bnxt *bp = dev->data->dev_private; 2097 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2098 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2099 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2100 int ret; 2101 2102 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 2103 fw_major, fw_minor, fw_updt); 2104 2105 ret += 1; /* add the size of '\0' */ 2106 if (fw_size < (uint32_t)ret) 2107 return ret; 2108 else 2109 return 0; 2110 } 2111 2112 static void 2113 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2114 struct rte_eth_rxq_info *qinfo) 2115 { 2116 struct bnxt_rx_queue *rxq; 2117 2118 rxq = dev->data->rx_queues[queue_id]; 2119 2120 qinfo->mp = rxq->mb_pool; 2121 qinfo->scattered_rx = dev->data->scattered_rx; 2122 qinfo->nb_desc = rxq->nb_rx_desc; 2123 2124 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2125 qinfo->conf.rx_drop_en = 0; 2126 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2127 } 2128 2129 static void 2130 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2131 struct rte_eth_txq_info *qinfo) 2132 { 2133 struct bnxt_tx_queue *txq; 2134 2135 txq = dev->data->tx_queues[queue_id]; 2136 2137 qinfo->nb_desc = txq->nb_tx_desc; 2138 2139 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2140 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2141 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2142 2143 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2144 qinfo->conf.tx_rs_thresh = 0; 2145 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2146 } 2147 2148 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2149 { 2150 struct bnxt *bp = eth_dev->data->dev_private; 2151 uint32_t new_pkt_size; 2152 uint32_t rc = 0; 2153 uint32_t i; 2154 2155 rc = is_bnxt_in_error(bp); 2156 if (rc) 2157 return rc; 2158 2159 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2160 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2161 2162 #ifdef RTE_ARCH_X86 2163 /* 2164 * If vector-mode tx/rx is active, disallow any MTU change that would 2165 * require scattered receive support. 2166 */ 2167 if (eth_dev->data->dev_started && 2168 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 2169 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 2170 (new_pkt_size > 2171 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2172 PMD_DRV_LOG(ERR, 2173 "MTU change would require scattered rx support. "); 2174 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2175 return -EINVAL; 2176 } 2177 #endif 2178 2179 if (new_mtu > RTE_ETHER_MTU) { 2180 bp->flags |= BNXT_FLAG_JUMBO; 2181 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2182 DEV_RX_OFFLOAD_JUMBO_FRAME; 2183 } else { 2184 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2185 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2186 bp->flags &= ~BNXT_FLAG_JUMBO; 2187 } 2188 2189 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2190 2191 for (i = 0; i < bp->nr_vnics; i++) { 2192 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2193 uint16_t size = 0; 2194 2195 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN + 2196 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 2197 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2198 if (rc) 2199 break; 2200 2201 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2202 size -= RTE_PKTMBUF_HEADROOM; 2203 2204 if (size < new_mtu) { 2205 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2206 if (rc) 2207 return rc; 2208 } 2209 } 2210 2211 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2212 2213 return rc; 2214 } 2215 2216 static int 2217 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2218 { 2219 struct bnxt *bp = dev->data->dev_private; 2220 uint16_t vlan = bp->vlan; 2221 int rc; 2222 2223 rc = is_bnxt_in_error(bp); 2224 if (rc) 2225 return rc; 2226 2227 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2228 PMD_DRV_LOG(ERR, 2229 "PVID cannot be modified for this function\n"); 2230 return -ENOTSUP; 2231 } 2232 bp->vlan = on ? pvid : 0; 2233 2234 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2235 if (rc) 2236 bp->vlan = vlan; 2237 return rc; 2238 } 2239 2240 static int 2241 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2242 { 2243 struct bnxt *bp = dev->data->dev_private; 2244 int rc; 2245 2246 rc = is_bnxt_in_error(bp); 2247 if (rc) 2248 return rc; 2249 2250 return bnxt_hwrm_port_led_cfg(bp, true); 2251 } 2252 2253 static int 2254 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2255 { 2256 struct bnxt *bp = dev->data->dev_private; 2257 int rc; 2258 2259 rc = is_bnxt_in_error(bp); 2260 if (rc) 2261 return rc; 2262 2263 return bnxt_hwrm_port_led_cfg(bp, false); 2264 } 2265 2266 static uint32_t 2267 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2268 { 2269 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2270 uint32_t desc = 0, raw_cons = 0, cons; 2271 struct bnxt_cp_ring_info *cpr; 2272 struct bnxt_rx_queue *rxq; 2273 struct rx_pkt_cmpl *rxcmp; 2274 int rc; 2275 2276 rc = is_bnxt_in_error(bp); 2277 if (rc) 2278 return rc; 2279 2280 rxq = dev->data->rx_queues[rx_queue_id]; 2281 cpr = rxq->cp_ring; 2282 raw_cons = cpr->cp_raw_cons; 2283 2284 while (1) { 2285 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2286 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2287 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2288 2289 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2290 break; 2291 } else { 2292 raw_cons++; 2293 desc++; 2294 } 2295 } 2296 2297 return desc; 2298 } 2299 2300 static int 2301 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2302 { 2303 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2304 struct bnxt_rx_ring_info *rxr; 2305 struct bnxt_cp_ring_info *cpr; 2306 struct bnxt_sw_rx_bd *rx_buf; 2307 struct rx_pkt_cmpl *rxcmp; 2308 uint32_t cons, cp_cons; 2309 int rc; 2310 2311 if (!rxq) 2312 return -EINVAL; 2313 2314 rc = is_bnxt_in_error(rxq->bp); 2315 if (rc) 2316 return rc; 2317 2318 cpr = rxq->cp_ring; 2319 rxr = rxq->rx_ring; 2320 2321 if (offset >= rxq->nb_rx_desc) 2322 return -EINVAL; 2323 2324 cons = RING_CMP(cpr->cp_ring_struct, offset); 2325 cp_cons = cpr->cp_raw_cons; 2326 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2327 2328 if (cons > cp_cons) { 2329 if (CMPL_VALID(rxcmp, cpr->valid)) 2330 return RTE_ETH_RX_DESC_DONE; 2331 } else { 2332 if (CMPL_VALID(rxcmp, !cpr->valid)) 2333 return RTE_ETH_RX_DESC_DONE; 2334 } 2335 rx_buf = &rxr->rx_buf_ring[cons]; 2336 if (rx_buf->mbuf == NULL) 2337 return RTE_ETH_RX_DESC_UNAVAIL; 2338 2339 2340 return RTE_ETH_RX_DESC_AVAIL; 2341 } 2342 2343 static int 2344 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2345 { 2346 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2347 struct bnxt_tx_ring_info *txr; 2348 struct bnxt_cp_ring_info *cpr; 2349 struct bnxt_sw_tx_bd *tx_buf; 2350 struct tx_pkt_cmpl *txcmp; 2351 uint32_t cons, cp_cons; 2352 int rc; 2353 2354 if (!txq) 2355 return -EINVAL; 2356 2357 rc = is_bnxt_in_error(txq->bp); 2358 if (rc) 2359 return rc; 2360 2361 cpr = txq->cp_ring; 2362 txr = txq->tx_ring; 2363 2364 if (offset >= txq->nb_tx_desc) 2365 return -EINVAL; 2366 2367 cons = RING_CMP(cpr->cp_ring_struct, offset); 2368 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2369 cp_cons = cpr->cp_raw_cons; 2370 2371 if (cons > cp_cons) { 2372 if (CMPL_VALID(txcmp, cpr->valid)) 2373 return RTE_ETH_TX_DESC_UNAVAIL; 2374 } else { 2375 if (CMPL_VALID(txcmp, !cpr->valid)) 2376 return RTE_ETH_TX_DESC_UNAVAIL; 2377 } 2378 tx_buf = &txr->tx_buf_ring[cons]; 2379 if (tx_buf->mbuf == NULL) 2380 return RTE_ETH_TX_DESC_DONE; 2381 2382 return RTE_ETH_TX_DESC_FULL; 2383 } 2384 2385 static struct bnxt_filter_info * 2386 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2387 struct rte_eth_ethertype_filter *efilter, 2388 struct bnxt_vnic_info *vnic0, 2389 struct bnxt_vnic_info *vnic, 2390 int *ret) 2391 { 2392 struct bnxt_filter_info *mfilter = NULL; 2393 int match = 0; 2394 *ret = 0; 2395 2396 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2397 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2398 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2399 " ethertype filter.", efilter->ether_type); 2400 *ret = -EINVAL; 2401 goto exit; 2402 } 2403 if (efilter->queue >= bp->rx_nr_rings) { 2404 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2405 *ret = -EINVAL; 2406 goto exit; 2407 } 2408 2409 vnic0 = &bp->vnic_info[0]; 2410 vnic = &bp->vnic_info[efilter->queue]; 2411 if (vnic == NULL) { 2412 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2413 *ret = -EINVAL; 2414 goto exit; 2415 } 2416 2417 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2418 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2419 if ((!memcmp(efilter->mac_addr.addr_bytes, 2420 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2421 mfilter->flags == 2422 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2423 mfilter->ethertype == efilter->ether_type)) { 2424 match = 1; 2425 break; 2426 } 2427 } 2428 } else { 2429 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2430 if ((!memcmp(efilter->mac_addr.addr_bytes, 2431 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2432 mfilter->ethertype == efilter->ether_type && 2433 mfilter->flags == 2434 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2435 match = 1; 2436 break; 2437 } 2438 } 2439 2440 if (match) 2441 *ret = -EEXIST; 2442 2443 exit: 2444 return mfilter; 2445 } 2446 2447 static int 2448 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2449 enum rte_filter_op filter_op, 2450 void *arg) 2451 { 2452 struct bnxt *bp = dev->data->dev_private; 2453 struct rte_eth_ethertype_filter *efilter = 2454 (struct rte_eth_ethertype_filter *)arg; 2455 struct bnxt_filter_info *bfilter, *filter1; 2456 struct bnxt_vnic_info *vnic, *vnic0; 2457 int ret; 2458 2459 if (filter_op == RTE_ETH_FILTER_NOP) 2460 return 0; 2461 2462 if (arg == NULL) { 2463 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2464 filter_op); 2465 return -EINVAL; 2466 } 2467 2468 vnic0 = &bp->vnic_info[0]; 2469 vnic = &bp->vnic_info[efilter->queue]; 2470 2471 switch (filter_op) { 2472 case RTE_ETH_FILTER_ADD: 2473 bnxt_match_and_validate_ether_filter(bp, efilter, 2474 vnic0, vnic, &ret); 2475 if (ret < 0) 2476 return ret; 2477 2478 bfilter = bnxt_get_unused_filter(bp); 2479 if (bfilter == NULL) { 2480 PMD_DRV_LOG(ERR, 2481 "Not enough resources for a new filter.\n"); 2482 return -ENOMEM; 2483 } 2484 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2485 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 2486 RTE_ETHER_ADDR_LEN); 2487 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 2488 RTE_ETHER_ADDR_LEN); 2489 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2490 bfilter->ethertype = efilter->ether_type; 2491 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2492 2493 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 2494 if (filter1 == NULL) { 2495 ret = -EINVAL; 2496 goto cleanup; 2497 } 2498 bfilter->enables |= 2499 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2500 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2501 2502 bfilter->dst_id = vnic->fw_vnic_id; 2503 2504 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2505 bfilter->flags = 2506 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2507 } 2508 2509 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2510 if (ret) 2511 goto cleanup; 2512 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2513 break; 2514 case RTE_ETH_FILTER_DELETE: 2515 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 2516 vnic0, vnic, &ret); 2517 if (ret == -EEXIST) { 2518 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 2519 2520 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 2521 next); 2522 bnxt_free_filter(bp, filter1); 2523 } else if (ret == 0) { 2524 PMD_DRV_LOG(ERR, "No matching filter found\n"); 2525 } 2526 break; 2527 default: 2528 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2529 ret = -EINVAL; 2530 goto error; 2531 } 2532 return ret; 2533 cleanup: 2534 bnxt_free_filter(bp, bfilter); 2535 error: 2536 return ret; 2537 } 2538 2539 static inline int 2540 parse_ntuple_filter(struct bnxt *bp, 2541 struct rte_eth_ntuple_filter *nfilter, 2542 struct bnxt_filter_info *bfilter) 2543 { 2544 uint32_t en = 0; 2545 2546 if (nfilter->queue >= bp->rx_nr_rings) { 2547 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 2548 return -EINVAL; 2549 } 2550 2551 switch (nfilter->dst_port_mask) { 2552 case UINT16_MAX: 2553 bfilter->dst_port_mask = -1; 2554 bfilter->dst_port = nfilter->dst_port; 2555 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 2556 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2557 break; 2558 default: 2559 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 2560 return -EINVAL; 2561 } 2562 2563 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2564 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2565 2566 switch (nfilter->proto_mask) { 2567 case UINT8_MAX: 2568 if (nfilter->proto == 17) /* IPPROTO_UDP */ 2569 bfilter->ip_protocol = 17; 2570 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 2571 bfilter->ip_protocol = 6; 2572 else 2573 return -EINVAL; 2574 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2575 break; 2576 default: 2577 PMD_DRV_LOG(ERR, "invalid protocol mask."); 2578 return -EINVAL; 2579 } 2580 2581 switch (nfilter->dst_ip_mask) { 2582 case UINT32_MAX: 2583 bfilter->dst_ipaddr_mask[0] = -1; 2584 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 2585 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 2586 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2587 break; 2588 default: 2589 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 2590 return -EINVAL; 2591 } 2592 2593 switch (nfilter->src_ip_mask) { 2594 case UINT32_MAX: 2595 bfilter->src_ipaddr_mask[0] = -1; 2596 bfilter->src_ipaddr[0] = nfilter->src_ip; 2597 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 2598 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2599 break; 2600 default: 2601 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2602 return -EINVAL; 2603 } 2604 2605 switch (nfilter->src_port_mask) { 2606 case UINT16_MAX: 2607 bfilter->src_port_mask = -1; 2608 bfilter->src_port = nfilter->src_port; 2609 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2610 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2611 break; 2612 default: 2613 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2614 return -EINVAL; 2615 } 2616 2617 //TODO Priority 2618 //nfilter->priority = (uint8_t)filter->priority; 2619 2620 bfilter->enables = en; 2621 return 0; 2622 } 2623 2624 static struct bnxt_filter_info* 2625 bnxt_match_ntuple_filter(struct bnxt *bp, 2626 struct bnxt_filter_info *bfilter, 2627 struct bnxt_vnic_info **mvnic) 2628 { 2629 struct bnxt_filter_info *mfilter = NULL; 2630 int i; 2631 2632 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2633 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2634 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2635 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2636 bfilter->src_ipaddr_mask[0] == 2637 mfilter->src_ipaddr_mask[0] && 2638 bfilter->src_port == mfilter->src_port && 2639 bfilter->src_port_mask == mfilter->src_port_mask && 2640 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2641 bfilter->dst_ipaddr_mask[0] == 2642 mfilter->dst_ipaddr_mask[0] && 2643 bfilter->dst_port == mfilter->dst_port && 2644 bfilter->dst_port_mask == mfilter->dst_port_mask && 2645 bfilter->flags == mfilter->flags && 2646 bfilter->enables == mfilter->enables) { 2647 if (mvnic) 2648 *mvnic = vnic; 2649 return mfilter; 2650 } 2651 } 2652 } 2653 return NULL; 2654 } 2655 2656 static int 2657 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2658 struct rte_eth_ntuple_filter *nfilter, 2659 enum rte_filter_op filter_op) 2660 { 2661 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2662 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2663 int ret; 2664 2665 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2666 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2667 return -EINVAL; 2668 } 2669 2670 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2671 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2672 return -EINVAL; 2673 } 2674 2675 bfilter = bnxt_get_unused_filter(bp); 2676 if (bfilter == NULL) { 2677 PMD_DRV_LOG(ERR, 2678 "Not enough resources for a new filter.\n"); 2679 return -ENOMEM; 2680 } 2681 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2682 if (ret < 0) 2683 goto free_filter; 2684 2685 vnic = &bp->vnic_info[nfilter->queue]; 2686 vnic0 = &bp->vnic_info[0]; 2687 filter1 = STAILQ_FIRST(&vnic0->filter); 2688 if (filter1 == NULL) { 2689 ret = -EINVAL; 2690 goto free_filter; 2691 } 2692 2693 bfilter->dst_id = vnic->fw_vnic_id; 2694 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2695 bfilter->enables |= 2696 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2697 bfilter->ethertype = 0x800; 2698 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2699 2700 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2701 2702 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2703 bfilter->dst_id == mfilter->dst_id) { 2704 PMD_DRV_LOG(ERR, "filter exists.\n"); 2705 ret = -EEXIST; 2706 goto free_filter; 2707 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2708 bfilter->dst_id != mfilter->dst_id) { 2709 mfilter->dst_id = vnic->fw_vnic_id; 2710 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2711 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2712 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2713 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2714 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2715 goto free_filter; 2716 } 2717 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2718 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2719 ret = -ENOENT; 2720 goto free_filter; 2721 } 2722 2723 if (filter_op == RTE_ETH_FILTER_ADD) { 2724 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2725 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2726 if (ret) 2727 goto free_filter; 2728 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2729 } else { 2730 if (mfilter == NULL) { 2731 /* This should not happen. But for Coverity! */ 2732 ret = -ENOENT; 2733 goto free_filter; 2734 } 2735 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2736 2737 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2738 bnxt_free_filter(bp, mfilter); 2739 mfilter->fw_l2_filter_id = -1; 2740 bnxt_free_filter(bp, bfilter); 2741 bfilter->fw_l2_filter_id = -1; 2742 } 2743 2744 return 0; 2745 free_filter: 2746 bfilter->fw_l2_filter_id = -1; 2747 bnxt_free_filter(bp, bfilter); 2748 return ret; 2749 } 2750 2751 static int 2752 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2753 enum rte_filter_op filter_op, 2754 void *arg) 2755 { 2756 struct bnxt *bp = dev->data->dev_private; 2757 int ret; 2758 2759 if (filter_op == RTE_ETH_FILTER_NOP) 2760 return 0; 2761 2762 if (arg == NULL) { 2763 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2764 filter_op); 2765 return -EINVAL; 2766 } 2767 2768 switch (filter_op) { 2769 case RTE_ETH_FILTER_ADD: 2770 ret = bnxt_cfg_ntuple_filter(bp, 2771 (struct rte_eth_ntuple_filter *)arg, 2772 filter_op); 2773 break; 2774 case RTE_ETH_FILTER_DELETE: 2775 ret = bnxt_cfg_ntuple_filter(bp, 2776 (struct rte_eth_ntuple_filter *)arg, 2777 filter_op); 2778 break; 2779 default: 2780 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2781 ret = -EINVAL; 2782 break; 2783 } 2784 return ret; 2785 } 2786 2787 static int 2788 bnxt_parse_fdir_filter(struct bnxt *bp, 2789 struct rte_eth_fdir_filter *fdir, 2790 struct bnxt_filter_info *filter) 2791 { 2792 enum rte_fdir_mode fdir_mode = 2793 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2794 struct bnxt_vnic_info *vnic0, *vnic; 2795 struct bnxt_filter_info *filter1; 2796 uint32_t en = 0; 2797 int i; 2798 2799 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2800 return -EINVAL; 2801 2802 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2803 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2804 2805 switch (fdir->input.flow_type) { 2806 case RTE_ETH_FLOW_IPV4: 2807 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2808 /* FALLTHROUGH */ 2809 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2810 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2811 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2812 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2813 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2814 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2815 filter->ip_addr_type = 2816 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2817 filter->src_ipaddr_mask[0] = 0xffffffff; 2818 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2819 filter->dst_ipaddr_mask[0] = 0xffffffff; 2820 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2821 filter->ethertype = 0x800; 2822 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2823 break; 2824 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2825 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2826 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2827 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2828 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2829 filter->dst_port_mask = 0xffff; 2830 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2831 filter->src_port_mask = 0xffff; 2832 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2833 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2834 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2835 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2836 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2837 filter->ip_protocol = 6; 2838 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2839 filter->ip_addr_type = 2840 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2841 filter->src_ipaddr_mask[0] = 0xffffffff; 2842 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2843 filter->dst_ipaddr_mask[0] = 0xffffffff; 2844 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2845 filter->ethertype = 0x800; 2846 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2847 break; 2848 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2849 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2850 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2851 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2852 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2853 filter->dst_port_mask = 0xffff; 2854 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2855 filter->src_port_mask = 0xffff; 2856 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2857 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2858 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2859 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2860 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2861 filter->ip_protocol = 17; 2862 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2863 filter->ip_addr_type = 2864 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2865 filter->src_ipaddr_mask[0] = 0xffffffff; 2866 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2867 filter->dst_ipaddr_mask[0] = 0xffffffff; 2868 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2869 filter->ethertype = 0x800; 2870 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2871 break; 2872 case RTE_ETH_FLOW_IPV6: 2873 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2874 /* FALLTHROUGH */ 2875 filter->ip_addr_type = 2876 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2877 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2878 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2879 rte_memcpy(filter->src_ipaddr, 2880 fdir->input.flow.ipv6_flow.src_ip, 16); 2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2882 rte_memcpy(filter->dst_ipaddr, 2883 fdir->input.flow.ipv6_flow.dst_ip, 16); 2884 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2885 memset(filter->dst_ipaddr_mask, 0xff, 16); 2886 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2887 memset(filter->src_ipaddr_mask, 0xff, 16); 2888 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2889 filter->ethertype = 0x86dd; 2890 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2891 break; 2892 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2893 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2894 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2895 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2897 filter->dst_port_mask = 0xffff; 2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2899 filter->src_port_mask = 0xffff; 2900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2901 filter->ip_addr_type = 2902 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2903 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2904 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2905 rte_memcpy(filter->src_ipaddr, 2906 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2907 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2908 rte_memcpy(filter->dst_ipaddr, 2909 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2910 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2911 memset(filter->dst_ipaddr_mask, 0xff, 16); 2912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2913 memset(filter->src_ipaddr_mask, 0xff, 16); 2914 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2915 filter->ethertype = 0x86dd; 2916 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2917 break; 2918 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2919 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2921 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2923 filter->dst_port_mask = 0xffff; 2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2925 filter->src_port_mask = 0xffff; 2926 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2927 filter->ip_addr_type = 2928 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2929 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2930 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2931 rte_memcpy(filter->src_ipaddr, 2932 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2933 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2934 rte_memcpy(filter->dst_ipaddr, 2935 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2936 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2937 memset(filter->dst_ipaddr_mask, 0xff, 16); 2938 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2939 memset(filter->src_ipaddr_mask, 0xff, 16); 2940 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2941 filter->ethertype = 0x86dd; 2942 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2943 break; 2944 case RTE_ETH_FLOW_L2_PAYLOAD: 2945 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2946 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2947 break; 2948 case RTE_ETH_FLOW_VXLAN: 2949 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2950 return -EINVAL; 2951 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2952 filter->tunnel_type = 2953 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2954 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2955 break; 2956 case RTE_ETH_FLOW_NVGRE: 2957 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2958 return -EINVAL; 2959 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2960 filter->tunnel_type = 2961 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2962 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2963 break; 2964 case RTE_ETH_FLOW_UNKNOWN: 2965 case RTE_ETH_FLOW_RAW: 2966 case RTE_ETH_FLOW_FRAG_IPV4: 2967 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2968 case RTE_ETH_FLOW_FRAG_IPV6: 2969 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2970 case RTE_ETH_FLOW_IPV6_EX: 2971 case RTE_ETH_FLOW_IPV6_TCP_EX: 2972 case RTE_ETH_FLOW_IPV6_UDP_EX: 2973 case RTE_ETH_FLOW_GENEVE: 2974 /* FALLTHROUGH */ 2975 default: 2976 return -EINVAL; 2977 } 2978 2979 vnic0 = &bp->vnic_info[0]; 2980 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2981 if (vnic == NULL) { 2982 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2983 return -EINVAL; 2984 } 2985 2986 2987 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2988 rte_memcpy(filter->dst_macaddr, 2989 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2990 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2991 } 2992 2993 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2994 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2995 filter1 = STAILQ_FIRST(&vnic0->filter); 2996 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2997 } else { 2998 filter->dst_id = vnic->fw_vnic_id; 2999 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3000 if (filter->dst_macaddr[i] == 0x00) 3001 filter1 = STAILQ_FIRST(&vnic0->filter); 3002 else 3003 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 3004 } 3005 3006 if (filter1 == NULL) 3007 return -EINVAL; 3008 3009 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3010 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3011 3012 filter->enables = en; 3013 3014 return 0; 3015 } 3016 3017 static struct bnxt_filter_info * 3018 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 3019 struct bnxt_vnic_info **mvnic) 3020 { 3021 struct bnxt_filter_info *mf = NULL; 3022 int i; 3023 3024 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3025 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3026 3027 STAILQ_FOREACH(mf, &vnic->filter, next) { 3028 if (mf->filter_type == nf->filter_type && 3029 mf->flags == nf->flags && 3030 mf->src_port == nf->src_port && 3031 mf->src_port_mask == nf->src_port_mask && 3032 mf->dst_port == nf->dst_port && 3033 mf->dst_port_mask == nf->dst_port_mask && 3034 mf->ip_protocol == nf->ip_protocol && 3035 mf->ip_addr_type == nf->ip_addr_type && 3036 mf->ethertype == nf->ethertype && 3037 mf->vni == nf->vni && 3038 mf->tunnel_type == nf->tunnel_type && 3039 mf->l2_ovlan == nf->l2_ovlan && 3040 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 3041 mf->l2_ivlan == nf->l2_ivlan && 3042 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 3043 !memcmp(mf->l2_addr, nf->l2_addr, 3044 RTE_ETHER_ADDR_LEN) && 3045 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 3046 RTE_ETHER_ADDR_LEN) && 3047 !memcmp(mf->src_macaddr, nf->src_macaddr, 3048 RTE_ETHER_ADDR_LEN) && 3049 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 3050 RTE_ETHER_ADDR_LEN) && 3051 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 3052 sizeof(nf->src_ipaddr)) && 3053 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 3054 sizeof(nf->src_ipaddr_mask)) && 3055 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 3056 sizeof(nf->dst_ipaddr)) && 3057 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 3058 sizeof(nf->dst_ipaddr_mask))) { 3059 if (mvnic) 3060 *mvnic = vnic; 3061 return mf; 3062 } 3063 } 3064 } 3065 return NULL; 3066 } 3067 3068 static int 3069 bnxt_fdir_filter(struct rte_eth_dev *dev, 3070 enum rte_filter_op filter_op, 3071 void *arg) 3072 { 3073 struct bnxt *bp = dev->data->dev_private; 3074 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 3075 struct bnxt_filter_info *filter, *match; 3076 struct bnxt_vnic_info *vnic, *mvnic; 3077 int ret = 0, i; 3078 3079 if (filter_op == RTE_ETH_FILTER_NOP) 3080 return 0; 3081 3082 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 3083 return -EINVAL; 3084 3085 switch (filter_op) { 3086 case RTE_ETH_FILTER_ADD: 3087 case RTE_ETH_FILTER_DELETE: 3088 /* FALLTHROUGH */ 3089 filter = bnxt_get_unused_filter(bp); 3090 if (filter == NULL) { 3091 PMD_DRV_LOG(ERR, 3092 "Not enough resources for a new flow.\n"); 3093 return -ENOMEM; 3094 } 3095 3096 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 3097 if (ret != 0) 3098 goto free_filter; 3099 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3100 3101 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3102 vnic = &bp->vnic_info[0]; 3103 else 3104 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3105 3106 match = bnxt_match_fdir(bp, filter, &mvnic); 3107 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 3108 if (match->dst_id == vnic->fw_vnic_id) { 3109 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 3110 ret = -EEXIST; 3111 goto free_filter; 3112 } else { 3113 match->dst_id = vnic->fw_vnic_id; 3114 ret = bnxt_hwrm_set_ntuple_filter(bp, 3115 match->dst_id, 3116 match); 3117 STAILQ_REMOVE(&mvnic->filter, match, 3118 bnxt_filter_info, next); 3119 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 3120 PMD_DRV_LOG(ERR, 3121 "Filter with matching pattern exist\n"); 3122 PMD_DRV_LOG(ERR, 3123 "Updated it to new destination q\n"); 3124 goto free_filter; 3125 } 3126 } 3127 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3128 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 3129 ret = -ENOENT; 3130 goto free_filter; 3131 } 3132 3133 if (filter_op == RTE_ETH_FILTER_ADD) { 3134 ret = bnxt_hwrm_set_ntuple_filter(bp, 3135 filter->dst_id, 3136 filter); 3137 if (ret) 3138 goto free_filter; 3139 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 3140 } else { 3141 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 3142 STAILQ_REMOVE(&vnic->filter, match, 3143 bnxt_filter_info, next); 3144 bnxt_free_filter(bp, match); 3145 filter->fw_l2_filter_id = -1; 3146 bnxt_free_filter(bp, filter); 3147 } 3148 break; 3149 case RTE_ETH_FILTER_FLUSH: 3150 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3151 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3152 3153 STAILQ_FOREACH(filter, &vnic->filter, next) { 3154 if (filter->filter_type == 3155 HWRM_CFA_NTUPLE_FILTER) { 3156 ret = 3157 bnxt_hwrm_clear_ntuple_filter(bp, 3158 filter); 3159 STAILQ_REMOVE(&vnic->filter, filter, 3160 bnxt_filter_info, next); 3161 } 3162 } 3163 } 3164 return ret; 3165 case RTE_ETH_FILTER_UPDATE: 3166 case RTE_ETH_FILTER_STATS: 3167 case RTE_ETH_FILTER_INFO: 3168 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 3169 break; 3170 default: 3171 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 3172 ret = -EINVAL; 3173 break; 3174 } 3175 return ret; 3176 3177 free_filter: 3178 filter->fw_l2_filter_id = -1; 3179 bnxt_free_filter(bp, filter); 3180 return ret; 3181 } 3182 3183 static int 3184 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 3185 enum rte_filter_type filter_type, 3186 enum rte_filter_op filter_op, void *arg) 3187 { 3188 int ret = 0; 3189 3190 ret = is_bnxt_in_error(dev->data->dev_private); 3191 if (ret) 3192 return ret; 3193 3194 switch (filter_type) { 3195 case RTE_ETH_FILTER_TUNNEL: 3196 PMD_DRV_LOG(ERR, 3197 "filter type: %d: To be implemented\n", filter_type); 3198 break; 3199 case RTE_ETH_FILTER_FDIR: 3200 ret = bnxt_fdir_filter(dev, filter_op, arg); 3201 break; 3202 case RTE_ETH_FILTER_NTUPLE: 3203 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3204 break; 3205 case RTE_ETH_FILTER_ETHERTYPE: 3206 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3207 break; 3208 case RTE_ETH_FILTER_GENERIC: 3209 if (filter_op != RTE_ETH_FILTER_GET) 3210 return -EINVAL; 3211 *(const void **)arg = &bnxt_flow_ops; 3212 break; 3213 default: 3214 PMD_DRV_LOG(ERR, 3215 "Filter type (%d) not supported", filter_type); 3216 ret = -EINVAL; 3217 break; 3218 } 3219 return ret; 3220 } 3221 3222 static const uint32_t * 3223 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3224 { 3225 static const uint32_t ptypes[] = { 3226 RTE_PTYPE_L2_ETHER_VLAN, 3227 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3228 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3229 RTE_PTYPE_L4_ICMP, 3230 RTE_PTYPE_L4_TCP, 3231 RTE_PTYPE_L4_UDP, 3232 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3233 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3234 RTE_PTYPE_INNER_L4_ICMP, 3235 RTE_PTYPE_INNER_L4_TCP, 3236 RTE_PTYPE_INNER_L4_UDP, 3237 RTE_PTYPE_UNKNOWN 3238 }; 3239 3240 if (!dev->rx_pkt_burst) 3241 return NULL; 3242 3243 return ptypes; 3244 } 3245 3246 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3247 int reg_win) 3248 { 3249 uint32_t reg_base = *reg_arr & 0xfffff000; 3250 uint32_t win_off; 3251 int i; 3252 3253 for (i = 0; i < count; i++) { 3254 if ((reg_arr[i] & 0xfffff000) != reg_base) 3255 return -ERANGE; 3256 } 3257 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3258 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3259 return 0; 3260 } 3261 3262 static int bnxt_map_ptp_regs(struct bnxt *bp) 3263 { 3264 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3265 uint32_t *reg_arr; 3266 int rc, i; 3267 3268 reg_arr = ptp->rx_regs; 3269 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3270 if (rc) 3271 return rc; 3272 3273 reg_arr = ptp->tx_regs; 3274 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3275 if (rc) 3276 return rc; 3277 3278 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3279 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3280 3281 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3282 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3283 3284 return 0; 3285 } 3286 3287 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3288 { 3289 rte_write32(0, (uint8_t *)bp->bar0 + 3290 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3291 rte_write32(0, (uint8_t *)bp->bar0 + 3292 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3293 } 3294 3295 static uint64_t bnxt_cc_read(struct bnxt *bp) 3296 { 3297 uint64_t ns; 3298 3299 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3300 BNXT_GRCPF_REG_SYNC_TIME)); 3301 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3302 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3303 return ns; 3304 } 3305 3306 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3307 { 3308 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3309 uint32_t fifo; 3310 3311 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3312 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3313 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3314 return -EAGAIN; 3315 3316 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3317 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3318 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3319 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3320 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3321 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3322 3323 return 0; 3324 } 3325 3326 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3327 { 3328 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3329 struct bnxt_pf_info *pf = &bp->pf; 3330 uint16_t port_id; 3331 uint32_t fifo; 3332 3333 if (!ptp) 3334 return -ENODEV; 3335 3336 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3337 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3338 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3339 return -EAGAIN; 3340 3341 port_id = pf->port_id; 3342 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3343 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3344 3345 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3346 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3347 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3348 /* bnxt_clr_rx_ts(bp); TBD */ 3349 return -EBUSY; 3350 } 3351 3352 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3353 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3354 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3355 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3356 3357 return 0; 3358 } 3359 3360 static int 3361 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3362 { 3363 uint64_t ns; 3364 struct bnxt *bp = dev->data->dev_private; 3365 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3366 3367 if (!ptp) 3368 return 0; 3369 3370 ns = rte_timespec_to_ns(ts); 3371 /* Set the timecounters to a new value. */ 3372 ptp->tc.nsec = ns; 3373 3374 return 0; 3375 } 3376 3377 static int 3378 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3379 { 3380 struct bnxt *bp = dev->data->dev_private; 3381 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3382 uint64_t ns, systime_cycles = 0; 3383 int rc = 0; 3384 3385 if (!ptp) 3386 return 0; 3387 3388 if (BNXT_CHIP_THOR(bp)) 3389 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3390 &systime_cycles); 3391 else 3392 systime_cycles = bnxt_cc_read(bp); 3393 3394 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3395 *ts = rte_ns_to_timespec(ns); 3396 3397 return rc; 3398 } 3399 static int 3400 bnxt_timesync_enable(struct rte_eth_dev *dev) 3401 { 3402 struct bnxt *bp = dev->data->dev_private; 3403 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3404 uint32_t shift = 0; 3405 int rc; 3406 3407 if (!ptp) 3408 return 0; 3409 3410 ptp->rx_filter = 1; 3411 ptp->tx_tstamp_en = 1; 3412 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3413 3414 rc = bnxt_hwrm_ptp_cfg(bp); 3415 if (rc) 3416 return rc; 3417 3418 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3419 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3420 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3421 3422 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3423 ptp->tc.cc_shift = shift; 3424 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3425 3426 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3427 ptp->rx_tstamp_tc.cc_shift = shift; 3428 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3429 3430 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3431 ptp->tx_tstamp_tc.cc_shift = shift; 3432 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3433 3434 if (!BNXT_CHIP_THOR(bp)) 3435 bnxt_map_ptp_regs(bp); 3436 3437 return 0; 3438 } 3439 3440 static int 3441 bnxt_timesync_disable(struct rte_eth_dev *dev) 3442 { 3443 struct bnxt *bp = dev->data->dev_private; 3444 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3445 3446 if (!ptp) 3447 return 0; 3448 3449 ptp->rx_filter = 0; 3450 ptp->tx_tstamp_en = 0; 3451 ptp->rxctl = 0; 3452 3453 bnxt_hwrm_ptp_cfg(bp); 3454 3455 if (!BNXT_CHIP_THOR(bp)) 3456 bnxt_unmap_ptp_regs(bp); 3457 3458 return 0; 3459 } 3460 3461 static int 3462 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3463 struct timespec *timestamp, 3464 uint32_t flags __rte_unused) 3465 { 3466 struct bnxt *bp = dev->data->dev_private; 3467 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3468 uint64_t rx_tstamp_cycles = 0; 3469 uint64_t ns; 3470 3471 if (!ptp) 3472 return 0; 3473 3474 if (BNXT_CHIP_THOR(bp)) 3475 rx_tstamp_cycles = ptp->rx_timestamp; 3476 else 3477 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3478 3479 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3480 *timestamp = rte_ns_to_timespec(ns); 3481 return 0; 3482 } 3483 3484 static int 3485 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3486 struct timespec *timestamp) 3487 { 3488 struct bnxt *bp = dev->data->dev_private; 3489 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3490 uint64_t tx_tstamp_cycles = 0; 3491 uint64_t ns; 3492 int rc = 0; 3493 3494 if (!ptp) 3495 return 0; 3496 3497 if (BNXT_CHIP_THOR(bp)) 3498 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3499 &tx_tstamp_cycles); 3500 else 3501 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3502 3503 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3504 *timestamp = rte_ns_to_timespec(ns); 3505 3506 return rc; 3507 } 3508 3509 static int 3510 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3511 { 3512 struct bnxt *bp = dev->data->dev_private; 3513 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3514 3515 if (!ptp) 3516 return 0; 3517 3518 ptp->tc.nsec += delta; 3519 3520 return 0; 3521 } 3522 3523 static int 3524 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3525 { 3526 struct bnxt *bp = dev->data->dev_private; 3527 int rc; 3528 uint32_t dir_entries; 3529 uint32_t entry_length; 3530 3531 rc = is_bnxt_in_error(bp); 3532 if (rc) 3533 return rc; 3534 3535 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 3536 bp->pdev->addr.domain, bp->pdev->addr.bus, 3537 bp->pdev->addr.devid, bp->pdev->addr.function); 3538 3539 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3540 if (rc != 0) 3541 return rc; 3542 3543 return dir_entries * entry_length; 3544 } 3545 3546 static int 3547 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3548 struct rte_dev_eeprom_info *in_eeprom) 3549 { 3550 struct bnxt *bp = dev->data->dev_private; 3551 uint32_t index; 3552 uint32_t offset; 3553 int rc; 3554 3555 rc = is_bnxt_in_error(bp); 3556 if (rc) 3557 return rc; 3558 3559 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3560 "len = %d\n", bp->pdev->addr.domain, 3561 bp->pdev->addr.bus, bp->pdev->addr.devid, 3562 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3563 3564 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3565 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3566 in_eeprom->data); 3567 3568 index = in_eeprom->offset >> 24; 3569 offset = in_eeprom->offset & 0xffffff; 3570 3571 if (index != 0) 3572 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3573 in_eeprom->length, in_eeprom->data); 3574 3575 return 0; 3576 } 3577 3578 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3579 { 3580 switch (dir_type) { 3581 case BNX_DIR_TYPE_CHIMP_PATCH: 3582 case BNX_DIR_TYPE_BOOTCODE: 3583 case BNX_DIR_TYPE_BOOTCODE_2: 3584 case BNX_DIR_TYPE_APE_FW: 3585 case BNX_DIR_TYPE_APE_PATCH: 3586 case BNX_DIR_TYPE_KONG_FW: 3587 case BNX_DIR_TYPE_KONG_PATCH: 3588 case BNX_DIR_TYPE_BONO_FW: 3589 case BNX_DIR_TYPE_BONO_PATCH: 3590 /* FALLTHROUGH */ 3591 return true; 3592 } 3593 3594 return false; 3595 } 3596 3597 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3598 { 3599 switch (dir_type) { 3600 case BNX_DIR_TYPE_AVS: 3601 case BNX_DIR_TYPE_EXP_ROM_MBA: 3602 case BNX_DIR_TYPE_PCIE: 3603 case BNX_DIR_TYPE_TSCF_UCODE: 3604 case BNX_DIR_TYPE_EXT_PHY: 3605 case BNX_DIR_TYPE_CCM: 3606 case BNX_DIR_TYPE_ISCSI_BOOT: 3607 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3608 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3609 /* FALLTHROUGH */ 3610 return true; 3611 } 3612 3613 return false; 3614 } 3615 3616 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3617 { 3618 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3619 bnxt_dir_type_is_other_exec_format(dir_type); 3620 } 3621 3622 static int 3623 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3624 struct rte_dev_eeprom_info *in_eeprom) 3625 { 3626 struct bnxt *bp = dev->data->dev_private; 3627 uint8_t index, dir_op; 3628 uint16_t type, ext, ordinal, attr; 3629 int rc; 3630 3631 rc = is_bnxt_in_error(bp); 3632 if (rc) 3633 return rc; 3634 3635 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3636 "len = %d\n", bp->pdev->addr.domain, 3637 bp->pdev->addr.bus, bp->pdev->addr.devid, 3638 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3639 3640 if (!BNXT_PF(bp)) { 3641 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3642 return -EINVAL; 3643 } 3644 3645 type = in_eeprom->magic >> 16; 3646 3647 if (type == 0xffff) { /* special value for directory operations */ 3648 index = in_eeprom->magic & 0xff; 3649 dir_op = in_eeprom->magic >> 8; 3650 if (index == 0) 3651 return -EINVAL; 3652 switch (dir_op) { 3653 case 0x0e: /* erase */ 3654 if (in_eeprom->offset != ~in_eeprom->magic) 3655 return -EINVAL; 3656 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3657 default: 3658 return -EINVAL; 3659 } 3660 } 3661 3662 /* Create or re-write an NVM item: */ 3663 if (bnxt_dir_type_is_executable(type) == true) 3664 return -EOPNOTSUPP; 3665 ext = in_eeprom->magic & 0xffff; 3666 ordinal = in_eeprom->offset >> 16; 3667 attr = in_eeprom->offset & 0xffff; 3668 3669 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3670 in_eeprom->data, in_eeprom->length); 3671 } 3672 3673 /* 3674 * Initialization 3675 */ 3676 3677 static const struct eth_dev_ops bnxt_dev_ops = { 3678 .dev_infos_get = bnxt_dev_info_get_op, 3679 .dev_close = bnxt_dev_close_op, 3680 .dev_configure = bnxt_dev_configure_op, 3681 .dev_start = bnxt_dev_start_op, 3682 .dev_stop = bnxt_dev_stop_op, 3683 .dev_set_link_up = bnxt_dev_set_link_up_op, 3684 .dev_set_link_down = bnxt_dev_set_link_down_op, 3685 .stats_get = bnxt_stats_get_op, 3686 .stats_reset = bnxt_stats_reset_op, 3687 .rx_queue_setup = bnxt_rx_queue_setup_op, 3688 .rx_queue_release = bnxt_rx_queue_release_op, 3689 .tx_queue_setup = bnxt_tx_queue_setup_op, 3690 .tx_queue_release = bnxt_tx_queue_release_op, 3691 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3692 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3693 .reta_update = bnxt_reta_update_op, 3694 .reta_query = bnxt_reta_query_op, 3695 .rss_hash_update = bnxt_rss_hash_update_op, 3696 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3697 .link_update = bnxt_link_update_op, 3698 .promiscuous_enable = bnxt_promiscuous_enable_op, 3699 .promiscuous_disable = bnxt_promiscuous_disable_op, 3700 .allmulticast_enable = bnxt_allmulticast_enable_op, 3701 .allmulticast_disable = bnxt_allmulticast_disable_op, 3702 .mac_addr_add = bnxt_mac_addr_add_op, 3703 .mac_addr_remove = bnxt_mac_addr_remove_op, 3704 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3705 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3706 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3707 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3708 .vlan_filter_set = bnxt_vlan_filter_set_op, 3709 .vlan_offload_set = bnxt_vlan_offload_set_op, 3710 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3711 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3712 .mtu_set = bnxt_mtu_set_op, 3713 .mac_addr_set = bnxt_set_default_mac_addr_op, 3714 .xstats_get = bnxt_dev_xstats_get_op, 3715 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3716 .xstats_reset = bnxt_dev_xstats_reset_op, 3717 .fw_version_get = bnxt_fw_version_get, 3718 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3719 .rxq_info_get = bnxt_rxq_info_get_op, 3720 .txq_info_get = bnxt_txq_info_get_op, 3721 .dev_led_on = bnxt_dev_led_on_op, 3722 .dev_led_off = bnxt_dev_led_off_op, 3723 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3724 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3725 .rx_queue_count = bnxt_rx_queue_count_op, 3726 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3727 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3728 .rx_queue_start = bnxt_rx_queue_start, 3729 .rx_queue_stop = bnxt_rx_queue_stop, 3730 .tx_queue_start = bnxt_tx_queue_start, 3731 .tx_queue_stop = bnxt_tx_queue_stop, 3732 .filter_ctrl = bnxt_filter_ctrl_op, 3733 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3734 .get_eeprom_length = bnxt_get_eeprom_length_op, 3735 .get_eeprom = bnxt_get_eeprom_op, 3736 .set_eeprom = bnxt_set_eeprom_op, 3737 .timesync_enable = bnxt_timesync_enable, 3738 .timesync_disable = bnxt_timesync_disable, 3739 .timesync_read_time = bnxt_timesync_read_time, 3740 .timesync_write_time = bnxt_timesync_write_time, 3741 .timesync_adjust_time = bnxt_timesync_adjust_time, 3742 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3743 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3744 }; 3745 3746 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3747 { 3748 uint32_t offset; 3749 3750 /* Only pre-map the reset GRC registers using window 3 */ 3751 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3752 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3753 3754 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3755 3756 return offset; 3757 } 3758 3759 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3760 { 3761 struct bnxt_error_recovery_info *info = bp->recovery_info; 3762 uint32_t reg_base = 0xffffffff; 3763 int i; 3764 3765 /* Only pre-map the monitoring GRC registers using window 2 */ 3766 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3767 uint32_t reg = info->status_regs[i]; 3768 3769 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3770 continue; 3771 3772 if (reg_base == 0xffffffff) 3773 reg_base = reg & 0xfffff000; 3774 if ((reg & 0xfffff000) != reg_base) 3775 return -ERANGE; 3776 3777 /* Use mask 0xffc as the Lower 2 bits indicates 3778 * address space location 3779 */ 3780 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3781 (reg & 0xffc); 3782 } 3783 3784 if (reg_base == 0xffffffff) 3785 return 0; 3786 3787 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3788 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3789 3790 return 0; 3791 } 3792 3793 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3794 { 3795 struct bnxt_error_recovery_info *info = bp->recovery_info; 3796 uint32_t delay = info->delay_after_reset[index]; 3797 uint32_t val = info->reset_reg_val[index]; 3798 uint32_t reg = info->reset_reg[index]; 3799 uint32_t type, offset; 3800 3801 type = BNXT_FW_STATUS_REG_TYPE(reg); 3802 offset = BNXT_FW_STATUS_REG_OFF(reg); 3803 3804 switch (type) { 3805 case BNXT_FW_STATUS_REG_TYPE_CFG: 3806 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3807 break; 3808 case BNXT_FW_STATUS_REG_TYPE_GRC: 3809 offset = bnxt_map_reset_regs(bp, offset); 3810 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3811 break; 3812 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3813 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3814 break; 3815 } 3816 /* wait on a specific interval of time until core reset is complete */ 3817 if (delay) 3818 rte_delay_ms(delay); 3819 } 3820 3821 static void bnxt_dev_cleanup(struct bnxt *bp) 3822 { 3823 bnxt_set_hwrm_link_config(bp, false); 3824 bp->link_info.link_up = 0; 3825 if (bp->dev_stopped == 0) 3826 bnxt_dev_stop_op(bp->eth_dev); 3827 3828 bnxt_uninit_resources(bp, true); 3829 } 3830 3831 static int bnxt_restore_filters(struct bnxt *bp) 3832 { 3833 struct rte_eth_dev *dev = bp->eth_dev; 3834 int ret = 0; 3835 3836 if (dev->data->all_multicast) 3837 ret = bnxt_allmulticast_enable_op(dev); 3838 if (dev->data->promiscuous) 3839 ret = bnxt_promiscuous_enable_op(dev); 3840 3841 /* TODO restore other filters as well */ 3842 return ret; 3843 } 3844 3845 static void bnxt_dev_recover(void *arg) 3846 { 3847 struct bnxt *bp = arg; 3848 int timeout = bp->fw_reset_max_msecs; 3849 int rc = 0; 3850 3851 /* Clear Error flag so that device re-init should happen */ 3852 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 3853 3854 do { 3855 rc = bnxt_hwrm_ver_get(bp); 3856 if (rc == 0) 3857 break; 3858 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 3859 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 3860 } while (rc && timeout); 3861 3862 if (rc) { 3863 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 3864 goto err; 3865 } 3866 3867 rc = bnxt_init_resources(bp, true); 3868 if (rc) { 3869 PMD_DRV_LOG(ERR, 3870 "Failed to initialize resources after reset\n"); 3871 goto err; 3872 } 3873 /* clear reset flag as the device is initialized now */ 3874 bp->flags &= ~BNXT_FLAG_FW_RESET; 3875 3876 rc = bnxt_dev_start_op(bp->eth_dev); 3877 if (rc) { 3878 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 3879 goto err; 3880 } 3881 3882 rc = bnxt_restore_filters(bp); 3883 if (rc) 3884 goto err; 3885 3886 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 3887 return; 3888 err: 3889 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3890 bnxt_uninit_resources(bp, false); 3891 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 3892 } 3893 3894 void bnxt_dev_reset_and_resume(void *arg) 3895 { 3896 struct bnxt *bp = arg; 3897 int rc; 3898 3899 bnxt_dev_cleanup(bp); 3900 3901 bnxt_wait_for_device_shutdown(bp); 3902 3903 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 3904 bnxt_dev_recover, (void *)bp); 3905 if (rc) 3906 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 3907 } 3908 3909 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 3910 { 3911 struct bnxt_error_recovery_info *info = bp->recovery_info; 3912 uint32_t reg = info->status_regs[index]; 3913 uint32_t type, offset, val = 0; 3914 3915 type = BNXT_FW_STATUS_REG_TYPE(reg); 3916 offset = BNXT_FW_STATUS_REG_OFF(reg); 3917 3918 switch (type) { 3919 case BNXT_FW_STATUS_REG_TYPE_CFG: 3920 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 3921 break; 3922 case BNXT_FW_STATUS_REG_TYPE_GRC: 3923 offset = info->mapped_status_regs[index]; 3924 /* FALLTHROUGH */ 3925 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3926 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3927 offset)); 3928 break; 3929 } 3930 3931 return val; 3932 } 3933 3934 static int bnxt_fw_reset_all(struct bnxt *bp) 3935 { 3936 struct bnxt_error_recovery_info *info = bp->recovery_info; 3937 uint32_t i; 3938 int rc = 0; 3939 3940 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3941 /* Reset through master function driver */ 3942 for (i = 0; i < info->reg_array_cnt; i++) 3943 bnxt_write_fw_reset_reg(bp, i); 3944 /* Wait for time specified by FW after triggering reset */ 3945 rte_delay_ms(info->master_func_wait_period_after_reset); 3946 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 3947 /* Reset with the help of Kong processor */ 3948 rc = bnxt_hwrm_fw_reset(bp); 3949 if (rc) 3950 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 3951 } 3952 3953 return rc; 3954 } 3955 3956 static void bnxt_fw_reset_cb(void *arg) 3957 { 3958 struct bnxt *bp = arg; 3959 struct bnxt_error_recovery_info *info = bp->recovery_info; 3960 int rc = 0; 3961 3962 /* Only Master function can do FW reset */ 3963 if (bnxt_is_master_func(bp) && 3964 bnxt_is_recovery_enabled(bp)) { 3965 rc = bnxt_fw_reset_all(bp); 3966 if (rc) { 3967 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 3968 return; 3969 } 3970 } 3971 3972 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 3973 * EXCEPTION_FATAL_ASYNC event to all the functions 3974 * (including MASTER FUNC). After receiving this Async, all the active 3975 * drivers should treat this case as FW initiated recovery 3976 */ 3977 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3978 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 3979 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 3980 3981 /* To recover from error */ 3982 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 3983 (void *)bp); 3984 } 3985 } 3986 3987 /* Driver should poll FW heartbeat, reset_counter with the frequency 3988 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 3989 * When the driver detects heartbeat stop or change in reset_counter, 3990 * it has to trigger a reset to recover from the error condition. 3991 * A “master PF” is the function who will have the privilege to 3992 * initiate the chimp reset. The master PF will be elected by the 3993 * firmware and will be notified through async message. 3994 */ 3995 static void bnxt_check_fw_health(void *arg) 3996 { 3997 struct bnxt *bp = arg; 3998 struct bnxt_error_recovery_info *info = bp->recovery_info; 3999 uint32_t val = 0, wait_msec; 4000 4001 if (!info || !bnxt_is_recovery_enabled(bp) || 4002 is_bnxt_in_error(bp)) 4003 return; 4004 4005 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4006 if (val == info->last_heart_beat) 4007 goto reset; 4008 4009 info->last_heart_beat = val; 4010 4011 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4012 if (val != info->last_reset_counter) 4013 goto reset; 4014 4015 info->last_reset_counter = val; 4016 4017 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4018 bnxt_check_fw_health, (void *)bp); 4019 4020 return; 4021 reset: 4022 /* Stop DMA to/from device */ 4023 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4024 bp->flags |= BNXT_FLAG_FW_RESET; 4025 4026 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4027 4028 if (bnxt_is_master_func(bp)) 4029 wait_msec = info->master_func_wait_period; 4030 else 4031 wait_msec = info->normal_func_wait_period; 4032 4033 rte_eal_alarm_set(US_PER_MS * wait_msec, 4034 bnxt_fw_reset_cb, (void *)bp); 4035 } 4036 4037 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4038 { 4039 uint32_t polling_freq; 4040 4041 if (!bnxt_is_recovery_enabled(bp)) 4042 return; 4043 4044 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4045 return; 4046 4047 polling_freq = bp->recovery_info->driver_polling_freq; 4048 4049 rte_eal_alarm_set(US_PER_MS * polling_freq, 4050 bnxt_check_fw_health, (void *)bp); 4051 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4052 } 4053 4054 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4055 { 4056 if (!bnxt_is_recovery_enabled(bp)) 4057 return; 4058 4059 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4060 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4061 } 4062 4063 static bool bnxt_vf_pciid(uint16_t id) 4064 { 4065 if (id == BROADCOM_DEV_ID_57304_VF || 4066 id == BROADCOM_DEV_ID_57406_VF || 4067 id == BROADCOM_DEV_ID_5731X_VF || 4068 id == BROADCOM_DEV_ID_5741X_VF || 4069 id == BROADCOM_DEV_ID_57414_VF || 4070 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 4071 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 || 4072 id == BROADCOM_DEV_ID_58802_VF || 4073 id == BROADCOM_DEV_ID_57500_VF1 || 4074 id == BROADCOM_DEV_ID_57500_VF2) 4075 return true; 4076 return false; 4077 } 4078 4079 bool bnxt_stratus_device(struct bnxt *bp) 4080 { 4081 uint16_t id = bp->pdev->id.device_id; 4082 4083 if (id == BROADCOM_DEV_ID_STRATUS_NIC || 4084 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 4085 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2) 4086 return true; 4087 return false; 4088 } 4089 4090 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4091 { 4092 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4093 struct bnxt *bp = eth_dev->data->dev_private; 4094 4095 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4096 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4097 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4098 if (!bp->bar0 || !bp->doorbell_base) { 4099 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4100 return -ENODEV; 4101 } 4102 4103 bp->eth_dev = eth_dev; 4104 bp->pdev = pci_dev; 4105 4106 return 0; 4107 } 4108 4109 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp, 4110 struct bnxt_ctx_pg_info *ctx_pg, 4111 uint32_t mem_size, 4112 const char *suffix, 4113 uint16_t idx) 4114 { 4115 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4116 const struct rte_memzone *mz = NULL; 4117 char mz_name[RTE_MEMZONE_NAMESIZE]; 4118 rte_iova_t mz_phys_addr; 4119 uint64_t valid_bits = 0; 4120 uint32_t sz; 4121 int i; 4122 4123 if (!mem_size) 4124 return 0; 4125 4126 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4127 BNXT_PAGE_SIZE; 4128 rmem->page_size = BNXT_PAGE_SIZE; 4129 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4130 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4131 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4132 4133 valid_bits = PTU_PTE_VALID; 4134 4135 if (rmem->nr_pages > 1) { 4136 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4137 "bnxt_ctx_pg_tbl%s_%x_%d", 4138 suffix, idx, bp->eth_dev->data->port_id); 4139 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4140 mz = rte_memzone_lookup(mz_name); 4141 if (!mz) { 4142 mz = rte_memzone_reserve_aligned(mz_name, 4143 rmem->nr_pages * 8, 4144 SOCKET_ID_ANY, 4145 RTE_MEMZONE_2MB | 4146 RTE_MEMZONE_SIZE_HINT_ONLY | 4147 RTE_MEMZONE_IOVA_CONTIG, 4148 BNXT_PAGE_SIZE); 4149 if (mz == NULL) 4150 return -ENOMEM; 4151 } 4152 4153 memset(mz->addr, 0, mz->len); 4154 mz_phys_addr = mz->iova; 4155 if ((unsigned long)mz->addr == mz_phys_addr) { 4156 PMD_DRV_LOG(DEBUG, 4157 "physical address same as virtual\n"); 4158 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4159 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4160 if (mz_phys_addr == RTE_BAD_IOVA) { 4161 PMD_DRV_LOG(ERR, 4162 "unable to map addr to phys memory\n"); 4163 return -ENOMEM; 4164 } 4165 } 4166 rte_mem_lock_page(((char *)mz->addr)); 4167 4168 rmem->pg_tbl = mz->addr; 4169 rmem->pg_tbl_map = mz_phys_addr; 4170 rmem->pg_tbl_mz = mz; 4171 } 4172 4173 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4174 suffix, idx, bp->eth_dev->data->port_id); 4175 mz = rte_memzone_lookup(mz_name); 4176 if (!mz) { 4177 mz = rte_memzone_reserve_aligned(mz_name, 4178 mem_size, 4179 SOCKET_ID_ANY, 4180 RTE_MEMZONE_1GB | 4181 RTE_MEMZONE_SIZE_HINT_ONLY | 4182 RTE_MEMZONE_IOVA_CONTIG, 4183 BNXT_PAGE_SIZE); 4184 if (mz == NULL) 4185 return -ENOMEM; 4186 } 4187 4188 memset(mz->addr, 0, mz->len); 4189 mz_phys_addr = mz->iova; 4190 if ((unsigned long)mz->addr == mz_phys_addr) { 4191 PMD_DRV_LOG(DEBUG, 4192 "Memzone physical address same as virtual.\n"); 4193 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4194 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE) 4195 rte_mem_lock_page(((char *)mz->addr) + sz); 4196 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4197 if (mz_phys_addr == RTE_BAD_IOVA) { 4198 PMD_DRV_LOG(ERR, 4199 "unable to map addr to phys memory\n"); 4200 return -ENOMEM; 4201 } 4202 } 4203 4204 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4205 rte_mem_lock_page(((char *)mz->addr) + sz); 4206 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4207 rmem->dma_arr[i] = mz_phys_addr + sz; 4208 4209 if (rmem->nr_pages > 1) { 4210 if (i == rmem->nr_pages - 2 && 4211 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4212 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4213 else if (i == rmem->nr_pages - 1 && 4214 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4215 valid_bits |= PTU_PTE_LAST; 4216 4217 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4218 valid_bits); 4219 } 4220 } 4221 4222 rmem->mz = mz; 4223 if (rmem->vmem_size) 4224 rmem->vmem = (void **)mz->addr; 4225 rmem->dma_arr[0] = mz_phys_addr; 4226 return 0; 4227 } 4228 4229 static void bnxt_free_ctx_mem(struct bnxt *bp) 4230 { 4231 int i; 4232 4233 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4234 return; 4235 4236 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4237 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4238 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4239 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4240 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4241 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4242 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4243 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4244 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4245 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4246 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4247 4248 for (i = 0; i < BNXT_MAX_Q; i++) { 4249 if (bp->ctx->tqm_mem[i]) 4250 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4251 } 4252 4253 rte_free(bp->ctx); 4254 bp->ctx = NULL; 4255 } 4256 4257 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4258 4259 #define min_t(type, x, y) ({ \ 4260 type __min1 = (x); \ 4261 type __min2 = (y); \ 4262 __min1 < __min2 ? __min1 : __min2; }) 4263 4264 #define max_t(type, x, y) ({ \ 4265 type __max1 = (x); \ 4266 type __max2 = (y); \ 4267 __max1 > __max2 ? __max1 : __max2; }) 4268 4269 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4270 4271 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4272 { 4273 struct bnxt_ctx_pg_info *ctx_pg; 4274 struct bnxt_ctx_mem_info *ctx; 4275 uint32_t mem_size, ena, entries; 4276 int i, rc; 4277 4278 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4279 if (rc) { 4280 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4281 return rc; 4282 } 4283 ctx = bp->ctx; 4284 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4285 return 0; 4286 4287 ctx_pg = &ctx->qp_mem; 4288 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4289 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4290 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4291 if (rc) 4292 return rc; 4293 4294 ctx_pg = &ctx->srq_mem; 4295 ctx_pg->entries = ctx->srq_max_l2_entries; 4296 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4297 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4298 if (rc) 4299 return rc; 4300 4301 ctx_pg = &ctx->cq_mem; 4302 ctx_pg->entries = ctx->cq_max_l2_entries; 4303 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4304 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4305 if (rc) 4306 return rc; 4307 4308 ctx_pg = &ctx->vnic_mem; 4309 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4310 ctx->vnic_max_ring_table_entries; 4311 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4312 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4313 if (rc) 4314 return rc; 4315 4316 ctx_pg = &ctx->stat_mem; 4317 ctx_pg->entries = ctx->stat_max_entries; 4318 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4319 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4320 if (rc) 4321 return rc; 4322 4323 entries = ctx->qp_max_l2_entries + 4324 ctx->vnic_max_vnic_entries + 4325 ctx->tqm_min_entries_per_ring; 4326 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4327 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring, 4328 ctx->tqm_max_entries_per_ring); 4329 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) { 4330 ctx_pg = ctx->tqm_mem[i]; 4331 /* use min tqm entries for now. */ 4332 ctx_pg->entries = entries; 4333 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4334 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4335 if (rc) 4336 return rc; 4337 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4338 } 4339 4340 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4341 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4342 if (rc) 4343 PMD_DRV_LOG(ERR, 4344 "Failed to configure context mem: rc = %d\n", rc); 4345 else 4346 ctx->flags |= BNXT_CTX_FLAG_INITED; 4347 4348 return rc; 4349 } 4350 4351 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4352 { 4353 struct rte_pci_device *pci_dev = bp->pdev; 4354 char mz_name[RTE_MEMZONE_NAMESIZE]; 4355 const struct rte_memzone *mz = NULL; 4356 uint32_t total_alloc_len; 4357 rte_iova_t mz_phys_addr; 4358 4359 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4360 return 0; 4361 4362 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4363 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4364 pci_dev->addr.bus, pci_dev->addr.devid, 4365 pci_dev->addr.function, "rx_port_stats"); 4366 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4367 mz = rte_memzone_lookup(mz_name); 4368 total_alloc_len = 4369 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4370 sizeof(struct rx_port_stats_ext) + 512); 4371 if (!mz) { 4372 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4373 SOCKET_ID_ANY, 4374 RTE_MEMZONE_2MB | 4375 RTE_MEMZONE_SIZE_HINT_ONLY | 4376 RTE_MEMZONE_IOVA_CONTIG); 4377 if (mz == NULL) 4378 return -ENOMEM; 4379 } 4380 memset(mz->addr, 0, mz->len); 4381 mz_phys_addr = mz->iova; 4382 if ((unsigned long)mz->addr == mz_phys_addr) { 4383 PMD_DRV_LOG(DEBUG, 4384 "Memzone physical address same as virtual.\n"); 4385 PMD_DRV_LOG(DEBUG, 4386 "Using rte_mem_virt2iova()\n"); 4387 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4388 if (mz_phys_addr == RTE_BAD_IOVA) { 4389 PMD_DRV_LOG(ERR, 4390 "Can't map address to physical memory\n"); 4391 return -ENOMEM; 4392 } 4393 } 4394 4395 bp->rx_mem_zone = (const void *)mz; 4396 bp->hw_rx_port_stats = mz->addr; 4397 bp->hw_rx_port_stats_map = mz_phys_addr; 4398 4399 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4400 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4401 pci_dev->addr.bus, pci_dev->addr.devid, 4402 pci_dev->addr.function, "tx_port_stats"); 4403 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4404 mz = rte_memzone_lookup(mz_name); 4405 total_alloc_len = 4406 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4407 sizeof(struct tx_port_stats_ext) + 512); 4408 if (!mz) { 4409 mz = rte_memzone_reserve(mz_name, 4410 total_alloc_len, 4411 SOCKET_ID_ANY, 4412 RTE_MEMZONE_2MB | 4413 RTE_MEMZONE_SIZE_HINT_ONLY | 4414 RTE_MEMZONE_IOVA_CONTIG); 4415 if (mz == NULL) 4416 return -ENOMEM; 4417 } 4418 memset(mz->addr, 0, mz->len); 4419 mz_phys_addr = mz->iova; 4420 if ((unsigned long)mz->addr == mz_phys_addr) { 4421 PMD_DRV_LOG(DEBUG, 4422 "Memzone physical address same as virtual\n"); 4423 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4424 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4425 if (mz_phys_addr == RTE_BAD_IOVA) { 4426 PMD_DRV_LOG(ERR, 4427 "Can't map address to physical memory\n"); 4428 return -ENOMEM; 4429 } 4430 } 4431 4432 bp->tx_mem_zone = (const void *)mz; 4433 bp->hw_tx_port_stats = mz->addr; 4434 bp->hw_tx_port_stats_map = mz_phys_addr; 4435 bp->flags |= BNXT_FLAG_PORT_STATS; 4436 4437 /* Display extended statistics if FW supports it */ 4438 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4439 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4440 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4441 return 0; 4442 4443 bp->hw_rx_port_stats_ext = (void *) 4444 ((uint8_t *)bp->hw_rx_port_stats + 4445 sizeof(struct rx_port_stats)); 4446 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4447 sizeof(struct rx_port_stats); 4448 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4449 4450 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4451 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4452 bp->hw_tx_port_stats_ext = (void *) 4453 ((uint8_t *)bp->hw_tx_port_stats + 4454 sizeof(struct tx_port_stats)); 4455 bp->hw_tx_port_stats_ext_map = 4456 bp->hw_tx_port_stats_map + 4457 sizeof(struct tx_port_stats); 4458 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4459 } 4460 4461 return 0; 4462 } 4463 4464 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4465 { 4466 struct bnxt *bp = eth_dev->data->dev_private; 4467 int rc = 0; 4468 4469 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4470 RTE_ETHER_ADDR_LEN * 4471 bp->max_l2_ctx, 4472 0); 4473 if (eth_dev->data->mac_addrs == NULL) { 4474 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4475 return -ENOMEM; 4476 } 4477 4478 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) { 4479 if (BNXT_PF(bp)) 4480 return -EINVAL; 4481 4482 /* Generate a random MAC address, if none was assigned by PF */ 4483 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4484 bnxt_eth_hw_addr_random(bp->mac_addr); 4485 PMD_DRV_LOG(INFO, 4486 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4487 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4488 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4489 4490 rc = bnxt_hwrm_set_mac(bp); 4491 if (!rc) 4492 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr, 4493 RTE_ETHER_ADDR_LEN); 4494 return rc; 4495 } 4496 4497 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4498 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN); 4499 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4500 4501 return rc; 4502 } 4503 4504 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4505 { 4506 int rc = 0; 4507 4508 /* MAC is already configured in FW */ 4509 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) 4510 return 0; 4511 4512 /* Restore the old MAC configured */ 4513 rc = bnxt_hwrm_set_mac(bp); 4514 if (rc) 4515 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4516 4517 return rc; 4518 } 4519 4520 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4521 { 4522 if (!BNXT_PF(bp)) 4523 return; 4524 4525 #define ALLOW_FUNC(x) \ 4526 { \ 4527 uint32_t arg = (x); \ 4528 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 4529 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 4530 } 4531 4532 /* Forward all requests if firmware is new enough */ 4533 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 4534 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 4535 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 4536 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 4537 } else { 4538 PMD_DRV_LOG(WARNING, 4539 "Firmware too old for VF mailbox functionality\n"); 4540 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 4541 } 4542 4543 /* 4544 * The following are used for driver cleanup. If we disallow these, 4545 * VF drivers can't clean up cleanly. 4546 */ 4547 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 4548 ALLOW_FUNC(HWRM_VNIC_FREE); 4549 ALLOW_FUNC(HWRM_RING_FREE); 4550 ALLOW_FUNC(HWRM_RING_GRP_FREE); 4551 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 4552 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 4553 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 4554 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 4555 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 4556 } 4557 4558 static int bnxt_init_fw(struct bnxt *bp) 4559 { 4560 uint16_t mtu; 4561 int rc = 0; 4562 4563 rc = bnxt_hwrm_ver_get(bp); 4564 if (rc) 4565 return rc; 4566 4567 rc = bnxt_hwrm_func_reset(bp); 4568 if (rc) 4569 return -EIO; 4570 4571 rc = bnxt_hwrm_vnic_qcaps(bp); 4572 if (rc) 4573 return rc; 4574 4575 rc = bnxt_hwrm_queue_qportcfg(bp); 4576 if (rc) 4577 return rc; 4578 4579 /* Get the MAX capabilities for this function. 4580 * This function also allocates context memory for TQM rings and 4581 * informs the firmware about this allocated backing store memory. 4582 */ 4583 rc = bnxt_hwrm_func_qcaps(bp); 4584 if (rc) 4585 return rc; 4586 4587 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 4588 if (rc) 4589 return rc; 4590 4591 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 4592 if (rc) 4593 return rc; 4594 4595 /* Get the adapter error recovery support info */ 4596 rc = bnxt_hwrm_error_recovery_qcfg(bp); 4597 if (rc) 4598 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY; 4599 4600 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU && 4601 mtu != bp->eth_dev->data->mtu) 4602 bp->eth_dev->data->mtu = mtu; 4603 4604 bnxt_hwrm_port_led_qcaps(bp); 4605 4606 return 0; 4607 } 4608 4609 static int 4610 bnxt_init_locks(struct bnxt *bp) 4611 { 4612 int err; 4613 4614 err = pthread_mutex_init(&bp->flow_lock, NULL); 4615 if (err) 4616 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 4617 return err; 4618 } 4619 4620 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 4621 { 4622 int rc; 4623 4624 rc = bnxt_init_fw(bp); 4625 if (rc) 4626 return rc; 4627 4628 if (!reconfig_dev) { 4629 rc = bnxt_setup_mac_addr(bp->eth_dev); 4630 if (rc) 4631 return rc; 4632 } else { 4633 rc = bnxt_restore_dflt_mac(bp); 4634 if (rc) 4635 return rc; 4636 } 4637 4638 bnxt_config_vf_req_fwd(bp); 4639 4640 rc = bnxt_hwrm_func_driver_register(bp); 4641 if (rc) { 4642 PMD_DRV_LOG(ERR, "Failed to register driver"); 4643 return -EBUSY; 4644 } 4645 4646 if (BNXT_PF(bp)) { 4647 if (bp->pdev->max_vfs) { 4648 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 4649 if (rc) { 4650 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 4651 return rc; 4652 } 4653 } else { 4654 rc = bnxt_hwrm_allocate_pf_only(bp); 4655 if (rc) { 4656 PMD_DRV_LOG(ERR, 4657 "Failed to allocate PF resources"); 4658 return rc; 4659 } 4660 } 4661 } 4662 4663 rc = bnxt_alloc_mem(bp, reconfig_dev); 4664 if (rc) 4665 return rc; 4666 4667 rc = bnxt_setup_int(bp); 4668 if (rc) 4669 return rc; 4670 4671 bnxt_init_nic(bp); 4672 4673 rc = bnxt_request_int(bp); 4674 if (rc) 4675 return rc; 4676 4677 rc = bnxt_init_locks(bp); 4678 if (rc) 4679 return rc; 4680 4681 return 0; 4682 } 4683 4684 static int 4685 bnxt_dev_init(struct rte_eth_dev *eth_dev) 4686 { 4687 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4688 static int version_printed; 4689 struct bnxt *bp; 4690 int rc; 4691 4692 if (version_printed++ == 0) 4693 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 4694 4695 eth_dev->dev_ops = &bnxt_dev_ops; 4696 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 4697 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 4698 4699 /* 4700 * For secondary processes, we don't initialise any further 4701 * as primary has already done this work. 4702 */ 4703 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4704 return 0; 4705 4706 rte_eth_copy_pci_info(eth_dev, pci_dev); 4707 4708 bp = eth_dev->data->dev_private; 4709 4710 bp->dev_stopped = 1; 4711 4712 if (bnxt_vf_pciid(pci_dev->id.device_id)) 4713 bp->flags |= BNXT_FLAG_VF; 4714 4715 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 || 4716 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 || 4717 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 || 4718 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 || 4719 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2) 4720 bp->flags |= BNXT_FLAG_THOR_CHIP; 4721 4722 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 4723 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 4724 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 4725 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 4726 bp->flags |= BNXT_FLAG_STINGRAY; 4727 4728 rc = bnxt_init_board(eth_dev); 4729 if (rc) { 4730 PMD_DRV_LOG(ERR, 4731 "Failed to initialize board rc: %x\n", rc); 4732 return rc; 4733 } 4734 4735 rc = bnxt_alloc_hwrm_resources(bp); 4736 if (rc) { 4737 PMD_DRV_LOG(ERR, 4738 "Failed to allocate hwrm resource rc: %x\n", rc); 4739 goto error_free; 4740 } 4741 rc = bnxt_init_resources(bp, false); 4742 if (rc) 4743 goto error_free; 4744 4745 rc = bnxt_alloc_stats_mem(bp); 4746 if (rc) 4747 goto error_free; 4748 4749 PMD_DRV_LOG(INFO, 4750 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 4751 pci_dev->mem_resource[0].phys_addr, 4752 pci_dev->mem_resource[0].addr); 4753 4754 return 0; 4755 4756 error_free: 4757 bnxt_dev_uninit(eth_dev); 4758 return rc; 4759 } 4760 4761 static void 4762 bnxt_uninit_locks(struct bnxt *bp) 4763 { 4764 pthread_mutex_destroy(&bp->flow_lock); 4765 } 4766 4767 static int 4768 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 4769 { 4770 int rc; 4771 4772 bnxt_free_int(bp); 4773 bnxt_free_mem(bp, reconfig_dev); 4774 bnxt_hwrm_func_buf_unrgtr(bp); 4775 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 4776 bp->flags &= ~BNXT_FLAG_REGISTERED; 4777 bnxt_free_ctx_mem(bp); 4778 if (!reconfig_dev) { 4779 bnxt_free_hwrm_resources(bp); 4780 4781 if (bp->recovery_info != NULL) { 4782 rte_free(bp->recovery_info); 4783 bp->recovery_info = NULL; 4784 } 4785 } 4786 4787 rte_free(bp->ptp_cfg); 4788 bp->ptp_cfg = NULL; 4789 return rc; 4790 } 4791 4792 static int 4793 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 4794 { 4795 struct bnxt *bp = eth_dev->data->dev_private; 4796 int rc; 4797 4798 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4799 return -EPERM; 4800 4801 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 4802 4803 rc = bnxt_uninit_resources(bp, false); 4804 4805 if (bp->grp_info != NULL) { 4806 rte_free(bp->grp_info); 4807 bp->grp_info = NULL; 4808 } 4809 4810 if (bp->tx_mem_zone) { 4811 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 4812 bp->tx_mem_zone = NULL; 4813 } 4814 4815 if (bp->rx_mem_zone) { 4816 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 4817 bp->rx_mem_zone = NULL; 4818 } 4819 4820 if (bp->dev_stopped == 0) 4821 bnxt_dev_close_op(eth_dev); 4822 if (bp->pf.vf_info) 4823 rte_free(bp->pf.vf_info); 4824 eth_dev->dev_ops = NULL; 4825 eth_dev->rx_pkt_burst = NULL; 4826 eth_dev->tx_pkt_burst = NULL; 4827 4828 bnxt_uninit_locks(bp); 4829 4830 return rc; 4831 } 4832 4833 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4834 struct rte_pci_device *pci_dev) 4835 { 4836 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 4837 bnxt_dev_init); 4838 } 4839 4840 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 4841 { 4842 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 4843 return rte_eth_dev_pci_generic_remove(pci_dev, 4844 bnxt_dev_uninit); 4845 else 4846 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 4847 } 4848 4849 static struct rte_pci_driver bnxt_rte_pmd = { 4850 .id_table = bnxt_pci_id_map, 4851 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4852 .probe = bnxt_pci_probe, 4853 .remove = bnxt_pci_remove, 4854 }; 4855 4856 static bool 4857 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4858 { 4859 if (strcmp(dev->device->driver->name, drv->driver.name)) 4860 return false; 4861 4862 return true; 4863 } 4864 4865 bool is_bnxt_supported(struct rte_eth_dev *dev) 4866 { 4867 return is_device_supported(dev, &bnxt_rte_pmd); 4868 } 4869 4870 RTE_INIT(bnxt_init_log) 4871 { 4872 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 4873 if (bnxt_logtype_driver >= 0) 4874 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 4875 } 4876 4877 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 4878 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 4879 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 4880