1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 101 static const char *const bnxt_dev_args[] = { 102 BNXT_DEVARG_REPRESENTOR, 103 BNXT_DEVARG_TRUFLOW, 104 BNXT_DEVARG_FLOW_XSTAT, 105 BNXT_DEVARG_MAX_NUM_KFLOWS, 106 BNXT_DEVARG_REP_BASED_PF, 107 BNXT_DEVARG_REP_IS_PF, 108 BNXT_DEVARG_REP_Q_R2F, 109 BNXT_DEVARG_REP_Q_F2R, 110 BNXT_DEVARG_REP_FC_R2F, 111 BNXT_DEVARG_REP_FC_F2R, 112 NULL 113 }; 114 115 /* 116 * truflow == false to disable the feature 117 * truflow == true to enable the feature 118 */ 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 120 121 /* 122 * flow_xstat == false to disable the feature 123 * flow_xstat == true to enable the feature 124 */ 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 126 127 /* 128 * rep_is_pf == false to indicate VF representor 129 * rep_is_pf == true to indicate PF representor 130 */ 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 132 133 /* 134 * rep_based_pf == Physical index of the PF 135 */ 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 137 /* 138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 139 */ 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 141 142 /* 143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 144 */ 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 146 147 /* 148 * rep_fc_r2f == Flow control for the representor to endpoint direction 149 */ 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 151 152 /* 153 * rep_fc_f2r == Flow control for the endpoint to representor direction 154 */ 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 156 157 int bnxt_cfa_code_dynfield_offset = -1; 158 159 /* 160 * max_num_kflows must be >= 32 161 * and must be a power-of-2 supported value 162 * return: 1 -> invalid 163 * 0 -> valid 164 */ 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 166 { 167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 168 return 1; 169 return 0; 170 } 171 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 177 static int bnxt_restore_vlan_filters(struct bnxt *bp); 178 static void bnxt_dev_recover(void *arg); 179 static void bnxt_free_error_recovery_info(struct bnxt *bp); 180 static void bnxt_free_rep_info(struct bnxt *bp); 181 182 int is_bnxt_in_error(struct bnxt *bp) 183 { 184 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 185 return -EIO; 186 if (bp->flags & BNXT_FLAG_FW_RESET) 187 return -EBUSY; 188 189 return 0; 190 } 191 192 /***********************/ 193 194 /* 195 * High level utility functions 196 */ 197 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 199 { 200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 201 BNXT_RSS_TBL_SIZE_P5); 202 203 if (!BNXT_CHIP_P5(bp)) 204 return 1; 205 206 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 207 BNXT_RSS_ENTRIES_PER_CTX_P5) / 208 BNXT_RSS_ENTRIES_PER_CTX_P5; 209 } 210 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 212 { 213 if (!BNXT_CHIP_P5(bp)) 214 return HW_HASH_INDEX_SIZE; 215 216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 217 } 218 219 static void bnxt_free_parent_info(struct bnxt *bp) 220 { 221 rte_free(bp->parent); 222 } 223 224 static void bnxt_free_pf_info(struct bnxt *bp) 225 { 226 rte_free(bp->pf); 227 } 228 229 static void bnxt_free_link_info(struct bnxt *bp) 230 { 231 rte_free(bp->link_info); 232 } 233 234 static void bnxt_free_leds_info(struct bnxt *bp) 235 { 236 if (BNXT_VF(bp)) 237 return; 238 239 rte_free(bp->leds); 240 bp->leds = NULL; 241 } 242 243 static void bnxt_free_flow_stats_info(struct bnxt *bp) 244 { 245 rte_free(bp->flow_stat); 246 bp->flow_stat = NULL; 247 } 248 249 static void bnxt_free_cos_queues(struct bnxt *bp) 250 { 251 rte_free(bp->rx_cos_queue); 252 rte_free(bp->tx_cos_queue); 253 } 254 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 256 { 257 bnxt_free_filter_mem(bp); 258 bnxt_free_vnic_attributes(bp); 259 bnxt_free_vnic_mem(bp); 260 261 /* tx/rx rings are configured as part of *_queue_setup callbacks. 262 * If the number of rings change across fw update, 263 * we don't have much choice except to warn the user. 264 */ 265 if (!reconfig) { 266 bnxt_free_stats(bp); 267 bnxt_free_tx_rings(bp); 268 bnxt_free_rx_rings(bp); 269 } 270 bnxt_free_async_cp_ring(bp); 271 bnxt_free_rxtx_nq_ring(bp); 272 273 rte_free(bp->grp_info); 274 bp->grp_info = NULL; 275 } 276 277 static int bnxt_alloc_parent_info(struct bnxt *bp) 278 { 279 bp->parent = rte_zmalloc("bnxt_parent_info", 280 sizeof(struct bnxt_parent_info), 0); 281 if (bp->parent == NULL) 282 return -ENOMEM; 283 284 return 0; 285 } 286 287 static int bnxt_alloc_pf_info(struct bnxt *bp) 288 { 289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 290 if (bp->pf == NULL) 291 return -ENOMEM; 292 293 return 0; 294 } 295 296 static int bnxt_alloc_link_info(struct bnxt *bp) 297 { 298 bp->link_info = 299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 300 if (bp->link_info == NULL) 301 return -ENOMEM; 302 303 return 0; 304 } 305 306 static int bnxt_alloc_leds_info(struct bnxt *bp) 307 { 308 if (BNXT_VF(bp)) 309 return 0; 310 311 bp->leds = rte_zmalloc("bnxt_leds", 312 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 313 0); 314 if (bp->leds == NULL) 315 return -ENOMEM; 316 317 return 0; 318 } 319 320 static int bnxt_alloc_cos_queues(struct bnxt *bp) 321 { 322 bp->rx_cos_queue = 323 rte_zmalloc("bnxt_rx_cosq", 324 BNXT_COS_QUEUE_COUNT * 325 sizeof(struct bnxt_cos_queue_info), 326 0); 327 if (bp->rx_cos_queue == NULL) 328 return -ENOMEM; 329 330 bp->tx_cos_queue = 331 rte_zmalloc("bnxt_tx_cosq", 332 BNXT_COS_QUEUE_COUNT * 333 sizeof(struct bnxt_cos_queue_info), 334 0); 335 if (bp->tx_cos_queue == NULL) 336 return -ENOMEM; 337 338 return 0; 339 } 340 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 342 { 343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 344 sizeof(struct bnxt_flow_stat_info), 0); 345 if (bp->flow_stat == NULL) 346 return -ENOMEM; 347 348 return 0; 349 } 350 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 352 { 353 int rc; 354 355 rc = bnxt_alloc_ring_grps(bp); 356 if (rc) 357 goto alloc_mem_err; 358 359 rc = bnxt_alloc_async_ring_struct(bp); 360 if (rc) 361 goto alloc_mem_err; 362 363 rc = bnxt_alloc_vnic_mem(bp); 364 if (rc) 365 goto alloc_mem_err; 366 367 rc = bnxt_alloc_vnic_attributes(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_filter_mem(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_async_cp_ring(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_rxtx_nq_ring(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 if (BNXT_FLOW_XSTATS_EN(bp)) { 384 rc = bnxt_alloc_flow_stats_info(bp); 385 if (rc) 386 goto alloc_mem_err; 387 } 388 389 return 0; 390 391 alloc_mem_err: 392 bnxt_free_mem(bp, reconfig); 393 return rc; 394 } 395 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 397 { 398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 400 uint64_t rx_offloads = dev_conf->rxmode.offloads; 401 struct bnxt_rx_queue *rxq; 402 unsigned int j; 403 int rc; 404 405 rc = bnxt_vnic_grp_alloc(bp, vnic); 406 if (rc) 407 goto err_out; 408 409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 410 vnic_id, vnic, vnic->fw_grp_ids); 411 412 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 413 if (rc) 414 goto err_out; 415 416 /* Alloc RSS context only if RSS mode is enabled */ 417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 418 int j, nr_ctxs = bnxt_rss_ctxts(bp); 419 420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 423 PMD_DRV_LOG(ERR, 424 "Only queues 0-%d will be in RSS table\n", 425 BNXT_RSS_TBL_SIZE_P5 - 1); 426 } 427 428 rc = 0; 429 for (j = 0; j < nr_ctxs; j++) { 430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 431 if (rc) 432 break; 433 } 434 if (rc) { 435 PMD_DRV_LOG(ERR, 436 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 437 vnic_id, j, rc); 438 goto err_out; 439 } 440 vnic->num_lb_ctxts = nr_ctxs; 441 } 442 443 /* 444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 445 * setting is not available at this time, it will not be 446 * configured correctly in the CFA. 447 */ 448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 449 vnic->vlan_strip = true; 450 else 451 vnic->vlan_strip = false; 452 453 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 454 if (rc) 455 goto err_out; 456 457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 458 if (rc) 459 goto err_out; 460 461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 462 rxq = bp->eth_dev->data->rx_queues[j]; 463 464 PMD_DRV_LOG(DEBUG, 465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 466 j, rxq->vnic, rxq->vnic->fw_grp_ids); 467 468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 470 else 471 vnic->rx_queue_cnt++; 472 } 473 474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 475 476 rc = bnxt_vnic_rss_configure(bp, vnic); 477 if (rc) 478 goto err_out; 479 480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 481 482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 484 else 485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 486 487 return 0; 488 err_out: 489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 490 vnic_id, rc); 491 return rc; 492 } 493 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 495 { 496 int rc = 0; 497 498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 499 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 500 if (rc) 501 return rc; 502 503 PMD_DRV_LOG(DEBUG, 504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 505 " rx_fc_in_tbl.ctx_id = %d\n", 506 bp->flow_stat->rx_fc_in_tbl.va, 507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 508 bp->flow_stat->rx_fc_in_tbl.ctx_id); 509 510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 511 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 512 if (rc) 513 return rc; 514 515 PMD_DRV_LOG(DEBUG, 516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 517 " rx_fc_out_tbl.ctx_id = %d\n", 518 bp->flow_stat->rx_fc_out_tbl.va, 519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 520 bp->flow_stat->rx_fc_out_tbl.ctx_id); 521 522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 523 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 524 if (rc) 525 return rc; 526 527 PMD_DRV_LOG(DEBUG, 528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 529 " tx_fc_in_tbl.ctx_id = %d\n", 530 bp->flow_stat->tx_fc_in_tbl.va, 531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 532 bp->flow_stat->tx_fc_in_tbl.ctx_id); 533 534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 535 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 536 if (rc) 537 return rc; 538 539 PMD_DRV_LOG(DEBUG, 540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 541 " tx_fc_out_tbl.ctx_id = %d\n", 542 bp->flow_stat->tx_fc_out_tbl.va, 543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 544 bp->flow_stat->tx_fc_out_tbl.ctx_id); 545 546 memset(bp->flow_stat->rx_fc_out_tbl.va, 547 0, 548 bp->flow_stat->rx_fc_out_tbl.size); 549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 551 bp->flow_stat->rx_fc_out_tbl.ctx_id, 552 bp->flow_stat->max_fc, 553 true); 554 if (rc) 555 return rc; 556 557 memset(bp->flow_stat->tx_fc_out_tbl.va, 558 0, 559 bp->flow_stat->tx_fc_out_tbl.size); 560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 562 bp->flow_stat->tx_fc_out_tbl.ctx_id, 563 bp->flow_stat->max_fc, 564 true); 565 566 return rc; 567 } 568 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 570 struct bnxt_ctx_mem_buf_info *ctx) 571 { 572 if (!ctx) 573 return -EINVAL; 574 575 ctx->va = rte_zmalloc(type, size, 0); 576 if (ctx->va == NULL) 577 return -ENOMEM; 578 rte_mem_lock_page(ctx->va); 579 ctx->size = size; 580 ctx->dma = rte_mem_virt2iova(ctx->va); 581 if (ctx->dma == RTE_BAD_IOVA) 582 return -ENOMEM; 583 584 return 0; 585 } 586 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 588 { 589 struct rte_pci_device *pdev = bp->pdev; 590 char type[RTE_MEMZONE_NAMESIZE]; 591 uint16_t max_fc; 592 int rc = 0; 593 594 max_fc = bp->flow_stat->max_fc; 595 596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 598 /* 4 bytes for each counter-id */ 599 rc = bnxt_alloc_ctx_mem_buf(type, 600 max_fc * 4, 601 &bp->flow_stat->rx_fc_in_tbl); 602 if (rc) 603 return rc; 604 605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 608 rc = bnxt_alloc_ctx_mem_buf(type, 609 max_fc * 16, 610 &bp->flow_stat->rx_fc_out_tbl); 611 if (rc) 612 return rc; 613 614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 616 /* 4 bytes for each counter-id */ 617 rc = bnxt_alloc_ctx_mem_buf(type, 618 max_fc * 4, 619 &bp->flow_stat->tx_fc_in_tbl); 620 if (rc) 621 return rc; 622 623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 626 rc = bnxt_alloc_ctx_mem_buf(type, 627 max_fc * 16, 628 &bp->flow_stat->tx_fc_out_tbl); 629 if (rc) 630 return rc; 631 632 rc = bnxt_register_fc_ctx_mem(bp); 633 634 return rc; 635 } 636 637 static int bnxt_init_ctx_mem(struct bnxt *bp) 638 { 639 int rc = 0; 640 641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 643 !BNXT_FLOW_XSTATS_EN(bp)) 644 return 0; 645 646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 647 if (rc) 648 return rc; 649 650 rc = bnxt_init_fc_ctx_mem(bp); 651 652 return rc; 653 } 654 655 static int bnxt_update_phy_setting(struct bnxt *bp) 656 { 657 struct rte_eth_link new; 658 int rc; 659 660 rc = bnxt_get_hwrm_link_config(bp, &new); 661 if (rc) { 662 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 663 return rc; 664 } 665 666 /* 667 * On BCM957508-N2100 adapters, FW will not allow any user other 668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 669 * always returns link up. Force phy update always in that case. 670 */ 671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 672 rc = bnxt_set_hwrm_link_config(bp, true); 673 if (rc) { 674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 675 return rc; 676 } 677 } 678 679 return rc; 680 } 681 682 static int bnxt_start_nic(struct bnxt *bp) 683 { 684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 686 uint32_t intr_vector = 0; 687 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 688 uint32_t vec = BNXT_MISC_VEC_ID; 689 unsigned int i, j; 690 int rc; 691 692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 693 bp->eth_dev->data->dev_conf.rxmode.offloads |= 694 DEV_RX_OFFLOAD_JUMBO_FRAME; 695 bp->flags |= BNXT_FLAG_JUMBO; 696 } else { 697 bp->eth_dev->data->dev_conf.rxmode.offloads &= 698 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 699 bp->flags &= ~BNXT_FLAG_JUMBO; 700 } 701 702 /* THOR does not support ring groups. 703 * But we will use the array to save RSS context IDs. 704 */ 705 if (BNXT_CHIP_P5(bp)) 706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 707 708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 709 if (rc) { 710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 711 goto err_out; 712 } 713 714 rc = bnxt_alloc_hwrm_rings(bp); 715 if (rc) { 716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 717 goto err_out; 718 } 719 720 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 721 if (rc) { 722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 723 goto err_out; 724 } 725 726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 727 goto skip_cosq_cfg; 728 729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 730 if (bp->rx_cos_queue[i].id != 0xff) { 731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 732 733 if (!vnic) { 734 PMD_DRV_LOG(ERR, 735 "Num pools more than FW profile\n"); 736 rc = -EINVAL; 737 goto err_out; 738 } 739 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 740 bp->rx_cosq_cnt++; 741 } 742 } 743 744 skip_cosq_cfg: 745 rc = bnxt_mq_rx_configure(bp); 746 if (rc) { 747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 748 goto err_out; 749 } 750 751 /* default vnic 0 */ 752 rc = bnxt_setup_one_vnic(bp, 0); 753 if (rc) 754 goto err_out; 755 /* VNIC configuration */ 756 if (BNXT_RFS_NEEDS_VNIC(bp)) { 757 for (i = 1; i < bp->nr_vnics; i++) { 758 rc = bnxt_setup_one_vnic(bp, i); 759 if (rc) 760 goto err_out; 761 } 762 } 763 764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 765 if (rc) { 766 PMD_DRV_LOG(ERR, 767 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 768 goto err_out; 769 } 770 771 /* check and configure queue intr-vector mapping */ 772 if ((rte_intr_cap_multiple(intr_handle) || 773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 775 intr_vector = bp->eth_dev->data->nb_rx_queues; 776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 777 if (intr_vector > bp->rx_cp_nr_rings) { 778 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 779 bp->rx_cp_nr_rings); 780 return -ENOTSUP; 781 } 782 rc = rte_intr_efd_enable(intr_handle, intr_vector); 783 if (rc) 784 return rc; 785 } 786 787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 788 intr_handle->intr_vec = 789 rte_zmalloc("intr_vec", 790 bp->eth_dev->data->nb_rx_queues * 791 sizeof(int), 0); 792 if (intr_handle->intr_vec == NULL) { 793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 794 " intr_vec", bp->eth_dev->data->nb_rx_queues); 795 rc = -ENOMEM; 796 goto err_disable; 797 } 798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 800 intr_handle->intr_vec, intr_handle->nb_efd, 801 intr_handle->max_intr); 802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 803 queue_id++) { 804 intr_handle->intr_vec[queue_id] = 805 vec + BNXT_RX_VEC_START; 806 if (vec < base + intr_handle->nb_efd - 1) 807 vec++; 808 } 809 } 810 811 /* enable uio/vfio intr/eventfd mapping */ 812 rc = rte_intr_enable(intr_handle); 813 #ifndef RTE_EXEC_ENV_FREEBSD 814 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 815 if (rc) 816 goto err_free; 817 #endif 818 819 rc = bnxt_update_phy_setting(bp); 820 if (rc) 821 goto err_free; 822 823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 824 if (!bp->mark_table) 825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 826 827 return 0; 828 829 err_free: 830 rte_free(intr_handle->intr_vec); 831 err_disable: 832 rte_intr_efd_disable(intr_handle); 833 err_out: 834 /* Some of the error status returned by FW may not be from errno.h */ 835 if (rc > 0) 836 rc = -EIO; 837 838 return rc; 839 } 840 841 static int bnxt_shutdown_nic(struct bnxt *bp) 842 { 843 bnxt_free_all_hwrm_resources(bp); 844 bnxt_free_all_filters(bp); 845 bnxt_free_all_vnics(bp); 846 return 0; 847 } 848 849 /* 850 * Device configuration and status function 851 */ 852 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 854 { 855 uint32_t link_speed = bp->link_info->support_speeds; 856 uint32_t speed_capa = 0; 857 858 /* If PAM4 is configured, use PAM4 supported speed */ 859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 860 link_speed = bp->link_info->support_pam4_speeds; 861 862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 863 speed_capa |= ETH_LINK_SPEED_100M; 864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 865 speed_capa |= ETH_LINK_SPEED_100M_HD; 866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 867 speed_capa |= ETH_LINK_SPEED_1G; 868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 869 speed_capa |= ETH_LINK_SPEED_2_5G; 870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 871 speed_capa |= ETH_LINK_SPEED_10G; 872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 873 speed_capa |= ETH_LINK_SPEED_20G; 874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 875 speed_capa |= ETH_LINK_SPEED_25G; 876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 877 speed_capa |= ETH_LINK_SPEED_40G; 878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 879 speed_capa |= ETH_LINK_SPEED_50G; 880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 881 speed_capa |= ETH_LINK_SPEED_100G; 882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 883 speed_capa |= ETH_LINK_SPEED_50G; 884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 885 speed_capa |= ETH_LINK_SPEED_100G; 886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 887 speed_capa |= ETH_LINK_SPEED_200G; 888 889 if (bp->link_info->auto_mode == 890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 891 speed_capa |= ETH_LINK_SPEED_FIXED; 892 else 893 speed_capa |= ETH_LINK_SPEED_AUTONEG; 894 895 return speed_capa; 896 } 897 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 899 struct rte_eth_dev_info *dev_info) 900 { 901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 902 struct bnxt *bp = eth_dev->data->dev_private; 903 uint16_t max_vnics, i, j, vpool, vrxq; 904 unsigned int max_rx_rings; 905 int rc; 906 907 rc = is_bnxt_in_error(bp); 908 if (rc) 909 return rc; 910 911 /* MAC Specifics */ 912 dev_info->max_mac_addrs = bp->max_l2_ctx; 913 dev_info->max_hash_mac_addrs = 0; 914 915 /* PF/VF specifics */ 916 if (BNXT_PF(bp)) 917 dev_info->max_vfs = pdev->max_vfs; 918 919 max_rx_rings = bnxt_max_rings(bp); 920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 921 dev_info->max_rx_queues = max_rx_rings; 922 dev_info->max_tx_queues = max_rx_rings; 923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 924 dev_info->hash_key_size = 40; 925 max_vnics = bp->max_vnics; 926 927 /* MTU specifics */ 928 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 929 dev_info->max_mtu = BNXT_MAX_MTU; 930 931 /* Fast path specifics */ 932 dev_info->min_rx_bufsize = 1; 933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 934 935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 940 dev_info->tx_queue_offload_capa; 941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 942 943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 944 945 /* *INDENT-OFF* */ 946 dev_info->default_rxconf = (struct rte_eth_rxconf) { 947 .rx_thresh = { 948 .pthresh = 8, 949 .hthresh = 8, 950 .wthresh = 0, 951 }, 952 .rx_free_thresh = 32, 953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 954 }; 955 956 dev_info->default_txconf = (struct rte_eth_txconf) { 957 .tx_thresh = { 958 .pthresh = 32, 959 .hthresh = 0, 960 .wthresh = 0, 961 }, 962 .tx_free_thresh = 32, 963 .tx_rs_thresh = 32, 964 }; 965 eth_dev->data->dev_conf.intr_conf.lsc = 1; 966 967 eth_dev->data->dev_conf.intr_conf.rxq = 1; 968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 972 973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 974 dev_info->switch_info.name = eth_dev->device->name; 975 dev_info->switch_info.domain_id = bp->switch_domain_id; 976 dev_info->switch_info.port_id = 977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 978 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 979 } 980 981 /* *INDENT-ON* */ 982 983 /* 984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 985 * need further investigation. 986 */ 987 988 /* VMDq resources */ 989 vpool = 64; /* ETH_64_POOLS */ 990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 991 for (i = 0; i < 4; vpool >>= 1, i++) { 992 if (max_vnics > vpool) { 993 for (j = 0; j < 5; vrxq >>= 1, j++) { 994 if (dev_info->max_rx_queues > vrxq) { 995 if (vpool > vrxq) 996 vpool = vrxq; 997 goto found; 998 } 999 } 1000 /* Not enough resources to support VMDq */ 1001 break; 1002 } 1003 } 1004 /* Not enough resources to support VMDq */ 1005 vpool = 0; 1006 vrxq = 0; 1007 found: 1008 dev_info->max_vmdq_pools = vpool; 1009 dev_info->vmdq_queue_num = vrxq; 1010 1011 dev_info->vmdq_pool_base = 0; 1012 dev_info->vmdq_queue_base = 0; 1013 1014 return 0; 1015 } 1016 1017 /* Configure the device based on the configuration provided */ 1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1019 { 1020 struct bnxt *bp = eth_dev->data->dev_private; 1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1022 int rc; 1023 1024 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1025 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1028 1029 rc = is_bnxt_in_error(bp); 1030 if (rc) 1031 return rc; 1032 1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1034 rc = bnxt_hwrm_check_vf_rings(bp); 1035 if (rc) { 1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1037 return -ENOSPC; 1038 } 1039 1040 /* If a resource has already been allocated - in this case 1041 * it is the async completion ring, free it. Reallocate it after 1042 * resource reservation. This will ensure the resource counts 1043 * are calculated correctly. 1044 */ 1045 1046 pthread_mutex_lock(&bp->def_cp_lock); 1047 1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1049 bnxt_disable_int(bp); 1050 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1051 } 1052 1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1054 if (rc) { 1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1056 pthread_mutex_unlock(&bp->def_cp_lock); 1057 return -ENOSPC; 1058 } 1059 1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1061 rc = bnxt_alloc_async_cp_ring(bp); 1062 if (rc) { 1063 pthread_mutex_unlock(&bp->def_cp_lock); 1064 return rc; 1065 } 1066 bnxt_enable_int(bp); 1067 } 1068 1069 pthread_mutex_unlock(&bp->def_cp_lock); 1070 } 1071 1072 /* Inherit new configurations */ 1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1078 bp->max_stat_ctx) 1079 goto resource_error; 1080 1081 if (BNXT_HAS_RING_GRPS(bp) && 1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1083 goto resource_error; 1084 1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1086 bp->max_vnics < eth_dev->data->nb_rx_queues) 1087 goto resource_error; 1088 1089 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1090 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1091 1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1095 1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1097 eth_dev->data->mtu = 1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1100 BNXT_NUM_VLANS; 1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1102 } 1103 return 0; 1104 1105 resource_error: 1106 PMD_DRV_LOG(ERR, 1107 "Insufficient resources to support requested config\n"); 1108 PMD_DRV_LOG(ERR, 1109 "Num Queues Requested: Tx %d, Rx %d\n", 1110 eth_dev->data->nb_tx_queues, 1111 eth_dev->data->nb_rx_queues); 1112 PMD_DRV_LOG(ERR, 1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1116 return -ENOSPC; 1117 } 1118 1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1120 { 1121 struct rte_eth_link *link = ð_dev->data->dev_link; 1122 1123 if (link->link_status) 1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1125 eth_dev->data->port_id, 1126 (uint32_t)link->link_speed, 1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1128 ("full-duplex") : ("half-duplex\n")); 1129 else 1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1131 eth_dev->data->port_id); 1132 } 1133 1134 /* 1135 * Determine whether the current configuration requires support for scattered 1136 * receive; return 1 if scattered receive is required and 0 if not. 1137 */ 1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1139 { 1140 uint16_t buf_size; 1141 int i; 1142 1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1144 return 1; 1145 1146 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1147 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1148 1149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1150 RTE_PKTMBUF_HEADROOM); 1151 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1152 return 1; 1153 } 1154 return 0; 1155 } 1156 1157 static eth_rx_burst_t 1158 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1159 { 1160 struct bnxt *bp = eth_dev->data->dev_private; 1161 1162 /* Disable vector mode RX for Stingray2 for now */ 1163 if (BNXT_CHIP_SR2(bp)) { 1164 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1165 return bnxt_recv_pkts; 1166 } 1167 1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1169 #ifndef RTE_LIBRTE_IEEE1588 1170 /* 1171 * Vector mode receive can be enabled only if scatter rx is not 1172 * in use and rx offloads are limited to VLAN stripping and 1173 * CRC stripping. 1174 */ 1175 if (!eth_dev->data->scattered_rx && 1176 !(eth_dev->data->dev_conf.rxmode.offloads & 1177 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1178 DEV_RX_OFFLOAD_KEEP_CRC | 1179 DEV_RX_OFFLOAD_JUMBO_FRAME | 1180 DEV_RX_OFFLOAD_IPV4_CKSUM | 1181 DEV_RX_OFFLOAD_UDP_CKSUM | 1182 DEV_RX_OFFLOAD_TCP_CKSUM | 1183 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1184 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1185 DEV_RX_OFFLOAD_RSS_HASH | 1186 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1187 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && 1188 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1189 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1190 eth_dev->data->port_id); 1191 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1192 return bnxt_recv_pkts_vec; 1193 } 1194 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1195 eth_dev->data->port_id); 1196 PMD_DRV_LOG(INFO, 1197 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1198 eth_dev->data->port_id, 1199 eth_dev->data->scattered_rx, 1200 eth_dev->data->dev_conf.rxmode.offloads); 1201 #endif 1202 #endif 1203 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1204 return bnxt_recv_pkts; 1205 } 1206 1207 static eth_tx_burst_t 1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1209 { 1210 struct bnxt *bp = eth_dev->data->dev_private; 1211 1212 /* Disable vector mode TX for Stingray2 for now */ 1213 if (BNXT_CHIP_SR2(bp)) 1214 return bnxt_xmit_pkts; 1215 1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1217 #ifndef RTE_LIBRTE_IEEE1588 1218 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1219 1220 /* 1221 * Vector mode transmit can be enabled only if not using scatter rx 1222 * or tx offloads. 1223 */ 1224 if (!eth_dev->data->scattered_rx && 1225 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && 1226 !BNXT_TRUFLOW_EN(bp) && 1227 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1228 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1229 eth_dev->data->port_id); 1230 return bnxt_xmit_pkts_vec; 1231 } 1232 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1233 eth_dev->data->port_id); 1234 PMD_DRV_LOG(INFO, 1235 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1236 eth_dev->data->port_id, 1237 eth_dev->data->scattered_rx, 1238 offloads); 1239 #endif 1240 #endif 1241 return bnxt_xmit_pkts; 1242 } 1243 1244 static int bnxt_handle_if_change_status(struct bnxt *bp) 1245 { 1246 int rc; 1247 1248 /* Since fw has undergone a reset and lost all contexts, 1249 * set fatal flag to not issue hwrm during cleanup 1250 */ 1251 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1252 bnxt_uninit_resources(bp, true); 1253 1254 /* clear fatal flag so that re-init happens */ 1255 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1256 rc = bnxt_init_resources(bp, true); 1257 1258 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1259 1260 return rc; 1261 } 1262 1263 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1264 { 1265 struct bnxt *bp = eth_dev->data->dev_private; 1266 int rc = 0; 1267 1268 if (!bp->link_info->link_up) 1269 rc = bnxt_set_hwrm_link_config(bp, true); 1270 if (!rc) 1271 eth_dev->data->dev_link.link_status = 1; 1272 1273 bnxt_print_link_info(eth_dev); 1274 return rc; 1275 } 1276 1277 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1278 { 1279 struct bnxt *bp = eth_dev->data->dev_private; 1280 1281 eth_dev->data->dev_link.link_status = 0; 1282 bnxt_set_hwrm_link_config(bp, false); 1283 bp->link_info->link_up = 0; 1284 1285 return 0; 1286 } 1287 1288 static void bnxt_free_switch_domain(struct bnxt *bp) 1289 { 1290 int rc = 0; 1291 1292 if (bp->switch_domain_id) { 1293 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1294 if (rc) 1295 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1296 bp->switch_domain_id, rc); 1297 } 1298 } 1299 1300 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1301 { 1302 struct bnxt *bp = eth_dev->data->dev_private; 1303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1305 struct rte_eth_link link; 1306 int ret; 1307 1308 eth_dev->data->dev_started = 0; 1309 eth_dev->data->scattered_rx = 0; 1310 1311 /* Prevent crashes when queues are still in use */ 1312 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1313 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1314 1315 bnxt_disable_int(bp); 1316 1317 /* disable uio/vfio intr/eventfd mapping */ 1318 rte_intr_disable(intr_handle); 1319 1320 /* Stop the child representors for this device */ 1321 ret = bnxt_rep_stop_all(bp); 1322 if (ret != 0) 1323 return ret; 1324 1325 /* delete the bnxt ULP port details */ 1326 bnxt_ulp_port_deinit(bp); 1327 1328 bnxt_cancel_fw_health_check(bp); 1329 1330 /* Do not bring link down during reset recovery */ 1331 if (!is_bnxt_in_error(bp)) { 1332 bnxt_dev_set_link_down_op(eth_dev); 1333 /* Wait for link to be reset */ 1334 if (BNXT_SINGLE_PF(bp)) 1335 rte_delay_ms(500); 1336 /* clear the recorded link status */ 1337 memset(&link, 0, sizeof(link)); 1338 rte_eth_linkstatus_set(eth_dev, &link); 1339 } 1340 1341 /* Clean queue intr-vector mapping */ 1342 rte_intr_efd_disable(intr_handle); 1343 if (intr_handle->intr_vec != NULL) { 1344 rte_free(intr_handle->intr_vec); 1345 intr_handle->intr_vec = NULL; 1346 } 1347 1348 bnxt_hwrm_port_clr_stats(bp); 1349 bnxt_free_tx_mbufs(bp); 1350 bnxt_free_rx_mbufs(bp); 1351 /* Process any remaining notifications in default completion queue */ 1352 bnxt_int_handler(eth_dev); 1353 bnxt_shutdown_nic(bp); 1354 bnxt_hwrm_if_change(bp, false); 1355 1356 rte_free(bp->mark_table); 1357 bp->mark_table = NULL; 1358 1359 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1360 bp->rx_cosq_cnt = 0; 1361 /* All filters are deleted on a port stop. */ 1362 if (BNXT_FLOW_XSTATS_EN(bp)) 1363 bp->flow_stat->flow_count = 0; 1364 1365 return 0; 1366 } 1367 1368 /* Unload the driver, release resources */ 1369 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1370 { 1371 struct bnxt *bp = eth_dev->data->dev_private; 1372 1373 pthread_mutex_lock(&bp->err_recovery_lock); 1374 if (bp->flags & BNXT_FLAG_FW_RESET) { 1375 PMD_DRV_LOG(ERR, 1376 "Adapter recovering from error..Please retry\n"); 1377 pthread_mutex_unlock(&bp->err_recovery_lock); 1378 return -EAGAIN; 1379 } 1380 pthread_mutex_unlock(&bp->err_recovery_lock); 1381 1382 return bnxt_dev_stop(eth_dev); 1383 } 1384 1385 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1386 { 1387 struct bnxt *bp = eth_dev->data->dev_private; 1388 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1389 int vlan_mask = 0; 1390 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1391 1392 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1393 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1394 return -EINVAL; 1395 } 1396 1397 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1398 PMD_DRV_LOG(ERR, 1399 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1400 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1401 1402 do { 1403 rc = bnxt_hwrm_if_change(bp, true); 1404 if (rc == 0 || rc != -EAGAIN) 1405 break; 1406 1407 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1408 } while (retry_cnt--); 1409 1410 if (rc) 1411 return rc; 1412 1413 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1414 rc = bnxt_handle_if_change_status(bp); 1415 if (rc) 1416 return rc; 1417 } 1418 1419 bnxt_enable_int(bp); 1420 1421 rc = bnxt_start_nic(bp); 1422 if (rc) 1423 goto error; 1424 1425 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1426 eth_dev->data->dev_started = 1; 1427 1428 bnxt_link_update_op(eth_dev, 1); 1429 1430 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1431 vlan_mask |= ETH_VLAN_FILTER_MASK; 1432 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1433 vlan_mask |= ETH_VLAN_STRIP_MASK; 1434 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1435 if (rc) 1436 goto error; 1437 1438 /* Initialize bnxt ULP port details */ 1439 rc = bnxt_ulp_port_init(bp); 1440 if (rc) 1441 goto error; 1442 1443 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1444 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1445 1446 bnxt_schedule_fw_health_check(bp); 1447 1448 return 0; 1449 1450 error: 1451 bnxt_dev_stop(eth_dev); 1452 return rc; 1453 } 1454 1455 static void 1456 bnxt_uninit_locks(struct bnxt *bp) 1457 { 1458 pthread_mutex_destroy(&bp->flow_lock); 1459 pthread_mutex_destroy(&bp->def_cp_lock); 1460 pthread_mutex_destroy(&bp->health_check_lock); 1461 pthread_mutex_destroy(&bp->err_recovery_lock); 1462 if (bp->rep_info) { 1463 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1464 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1465 } 1466 } 1467 1468 static void bnxt_drv_uninit(struct bnxt *bp) 1469 { 1470 bnxt_free_switch_domain(bp); 1471 bnxt_free_leds_info(bp); 1472 bnxt_free_cos_queues(bp); 1473 bnxt_free_link_info(bp); 1474 bnxt_free_pf_info(bp); 1475 bnxt_free_parent_info(bp); 1476 bnxt_uninit_locks(bp); 1477 1478 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1479 bp->tx_mem_zone = NULL; 1480 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1481 bp->rx_mem_zone = NULL; 1482 1483 bnxt_hwrm_free_vf_info(bp); 1484 1485 rte_free(bp->grp_info); 1486 bp->grp_info = NULL; 1487 } 1488 1489 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1490 { 1491 struct bnxt *bp = eth_dev->data->dev_private; 1492 int ret = 0; 1493 1494 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1495 return 0; 1496 1497 pthread_mutex_lock(&bp->err_recovery_lock); 1498 if (bp->flags & BNXT_FLAG_FW_RESET) { 1499 PMD_DRV_LOG(ERR, 1500 "Adapter recovering from error...Please retry\n"); 1501 pthread_mutex_unlock(&bp->err_recovery_lock); 1502 return -EAGAIN; 1503 } 1504 pthread_mutex_unlock(&bp->err_recovery_lock); 1505 1506 /* cancel the recovery handler before remove dev */ 1507 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1508 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1509 bnxt_cancel_fc_thread(bp); 1510 1511 if (eth_dev->data->dev_started) 1512 ret = bnxt_dev_stop(eth_dev); 1513 1514 bnxt_uninit_resources(bp, false); 1515 1516 bnxt_drv_uninit(bp); 1517 1518 return ret; 1519 } 1520 1521 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1522 uint32_t index) 1523 { 1524 struct bnxt *bp = eth_dev->data->dev_private; 1525 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1526 struct bnxt_vnic_info *vnic; 1527 struct bnxt_filter_info *filter, *temp_filter; 1528 uint32_t i; 1529 1530 if (is_bnxt_in_error(bp)) 1531 return; 1532 1533 /* 1534 * Loop through all VNICs from the specified filter flow pools to 1535 * remove the corresponding MAC addr filter 1536 */ 1537 for (i = 0; i < bp->nr_vnics; i++) { 1538 if (!(pool_mask & (1ULL << i))) 1539 continue; 1540 1541 vnic = &bp->vnic_info[i]; 1542 filter = STAILQ_FIRST(&vnic->filter); 1543 while (filter) { 1544 temp_filter = STAILQ_NEXT(filter, next); 1545 if (filter->mac_index == index) { 1546 STAILQ_REMOVE(&vnic->filter, filter, 1547 bnxt_filter_info, next); 1548 bnxt_hwrm_clear_l2_filter(bp, filter); 1549 bnxt_free_filter(bp, filter); 1550 } 1551 filter = temp_filter; 1552 } 1553 } 1554 } 1555 1556 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1557 struct rte_ether_addr *mac_addr, uint32_t index, 1558 uint32_t pool) 1559 { 1560 struct bnxt_filter_info *filter; 1561 int rc = 0; 1562 1563 /* Attach requested MAC address to the new l2_filter */ 1564 STAILQ_FOREACH(filter, &vnic->filter, next) { 1565 if (filter->mac_index == index) { 1566 PMD_DRV_LOG(DEBUG, 1567 "MAC addr already existed for pool %d\n", 1568 pool); 1569 return 0; 1570 } 1571 } 1572 1573 filter = bnxt_alloc_filter(bp); 1574 if (!filter) { 1575 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1576 return -ENODEV; 1577 } 1578 1579 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1580 * if the MAC that's been programmed now is a different one, then, 1581 * copy that addr to filter->l2_addr 1582 */ 1583 if (mac_addr) 1584 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1585 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1586 1587 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1588 if (!rc) { 1589 filter->mac_index = index; 1590 if (filter->mac_index == 0) 1591 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1592 else 1593 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1594 } else { 1595 bnxt_free_filter(bp, filter); 1596 } 1597 1598 return rc; 1599 } 1600 1601 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1602 struct rte_ether_addr *mac_addr, 1603 uint32_t index, uint32_t pool) 1604 { 1605 struct bnxt *bp = eth_dev->data->dev_private; 1606 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1607 int rc = 0; 1608 1609 rc = is_bnxt_in_error(bp); 1610 if (rc) 1611 return rc; 1612 1613 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1614 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1615 return -ENOTSUP; 1616 } 1617 1618 if (!vnic) { 1619 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1620 return -EINVAL; 1621 } 1622 1623 /* Filter settings will get applied when port is started */ 1624 if (!eth_dev->data->dev_started) 1625 return 0; 1626 1627 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1628 1629 return rc; 1630 } 1631 1632 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1633 { 1634 int rc = 0; 1635 struct bnxt *bp = eth_dev->data->dev_private; 1636 struct rte_eth_link new; 1637 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1638 BNXT_MIN_LINK_WAIT_CNT; 1639 1640 rc = is_bnxt_in_error(bp); 1641 if (rc) 1642 return rc; 1643 1644 memset(&new, 0, sizeof(new)); 1645 do { 1646 /* Retrieve link info from hardware */ 1647 rc = bnxt_get_hwrm_link_config(bp, &new); 1648 if (rc) { 1649 new.link_speed = ETH_LINK_SPEED_100M; 1650 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1651 PMD_DRV_LOG(ERR, 1652 "Failed to retrieve link rc = 0x%x!\n", rc); 1653 goto out; 1654 } 1655 1656 if (!wait_to_complete || new.link_status) 1657 break; 1658 1659 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1660 } while (cnt--); 1661 1662 /* Only single function PF can bring phy down. 1663 * When port is stopped, report link down for VF/MH/NPAR functions. 1664 */ 1665 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1666 memset(&new, 0, sizeof(new)); 1667 1668 out: 1669 /* Timed out or success */ 1670 if (new.link_status != eth_dev->data->dev_link.link_status || 1671 new.link_speed != eth_dev->data->dev_link.link_speed) { 1672 rte_eth_linkstatus_set(eth_dev, &new); 1673 1674 rte_eth_dev_callback_process(eth_dev, 1675 RTE_ETH_EVENT_INTR_LSC, 1676 NULL); 1677 1678 bnxt_print_link_info(eth_dev); 1679 } 1680 1681 return rc; 1682 } 1683 1684 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1685 { 1686 struct bnxt *bp = eth_dev->data->dev_private; 1687 struct bnxt_vnic_info *vnic; 1688 uint32_t old_flags; 1689 int rc; 1690 1691 rc = is_bnxt_in_error(bp); 1692 if (rc) 1693 return rc; 1694 1695 /* Filter settings will get applied when port is started */ 1696 if (!eth_dev->data->dev_started) 1697 return 0; 1698 1699 if (bp->vnic_info == NULL) 1700 return 0; 1701 1702 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1703 1704 old_flags = vnic->flags; 1705 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1706 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1707 if (rc != 0) 1708 vnic->flags = old_flags; 1709 1710 return rc; 1711 } 1712 1713 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1714 { 1715 struct bnxt *bp = eth_dev->data->dev_private; 1716 struct bnxt_vnic_info *vnic; 1717 uint32_t old_flags; 1718 int rc; 1719 1720 rc = is_bnxt_in_error(bp); 1721 if (rc) 1722 return rc; 1723 1724 /* Filter settings will get applied when port is started */ 1725 if (!eth_dev->data->dev_started) 1726 return 0; 1727 1728 if (bp->vnic_info == NULL) 1729 return 0; 1730 1731 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1732 1733 old_flags = vnic->flags; 1734 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1735 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1736 if (rc != 0) 1737 vnic->flags = old_flags; 1738 1739 return rc; 1740 } 1741 1742 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1743 { 1744 struct bnxt *bp = eth_dev->data->dev_private; 1745 struct bnxt_vnic_info *vnic; 1746 uint32_t old_flags; 1747 int rc; 1748 1749 rc = is_bnxt_in_error(bp); 1750 if (rc) 1751 return rc; 1752 1753 /* Filter settings will get applied when port is started */ 1754 if (!eth_dev->data->dev_started) 1755 return 0; 1756 1757 if (bp->vnic_info == NULL) 1758 return 0; 1759 1760 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1761 1762 old_flags = vnic->flags; 1763 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1765 if (rc != 0) 1766 vnic->flags = old_flags; 1767 1768 return rc; 1769 } 1770 1771 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1772 { 1773 struct bnxt *bp = eth_dev->data->dev_private; 1774 struct bnxt_vnic_info *vnic; 1775 uint32_t old_flags; 1776 int rc; 1777 1778 rc = is_bnxt_in_error(bp); 1779 if (rc) 1780 return rc; 1781 1782 /* Filter settings will get applied when port is started */ 1783 if (!eth_dev->data->dev_started) 1784 return 0; 1785 1786 if (bp->vnic_info == NULL) 1787 return 0; 1788 1789 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1790 1791 old_flags = vnic->flags; 1792 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1793 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1794 if (rc != 0) 1795 vnic->flags = old_flags; 1796 1797 return rc; 1798 } 1799 1800 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1801 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1802 { 1803 if (qid >= bp->rx_nr_rings) 1804 return NULL; 1805 1806 return bp->eth_dev->data->rx_queues[qid]; 1807 } 1808 1809 /* Return rxq corresponding to a given rss table ring/group ID. */ 1810 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1811 { 1812 struct bnxt_rx_queue *rxq; 1813 unsigned int i; 1814 1815 if (!BNXT_HAS_RING_GRPS(bp)) { 1816 for (i = 0; i < bp->rx_nr_rings; i++) { 1817 rxq = bp->eth_dev->data->rx_queues[i]; 1818 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1819 return rxq->index; 1820 } 1821 } else { 1822 for (i = 0; i < bp->rx_nr_rings; i++) { 1823 if (bp->grp_info[i].fw_grp_id == fwr) 1824 return i; 1825 } 1826 } 1827 1828 return INVALID_HW_RING_ID; 1829 } 1830 1831 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1832 struct rte_eth_rss_reta_entry64 *reta_conf, 1833 uint16_t reta_size) 1834 { 1835 struct bnxt *bp = eth_dev->data->dev_private; 1836 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1837 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1838 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1839 uint16_t idx, sft; 1840 int i, rc; 1841 1842 rc = is_bnxt_in_error(bp); 1843 if (rc) 1844 return rc; 1845 1846 if (!vnic->rss_table) 1847 return -EINVAL; 1848 1849 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1850 return -EINVAL; 1851 1852 if (reta_size != tbl_size) { 1853 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1854 "(%d) must equal the size supported by the hardware " 1855 "(%d)\n", reta_size, tbl_size); 1856 return -EINVAL; 1857 } 1858 1859 for (i = 0; i < reta_size; i++) { 1860 struct bnxt_rx_queue *rxq; 1861 1862 idx = i / RTE_RETA_GROUP_SIZE; 1863 sft = i % RTE_RETA_GROUP_SIZE; 1864 1865 if (!(reta_conf[idx].mask & (1ULL << sft))) 1866 continue; 1867 1868 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1869 if (!rxq) { 1870 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1871 return -EINVAL; 1872 } 1873 1874 if (BNXT_CHIP_P5(bp)) { 1875 vnic->rss_table[i * 2] = 1876 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1877 vnic->rss_table[i * 2 + 1] = 1878 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1879 } else { 1880 vnic->rss_table[i] = 1881 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1882 } 1883 } 1884 1885 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1886 return rc; 1887 } 1888 1889 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1890 struct rte_eth_rss_reta_entry64 *reta_conf, 1891 uint16_t reta_size) 1892 { 1893 struct bnxt *bp = eth_dev->data->dev_private; 1894 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1895 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1896 uint16_t idx, sft, i; 1897 int rc; 1898 1899 rc = is_bnxt_in_error(bp); 1900 if (rc) 1901 return rc; 1902 1903 /* Retrieve from the default VNIC */ 1904 if (!vnic) 1905 return -EINVAL; 1906 if (!vnic->rss_table) 1907 return -EINVAL; 1908 1909 if (reta_size != tbl_size) { 1910 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1911 "(%d) must equal the size supported by the hardware " 1912 "(%d)\n", reta_size, tbl_size); 1913 return -EINVAL; 1914 } 1915 1916 for (idx = 0, i = 0; i < reta_size; i++) { 1917 idx = i / RTE_RETA_GROUP_SIZE; 1918 sft = i % RTE_RETA_GROUP_SIZE; 1919 1920 if (reta_conf[idx].mask & (1ULL << sft)) { 1921 uint16_t qid; 1922 1923 if (BNXT_CHIP_P5(bp)) 1924 qid = bnxt_rss_to_qid(bp, 1925 vnic->rss_table[i * 2]); 1926 else 1927 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1928 1929 if (qid == INVALID_HW_RING_ID) { 1930 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1931 return -EINVAL; 1932 } 1933 reta_conf[idx].reta[sft] = qid; 1934 } 1935 } 1936 1937 return 0; 1938 } 1939 1940 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1941 struct rte_eth_rss_conf *rss_conf) 1942 { 1943 struct bnxt *bp = eth_dev->data->dev_private; 1944 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1945 struct bnxt_vnic_info *vnic; 1946 int rc; 1947 1948 rc = is_bnxt_in_error(bp); 1949 if (rc) 1950 return rc; 1951 1952 /* 1953 * If RSS enablement were different than dev_configure, 1954 * then return -EINVAL 1955 */ 1956 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1957 if (!rss_conf->rss_hf) 1958 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1959 } else { 1960 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1961 return -EINVAL; 1962 } 1963 1964 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1965 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 1966 rss_conf, 1967 sizeof(*rss_conf)); 1968 1969 /* Update the default RSS VNIC(s) */ 1970 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1971 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1972 vnic->hash_mode = 1973 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 1974 ETH_RSS_LEVEL(rss_conf->rss_hf)); 1975 1976 /* 1977 * If hashkey is not specified, use the previously configured 1978 * hashkey 1979 */ 1980 if (!rss_conf->rss_key) 1981 goto rss_config; 1982 1983 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1984 PMD_DRV_LOG(ERR, 1985 "Invalid hashkey length, should be 16 bytes\n"); 1986 return -EINVAL; 1987 } 1988 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1989 1990 rss_config: 1991 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1992 return rc; 1993 } 1994 1995 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1996 struct rte_eth_rss_conf *rss_conf) 1997 { 1998 struct bnxt *bp = eth_dev->data->dev_private; 1999 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2000 int len, rc; 2001 uint32_t hash_types; 2002 2003 rc = is_bnxt_in_error(bp); 2004 if (rc) 2005 return rc; 2006 2007 /* RSS configuration is the same for all VNICs */ 2008 if (vnic && vnic->rss_hash_key) { 2009 if (rss_conf->rss_key) { 2010 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2011 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2012 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2013 } 2014 2015 hash_types = vnic->hash_type; 2016 rss_conf->rss_hf = 0; 2017 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2018 rss_conf->rss_hf |= ETH_RSS_IPV4; 2019 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2020 } 2021 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2022 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2023 hash_types &= 2024 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2025 } 2026 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2027 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2028 hash_types &= 2029 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2030 } 2031 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2032 rss_conf->rss_hf |= ETH_RSS_IPV6; 2033 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2034 } 2035 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2036 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2037 hash_types &= 2038 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2039 } 2040 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2041 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2042 hash_types &= 2043 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2044 } 2045 2046 rss_conf->rss_hf |= 2047 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2048 2049 if (hash_types) { 2050 PMD_DRV_LOG(ERR, 2051 "Unknown RSS config from firmware (%08x), RSS disabled", 2052 vnic->hash_type); 2053 return -ENOTSUP; 2054 } 2055 } else { 2056 rss_conf->rss_hf = 0; 2057 } 2058 return 0; 2059 } 2060 2061 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2062 struct rte_eth_fc_conf *fc_conf) 2063 { 2064 struct bnxt *bp = dev->data->dev_private; 2065 struct rte_eth_link link_info; 2066 int rc; 2067 2068 rc = is_bnxt_in_error(bp); 2069 if (rc) 2070 return rc; 2071 2072 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2073 if (rc) 2074 return rc; 2075 2076 memset(fc_conf, 0, sizeof(*fc_conf)); 2077 if (bp->link_info->auto_pause) 2078 fc_conf->autoneg = 1; 2079 switch (bp->link_info->pause) { 2080 case 0: 2081 fc_conf->mode = RTE_FC_NONE; 2082 break; 2083 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2084 fc_conf->mode = RTE_FC_TX_PAUSE; 2085 break; 2086 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2087 fc_conf->mode = RTE_FC_RX_PAUSE; 2088 break; 2089 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2090 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2091 fc_conf->mode = RTE_FC_FULL; 2092 break; 2093 } 2094 return 0; 2095 } 2096 2097 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2098 struct rte_eth_fc_conf *fc_conf) 2099 { 2100 struct bnxt *bp = dev->data->dev_private; 2101 int rc; 2102 2103 rc = is_bnxt_in_error(bp); 2104 if (rc) 2105 return rc; 2106 2107 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2108 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 2109 return -ENOTSUP; 2110 } 2111 2112 switch (fc_conf->mode) { 2113 case RTE_FC_NONE: 2114 bp->link_info->auto_pause = 0; 2115 bp->link_info->force_pause = 0; 2116 break; 2117 case RTE_FC_RX_PAUSE: 2118 if (fc_conf->autoneg) { 2119 bp->link_info->auto_pause = 2120 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2121 bp->link_info->force_pause = 0; 2122 } else { 2123 bp->link_info->auto_pause = 0; 2124 bp->link_info->force_pause = 2125 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2126 } 2127 break; 2128 case RTE_FC_TX_PAUSE: 2129 if (fc_conf->autoneg) { 2130 bp->link_info->auto_pause = 2131 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2132 bp->link_info->force_pause = 0; 2133 } else { 2134 bp->link_info->auto_pause = 0; 2135 bp->link_info->force_pause = 2136 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2137 } 2138 break; 2139 case RTE_FC_FULL: 2140 if (fc_conf->autoneg) { 2141 bp->link_info->auto_pause = 2142 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2143 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2144 bp->link_info->force_pause = 0; 2145 } else { 2146 bp->link_info->auto_pause = 0; 2147 bp->link_info->force_pause = 2148 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2149 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2150 } 2151 break; 2152 } 2153 return bnxt_set_hwrm_link_config(bp, true); 2154 } 2155 2156 /* Add UDP tunneling port */ 2157 static int 2158 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2159 struct rte_eth_udp_tunnel *udp_tunnel) 2160 { 2161 struct bnxt *bp = eth_dev->data->dev_private; 2162 uint16_t tunnel_type = 0; 2163 int rc = 0; 2164 2165 rc = is_bnxt_in_error(bp); 2166 if (rc) 2167 return rc; 2168 2169 switch (udp_tunnel->prot_type) { 2170 case RTE_TUNNEL_TYPE_VXLAN: 2171 if (bp->vxlan_port_cnt) { 2172 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2173 udp_tunnel->udp_port); 2174 if (bp->vxlan_port != udp_tunnel->udp_port) { 2175 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2176 return -ENOSPC; 2177 } 2178 bp->vxlan_port_cnt++; 2179 return 0; 2180 } 2181 tunnel_type = 2182 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2183 bp->vxlan_port_cnt++; 2184 break; 2185 case RTE_TUNNEL_TYPE_GENEVE: 2186 if (bp->geneve_port_cnt) { 2187 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2188 udp_tunnel->udp_port); 2189 if (bp->geneve_port != udp_tunnel->udp_port) { 2190 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2191 return -ENOSPC; 2192 } 2193 bp->geneve_port_cnt++; 2194 return 0; 2195 } 2196 tunnel_type = 2197 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2198 bp->geneve_port_cnt++; 2199 break; 2200 default: 2201 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2202 return -ENOTSUP; 2203 } 2204 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2205 tunnel_type); 2206 return rc; 2207 } 2208 2209 static int 2210 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2211 struct rte_eth_udp_tunnel *udp_tunnel) 2212 { 2213 struct bnxt *bp = eth_dev->data->dev_private; 2214 uint16_t tunnel_type = 0; 2215 uint16_t port = 0; 2216 int rc = 0; 2217 2218 rc = is_bnxt_in_error(bp); 2219 if (rc) 2220 return rc; 2221 2222 switch (udp_tunnel->prot_type) { 2223 case RTE_TUNNEL_TYPE_VXLAN: 2224 if (!bp->vxlan_port_cnt) { 2225 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2226 return -EINVAL; 2227 } 2228 if (bp->vxlan_port != udp_tunnel->udp_port) { 2229 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2230 udp_tunnel->udp_port, bp->vxlan_port); 2231 return -EINVAL; 2232 } 2233 if (--bp->vxlan_port_cnt) 2234 return 0; 2235 2236 tunnel_type = 2237 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2238 port = bp->vxlan_fw_dst_port_id; 2239 break; 2240 case RTE_TUNNEL_TYPE_GENEVE: 2241 if (!bp->geneve_port_cnt) { 2242 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2243 return -EINVAL; 2244 } 2245 if (bp->geneve_port != udp_tunnel->udp_port) { 2246 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2247 udp_tunnel->udp_port, bp->geneve_port); 2248 return -EINVAL; 2249 } 2250 if (--bp->geneve_port_cnt) 2251 return 0; 2252 2253 tunnel_type = 2254 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2255 port = bp->geneve_fw_dst_port_id; 2256 break; 2257 default: 2258 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2259 return -ENOTSUP; 2260 } 2261 2262 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2263 return rc; 2264 } 2265 2266 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2267 { 2268 struct bnxt_filter_info *filter; 2269 struct bnxt_vnic_info *vnic; 2270 int rc = 0; 2271 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2272 2273 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2274 filter = STAILQ_FIRST(&vnic->filter); 2275 while (filter) { 2276 /* Search for this matching MAC+VLAN filter */ 2277 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2278 /* Delete the filter */ 2279 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2280 if (rc) 2281 return rc; 2282 STAILQ_REMOVE(&vnic->filter, filter, 2283 bnxt_filter_info, next); 2284 bnxt_free_filter(bp, filter); 2285 PMD_DRV_LOG(INFO, 2286 "Deleted vlan filter for %d\n", 2287 vlan_id); 2288 return 0; 2289 } 2290 filter = STAILQ_NEXT(filter, next); 2291 } 2292 return -ENOENT; 2293 } 2294 2295 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2296 { 2297 struct bnxt_filter_info *filter; 2298 struct bnxt_vnic_info *vnic; 2299 int rc = 0; 2300 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2301 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2302 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2303 2304 /* Implementation notes on the use of VNIC in this command: 2305 * 2306 * By default, these filters belong to default vnic for the function. 2307 * Once these filters are set up, only destination VNIC can be modified. 2308 * If the destination VNIC is not specified in this command, 2309 * then the HWRM shall only create an l2 context id. 2310 */ 2311 2312 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2313 filter = STAILQ_FIRST(&vnic->filter); 2314 /* Check if the VLAN has already been added */ 2315 while (filter) { 2316 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2317 return -EEXIST; 2318 2319 filter = STAILQ_NEXT(filter, next); 2320 } 2321 2322 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2323 * command to create MAC+VLAN filter with the right flags, enables set. 2324 */ 2325 filter = bnxt_alloc_filter(bp); 2326 if (!filter) { 2327 PMD_DRV_LOG(ERR, 2328 "MAC/VLAN filter alloc failed\n"); 2329 return -ENOMEM; 2330 } 2331 /* MAC + VLAN ID filter */ 2332 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2333 * untagged packets are received 2334 * 2335 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2336 * packets and only the programmed vlan's packets are received 2337 */ 2338 filter->l2_ivlan = vlan_id; 2339 filter->l2_ivlan_mask = 0x0FFF; 2340 filter->enables |= en; 2341 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2342 2343 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2344 if (rc) { 2345 /* Free the newly allocated filter as we were 2346 * not able to create the filter in hardware. 2347 */ 2348 bnxt_free_filter(bp, filter); 2349 return rc; 2350 } 2351 2352 filter->mac_index = 0; 2353 /* Add this new filter to the list */ 2354 if (vlan_id == 0) 2355 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2356 else 2357 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2358 2359 PMD_DRV_LOG(INFO, 2360 "Added Vlan filter for %d\n", vlan_id); 2361 return rc; 2362 } 2363 2364 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2365 uint16_t vlan_id, int on) 2366 { 2367 struct bnxt *bp = eth_dev->data->dev_private; 2368 int rc; 2369 2370 rc = is_bnxt_in_error(bp); 2371 if (rc) 2372 return rc; 2373 2374 if (!eth_dev->data->dev_started) { 2375 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2376 return -EINVAL; 2377 } 2378 2379 /* These operations apply to ALL existing MAC/VLAN filters */ 2380 if (on) 2381 return bnxt_add_vlan_filter(bp, vlan_id); 2382 else 2383 return bnxt_del_vlan_filter(bp, vlan_id); 2384 } 2385 2386 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2387 struct bnxt_vnic_info *vnic) 2388 { 2389 struct bnxt_filter_info *filter; 2390 int rc; 2391 2392 filter = STAILQ_FIRST(&vnic->filter); 2393 while (filter) { 2394 if (filter->mac_index == 0 && 2395 !memcmp(filter->l2_addr, bp->mac_addr, 2396 RTE_ETHER_ADDR_LEN)) { 2397 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2398 if (!rc) { 2399 STAILQ_REMOVE(&vnic->filter, filter, 2400 bnxt_filter_info, next); 2401 bnxt_free_filter(bp, filter); 2402 } 2403 return rc; 2404 } 2405 filter = STAILQ_NEXT(filter, next); 2406 } 2407 return 0; 2408 } 2409 2410 static int 2411 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2412 { 2413 struct bnxt_vnic_info *vnic; 2414 unsigned int i; 2415 int rc; 2416 2417 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2418 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2419 /* Remove any VLAN filters programmed */ 2420 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2421 bnxt_del_vlan_filter(bp, i); 2422 2423 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2424 if (rc) 2425 return rc; 2426 } else { 2427 /* Default filter will allow packets that match the 2428 * dest mac. So, it has to be deleted, otherwise, we 2429 * will endup receiving vlan packets for which the 2430 * filter is not programmed, when hw-vlan-filter 2431 * configuration is ON 2432 */ 2433 bnxt_del_dflt_mac_filter(bp, vnic); 2434 /* This filter will allow only untagged packets */ 2435 bnxt_add_vlan_filter(bp, 0); 2436 } 2437 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2438 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2439 2440 return 0; 2441 } 2442 2443 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2444 { 2445 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2446 unsigned int i; 2447 int rc; 2448 2449 /* Destroy vnic filters and vnic */ 2450 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2451 DEV_RX_OFFLOAD_VLAN_FILTER) { 2452 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2453 bnxt_del_vlan_filter(bp, i); 2454 } 2455 bnxt_del_dflt_mac_filter(bp, vnic); 2456 2457 rc = bnxt_hwrm_vnic_free(bp, vnic); 2458 if (rc) 2459 return rc; 2460 2461 rte_free(vnic->fw_grp_ids); 2462 vnic->fw_grp_ids = NULL; 2463 2464 vnic->rx_queue_cnt = 0; 2465 2466 return 0; 2467 } 2468 2469 static int 2470 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2471 { 2472 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2473 int rc; 2474 2475 /* Destroy, recreate and reconfigure the default vnic */ 2476 rc = bnxt_free_one_vnic(bp, 0); 2477 if (rc) 2478 return rc; 2479 2480 /* default vnic 0 */ 2481 rc = bnxt_setup_one_vnic(bp, 0); 2482 if (rc) 2483 return rc; 2484 2485 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2486 DEV_RX_OFFLOAD_VLAN_FILTER) { 2487 rc = bnxt_add_vlan_filter(bp, 0); 2488 if (rc) 2489 return rc; 2490 rc = bnxt_restore_vlan_filters(bp); 2491 if (rc) 2492 return rc; 2493 } else { 2494 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2495 if (rc) 2496 return rc; 2497 } 2498 2499 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2500 if (rc) 2501 return rc; 2502 2503 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2504 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2505 2506 return rc; 2507 } 2508 2509 static int 2510 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2511 { 2512 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2513 struct bnxt *bp = dev->data->dev_private; 2514 int rc; 2515 2516 rc = is_bnxt_in_error(bp); 2517 if (rc) 2518 return rc; 2519 2520 /* Filter settings will get applied when port is started */ 2521 if (!dev->data->dev_started) 2522 return 0; 2523 2524 if (mask & ETH_VLAN_FILTER_MASK) { 2525 /* Enable or disable VLAN filtering */ 2526 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2527 if (rc) 2528 return rc; 2529 } 2530 2531 if (mask & ETH_VLAN_STRIP_MASK) { 2532 /* Enable or disable VLAN stripping */ 2533 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2534 if (rc) 2535 return rc; 2536 } 2537 2538 if (mask & ETH_VLAN_EXTEND_MASK) { 2539 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2540 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2541 else 2542 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2543 } 2544 2545 return 0; 2546 } 2547 2548 static int 2549 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2550 uint16_t tpid) 2551 { 2552 struct bnxt *bp = dev->data->dev_private; 2553 int qinq = dev->data->dev_conf.rxmode.offloads & 2554 DEV_RX_OFFLOAD_VLAN_EXTEND; 2555 2556 if (vlan_type != ETH_VLAN_TYPE_INNER && 2557 vlan_type != ETH_VLAN_TYPE_OUTER) { 2558 PMD_DRV_LOG(ERR, 2559 "Unsupported vlan type."); 2560 return -EINVAL; 2561 } 2562 if (!qinq) { 2563 PMD_DRV_LOG(ERR, 2564 "QinQ not enabled. Needs to be ON as we can " 2565 "accelerate only outer vlan\n"); 2566 return -EINVAL; 2567 } 2568 2569 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2570 switch (tpid) { 2571 case RTE_ETHER_TYPE_QINQ: 2572 bp->outer_tpid_bd = 2573 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2574 break; 2575 case RTE_ETHER_TYPE_VLAN: 2576 bp->outer_tpid_bd = 2577 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2578 break; 2579 case RTE_ETHER_TYPE_QINQ1: 2580 bp->outer_tpid_bd = 2581 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2582 break; 2583 case RTE_ETHER_TYPE_QINQ2: 2584 bp->outer_tpid_bd = 2585 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2586 break; 2587 case RTE_ETHER_TYPE_QINQ3: 2588 bp->outer_tpid_bd = 2589 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2590 break; 2591 default: 2592 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2593 return -EINVAL; 2594 } 2595 bp->outer_tpid_bd |= tpid; 2596 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2597 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2598 PMD_DRV_LOG(ERR, 2599 "Can accelerate only outer vlan in QinQ\n"); 2600 return -EINVAL; 2601 } 2602 2603 return 0; 2604 } 2605 2606 static int 2607 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2608 struct rte_ether_addr *addr) 2609 { 2610 struct bnxt *bp = dev->data->dev_private; 2611 /* Default Filter is tied to VNIC 0 */ 2612 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2613 int rc; 2614 2615 rc = is_bnxt_in_error(bp); 2616 if (rc) 2617 return rc; 2618 2619 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2620 return -EPERM; 2621 2622 if (rte_is_zero_ether_addr(addr)) 2623 return -EINVAL; 2624 2625 /* Filter settings will get applied when port is started */ 2626 if (!dev->data->dev_started) 2627 return 0; 2628 2629 /* Check if the requested MAC is already added */ 2630 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2631 return 0; 2632 2633 /* Destroy filter and re-create it */ 2634 bnxt_del_dflt_mac_filter(bp, vnic); 2635 2636 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2637 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2638 /* This filter will allow only untagged packets */ 2639 rc = bnxt_add_vlan_filter(bp, 0); 2640 } else { 2641 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2642 } 2643 2644 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2645 return rc; 2646 } 2647 2648 static int 2649 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2650 struct rte_ether_addr *mc_addr_set, 2651 uint32_t nb_mc_addr) 2652 { 2653 struct bnxt *bp = eth_dev->data->dev_private; 2654 char *mc_addr_list = (char *)mc_addr_set; 2655 struct bnxt_vnic_info *vnic; 2656 uint32_t off = 0, i = 0; 2657 int rc; 2658 2659 rc = is_bnxt_in_error(bp); 2660 if (rc) 2661 return rc; 2662 2663 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2664 2665 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2666 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2667 goto allmulti; 2668 } 2669 2670 /* TODO Check for Duplicate mcast addresses */ 2671 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2672 for (i = 0; i < nb_mc_addr; i++) { 2673 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2674 RTE_ETHER_ADDR_LEN); 2675 off += RTE_ETHER_ADDR_LEN; 2676 } 2677 2678 vnic->mc_addr_cnt = i; 2679 if (vnic->mc_addr_cnt) 2680 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2681 else 2682 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2683 2684 allmulti: 2685 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2686 } 2687 2688 static int 2689 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2690 { 2691 struct bnxt *bp = dev->data->dev_private; 2692 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2693 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2694 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2695 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2696 int ret; 2697 2698 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2699 fw_major, fw_minor, fw_updt, fw_rsvd); 2700 2701 ret += 1; /* add the size of '\0' */ 2702 if (fw_size < (uint32_t)ret) 2703 return ret; 2704 else 2705 return 0; 2706 } 2707 2708 static void 2709 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2710 struct rte_eth_rxq_info *qinfo) 2711 { 2712 struct bnxt *bp = dev->data->dev_private; 2713 struct bnxt_rx_queue *rxq; 2714 2715 if (is_bnxt_in_error(bp)) 2716 return; 2717 2718 rxq = dev->data->rx_queues[queue_id]; 2719 2720 qinfo->mp = rxq->mb_pool; 2721 qinfo->scattered_rx = dev->data->scattered_rx; 2722 qinfo->nb_desc = rxq->nb_rx_desc; 2723 2724 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2725 qinfo->conf.rx_drop_en = rxq->drop_en; 2726 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2727 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2728 } 2729 2730 static void 2731 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2732 struct rte_eth_txq_info *qinfo) 2733 { 2734 struct bnxt *bp = dev->data->dev_private; 2735 struct bnxt_tx_queue *txq; 2736 2737 if (is_bnxt_in_error(bp)) 2738 return; 2739 2740 txq = dev->data->tx_queues[queue_id]; 2741 2742 qinfo->nb_desc = txq->nb_tx_desc; 2743 2744 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2745 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2746 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2747 2748 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2749 qinfo->conf.tx_rs_thresh = 0; 2750 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2751 qinfo->conf.offloads = txq->offloads; 2752 } 2753 2754 static const struct { 2755 eth_rx_burst_t pkt_burst; 2756 const char *info; 2757 } bnxt_rx_burst_info[] = { 2758 {bnxt_recv_pkts, "Scalar"}, 2759 #if defined(RTE_ARCH_X86) 2760 {bnxt_recv_pkts_vec, "Vector SSE"}, 2761 #elif defined(RTE_ARCH_ARM64) 2762 {bnxt_recv_pkts_vec, "Vector Neon"}, 2763 #endif 2764 }; 2765 2766 static int 2767 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2768 struct rte_eth_burst_mode *mode) 2769 { 2770 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2771 size_t i; 2772 2773 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2774 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2775 snprintf(mode->info, sizeof(mode->info), "%s", 2776 bnxt_rx_burst_info[i].info); 2777 return 0; 2778 } 2779 } 2780 2781 return -EINVAL; 2782 } 2783 2784 static const struct { 2785 eth_tx_burst_t pkt_burst; 2786 const char *info; 2787 } bnxt_tx_burst_info[] = { 2788 {bnxt_xmit_pkts, "Scalar"}, 2789 #if defined(RTE_ARCH_X86) 2790 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2791 #elif defined(RTE_ARCH_ARM64) 2792 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2793 #endif 2794 }; 2795 2796 static int 2797 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2798 struct rte_eth_burst_mode *mode) 2799 { 2800 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2801 size_t i; 2802 2803 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2804 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2805 snprintf(mode->info, sizeof(mode->info), "%s", 2806 bnxt_tx_burst_info[i].info); 2807 return 0; 2808 } 2809 } 2810 2811 return -EINVAL; 2812 } 2813 2814 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2815 { 2816 struct bnxt *bp = eth_dev->data->dev_private; 2817 uint32_t new_pkt_size; 2818 uint32_t rc = 0; 2819 uint32_t i; 2820 2821 rc = is_bnxt_in_error(bp); 2822 if (rc) 2823 return rc; 2824 2825 /* Exit if receive queues are not configured yet */ 2826 if (!eth_dev->data->nb_rx_queues) 2827 return rc; 2828 2829 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2830 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2831 2832 /* 2833 * Disallow any MTU change that would require scattered receive support 2834 * if it is not already enabled. 2835 */ 2836 if (eth_dev->data->dev_started && 2837 !eth_dev->data->scattered_rx && 2838 (new_pkt_size > 2839 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2840 PMD_DRV_LOG(ERR, 2841 "MTU change would require scattered rx support. "); 2842 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2843 return -EINVAL; 2844 } 2845 2846 if (new_mtu > RTE_ETHER_MTU) { 2847 bp->flags |= BNXT_FLAG_JUMBO; 2848 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2849 DEV_RX_OFFLOAD_JUMBO_FRAME; 2850 } else { 2851 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2852 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2853 bp->flags &= ~BNXT_FLAG_JUMBO; 2854 } 2855 2856 /* Is there a change in mtu setting? */ 2857 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2858 return rc; 2859 2860 for (i = 0; i < bp->nr_vnics; i++) { 2861 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2862 uint16_t size = 0; 2863 2864 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2865 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2866 if (rc) 2867 break; 2868 2869 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2870 size -= RTE_PKTMBUF_HEADROOM; 2871 2872 if (size < new_mtu) { 2873 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2874 if (rc) 2875 return rc; 2876 } 2877 } 2878 2879 if (!rc) 2880 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2881 2882 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2883 2884 return rc; 2885 } 2886 2887 static int 2888 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2889 { 2890 struct bnxt *bp = dev->data->dev_private; 2891 uint16_t vlan = bp->vlan; 2892 int rc; 2893 2894 rc = is_bnxt_in_error(bp); 2895 if (rc) 2896 return rc; 2897 2898 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2899 PMD_DRV_LOG(ERR, 2900 "PVID cannot be modified for this function\n"); 2901 return -ENOTSUP; 2902 } 2903 bp->vlan = on ? pvid : 0; 2904 2905 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2906 if (rc) 2907 bp->vlan = vlan; 2908 return rc; 2909 } 2910 2911 static int 2912 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2913 { 2914 struct bnxt *bp = dev->data->dev_private; 2915 int rc; 2916 2917 rc = is_bnxt_in_error(bp); 2918 if (rc) 2919 return rc; 2920 2921 return bnxt_hwrm_port_led_cfg(bp, true); 2922 } 2923 2924 static int 2925 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2926 { 2927 struct bnxt *bp = dev->data->dev_private; 2928 int rc; 2929 2930 rc = is_bnxt_in_error(bp); 2931 if (rc) 2932 return rc; 2933 2934 return bnxt_hwrm_port_led_cfg(bp, false); 2935 } 2936 2937 static uint32_t 2938 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2939 { 2940 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2941 uint32_t desc = 0, raw_cons = 0, cons; 2942 struct bnxt_cp_ring_info *cpr; 2943 struct bnxt_rx_queue *rxq; 2944 struct rx_pkt_cmpl *rxcmp; 2945 int rc; 2946 2947 rc = is_bnxt_in_error(bp); 2948 if (rc) 2949 return rc; 2950 2951 rxq = dev->data->rx_queues[rx_queue_id]; 2952 cpr = rxq->cp_ring; 2953 raw_cons = cpr->cp_raw_cons; 2954 2955 while (1) { 2956 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2957 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2958 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2959 2960 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2961 break; 2962 } else { 2963 raw_cons++; 2964 desc++; 2965 } 2966 } 2967 2968 return desc; 2969 } 2970 2971 static int 2972 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2973 { 2974 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2975 struct bnxt_rx_ring_info *rxr; 2976 struct bnxt_cp_ring_info *cpr; 2977 struct rte_mbuf *rx_buf; 2978 struct rx_pkt_cmpl *rxcmp; 2979 uint32_t cons, cp_cons; 2980 int rc; 2981 2982 if (!rxq) 2983 return -EINVAL; 2984 2985 rc = is_bnxt_in_error(rxq->bp); 2986 if (rc) 2987 return rc; 2988 2989 cpr = rxq->cp_ring; 2990 rxr = rxq->rx_ring; 2991 2992 if (offset >= rxq->nb_rx_desc) 2993 return -EINVAL; 2994 2995 cons = RING_CMP(cpr->cp_ring_struct, offset); 2996 cp_cons = cpr->cp_raw_cons; 2997 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2998 2999 if (cons > cp_cons) { 3000 if (CMPL_VALID(rxcmp, cpr->valid)) 3001 return RTE_ETH_RX_DESC_DONE; 3002 } else { 3003 if (CMPL_VALID(rxcmp, !cpr->valid)) 3004 return RTE_ETH_RX_DESC_DONE; 3005 } 3006 rx_buf = rxr->rx_buf_ring[cons]; 3007 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) 3008 return RTE_ETH_RX_DESC_UNAVAIL; 3009 3010 3011 return RTE_ETH_RX_DESC_AVAIL; 3012 } 3013 3014 static int 3015 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3016 { 3017 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3018 struct bnxt_tx_ring_info *txr; 3019 struct bnxt_cp_ring_info *cpr; 3020 struct bnxt_sw_tx_bd *tx_buf; 3021 struct tx_pkt_cmpl *txcmp; 3022 uint32_t cons, cp_cons; 3023 int rc; 3024 3025 if (!txq) 3026 return -EINVAL; 3027 3028 rc = is_bnxt_in_error(txq->bp); 3029 if (rc) 3030 return rc; 3031 3032 cpr = txq->cp_ring; 3033 txr = txq->tx_ring; 3034 3035 if (offset >= txq->nb_tx_desc) 3036 return -EINVAL; 3037 3038 cons = RING_CMP(cpr->cp_ring_struct, offset); 3039 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3040 cp_cons = cpr->cp_raw_cons; 3041 3042 if (cons > cp_cons) { 3043 if (CMPL_VALID(txcmp, cpr->valid)) 3044 return RTE_ETH_TX_DESC_UNAVAIL; 3045 } else { 3046 if (CMPL_VALID(txcmp, !cpr->valid)) 3047 return RTE_ETH_TX_DESC_UNAVAIL; 3048 } 3049 tx_buf = &txr->tx_buf_ring[cons]; 3050 if (tx_buf->mbuf == NULL) 3051 return RTE_ETH_TX_DESC_DONE; 3052 3053 return RTE_ETH_TX_DESC_FULL; 3054 } 3055 3056 int 3057 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3058 enum rte_filter_type filter_type, 3059 enum rte_filter_op filter_op, void *arg) 3060 { 3061 struct bnxt *bp = dev->data->dev_private; 3062 int ret = 0; 3063 3064 if (!bp) 3065 return -EIO; 3066 3067 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3068 struct bnxt_representor *vfr = dev->data->dev_private; 3069 bp = vfr->parent_dev->data->dev_private; 3070 /* parent is deleted while children are still valid */ 3071 if (!bp) { 3072 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n", 3073 dev->data->port_id, 3074 filter_type, 3075 filter_op); 3076 return -EIO; 3077 } 3078 } 3079 3080 ret = is_bnxt_in_error(bp); 3081 if (ret) 3082 return ret; 3083 3084 switch (filter_type) { 3085 case RTE_ETH_FILTER_GENERIC: 3086 if (filter_op != RTE_ETH_FILTER_GET) 3087 return -EINVAL; 3088 3089 /* PMD supports thread-safe flow operations. rte_flow API 3090 * functions can avoid mutex for multi-thread safety. 3091 */ 3092 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3093 3094 if (BNXT_TRUFLOW_EN(bp)) 3095 *(const void **)arg = &bnxt_ulp_rte_flow_ops; 3096 else 3097 *(const void **)arg = &bnxt_flow_ops; 3098 break; 3099 default: 3100 PMD_DRV_LOG(ERR, 3101 "Filter type (%d) not supported", filter_type); 3102 ret = -EINVAL; 3103 break; 3104 } 3105 return ret; 3106 } 3107 3108 static const uint32_t * 3109 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3110 { 3111 static const uint32_t ptypes[] = { 3112 RTE_PTYPE_L2_ETHER_VLAN, 3113 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3114 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3115 RTE_PTYPE_L4_ICMP, 3116 RTE_PTYPE_L4_TCP, 3117 RTE_PTYPE_L4_UDP, 3118 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3119 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3120 RTE_PTYPE_INNER_L4_ICMP, 3121 RTE_PTYPE_INNER_L4_TCP, 3122 RTE_PTYPE_INNER_L4_UDP, 3123 RTE_PTYPE_UNKNOWN 3124 }; 3125 3126 if (!dev->rx_pkt_burst) 3127 return NULL; 3128 3129 return ptypes; 3130 } 3131 3132 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3133 int reg_win) 3134 { 3135 uint32_t reg_base = *reg_arr & 0xfffff000; 3136 uint32_t win_off; 3137 int i; 3138 3139 for (i = 0; i < count; i++) { 3140 if ((reg_arr[i] & 0xfffff000) != reg_base) 3141 return -ERANGE; 3142 } 3143 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3144 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3145 return 0; 3146 } 3147 3148 static int bnxt_map_ptp_regs(struct bnxt *bp) 3149 { 3150 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3151 uint32_t *reg_arr; 3152 int rc, i; 3153 3154 reg_arr = ptp->rx_regs; 3155 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3156 if (rc) 3157 return rc; 3158 3159 reg_arr = ptp->tx_regs; 3160 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3161 if (rc) 3162 return rc; 3163 3164 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3165 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3166 3167 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3168 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3169 3170 return 0; 3171 } 3172 3173 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3174 { 3175 rte_write32(0, (uint8_t *)bp->bar0 + 3176 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3177 rte_write32(0, (uint8_t *)bp->bar0 + 3178 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3179 } 3180 3181 static uint64_t bnxt_cc_read(struct bnxt *bp) 3182 { 3183 uint64_t ns; 3184 3185 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3186 BNXT_GRCPF_REG_SYNC_TIME)); 3187 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3188 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3189 return ns; 3190 } 3191 3192 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3193 { 3194 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3195 uint32_t fifo; 3196 3197 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3198 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3199 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3200 return -EAGAIN; 3201 3202 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3203 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3204 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3205 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3206 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3207 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3208 3209 return 0; 3210 } 3211 3212 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3213 { 3214 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3215 struct bnxt_pf_info *pf = bp->pf; 3216 uint16_t port_id; 3217 uint32_t fifo; 3218 3219 if (!ptp) 3220 return -ENODEV; 3221 3222 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3223 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3224 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3225 return -EAGAIN; 3226 3227 port_id = pf->port_id; 3228 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3229 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3230 3231 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3232 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3233 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3234 /* bnxt_clr_rx_ts(bp); TBD */ 3235 return -EBUSY; 3236 } 3237 3238 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3239 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3240 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3241 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3242 3243 return 0; 3244 } 3245 3246 static int 3247 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3248 { 3249 uint64_t ns; 3250 struct bnxt *bp = dev->data->dev_private; 3251 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3252 3253 if (!ptp) 3254 return 0; 3255 3256 ns = rte_timespec_to_ns(ts); 3257 /* Set the timecounters to a new value. */ 3258 ptp->tc.nsec = ns; 3259 3260 return 0; 3261 } 3262 3263 static int 3264 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3265 { 3266 struct bnxt *bp = dev->data->dev_private; 3267 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3268 uint64_t ns, systime_cycles = 0; 3269 int rc = 0; 3270 3271 if (!ptp) 3272 return 0; 3273 3274 if (BNXT_CHIP_P5(bp)) 3275 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3276 &systime_cycles); 3277 else 3278 systime_cycles = bnxt_cc_read(bp); 3279 3280 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3281 *ts = rte_ns_to_timespec(ns); 3282 3283 return rc; 3284 } 3285 static int 3286 bnxt_timesync_enable(struct rte_eth_dev *dev) 3287 { 3288 struct bnxt *bp = dev->data->dev_private; 3289 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3290 uint32_t shift = 0; 3291 int rc; 3292 3293 if (!ptp) 3294 return 0; 3295 3296 ptp->rx_filter = 1; 3297 ptp->tx_tstamp_en = 1; 3298 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3299 3300 rc = bnxt_hwrm_ptp_cfg(bp); 3301 if (rc) 3302 return rc; 3303 3304 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3305 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3306 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3307 3308 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3309 ptp->tc.cc_shift = shift; 3310 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3311 3312 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3313 ptp->rx_tstamp_tc.cc_shift = shift; 3314 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3315 3316 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3317 ptp->tx_tstamp_tc.cc_shift = shift; 3318 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3319 3320 if (!BNXT_CHIP_P5(bp)) 3321 bnxt_map_ptp_regs(bp); 3322 3323 return 0; 3324 } 3325 3326 static int 3327 bnxt_timesync_disable(struct rte_eth_dev *dev) 3328 { 3329 struct bnxt *bp = dev->data->dev_private; 3330 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3331 3332 if (!ptp) 3333 return 0; 3334 3335 ptp->rx_filter = 0; 3336 ptp->tx_tstamp_en = 0; 3337 ptp->rxctl = 0; 3338 3339 bnxt_hwrm_ptp_cfg(bp); 3340 3341 if (!BNXT_CHIP_P5(bp)) 3342 bnxt_unmap_ptp_regs(bp); 3343 3344 return 0; 3345 } 3346 3347 static int 3348 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3349 struct timespec *timestamp, 3350 uint32_t flags __rte_unused) 3351 { 3352 struct bnxt *bp = dev->data->dev_private; 3353 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3354 uint64_t rx_tstamp_cycles = 0; 3355 uint64_t ns; 3356 3357 if (!ptp) 3358 return 0; 3359 3360 if (BNXT_CHIP_P5(bp)) 3361 rx_tstamp_cycles = ptp->rx_timestamp; 3362 else 3363 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3364 3365 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3366 *timestamp = rte_ns_to_timespec(ns); 3367 return 0; 3368 } 3369 3370 static int 3371 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3372 struct timespec *timestamp) 3373 { 3374 struct bnxt *bp = dev->data->dev_private; 3375 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3376 uint64_t tx_tstamp_cycles = 0; 3377 uint64_t ns; 3378 int rc = 0; 3379 3380 if (!ptp) 3381 return 0; 3382 3383 if (BNXT_CHIP_P5(bp)) 3384 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3385 &tx_tstamp_cycles); 3386 else 3387 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3388 3389 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3390 *timestamp = rte_ns_to_timespec(ns); 3391 3392 return rc; 3393 } 3394 3395 static int 3396 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3397 { 3398 struct bnxt *bp = dev->data->dev_private; 3399 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3400 3401 if (!ptp) 3402 return 0; 3403 3404 ptp->tc.nsec += delta; 3405 3406 return 0; 3407 } 3408 3409 static int 3410 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3411 { 3412 struct bnxt *bp = dev->data->dev_private; 3413 int rc; 3414 uint32_t dir_entries; 3415 uint32_t entry_length; 3416 3417 rc = is_bnxt_in_error(bp); 3418 if (rc) 3419 return rc; 3420 3421 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3422 bp->pdev->addr.domain, bp->pdev->addr.bus, 3423 bp->pdev->addr.devid, bp->pdev->addr.function); 3424 3425 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3426 if (rc != 0) 3427 return rc; 3428 3429 return dir_entries * entry_length; 3430 } 3431 3432 static int 3433 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3434 struct rte_dev_eeprom_info *in_eeprom) 3435 { 3436 struct bnxt *bp = dev->data->dev_private; 3437 uint32_t index; 3438 uint32_t offset; 3439 int rc; 3440 3441 rc = is_bnxt_in_error(bp); 3442 if (rc) 3443 return rc; 3444 3445 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3446 bp->pdev->addr.domain, bp->pdev->addr.bus, 3447 bp->pdev->addr.devid, bp->pdev->addr.function, 3448 in_eeprom->offset, in_eeprom->length); 3449 3450 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3451 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3452 in_eeprom->data); 3453 3454 index = in_eeprom->offset >> 24; 3455 offset = in_eeprom->offset & 0xffffff; 3456 3457 if (index != 0) 3458 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3459 in_eeprom->length, in_eeprom->data); 3460 3461 return 0; 3462 } 3463 3464 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3465 { 3466 switch (dir_type) { 3467 case BNX_DIR_TYPE_CHIMP_PATCH: 3468 case BNX_DIR_TYPE_BOOTCODE: 3469 case BNX_DIR_TYPE_BOOTCODE_2: 3470 case BNX_DIR_TYPE_APE_FW: 3471 case BNX_DIR_TYPE_APE_PATCH: 3472 case BNX_DIR_TYPE_KONG_FW: 3473 case BNX_DIR_TYPE_KONG_PATCH: 3474 case BNX_DIR_TYPE_BONO_FW: 3475 case BNX_DIR_TYPE_BONO_PATCH: 3476 /* FALLTHROUGH */ 3477 return true; 3478 } 3479 3480 return false; 3481 } 3482 3483 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3484 { 3485 switch (dir_type) { 3486 case BNX_DIR_TYPE_AVS: 3487 case BNX_DIR_TYPE_EXP_ROM_MBA: 3488 case BNX_DIR_TYPE_PCIE: 3489 case BNX_DIR_TYPE_TSCF_UCODE: 3490 case BNX_DIR_TYPE_EXT_PHY: 3491 case BNX_DIR_TYPE_CCM: 3492 case BNX_DIR_TYPE_ISCSI_BOOT: 3493 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3494 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3495 /* FALLTHROUGH */ 3496 return true; 3497 } 3498 3499 return false; 3500 } 3501 3502 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3503 { 3504 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3505 bnxt_dir_type_is_other_exec_format(dir_type); 3506 } 3507 3508 static int 3509 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3510 struct rte_dev_eeprom_info *in_eeprom) 3511 { 3512 struct bnxt *bp = dev->data->dev_private; 3513 uint8_t index, dir_op; 3514 uint16_t type, ext, ordinal, attr; 3515 int rc; 3516 3517 rc = is_bnxt_in_error(bp); 3518 if (rc) 3519 return rc; 3520 3521 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3522 bp->pdev->addr.domain, bp->pdev->addr.bus, 3523 bp->pdev->addr.devid, bp->pdev->addr.function, 3524 in_eeprom->offset, in_eeprom->length); 3525 3526 if (!BNXT_PF(bp)) { 3527 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3528 return -EINVAL; 3529 } 3530 3531 type = in_eeprom->magic >> 16; 3532 3533 if (type == 0xffff) { /* special value for directory operations */ 3534 index = in_eeprom->magic & 0xff; 3535 dir_op = in_eeprom->magic >> 8; 3536 if (index == 0) 3537 return -EINVAL; 3538 switch (dir_op) { 3539 case 0x0e: /* erase */ 3540 if (in_eeprom->offset != ~in_eeprom->magic) 3541 return -EINVAL; 3542 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3543 default: 3544 return -EINVAL; 3545 } 3546 } 3547 3548 /* Create or re-write an NVM item: */ 3549 if (bnxt_dir_type_is_executable(type) == true) 3550 return -EOPNOTSUPP; 3551 ext = in_eeprom->magic & 0xffff; 3552 ordinal = in_eeprom->offset >> 16; 3553 attr = in_eeprom->offset & 0xffff; 3554 3555 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3556 in_eeprom->data, in_eeprom->length); 3557 } 3558 3559 /* 3560 * Initialization 3561 */ 3562 3563 static const struct eth_dev_ops bnxt_dev_ops = { 3564 .dev_infos_get = bnxt_dev_info_get_op, 3565 .dev_close = bnxt_dev_close_op, 3566 .dev_configure = bnxt_dev_configure_op, 3567 .dev_start = bnxt_dev_start_op, 3568 .dev_stop = bnxt_dev_stop_op, 3569 .dev_set_link_up = bnxt_dev_set_link_up_op, 3570 .dev_set_link_down = bnxt_dev_set_link_down_op, 3571 .stats_get = bnxt_stats_get_op, 3572 .stats_reset = bnxt_stats_reset_op, 3573 .rx_queue_setup = bnxt_rx_queue_setup_op, 3574 .rx_queue_release = bnxt_rx_queue_release_op, 3575 .tx_queue_setup = bnxt_tx_queue_setup_op, 3576 .tx_queue_release = bnxt_tx_queue_release_op, 3577 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3578 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3579 .reta_update = bnxt_reta_update_op, 3580 .reta_query = bnxt_reta_query_op, 3581 .rss_hash_update = bnxt_rss_hash_update_op, 3582 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3583 .link_update = bnxt_link_update_op, 3584 .promiscuous_enable = bnxt_promiscuous_enable_op, 3585 .promiscuous_disable = bnxt_promiscuous_disable_op, 3586 .allmulticast_enable = bnxt_allmulticast_enable_op, 3587 .allmulticast_disable = bnxt_allmulticast_disable_op, 3588 .mac_addr_add = bnxt_mac_addr_add_op, 3589 .mac_addr_remove = bnxt_mac_addr_remove_op, 3590 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3591 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3592 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3593 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3594 .vlan_filter_set = bnxt_vlan_filter_set_op, 3595 .vlan_offload_set = bnxt_vlan_offload_set_op, 3596 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3597 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3598 .mtu_set = bnxt_mtu_set_op, 3599 .mac_addr_set = bnxt_set_default_mac_addr_op, 3600 .xstats_get = bnxt_dev_xstats_get_op, 3601 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3602 .xstats_reset = bnxt_dev_xstats_reset_op, 3603 .fw_version_get = bnxt_fw_version_get, 3604 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3605 .rxq_info_get = bnxt_rxq_info_get_op, 3606 .txq_info_get = bnxt_txq_info_get_op, 3607 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 3608 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 3609 .dev_led_on = bnxt_dev_led_on_op, 3610 .dev_led_off = bnxt_dev_led_off_op, 3611 .rx_queue_start = bnxt_rx_queue_start, 3612 .rx_queue_stop = bnxt_rx_queue_stop, 3613 .tx_queue_start = bnxt_tx_queue_start, 3614 .tx_queue_stop = bnxt_tx_queue_stop, 3615 .filter_ctrl = bnxt_filter_ctrl_op, 3616 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3617 .get_eeprom_length = bnxt_get_eeprom_length_op, 3618 .get_eeprom = bnxt_get_eeprom_op, 3619 .set_eeprom = bnxt_set_eeprom_op, 3620 .timesync_enable = bnxt_timesync_enable, 3621 .timesync_disable = bnxt_timesync_disable, 3622 .timesync_read_time = bnxt_timesync_read_time, 3623 .timesync_write_time = bnxt_timesync_write_time, 3624 .timesync_adjust_time = bnxt_timesync_adjust_time, 3625 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3626 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3627 }; 3628 3629 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3630 { 3631 uint32_t offset; 3632 3633 /* Only pre-map the reset GRC registers using window 3 */ 3634 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3635 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3636 3637 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3638 3639 return offset; 3640 } 3641 3642 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3643 { 3644 struct bnxt_error_recovery_info *info = bp->recovery_info; 3645 uint32_t reg_base = 0xffffffff; 3646 int i; 3647 3648 /* Only pre-map the monitoring GRC registers using window 2 */ 3649 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3650 uint32_t reg = info->status_regs[i]; 3651 3652 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3653 continue; 3654 3655 if (reg_base == 0xffffffff) 3656 reg_base = reg & 0xfffff000; 3657 if ((reg & 0xfffff000) != reg_base) 3658 return -ERANGE; 3659 3660 /* Use mask 0xffc as the Lower 2 bits indicates 3661 * address space location 3662 */ 3663 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3664 (reg & 0xffc); 3665 } 3666 3667 if (reg_base == 0xffffffff) 3668 return 0; 3669 3670 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3671 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3672 3673 return 0; 3674 } 3675 3676 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3677 { 3678 struct bnxt_error_recovery_info *info = bp->recovery_info; 3679 uint32_t delay = info->delay_after_reset[index]; 3680 uint32_t val = info->reset_reg_val[index]; 3681 uint32_t reg = info->reset_reg[index]; 3682 uint32_t type, offset; 3683 3684 type = BNXT_FW_STATUS_REG_TYPE(reg); 3685 offset = BNXT_FW_STATUS_REG_OFF(reg); 3686 3687 switch (type) { 3688 case BNXT_FW_STATUS_REG_TYPE_CFG: 3689 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3690 break; 3691 case BNXT_FW_STATUS_REG_TYPE_GRC: 3692 offset = bnxt_map_reset_regs(bp, offset); 3693 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3694 break; 3695 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3696 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3697 break; 3698 } 3699 /* wait on a specific interval of time until core reset is complete */ 3700 if (delay) 3701 rte_delay_ms(delay); 3702 } 3703 3704 static void bnxt_dev_cleanup(struct bnxt *bp) 3705 { 3706 bp->eth_dev->data->dev_link.link_status = 0; 3707 bp->link_info->link_up = 0; 3708 if (bp->eth_dev->data->dev_started) 3709 bnxt_dev_stop(bp->eth_dev); 3710 3711 bnxt_uninit_resources(bp, true); 3712 } 3713 3714 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3715 { 3716 struct rte_eth_dev *dev = bp->eth_dev; 3717 struct rte_vlan_filter_conf *vfc; 3718 int vidx, vbit, rc; 3719 uint16_t vlan_id; 3720 3721 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3722 vfc = &dev->data->vlan_filter_conf; 3723 vidx = vlan_id / 64; 3724 vbit = vlan_id % 64; 3725 3726 /* Each bit corresponds to a VLAN id */ 3727 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3728 rc = bnxt_add_vlan_filter(bp, vlan_id); 3729 if (rc) 3730 return rc; 3731 } 3732 } 3733 3734 return 0; 3735 } 3736 3737 static int bnxt_restore_mac_filters(struct bnxt *bp) 3738 { 3739 struct rte_eth_dev *dev = bp->eth_dev; 3740 struct rte_eth_dev_info dev_info; 3741 struct rte_ether_addr *addr; 3742 uint64_t pool_mask; 3743 uint32_t pool = 0; 3744 uint16_t i; 3745 int rc; 3746 3747 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 3748 return 0; 3749 3750 rc = bnxt_dev_info_get_op(dev, &dev_info); 3751 if (rc) 3752 return rc; 3753 3754 /* replay MAC address configuration */ 3755 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3756 addr = &dev->data->mac_addrs[i]; 3757 3758 /* skip zero address */ 3759 if (rte_is_zero_ether_addr(addr)) 3760 continue; 3761 3762 pool = 0; 3763 pool_mask = dev->data->mac_pool_sel[i]; 3764 3765 do { 3766 if (pool_mask & 1ULL) { 3767 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3768 if (rc) 3769 return rc; 3770 } 3771 pool_mask >>= 1; 3772 pool++; 3773 } while (pool_mask); 3774 } 3775 3776 return 0; 3777 } 3778 3779 static int bnxt_restore_filters(struct bnxt *bp) 3780 { 3781 struct rte_eth_dev *dev = bp->eth_dev; 3782 int ret = 0; 3783 3784 if (dev->data->all_multicast) { 3785 ret = bnxt_allmulticast_enable_op(dev); 3786 if (ret) 3787 return ret; 3788 } 3789 if (dev->data->promiscuous) { 3790 ret = bnxt_promiscuous_enable_op(dev); 3791 if (ret) 3792 return ret; 3793 } 3794 3795 ret = bnxt_restore_mac_filters(bp); 3796 if (ret) 3797 return ret; 3798 3799 ret = bnxt_restore_vlan_filters(bp); 3800 /* TODO restore other filters as well */ 3801 return ret; 3802 } 3803 3804 static void bnxt_dev_recover(void *arg) 3805 { 3806 struct bnxt *bp = arg; 3807 int timeout = bp->fw_reset_max_msecs; 3808 int rc = 0; 3809 3810 pthread_mutex_lock(&bp->err_recovery_lock); 3811 /* Clear Error flag so that device re-init should happen */ 3812 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 3813 3814 do { 3815 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); 3816 if (rc == 0) 3817 break; 3818 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 3819 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 3820 } while (rc && timeout); 3821 3822 if (rc) { 3823 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 3824 goto err; 3825 } 3826 3827 rc = bnxt_init_resources(bp, true); 3828 if (rc) { 3829 PMD_DRV_LOG(ERR, 3830 "Failed to initialize resources after reset\n"); 3831 goto err; 3832 } 3833 /* clear reset flag as the device is initialized now */ 3834 bp->flags &= ~BNXT_FLAG_FW_RESET; 3835 3836 rc = bnxt_dev_start_op(bp->eth_dev); 3837 if (rc) { 3838 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 3839 goto err_start; 3840 } 3841 3842 rc = bnxt_restore_filters(bp); 3843 if (rc) 3844 goto err_start; 3845 3846 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 3847 pthread_mutex_unlock(&bp->err_recovery_lock); 3848 3849 return; 3850 err_start: 3851 bnxt_dev_stop(bp->eth_dev); 3852 err: 3853 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3854 bnxt_uninit_resources(bp, false); 3855 pthread_mutex_unlock(&bp->err_recovery_lock); 3856 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 3857 } 3858 3859 void bnxt_dev_reset_and_resume(void *arg) 3860 { 3861 struct bnxt *bp = arg; 3862 int rc; 3863 3864 bnxt_dev_cleanup(bp); 3865 3866 bnxt_wait_for_device_shutdown(bp); 3867 3868 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 3869 bnxt_dev_recover, (void *)bp); 3870 if (rc) 3871 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 3872 } 3873 3874 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 3875 { 3876 struct bnxt_error_recovery_info *info = bp->recovery_info; 3877 uint32_t reg = info->status_regs[index]; 3878 uint32_t type, offset, val = 0; 3879 3880 type = BNXT_FW_STATUS_REG_TYPE(reg); 3881 offset = BNXT_FW_STATUS_REG_OFF(reg); 3882 3883 switch (type) { 3884 case BNXT_FW_STATUS_REG_TYPE_CFG: 3885 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 3886 break; 3887 case BNXT_FW_STATUS_REG_TYPE_GRC: 3888 offset = info->mapped_status_regs[index]; 3889 /* FALLTHROUGH */ 3890 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3891 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3892 offset)); 3893 break; 3894 } 3895 3896 return val; 3897 } 3898 3899 static int bnxt_fw_reset_all(struct bnxt *bp) 3900 { 3901 struct bnxt_error_recovery_info *info = bp->recovery_info; 3902 uint32_t i; 3903 int rc = 0; 3904 3905 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3906 /* Reset through master function driver */ 3907 for (i = 0; i < info->reg_array_cnt; i++) 3908 bnxt_write_fw_reset_reg(bp, i); 3909 /* Wait for time specified by FW after triggering reset */ 3910 rte_delay_ms(info->master_func_wait_period_after_reset); 3911 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 3912 /* Reset with the help of Kong processor */ 3913 rc = bnxt_hwrm_fw_reset(bp); 3914 if (rc) 3915 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 3916 } 3917 3918 return rc; 3919 } 3920 3921 static void bnxt_fw_reset_cb(void *arg) 3922 { 3923 struct bnxt *bp = arg; 3924 struct bnxt_error_recovery_info *info = bp->recovery_info; 3925 int rc = 0; 3926 3927 /* Only Master function can do FW reset */ 3928 if (bnxt_is_master_func(bp) && 3929 bnxt_is_recovery_enabled(bp)) { 3930 rc = bnxt_fw_reset_all(bp); 3931 if (rc) { 3932 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 3933 return; 3934 } 3935 } 3936 3937 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 3938 * EXCEPTION_FATAL_ASYNC event to all the functions 3939 * (including MASTER FUNC). After receiving this Async, all the active 3940 * drivers should treat this case as FW initiated recovery 3941 */ 3942 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3943 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 3944 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 3945 3946 /* To recover from error */ 3947 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 3948 (void *)bp); 3949 } 3950 } 3951 3952 /* Driver should poll FW heartbeat, reset_counter with the frequency 3953 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 3954 * When the driver detects heartbeat stop or change in reset_counter, 3955 * it has to trigger a reset to recover from the error condition. 3956 * A “master PF” is the function who will have the privilege to 3957 * initiate the chimp reset. The master PF will be elected by the 3958 * firmware and will be notified through async message. 3959 */ 3960 static void bnxt_check_fw_health(void *arg) 3961 { 3962 struct bnxt *bp = arg; 3963 struct bnxt_error_recovery_info *info = bp->recovery_info; 3964 uint32_t val = 0, wait_msec; 3965 3966 if (!info || !bnxt_is_recovery_enabled(bp) || 3967 is_bnxt_in_error(bp)) 3968 return; 3969 3970 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 3971 if (val == info->last_heart_beat) 3972 goto reset; 3973 3974 info->last_heart_beat = val; 3975 3976 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 3977 if (val != info->last_reset_counter) 3978 goto reset; 3979 3980 info->last_reset_counter = val; 3981 3982 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 3983 bnxt_check_fw_health, (void *)bp); 3984 3985 return; 3986 reset: 3987 /* Stop DMA to/from device */ 3988 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3989 bp->flags |= BNXT_FLAG_FW_RESET; 3990 3991 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 3992 3993 if (bnxt_is_master_func(bp)) 3994 wait_msec = info->master_func_wait_period; 3995 else 3996 wait_msec = info->normal_func_wait_period; 3997 3998 rte_eal_alarm_set(US_PER_MS * wait_msec, 3999 bnxt_fw_reset_cb, (void *)bp); 4000 } 4001 4002 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4003 { 4004 uint32_t polling_freq; 4005 4006 pthread_mutex_lock(&bp->health_check_lock); 4007 4008 if (!bnxt_is_recovery_enabled(bp)) 4009 goto done; 4010 4011 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4012 goto done; 4013 4014 polling_freq = bp->recovery_info->driver_polling_freq; 4015 4016 rte_eal_alarm_set(US_PER_MS * polling_freq, 4017 bnxt_check_fw_health, (void *)bp); 4018 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4019 4020 done: 4021 pthread_mutex_unlock(&bp->health_check_lock); 4022 } 4023 4024 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4025 { 4026 if (!bnxt_is_recovery_enabled(bp)) 4027 return; 4028 4029 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4030 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4031 } 4032 4033 static bool bnxt_vf_pciid(uint16_t device_id) 4034 { 4035 switch (device_id) { 4036 case BROADCOM_DEV_ID_57304_VF: 4037 case BROADCOM_DEV_ID_57406_VF: 4038 case BROADCOM_DEV_ID_5731X_VF: 4039 case BROADCOM_DEV_ID_5741X_VF: 4040 case BROADCOM_DEV_ID_57414_VF: 4041 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4042 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4043 case BROADCOM_DEV_ID_58802_VF: 4044 case BROADCOM_DEV_ID_57500_VF1: 4045 case BROADCOM_DEV_ID_57500_VF2: 4046 case BROADCOM_DEV_ID_58818_VF: 4047 /* FALLTHROUGH */ 4048 return true; 4049 default: 4050 return false; 4051 } 4052 } 4053 4054 /* Phase 5 device */ 4055 static bool bnxt_p5_device(uint16_t device_id) 4056 { 4057 switch (device_id) { 4058 case BROADCOM_DEV_ID_57508: 4059 case BROADCOM_DEV_ID_57504: 4060 case BROADCOM_DEV_ID_57502: 4061 case BROADCOM_DEV_ID_57508_MF1: 4062 case BROADCOM_DEV_ID_57504_MF1: 4063 case BROADCOM_DEV_ID_57502_MF1: 4064 case BROADCOM_DEV_ID_57508_MF2: 4065 case BROADCOM_DEV_ID_57504_MF2: 4066 case BROADCOM_DEV_ID_57502_MF2: 4067 case BROADCOM_DEV_ID_57500_VF1: 4068 case BROADCOM_DEV_ID_57500_VF2: 4069 case BROADCOM_DEV_ID_58812: 4070 case BROADCOM_DEV_ID_58814: 4071 case BROADCOM_DEV_ID_58818: 4072 case BROADCOM_DEV_ID_58818_VF: 4073 /* FALLTHROUGH */ 4074 return true; 4075 default: 4076 return false; 4077 } 4078 } 4079 4080 bool bnxt_stratus_device(struct bnxt *bp) 4081 { 4082 uint16_t device_id = bp->pdev->id.device_id; 4083 4084 switch (device_id) { 4085 case BROADCOM_DEV_ID_STRATUS_NIC: 4086 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4087 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4088 /* FALLTHROUGH */ 4089 return true; 4090 default: 4091 return false; 4092 } 4093 } 4094 4095 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4096 { 4097 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4098 struct bnxt *bp = eth_dev->data->dev_private; 4099 4100 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4101 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4102 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4103 if (!bp->bar0 || !bp->doorbell_base) { 4104 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4105 return -ENODEV; 4106 } 4107 4108 bp->eth_dev = eth_dev; 4109 bp->pdev = pci_dev; 4110 4111 return 0; 4112 } 4113 4114 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4115 struct bnxt_ctx_pg_info *ctx_pg, 4116 uint32_t mem_size, 4117 const char *suffix, 4118 uint16_t idx) 4119 { 4120 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4121 const struct rte_memzone *mz = NULL; 4122 char mz_name[RTE_MEMZONE_NAMESIZE]; 4123 rte_iova_t mz_phys_addr; 4124 uint64_t valid_bits = 0; 4125 uint32_t sz; 4126 int i; 4127 4128 if (!mem_size) 4129 return 0; 4130 4131 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4132 BNXT_PAGE_SIZE; 4133 rmem->page_size = BNXT_PAGE_SIZE; 4134 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4135 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4136 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4137 4138 valid_bits = PTU_PTE_VALID; 4139 4140 if (rmem->nr_pages > 1) { 4141 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4142 "bnxt_ctx_pg_tbl%s_%x_%d", 4143 suffix, idx, bp->eth_dev->data->port_id); 4144 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4145 mz = rte_memzone_lookup(mz_name); 4146 if (!mz) { 4147 mz = rte_memzone_reserve_aligned(mz_name, 4148 rmem->nr_pages * 8, 4149 SOCKET_ID_ANY, 4150 RTE_MEMZONE_2MB | 4151 RTE_MEMZONE_SIZE_HINT_ONLY | 4152 RTE_MEMZONE_IOVA_CONTIG, 4153 BNXT_PAGE_SIZE); 4154 if (mz == NULL) 4155 return -ENOMEM; 4156 } 4157 4158 memset(mz->addr, 0, mz->len); 4159 mz_phys_addr = mz->iova; 4160 4161 rmem->pg_tbl = mz->addr; 4162 rmem->pg_tbl_map = mz_phys_addr; 4163 rmem->pg_tbl_mz = mz; 4164 } 4165 4166 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4167 suffix, idx, bp->eth_dev->data->port_id); 4168 mz = rte_memzone_lookup(mz_name); 4169 if (!mz) { 4170 mz = rte_memzone_reserve_aligned(mz_name, 4171 mem_size, 4172 SOCKET_ID_ANY, 4173 RTE_MEMZONE_1GB | 4174 RTE_MEMZONE_SIZE_HINT_ONLY | 4175 RTE_MEMZONE_IOVA_CONTIG, 4176 BNXT_PAGE_SIZE); 4177 if (mz == NULL) 4178 return -ENOMEM; 4179 } 4180 4181 memset(mz->addr, 0, mz->len); 4182 mz_phys_addr = mz->iova; 4183 4184 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4185 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4186 rmem->dma_arr[i] = mz_phys_addr + sz; 4187 4188 if (rmem->nr_pages > 1) { 4189 if (i == rmem->nr_pages - 2 && 4190 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4191 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4192 else if (i == rmem->nr_pages - 1 && 4193 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4194 valid_bits |= PTU_PTE_LAST; 4195 4196 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4197 valid_bits); 4198 } 4199 } 4200 4201 rmem->mz = mz; 4202 if (rmem->vmem_size) 4203 rmem->vmem = (void **)mz->addr; 4204 rmem->dma_arr[0] = mz_phys_addr; 4205 return 0; 4206 } 4207 4208 static void bnxt_free_ctx_mem(struct bnxt *bp) 4209 { 4210 int i; 4211 4212 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4213 return; 4214 4215 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4216 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4217 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4218 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4219 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4220 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4221 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4222 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4223 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4224 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4225 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4226 4227 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4228 if (bp->ctx->tqm_mem[i]) 4229 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4230 } 4231 4232 rte_free(bp->ctx); 4233 bp->ctx = NULL; 4234 } 4235 4236 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4237 4238 #define min_t(type, x, y) ({ \ 4239 type __min1 = (x); \ 4240 type __min2 = (y); \ 4241 __min1 < __min2 ? __min1 : __min2; }) 4242 4243 #define max_t(type, x, y) ({ \ 4244 type __max1 = (x); \ 4245 type __max2 = (y); \ 4246 __max1 > __max2 ? __max1 : __max2; }) 4247 4248 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4249 4250 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4251 { 4252 struct bnxt_ctx_pg_info *ctx_pg; 4253 struct bnxt_ctx_mem_info *ctx; 4254 uint32_t mem_size, ena, entries; 4255 uint32_t entries_sp, min; 4256 int i, rc; 4257 4258 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4259 if (rc) { 4260 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4261 return rc; 4262 } 4263 ctx = bp->ctx; 4264 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4265 return 0; 4266 4267 ctx_pg = &ctx->qp_mem; 4268 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4269 if (ctx->qp_entry_size) { 4270 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4271 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4272 if (rc) 4273 return rc; 4274 } 4275 4276 ctx_pg = &ctx->srq_mem; 4277 ctx_pg->entries = ctx->srq_max_l2_entries; 4278 if (ctx->srq_entry_size) { 4279 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4280 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4281 if (rc) 4282 return rc; 4283 } 4284 4285 ctx_pg = &ctx->cq_mem; 4286 ctx_pg->entries = ctx->cq_max_l2_entries; 4287 if (ctx->cq_entry_size) { 4288 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4289 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4290 if (rc) 4291 return rc; 4292 } 4293 4294 ctx_pg = &ctx->vnic_mem; 4295 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4296 ctx->vnic_max_ring_table_entries; 4297 if (ctx->vnic_entry_size) { 4298 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4299 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4300 if (rc) 4301 return rc; 4302 } 4303 4304 ctx_pg = &ctx->stat_mem; 4305 ctx_pg->entries = ctx->stat_max_entries; 4306 if (ctx->stat_entry_size) { 4307 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4308 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4309 if (rc) 4310 return rc; 4311 } 4312 4313 min = ctx->tqm_min_entries_per_ring; 4314 4315 entries_sp = ctx->qp_max_l2_entries + 4316 ctx->vnic_max_vnic_entries + 4317 2 * ctx->qp_min_qp1_entries + min; 4318 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4319 4320 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4321 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4322 entries = clamp_t(uint32_t, entries, min, 4323 ctx->tqm_max_entries_per_ring); 4324 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4325 ctx_pg = ctx->tqm_mem[i]; 4326 ctx_pg->entries = i ? entries : entries_sp; 4327 if (ctx->tqm_entry_size) { 4328 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4329 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4330 if (rc) 4331 return rc; 4332 } 4333 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4334 } 4335 4336 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4337 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4338 if (rc) 4339 PMD_DRV_LOG(ERR, 4340 "Failed to configure context mem: rc = %d\n", rc); 4341 else 4342 ctx->flags |= BNXT_CTX_FLAG_INITED; 4343 4344 return rc; 4345 } 4346 4347 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4348 { 4349 struct rte_pci_device *pci_dev = bp->pdev; 4350 char mz_name[RTE_MEMZONE_NAMESIZE]; 4351 const struct rte_memzone *mz = NULL; 4352 uint32_t total_alloc_len; 4353 rte_iova_t mz_phys_addr; 4354 4355 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4356 return 0; 4357 4358 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4359 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4360 pci_dev->addr.bus, pci_dev->addr.devid, 4361 pci_dev->addr.function, "rx_port_stats"); 4362 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4363 mz = rte_memzone_lookup(mz_name); 4364 total_alloc_len = 4365 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4366 sizeof(struct rx_port_stats_ext) + 512); 4367 if (!mz) { 4368 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4369 SOCKET_ID_ANY, 4370 RTE_MEMZONE_2MB | 4371 RTE_MEMZONE_SIZE_HINT_ONLY | 4372 RTE_MEMZONE_IOVA_CONTIG); 4373 if (mz == NULL) 4374 return -ENOMEM; 4375 } 4376 memset(mz->addr, 0, mz->len); 4377 mz_phys_addr = mz->iova; 4378 4379 bp->rx_mem_zone = (const void *)mz; 4380 bp->hw_rx_port_stats = mz->addr; 4381 bp->hw_rx_port_stats_map = mz_phys_addr; 4382 4383 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4384 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4385 pci_dev->addr.bus, pci_dev->addr.devid, 4386 pci_dev->addr.function, "tx_port_stats"); 4387 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4388 mz = rte_memzone_lookup(mz_name); 4389 total_alloc_len = 4390 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4391 sizeof(struct tx_port_stats_ext) + 512); 4392 if (!mz) { 4393 mz = rte_memzone_reserve(mz_name, 4394 total_alloc_len, 4395 SOCKET_ID_ANY, 4396 RTE_MEMZONE_2MB | 4397 RTE_MEMZONE_SIZE_HINT_ONLY | 4398 RTE_MEMZONE_IOVA_CONTIG); 4399 if (mz == NULL) 4400 return -ENOMEM; 4401 } 4402 memset(mz->addr, 0, mz->len); 4403 mz_phys_addr = mz->iova; 4404 4405 bp->tx_mem_zone = (const void *)mz; 4406 bp->hw_tx_port_stats = mz->addr; 4407 bp->hw_tx_port_stats_map = mz_phys_addr; 4408 bp->flags |= BNXT_FLAG_PORT_STATS; 4409 4410 /* Display extended statistics if FW supports it */ 4411 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4412 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4413 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4414 return 0; 4415 4416 bp->hw_rx_port_stats_ext = (void *) 4417 ((uint8_t *)bp->hw_rx_port_stats + 4418 sizeof(struct rx_port_stats)); 4419 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4420 sizeof(struct rx_port_stats); 4421 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4422 4423 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4424 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4425 bp->hw_tx_port_stats_ext = (void *) 4426 ((uint8_t *)bp->hw_tx_port_stats + 4427 sizeof(struct tx_port_stats)); 4428 bp->hw_tx_port_stats_ext_map = 4429 bp->hw_tx_port_stats_map + 4430 sizeof(struct tx_port_stats); 4431 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4432 } 4433 4434 return 0; 4435 } 4436 4437 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4438 { 4439 struct bnxt *bp = eth_dev->data->dev_private; 4440 int rc = 0; 4441 4442 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4443 RTE_ETHER_ADDR_LEN * 4444 bp->max_l2_ctx, 4445 0); 4446 if (eth_dev->data->mac_addrs == NULL) { 4447 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4448 return -ENOMEM; 4449 } 4450 4451 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4452 if (BNXT_PF(bp)) 4453 return -EINVAL; 4454 4455 /* Generate a random MAC address, if none was assigned by PF */ 4456 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4457 bnxt_eth_hw_addr_random(bp->mac_addr); 4458 PMD_DRV_LOG(INFO, 4459 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4460 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4461 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4462 4463 rc = bnxt_hwrm_set_mac(bp); 4464 if (rc) 4465 return rc; 4466 } 4467 4468 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4469 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4470 4471 return rc; 4472 } 4473 4474 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4475 { 4476 int rc = 0; 4477 4478 /* MAC is already configured in FW */ 4479 if (BNXT_HAS_DFLT_MAC_SET(bp)) 4480 return 0; 4481 4482 /* Restore the old MAC configured */ 4483 rc = bnxt_hwrm_set_mac(bp); 4484 if (rc) 4485 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4486 4487 return rc; 4488 } 4489 4490 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4491 { 4492 if (!BNXT_PF(bp)) 4493 return; 4494 4495 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 4496 4497 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 4498 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 4499 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 4500 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 4501 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 4502 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 4503 } 4504 4505 uint16_t 4506 bnxt_get_svif(uint16_t port_id, bool func_svif, 4507 enum bnxt_ulp_intf_type type) 4508 { 4509 struct rte_eth_dev *eth_dev; 4510 struct bnxt *bp; 4511 4512 eth_dev = &rte_eth_devices[port_id]; 4513 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4514 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4515 if (!vfr) 4516 return 0; 4517 4518 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4519 return vfr->svif; 4520 4521 eth_dev = vfr->parent_dev; 4522 } 4523 4524 bp = eth_dev->data->dev_private; 4525 4526 return func_svif ? bp->func_svif : bp->port_svif; 4527 } 4528 4529 uint16_t 4530 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 4531 { 4532 struct rte_eth_dev *eth_dev; 4533 struct bnxt_vnic_info *vnic; 4534 struct bnxt *bp; 4535 4536 eth_dev = &rte_eth_devices[port]; 4537 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4538 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4539 if (!vfr) 4540 return 0; 4541 4542 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4543 return vfr->dflt_vnic_id; 4544 4545 eth_dev = vfr->parent_dev; 4546 } 4547 4548 bp = eth_dev->data->dev_private; 4549 4550 vnic = BNXT_GET_DEFAULT_VNIC(bp); 4551 4552 return vnic->fw_vnic_id; 4553 } 4554 4555 uint16_t 4556 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 4557 { 4558 struct rte_eth_dev *eth_dev; 4559 struct bnxt *bp; 4560 4561 eth_dev = &rte_eth_devices[port]; 4562 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4563 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4564 if (!vfr) 4565 return 0; 4566 4567 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4568 return vfr->fw_fid; 4569 4570 eth_dev = vfr->parent_dev; 4571 } 4572 4573 bp = eth_dev->data->dev_private; 4574 4575 return bp->fw_fid; 4576 } 4577 4578 enum bnxt_ulp_intf_type 4579 bnxt_get_interface_type(uint16_t port) 4580 { 4581 struct rte_eth_dev *eth_dev; 4582 struct bnxt *bp; 4583 4584 eth_dev = &rte_eth_devices[port]; 4585 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 4586 return BNXT_ULP_INTF_TYPE_VF_REP; 4587 4588 bp = eth_dev->data->dev_private; 4589 if (BNXT_PF(bp)) 4590 return BNXT_ULP_INTF_TYPE_PF; 4591 else if (BNXT_VF_IS_TRUSTED(bp)) 4592 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 4593 else if (BNXT_VF(bp)) 4594 return BNXT_ULP_INTF_TYPE_VF; 4595 4596 return BNXT_ULP_INTF_TYPE_INVALID; 4597 } 4598 4599 uint16_t 4600 bnxt_get_phy_port_id(uint16_t port_id) 4601 { 4602 struct bnxt_representor *vfr; 4603 struct rte_eth_dev *eth_dev; 4604 struct bnxt *bp; 4605 4606 eth_dev = &rte_eth_devices[port_id]; 4607 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4608 vfr = eth_dev->data->dev_private; 4609 if (!vfr) 4610 return 0; 4611 4612 eth_dev = vfr->parent_dev; 4613 } 4614 4615 bp = eth_dev->data->dev_private; 4616 4617 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 4618 } 4619 4620 uint16_t 4621 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 4622 { 4623 struct rte_eth_dev *eth_dev; 4624 struct bnxt *bp; 4625 4626 eth_dev = &rte_eth_devices[port_id]; 4627 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4628 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4629 if (!vfr) 4630 return 0; 4631 4632 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4633 return vfr->fw_fid - 1; 4634 4635 eth_dev = vfr->parent_dev; 4636 } 4637 4638 bp = eth_dev->data->dev_private; 4639 4640 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 4641 } 4642 4643 uint16_t 4644 bnxt_get_vport(uint16_t port_id) 4645 { 4646 return (1 << bnxt_get_phy_port_id(port_id)); 4647 } 4648 4649 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 4650 { 4651 struct bnxt_error_recovery_info *info = bp->recovery_info; 4652 4653 if (info) { 4654 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 4655 memset(info, 0, sizeof(*info)); 4656 return; 4657 } 4658 4659 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4660 return; 4661 4662 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4663 sizeof(*info), 0); 4664 if (!info) 4665 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4666 4667 bp->recovery_info = info; 4668 } 4669 4670 static void bnxt_check_fw_status(struct bnxt *bp) 4671 { 4672 uint32_t fw_status; 4673 4674 if (!(bp->recovery_info && 4675 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 4676 return; 4677 4678 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 4679 if (fw_status != BNXT_FW_STATUS_HEALTHY) 4680 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 4681 fw_status); 4682 } 4683 4684 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 4685 { 4686 struct bnxt_error_recovery_info *info = bp->recovery_info; 4687 uint32_t status_loc; 4688 uint32_t sig_ver; 4689 4690 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 4691 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4692 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4693 BNXT_GRCP_WINDOW_2_BASE + 4694 offsetof(struct hcomm_status, 4695 sig_ver))); 4696 /* If the signature is absent, then FW does not support this feature */ 4697 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 4698 HCOMM_STATUS_SIGNATURE_VAL) 4699 return 0; 4700 4701 if (!info) { 4702 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4703 sizeof(*info), 0); 4704 if (!info) 4705 return -ENOMEM; 4706 bp->recovery_info = info; 4707 } else { 4708 memset(info, 0, sizeof(*info)); 4709 } 4710 4711 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4712 BNXT_GRCP_WINDOW_2_BASE + 4713 offsetof(struct hcomm_status, 4714 fw_status_loc))); 4715 4716 /* Only pre-map the FW health status GRC register */ 4717 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 4718 return 0; 4719 4720 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 4721 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 4722 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 4723 4724 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 4725 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4726 4727 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 4728 4729 return 0; 4730 } 4731 4732 /* This function gets the FW version along with the 4733 * capabilities(MAX and current) of the function, vnic, 4734 * error recovery, phy and other chip related info 4735 */ 4736 static int bnxt_get_config(struct bnxt *bp) 4737 { 4738 uint16_t mtu; 4739 int rc = 0; 4740 4741 bp->fw_cap = 0; 4742 4743 rc = bnxt_map_hcomm_fw_status_reg(bp); 4744 if (rc) 4745 return rc; 4746 4747 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 4748 if (rc) { 4749 bnxt_check_fw_status(bp); 4750 return rc; 4751 } 4752 4753 rc = bnxt_hwrm_func_reset(bp); 4754 if (rc) 4755 return -EIO; 4756 4757 rc = bnxt_hwrm_vnic_qcaps(bp); 4758 if (rc) 4759 return rc; 4760 4761 rc = bnxt_hwrm_queue_qportcfg(bp); 4762 if (rc) 4763 return rc; 4764 4765 /* Get the MAX capabilities for this function. 4766 * This function also allocates context memory for TQM rings and 4767 * informs the firmware about this allocated backing store memory. 4768 */ 4769 rc = bnxt_hwrm_func_qcaps(bp); 4770 if (rc) 4771 return rc; 4772 4773 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 4774 if (rc) 4775 return rc; 4776 4777 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 4778 if (rc) 4779 return rc; 4780 4781 bnxt_hwrm_port_mac_qcfg(bp); 4782 4783 bnxt_hwrm_parent_pf_qcfg(bp); 4784 4785 bnxt_hwrm_port_phy_qcaps(bp); 4786 4787 bnxt_alloc_error_recovery_info(bp); 4788 /* Get the adapter error recovery support info */ 4789 rc = bnxt_hwrm_error_recovery_qcfg(bp); 4790 if (rc) 4791 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4792 4793 bnxt_hwrm_port_led_qcaps(bp); 4794 4795 return 0; 4796 } 4797 4798 static int 4799 bnxt_init_locks(struct bnxt *bp) 4800 { 4801 int err; 4802 4803 err = pthread_mutex_init(&bp->flow_lock, NULL); 4804 if (err) { 4805 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 4806 return err; 4807 } 4808 4809 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 4810 if (err) { 4811 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 4812 return err; 4813 } 4814 4815 err = pthread_mutex_init(&bp->health_check_lock, NULL); 4816 if (err) { 4817 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 4818 return err; 4819 } 4820 4821 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 4822 if (err) 4823 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 4824 4825 return err; 4826 } 4827 4828 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 4829 { 4830 int rc = 0; 4831 4832 rc = bnxt_get_config(bp); 4833 if (rc) 4834 return rc; 4835 4836 if (!reconfig_dev) { 4837 rc = bnxt_setup_mac_addr(bp->eth_dev); 4838 if (rc) 4839 return rc; 4840 } else { 4841 rc = bnxt_restore_dflt_mac(bp); 4842 if (rc) 4843 return rc; 4844 } 4845 4846 bnxt_config_vf_req_fwd(bp); 4847 4848 rc = bnxt_hwrm_func_driver_register(bp); 4849 if (rc) { 4850 PMD_DRV_LOG(ERR, "Failed to register driver"); 4851 return -EBUSY; 4852 } 4853 4854 if (BNXT_PF(bp)) { 4855 if (bp->pdev->max_vfs) { 4856 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 4857 if (rc) { 4858 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 4859 return rc; 4860 } 4861 } else { 4862 rc = bnxt_hwrm_allocate_pf_only(bp); 4863 if (rc) { 4864 PMD_DRV_LOG(ERR, 4865 "Failed to allocate PF resources"); 4866 return rc; 4867 } 4868 } 4869 } 4870 4871 rc = bnxt_alloc_mem(bp, reconfig_dev); 4872 if (rc) 4873 return rc; 4874 4875 rc = bnxt_setup_int(bp); 4876 if (rc) 4877 return rc; 4878 4879 rc = bnxt_request_int(bp); 4880 if (rc) 4881 return rc; 4882 4883 rc = bnxt_init_ctx_mem(bp); 4884 if (rc) { 4885 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 4886 return rc; 4887 } 4888 4889 return 0; 4890 } 4891 4892 static int 4893 bnxt_parse_devarg_truflow(__rte_unused const char *key, 4894 const char *value, void *opaque_arg) 4895 { 4896 struct bnxt *bp = opaque_arg; 4897 unsigned long truflow; 4898 char *end = NULL; 4899 4900 if (!value || !opaque_arg) { 4901 PMD_DRV_LOG(ERR, 4902 "Invalid parameter passed to truflow devargs.\n"); 4903 return -EINVAL; 4904 } 4905 4906 truflow = strtoul(value, &end, 10); 4907 if (end == NULL || *end != '\0' || 4908 (truflow == ULONG_MAX && errno == ERANGE)) { 4909 PMD_DRV_LOG(ERR, 4910 "Invalid parameter passed to truflow devargs.\n"); 4911 return -EINVAL; 4912 } 4913 4914 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 4915 PMD_DRV_LOG(ERR, 4916 "Invalid value passed to truflow devargs.\n"); 4917 return -EINVAL; 4918 } 4919 4920 if (truflow) { 4921 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 4922 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 4923 } else { 4924 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; 4925 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); 4926 } 4927 4928 return 0; 4929 } 4930 4931 static int 4932 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 4933 const char *value, void *opaque_arg) 4934 { 4935 struct bnxt *bp = opaque_arg; 4936 unsigned long flow_xstat; 4937 char *end = NULL; 4938 4939 if (!value || !opaque_arg) { 4940 PMD_DRV_LOG(ERR, 4941 "Invalid parameter passed to flow_xstat devarg.\n"); 4942 return -EINVAL; 4943 } 4944 4945 flow_xstat = strtoul(value, &end, 10); 4946 if (end == NULL || *end != '\0' || 4947 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 4948 PMD_DRV_LOG(ERR, 4949 "Invalid parameter passed to flow_xstat devarg.\n"); 4950 return -EINVAL; 4951 } 4952 4953 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 4954 PMD_DRV_LOG(ERR, 4955 "Invalid value passed to flow_xstat devarg.\n"); 4956 return -EINVAL; 4957 } 4958 4959 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 4960 if (BNXT_FLOW_XSTATS_EN(bp)) 4961 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 4962 4963 return 0; 4964 } 4965 4966 static int 4967 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 4968 const char *value, void *opaque_arg) 4969 { 4970 struct bnxt *bp = opaque_arg; 4971 unsigned long max_num_kflows; 4972 char *end = NULL; 4973 4974 if (!value || !opaque_arg) { 4975 PMD_DRV_LOG(ERR, 4976 "Invalid parameter passed to max_num_kflows devarg.\n"); 4977 return -EINVAL; 4978 } 4979 4980 max_num_kflows = strtoul(value, &end, 10); 4981 if (end == NULL || *end != '\0' || 4982 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 4983 PMD_DRV_LOG(ERR, 4984 "Invalid parameter passed to max_num_kflows devarg.\n"); 4985 return -EINVAL; 4986 } 4987 4988 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 4989 PMD_DRV_LOG(ERR, 4990 "Invalid value passed to max_num_kflows devarg.\n"); 4991 return -EINVAL; 4992 } 4993 4994 bp->max_num_kflows = max_num_kflows; 4995 if (bp->max_num_kflows) 4996 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 4997 max_num_kflows); 4998 4999 return 0; 5000 } 5001 5002 static int 5003 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5004 const char *value, void *opaque_arg) 5005 { 5006 struct bnxt_representor *vfr_bp = opaque_arg; 5007 unsigned long rep_is_pf; 5008 char *end = NULL; 5009 5010 if (!value || !opaque_arg) { 5011 PMD_DRV_LOG(ERR, 5012 "Invalid parameter passed to rep_is_pf devargs.\n"); 5013 return -EINVAL; 5014 } 5015 5016 rep_is_pf = strtoul(value, &end, 10); 5017 if (end == NULL || *end != '\0' || 5018 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5019 PMD_DRV_LOG(ERR, 5020 "Invalid parameter passed to rep_is_pf devargs.\n"); 5021 return -EINVAL; 5022 } 5023 5024 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5025 PMD_DRV_LOG(ERR, 5026 "Invalid value passed to rep_is_pf devargs.\n"); 5027 return -EINVAL; 5028 } 5029 5030 vfr_bp->flags |= rep_is_pf; 5031 if (BNXT_REP_PF(vfr_bp)) 5032 PMD_DRV_LOG(INFO, "PF representor\n"); 5033 else 5034 PMD_DRV_LOG(INFO, "VF representor\n"); 5035 5036 return 0; 5037 } 5038 5039 static int 5040 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5041 const char *value, void *opaque_arg) 5042 { 5043 struct bnxt_representor *vfr_bp = opaque_arg; 5044 unsigned long rep_based_pf; 5045 char *end = NULL; 5046 5047 if (!value || !opaque_arg) { 5048 PMD_DRV_LOG(ERR, 5049 "Invalid parameter passed to rep_based_pf " 5050 "devargs.\n"); 5051 return -EINVAL; 5052 } 5053 5054 rep_based_pf = strtoul(value, &end, 10); 5055 if (end == NULL || *end != '\0' || 5056 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5057 PMD_DRV_LOG(ERR, 5058 "Invalid parameter passed to rep_based_pf " 5059 "devargs.\n"); 5060 return -EINVAL; 5061 } 5062 5063 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5064 PMD_DRV_LOG(ERR, 5065 "Invalid value passed to rep_based_pf devargs.\n"); 5066 return -EINVAL; 5067 } 5068 5069 vfr_bp->rep_based_pf = rep_based_pf; 5070 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5071 5072 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5073 5074 return 0; 5075 } 5076 5077 static int 5078 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5079 const char *value, void *opaque_arg) 5080 { 5081 struct bnxt_representor *vfr_bp = opaque_arg; 5082 unsigned long rep_q_r2f; 5083 char *end = NULL; 5084 5085 if (!value || !opaque_arg) { 5086 PMD_DRV_LOG(ERR, 5087 "Invalid parameter passed to rep_q_r2f " 5088 "devargs.\n"); 5089 return -EINVAL; 5090 } 5091 5092 rep_q_r2f = strtoul(value, &end, 10); 5093 if (end == NULL || *end != '\0' || 5094 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5095 PMD_DRV_LOG(ERR, 5096 "Invalid parameter passed to rep_q_r2f " 5097 "devargs.\n"); 5098 return -EINVAL; 5099 } 5100 5101 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5102 PMD_DRV_LOG(ERR, 5103 "Invalid value passed to rep_q_r2f devargs.\n"); 5104 return -EINVAL; 5105 } 5106 5107 vfr_bp->rep_q_r2f = rep_q_r2f; 5108 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5109 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5110 5111 return 0; 5112 } 5113 5114 static int 5115 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5116 const char *value, void *opaque_arg) 5117 { 5118 struct bnxt_representor *vfr_bp = opaque_arg; 5119 unsigned long rep_q_f2r; 5120 char *end = NULL; 5121 5122 if (!value || !opaque_arg) { 5123 PMD_DRV_LOG(ERR, 5124 "Invalid parameter passed to rep_q_f2r " 5125 "devargs.\n"); 5126 return -EINVAL; 5127 } 5128 5129 rep_q_f2r = strtoul(value, &end, 10); 5130 if (end == NULL || *end != '\0' || 5131 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5132 PMD_DRV_LOG(ERR, 5133 "Invalid parameter passed to rep_q_f2r " 5134 "devargs.\n"); 5135 return -EINVAL; 5136 } 5137 5138 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5139 PMD_DRV_LOG(ERR, 5140 "Invalid value passed to rep_q_f2r devargs.\n"); 5141 return -EINVAL; 5142 } 5143 5144 vfr_bp->rep_q_f2r = rep_q_f2r; 5145 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5146 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5147 5148 return 0; 5149 } 5150 5151 static int 5152 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5153 const char *value, void *opaque_arg) 5154 { 5155 struct bnxt_representor *vfr_bp = opaque_arg; 5156 unsigned long rep_fc_r2f; 5157 char *end = NULL; 5158 5159 if (!value || !opaque_arg) { 5160 PMD_DRV_LOG(ERR, 5161 "Invalid parameter passed to rep_fc_r2f " 5162 "devargs.\n"); 5163 return -EINVAL; 5164 } 5165 5166 rep_fc_r2f = strtoul(value, &end, 10); 5167 if (end == NULL || *end != '\0' || 5168 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5169 PMD_DRV_LOG(ERR, 5170 "Invalid parameter passed to rep_fc_r2f " 5171 "devargs.\n"); 5172 return -EINVAL; 5173 } 5174 5175 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5176 PMD_DRV_LOG(ERR, 5177 "Invalid value passed to rep_fc_r2f devargs.\n"); 5178 return -EINVAL; 5179 } 5180 5181 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5182 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5183 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5184 5185 return 0; 5186 } 5187 5188 static int 5189 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5190 const char *value, void *opaque_arg) 5191 { 5192 struct bnxt_representor *vfr_bp = opaque_arg; 5193 unsigned long rep_fc_f2r; 5194 char *end = NULL; 5195 5196 if (!value || !opaque_arg) { 5197 PMD_DRV_LOG(ERR, 5198 "Invalid parameter passed to rep_fc_f2r " 5199 "devargs.\n"); 5200 return -EINVAL; 5201 } 5202 5203 rep_fc_f2r = strtoul(value, &end, 10); 5204 if (end == NULL || *end != '\0' || 5205 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5206 PMD_DRV_LOG(ERR, 5207 "Invalid parameter passed to rep_fc_f2r " 5208 "devargs.\n"); 5209 return -EINVAL; 5210 } 5211 5212 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5213 PMD_DRV_LOG(ERR, 5214 "Invalid value passed to rep_fc_f2r devargs.\n"); 5215 return -EINVAL; 5216 } 5217 5218 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5219 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5220 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5221 5222 return 0; 5223 } 5224 5225 static void 5226 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5227 { 5228 struct rte_kvargs *kvlist; 5229 5230 if (devargs == NULL) 5231 return; 5232 5233 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5234 if (kvlist == NULL) 5235 return; 5236 5237 /* 5238 * Handler for "truflow" devarg. 5239 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" 5240 */ 5241 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5242 bnxt_parse_devarg_truflow, bp); 5243 5244 /* 5245 * Handler for "flow_xstat" devarg. 5246 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5247 */ 5248 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5249 bnxt_parse_devarg_flow_xstat, bp); 5250 5251 /* 5252 * Handler for "max_num_kflows" devarg. 5253 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5254 */ 5255 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5256 bnxt_parse_devarg_max_num_kflows, bp); 5257 5258 rte_kvargs_free(kvlist); 5259 } 5260 5261 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5262 { 5263 int rc = 0; 5264 5265 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5266 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5267 if (rc) 5268 PMD_DRV_LOG(ERR, 5269 "Failed to alloc switch domain: %d\n", rc); 5270 else 5271 PMD_DRV_LOG(INFO, 5272 "Switch domain allocated %d\n", 5273 bp->switch_domain_id); 5274 } 5275 5276 return rc; 5277 } 5278 5279 /* Allocate and initialize various fields in bnxt struct that 5280 * need to be allocated/destroyed only once in the lifetime of the driver 5281 */ 5282 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5283 { 5284 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5285 struct bnxt *bp = eth_dev->data->dev_private; 5286 int rc = 0; 5287 5288 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5289 5290 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5291 bp->flags |= BNXT_FLAG_VF; 5292 5293 if (bnxt_p5_device(pci_dev->id.device_id)) 5294 bp->flags |= BNXT_FLAG_CHIP_P5; 5295 5296 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5297 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5298 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5299 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5300 bp->flags |= BNXT_FLAG_STINGRAY; 5301 5302 if (BNXT_TRUFLOW_EN(bp)) { 5303 /* extra mbuf field is required to store CFA code from mark */ 5304 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5305 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5306 .size = sizeof(bnxt_cfa_code_dynfield_t), 5307 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5308 }; 5309 bnxt_cfa_code_dynfield_offset = 5310 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5311 if (bnxt_cfa_code_dynfield_offset < 0) { 5312 PMD_DRV_LOG(ERR, 5313 "Failed to register mbuf field for TruFlow mark\n"); 5314 return -rte_errno; 5315 } 5316 } 5317 5318 rc = bnxt_map_pci_bars(eth_dev); 5319 if (rc) { 5320 PMD_DRV_LOG(ERR, 5321 "Failed to initialize board rc: %x\n", rc); 5322 return rc; 5323 } 5324 5325 rc = bnxt_alloc_pf_info(bp); 5326 if (rc) 5327 return rc; 5328 5329 rc = bnxt_alloc_link_info(bp); 5330 if (rc) 5331 return rc; 5332 5333 rc = bnxt_alloc_parent_info(bp); 5334 if (rc) 5335 return rc; 5336 5337 rc = bnxt_alloc_hwrm_resources(bp); 5338 if (rc) { 5339 PMD_DRV_LOG(ERR, 5340 "Failed to allocate hwrm resource rc: %x\n", rc); 5341 return rc; 5342 } 5343 rc = bnxt_alloc_leds_info(bp); 5344 if (rc) 5345 return rc; 5346 5347 rc = bnxt_alloc_cos_queues(bp); 5348 if (rc) 5349 return rc; 5350 5351 rc = bnxt_init_locks(bp); 5352 if (rc) 5353 return rc; 5354 5355 rc = bnxt_alloc_switch_domain(bp); 5356 if (rc) 5357 return rc; 5358 5359 return rc; 5360 } 5361 5362 static int 5363 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5364 { 5365 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5366 static int version_printed; 5367 struct bnxt *bp; 5368 int rc; 5369 5370 if (version_printed++ == 0) 5371 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5372 5373 eth_dev->dev_ops = &bnxt_dev_ops; 5374 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 5375 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 5376 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 5377 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5378 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5379 5380 /* 5381 * For secondary processes, we don't initialise any further 5382 * as primary has already done this work. 5383 */ 5384 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5385 return 0; 5386 5387 rte_eth_copy_pci_info(eth_dev, pci_dev); 5388 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 5389 5390 bp = eth_dev->data->dev_private; 5391 5392 /* Parse dev arguments passed on when starting the DPDK application. */ 5393 bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5394 5395 rc = bnxt_drv_init(eth_dev); 5396 if (rc) 5397 goto error_free; 5398 5399 rc = bnxt_init_resources(bp, false); 5400 if (rc) 5401 goto error_free; 5402 5403 rc = bnxt_alloc_stats_mem(bp); 5404 if (rc) 5405 goto error_free; 5406 5407 PMD_DRV_LOG(INFO, 5408 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5409 pci_dev->mem_resource[0].phys_addr, 5410 pci_dev->mem_resource[0].addr); 5411 5412 return 0; 5413 5414 error_free: 5415 bnxt_dev_uninit(eth_dev); 5416 return rc; 5417 } 5418 5419 5420 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5421 { 5422 if (!ctx) 5423 return; 5424 5425 if (ctx->va) 5426 rte_free(ctx->va); 5427 5428 ctx->va = NULL; 5429 ctx->dma = RTE_BAD_IOVA; 5430 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5431 } 5432 5433 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5434 { 5435 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5436 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5437 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5438 bp->flow_stat->max_fc, 5439 false); 5440 5441 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5442 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5443 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5444 bp->flow_stat->max_fc, 5445 false); 5446 5447 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5448 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5449 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5450 5451 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5452 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5453 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5454 5455 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5456 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5457 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5458 5459 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5460 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5461 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5462 } 5463 5464 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5465 { 5466 bnxt_unregister_fc_ctx_mem(bp); 5467 5468 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5469 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5470 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5471 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5472 } 5473 5474 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5475 { 5476 if (BNXT_FLOW_XSTATS_EN(bp)) 5477 bnxt_uninit_fc_ctx_mem(bp); 5478 } 5479 5480 static void 5481 bnxt_free_error_recovery_info(struct bnxt *bp) 5482 { 5483 rte_free(bp->recovery_info); 5484 bp->recovery_info = NULL; 5485 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5486 } 5487 5488 static int 5489 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5490 { 5491 int rc; 5492 5493 bnxt_free_int(bp); 5494 bnxt_free_mem(bp, reconfig_dev); 5495 5496 bnxt_hwrm_func_buf_unrgtr(bp); 5497 rte_free(bp->pf->vf_req_buf); 5498 5499 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5500 bp->flags &= ~BNXT_FLAG_REGISTERED; 5501 bnxt_free_ctx_mem(bp); 5502 if (!reconfig_dev) { 5503 bnxt_free_hwrm_resources(bp); 5504 bnxt_free_error_recovery_info(bp); 5505 } 5506 5507 bnxt_uninit_ctx_mem(bp); 5508 5509 bnxt_free_flow_stats_info(bp); 5510 bnxt_free_rep_info(bp); 5511 rte_free(bp->ptp_cfg); 5512 bp->ptp_cfg = NULL; 5513 return rc; 5514 } 5515 5516 static int 5517 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5518 { 5519 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5520 return -EPERM; 5521 5522 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5523 5524 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5525 bnxt_dev_close_op(eth_dev); 5526 5527 return 0; 5528 } 5529 5530 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5531 { 5532 struct bnxt *bp = eth_dev->data->dev_private; 5533 struct rte_eth_dev *vf_rep_eth_dev; 5534 int ret = 0, i; 5535 5536 if (!bp) 5537 return -EINVAL; 5538 5539 for (i = 0; i < bp->num_reps; i++) { 5540 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5541 if (!vf_rep_eth_dev) 5542 continue; 5543 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 5544 vf_rep_eth_dev->data->port_id); 5545 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 5546 } 5547 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 5548 eth_dev->data->port_id); 5549 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5550 5551 return ret; 5552 } 5553 5554 static void bnxt_free_rep_info(struct bnxt *bp) 5555 { 5556 rte_free(bp->rep_info); 5557 bp->rep_info = NULL; 5558 rte_free(bp->cfa_code_map); 5559 bp->cfa_code_map = NULL; 5560 } 5561 5562 static int bnxt_init_rep_info(struct bnxt *bp) 5563 { 5564 int i = 0, rc; 5565 5566 if (bp->rep_info) 5567 return 0; 5568 5569 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5570 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5571 0); 5572 if (!bp->rep_info) { 5573 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5574 return -ENOMEM; 5575 } 5576 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5577 sizeof(*bp->cfa_code_map) * 5578 BNXT_MAX_CFA_CODE, 0); 5579 if (!bp->cfa_code_map) { 5580 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5581 bnxt_free_rep_info(bp); 5582 return -ENOMEM; 5583 } 5584 5585 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5586 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5587 5588 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 5589 if (rc) { 5590 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 5591 bnxt_free_rep_info(bp); 5592 return rc; 5593 } 5594 5595 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 5596 if (rc) { 5597 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 5598 bnxt_free_rep_info(bp); 5599 return rc; 5600 } 5601 5602 return rc; 5603 } 5604 5605 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 5606 struct rte_eth_devargs *eth_da, 5607 struct rte_eth_dev *backing_eth_dev, 5608 const char *dev_args) 5609 { 5610 struct rte_eth_dev *vf_rep_eth_dev; 5611 char name[RTE_ETH_NAME_MAX_LEN]; 5612 struct bnxt *backing_bp; 5613 uint16_t num_rep; 5614 int i, ret = 0; 5615 struct rte_kvargs *kvlist = NULL; 5616 5617 num_rep = eth_da->nb_representor_ports; 5618 if (num_rep > BNXT_MAX_VF_REPS) { 5619 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 5620 num_rep, BNXT_MAX_VF_REPS); 5621 return -EINVAL; 5622 } 5623 5624 if (num_rep >= RTE_MAX_ETHPORTS) { 5625 PMD_DRV_LOG(ERR, 5626 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 5627 num_rep, RTE_MAX_ETHPORTS); 5628 return -EINVAL; 5629 } 5630 5631 backing_bp = backing_eth_dev->data->dev_private; 5632 5633 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 5634 PMD_DRV_LOG(ERR, 5635 "Not a PF or trusted VF. No Representor support\n"); 5636 /* Returning an error is not an option. 5637 * Applications are not handling this correctly 5638 */ 5639 return 0; 5640 } 5641 5642 if (bnxt_init_rep_info(backing_bp)) 5643 return 0; 5644 5645 for (i = 0; i < num_rep; i++) { 5646 struct bnxt_representor representor = { 5647 .vf_id = eth_da->representor_ports[i], 5648 .switch_domain_id = backing_bp->switch_domain_id, 5649 .parent_dev = backing_eth_dev 5650 }; 5651 5652 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 5653 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 5654 representor.vf_id, BNXT_MAX_VF_REPS); 5655 continue; 5656 } 5657 5658 /* representor port net_bdf_port */ 5659 snprintf(name, sizeof(name), "net_%s_representor_%d", 5660 pci_dev->device.name, eth_da->representor_ports[i]); 5661 5662 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 5663 if (kvlist) { 5664 /* 5665 * Handler for "rep_is_pf" devarg. 5666 * Invoked as for ex: "-a 000:00:0d.0, 5667 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5668 */ 5669 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 5670 bnxt_parse_devarg_rep_is_pf, 5671 (void *)&representor); 5672 if (ret) { 5673 ret = -EINVAL; 5674 goto err; 5675 } 5676 /* 5677 * Handler for "rep_based_pf" devarg. 5678 * Invoked as for ex: "-a 000:00:0d.0, 5679 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5680 */ 5681 ret = rte_kvargs_process(kvlist, 5682 BNXT_DEVARG_REP_BASED_PF, 5683 bnxt_parse_devarg_rep_based_pf, 5684 (void *)&representor); 5685 if (ret) { 5686 ret = -EINVAL; 5687 goto err; 5688 } 5689 /* 5690 * Handler for "rep_based_pf" devarg. 5691 * Invoked as for ex: "-a 000:00:0d.0, 5692 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5693 */ 5694 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 5695 bnxt_parse_devarg_rep_q_r2f, 5696 (void *)&representor); 5697 if (ret) { 5698 ret = -EINVAL; 5699 goto err; 5700 } 5701 /* 5702 * Handler for "rep_based_pf" devarg. 5703 * Invoked as for ex: "-a 000:00:0d.0, 5704 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5705 */ 5706 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 5707 bnxt_parse_devarg_rep_q_f2r, 5708 (void *)&representor); 5709 if (ret) { 5710 ret = -EINVAL; 5711 goto err; 5712 } 5713 /* 5714 * Handler for "rep_based_pf" devarg. 5715 * Invoked as for ex: "-a 000:00:0d.0, 5716 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5717 */ 5718 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 5719 bnxt_parse_devarg_rep_fc_r2f, 5720 (void *)&representor); 5721 if (ret) { 5722 ret = -EINVAL; 5723 goto err; 5724 } 5725 /* 5726 * Handler for "rep_based_pf" devarg. 5727 * Invoked as for ex: "-a 000:00:0d.0, 5728 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5729 */ 5730 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 5731 bnxt_parse_devarg_rep_fc_f2r, 5732 (void *)&representor); 5733 if (ret) { 5734 ret = -EINVAL; 5735 goto err; 5736 } 5737 } 5738 5739 ret = rte_eth_dev_create(&pci_dev->device, name, 5740 sizeof(struct bnxt_representor), 5741 NULL, NULL, 5742 bnxt_representor_init, 5743 &representor); 5744 if (ret) { 5745 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 5746 "representor %s.", name); 5747 goto err; 5748 } 5749 5750 vf_rep_eth_dev = rte_eth_dev_allocated(name); 5751 if (!vf_rep_eth_dev) { 5752 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 5753 " for VF-Rep: %s.", name); 5754 ret = -ENODEV; 5755 goto err; 5756 } 5757 5758 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 5759 backing_eth_dev->data->port_id); 5760 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 5761 vf_rep_eth_dev; 5762 backing_bp->num_reps++; 5763 5764 } 5765 5766 rte_kvargs_free(kvlist); 5767 return 0; 5768 5769 err: 5770 /* If num_rep > 1, then rollback already created 5771 * ports, since we'll be failing the probe anyway 5772 */ 5773 if (num_rep > 1) 5774 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 5775 rte_errno = -ret; 5776 rte_kvargs_free(kvlist); 5777 5778 return ret; 5779 } 5780 5781 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5782 struct rte_pci_device *pci_dev) 5783 { 5784 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 5785 struct rte_eth_dev *backing_eth_dev; 5786 uint16_t num_rep; 5787 int ret = 0; 5788 5789 if (pci_dev->device.devargs) { 5790 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 5791 ð_da); 5792 if (ret) 5793 return ret; 5794 } 5795 5796 num_rep = eth_da.nb_representor_ports; 5797 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 5798 num_rep); 5799 5800 /* We could come here after first level of probe is already invoked 5801 * as part of an application bringup(OVS-DPDK vswitchd), so first check 5802 * for already allocated eth_dev for the backing device (PF/Trusted VF) 5803 */ 5804 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 5805 if (backing_eth_dev == NULL) { 5806 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 5807 sizeof(struct bnxt), 5808 eth_dev_pci_specific_init, pci_dev, 5809 bnxt_dev_init, NULL); 5810 5811 if (ret || !num_rep) 5812 return ret; 5813 5814 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 5815 } 5816 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 5817 backing_eth_dev->data->port_id); 5818 5819 if (!num_rep) 5820 return ret; 5821 5822 /* probe representor ports now */ 5823 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 5824 pci_dev->device.devargs->args); 5825 5826 return ret; 5827 } 5828 5829 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 5830 { 5831 struct rte_eth_dev *eth_dev; 5832 5833 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 5834 if (!eth_dev) 5835 return 0; /* Invoked typically only by OVS-DPDK, by the 5836 * time it comes here the eth_dev is already 5837 * deleted by rte_eth_dev_close(), so returning 5838 * +ve value will at least help in proper cleanup 5839 */ 5840 5841 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 5842 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 5843 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 5844 return rte_eth_dev_destroy(eth_dev, 5845 bnxt_representor_uninit); 5846 else 5847 return rte_eth_dev_destroy(eth_dev, 5848 bnxt_dev_uninit); 5849 } else { 5850 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 5851 } 5852 } 5853 5854 static struct rte_pci_driver bnxt_rte_pmd = { 5855 .id_table = bnxt_pci_id_map, 5856 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 5857 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 5858 * and OVS-DPDK 5859 */ 5860 .probe = bnxt_pci_probe, 5861 .remove = bnxt_pci_remove, 5862 }; 5863 5864 static bool 5865 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5866 { 5867 if (strcmp(dev->device->driver->name, drv->driver.name)) 5868 return false; 5869 5870 return true; 5871 } 5872 5873 bool is_bnxt_supported(struct rte_eth_dev *dev) 5874 { 5875 return is_device_supported(dev, &bnxt_rte_pmd); 5876 } 5877 5878 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 5879 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 5880 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 5881 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 5882