1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 #define BNXT_DEVARG_APP_ID "app-id" 101 102 static const char *const bnxt_dev_args[] = { 103 BNXT_DEVARG_REPRESENTOR, 104 BNXT_DEVARG_ACCUM_STATS, 105 BNXT_DEVARG_FLOW_XSTAT, 106 BNXT_DEVARG_MAX_NUM_KFLOWS, 107 BNXT_DEVARG_REP_BASED_PF, 108 BNXT_DEVARG_REP_IS_PF, 109 BNXT_DEVARG_REP_Q_R2F, 110 BNXT_DEVARG_REP_Q_F2R, 111 BNXT_DEVARG_REP_FC_R2F, 112 BNXT_DEVARG_REP_FC_F2R, 113 BNXT_DEVARG_APP_ID, 114 NULL 115 }; 116 117 /* 118 * accum-stats == false to disable flow counter accumulation 119 * accum-stats == true to enable flow counter accumulation 120 */ 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) 122 123 /* 124 * app-id = an non-negative 8-bit number 125 */ 126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255) 127 128 /* 129 * flow_xstat == false to disable the feature 130 * flow_xstat == true to enable the feature 131 */ 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 133 134 /* 135 * rep_is_pf == false to indicate VF representor 136 * rep_is_pf == true to indicate PF representor 137 */ 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 139 140 /* 141 * rep_based_pf == Physical index of the PF 142 */ 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 144 /* 145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 146 */ 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 148 149 /* 150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 151 */ 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 153 154 /* 155 * rep_fc_r2f == Flow control for the representor to endpoint direction 156 */ 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 158 159 /* 160 * rep_fc_f2r == Flow control for the endpoint to representor direction 161 */ 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 163 164 int bnxt_cfa_code_dynfield_offset = -1; 165 166 /* 167 * max_num_kflows must be >= 32 168 * and must be a power-of-2 supported value 169 * return: 1 -> invalid 170 * 0 -> valid 171 */ 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 173 { 174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 175 return 1; 176 return 0; 177 } 178 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 184 static int bnxt_restore_vlan_filters(struct bnxt *bp); 185 static void bnxt_dev_recover(void *arg); 186 static void bnxt_free_error_recovery_info(struct bnxt *bp); 187 static void bnxt_free_rep_info(struct bnxt *bp); 188 189 int is_bnxt_in_error(struct bnxt *bp) 190 { 191 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 192 return -EIO; 193 if (bp->flags & BNXT_FLAG_FW_RESET) 194 return -EBUSY; 195 196 return 0; 197 } 198 199 /***********************/ 200 201 /* 202 * High level utility functions 203 */ 204 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 206 { 207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 208 BNXT_RSS_TBL_SIZE_P5); 209 210 if (!BNXT_CHIP_P5(bp)) 211 return 1; 212 213 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 214 BNXT_RSS_ENTRIES_PER_CTX_P5) / 215 BNXT_RSS_ENTRIES_PER_CTX_P5; 216 } 217 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 219 { 220 if (!BNXT_CHIP_P5(bp)) 221 return HW_HASH_INDEX_SIZE; 222 223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 224 } 225 226 static void bnxt_free_parent_info(struct bnxt *bp) 227 { 228 rte_free(bp->parent); 229 bp->parent = NULL; 230 } 231 232 static void bnxt_free_pf_info(struct bnxt *bp) 233 { 234 rte_free(bp->pf); 235 bp->pf = NULL; 236 } 237 238 static void bnxt_free_link_info(struct bnxt *bp) 239 { 240 rte_free(bp->link_info); 241 bp->link_info = NULL; 242 } 243 244 static void bnxt_free_leds_info(struct bnxt *bp) 245 { 246 if (BNXT_VF(bp)) 247 return; 248 249 rte_free(bp->leds); 250 bp->leds = NULL; 251 } 252 253 static void bnxt_free_flow_stats_info(struct bnxt *bp) 254 { 255 rte_free(bp->flow_stat); 256 bp->flow_stat = NULL; 257 } 258 259 static void bnxt_free_cos_queues(struct bnxt *bp) 260 { 261 rte_free(bp->rx_cos_queue); 262 bp->rx_cos_queue = NULL; 263 rte_free(bp->tx_cos_queue); 264 bp->tx_cos_queue = NULL; 265 } 266 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 268 { 269 bnxt_free_filter_mem(bp); 270 bnxt_free_vnic_attributes(bp); 271 bnxt_free_vnic_mem(bp); 272 273 /* tx/rx rings are configured as part of *_queue_setup callbacks. 274 * If the number of rings change across fw update, 275 * we don't have much choice except to warn the user. 276 */ 277 if (!reconfig) { 278 bnxt_free_stats(bp); 279 bnxt_free_tx_rings(bp); 280 bnxt_free_rx_rings(bp); 281 } 282 bnxt_free_async_cp_ring(bp); 283 bnxt_free_rxtx_nq_ring(bp); 284 285 rte_free(bp->grp_info); 286 bp->grp_info = NULL; 287 } 288 289 static int bnxt_alloc_parent_info(struct bnxt *bp) 290 { 291 bp->parent = rte_zmalloc("bnxt_parent_info", 292 sizeof(struct bnxt_parent_info), 0); 293 if (bp->parent == NULL) 294 return -ENOMEM; 295 296 return 0; 297 } 298 299 static int bnxt_alloc_pf_info(struct bnxt *bp) 300 { 301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 302 if (bp->pf == NULL) 303 return -ENOMEM; 304 305 return 0; 306 } 307 308 static int bnxt_alloc_link_info(struct bnxt *bp) 309 { 310 bp->link_info = 311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 312 if (bp->link_info == NULL) 313 return -ENOMEM; 314 315 return 0; 316 } 317 318 static int bnxt_alloc_leds_info(struct bnxt *bp) 319 { 320 if (BNXT_VF(bp)) 321 return 0; 322 323 bp->leds = rte_zmalloc("bnxt_leds", 324 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 325 0); 326 if (bp->leds == NULL) 327 return -ENOMEM; 328 329 return 0; 330 } 331 332 static int bnxt_alloc_cos_queues(struct bnxt *bp) 333 { 334 bp->rx_cos_queue = 335 rte_zmalloc("bnxt_rx_cosq", 336 BNXT_COS_QUEUE_COUNT * 337 sizeof(struct bnxt_cos_queue_info), 338 0); 339 if (bp->rx_cos_queue == NULL) 340 return -ENOMEM; 341 342 bp->tx_cos_queue = 343 rte_zmalloc("bnxt_tx_cosq", 344 BNXT_COS_QUEUE_COUNT * 345 sizeof(struct bnxt_cos_queue_info), 346 0); 347 if (bp->tx_cos_queue == NULL) 348 return -ENOMEM; 349 350 return 0; 351 } 352 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 354 { 355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 356 sizeof(struct bnxt_flow_stat_info), 0); 357 if (bp->flow_stat == NULL) 358 return -ENOMEM; 359 360 return 0; 361 } 362 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 364 { 365 int rc; 366 367 rc = bnxt_alloc_ring_grps(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_async_ring_struct(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_vnic_mem(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_vnic_attributes(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 rc = bnxt_alloc_filter_mem(bp); 384 if (rc) 385 goto alloc_mem_err; 386 387 rc = bnxt_alloc_async_cp_ring(bp); 388 if (rc) 389 goto alloc_mem_err; 390 391 rc = bnxt_alloc_rxtx_nq_ring(bp); 392 if (rc) 393 goto alloc_mem_err; 394 395 if (BNXT_FLOW_XSTATS_EN(bp)) { 396 rc = bnxt_alloc_flow_stats_info(bp); 397 if (rc) 398 goto alloc_mem_err; 399 } 400 401 return 0; 402 403 alloc_mem_err: 404 bnxt_free_mem(bp, reconfig); 405 return rc; 406 } 407 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 409 { 410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 412 uint64_t rx_offloads = dev_conf->rxmode.offloads; 413 struct bnxt_rx_queue *rxq; 414 unsigned int j; 415 int rc; 416 417 rc = bnxt_vnic_grp_alloc(bp, vnic); 418 if (rc) 419 goto err_out; 420 421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 422 vnic_id, vnic, vnic->fw_grp_ids); 423 424 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 425 if (rc) 426 goto err_out; 427 428 /* Alloc RSS context only if RSS mode is enabled */ 429 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 430 int j, nr_ctxs = bnxt_rss_ctxts(bp); 431 432 /* RSS table size in Thor is 512. 433 * Cap max Rx rings to same value 434 */ 435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 438 goto err_out; 439 } 440 441 rc = 0; 442 for (j = 0; j < nr_ctxs; j++) { 443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 444 if (rc) 445 break; 446 } 447 if (rc) { 448 PMD_DRV_LOG(ERR, 449 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 450 vnic_id, j, rc); 451 goto err_out; 452 } 453 vnic->num_lb_ctxts = nr_ctxs; 454 } 455 456 /* 457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 458 * setting is not available at this time, it will not be 459 * configured correctly in the CFA. 460 */ 461 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 462 vnic->vlan_strip = true; 463 else 464 vnic->vlan_strip = false; 465 466 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 467 if (rc) 468 goto err_out; 469 470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 471 if (rc) 472 goto err_out; 473 474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 475 rxq = bp->eth_dev->data->rx_queues[j]; 476 477 PMD_DRV_LOG(DEBUG, 478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 479 j, rxq->vnic, rxq->vnic->fw_grp_ids); 480 481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 483 else 484 vnic->rx_queue_cnt++; 485 } 486 487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 488 489 rc = bnxt_vnic_rss_configure(bp, vnic); 490 if (rc) 491 goto err_out; 492 493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 494 495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 496 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ? 497 true : false); 498 if (rc) 499 goto err_out; 500 501 return 0; 502 err_out: 503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 504 vnic_id, rc); 505 return rc; 506 } 507 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 509 { 510 int rc = 0; 511 512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 513 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 514 if (rc) 515 return rc; 516 517 PMD_DRV_LOG(DEBUG, 518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 519 " rx_fc_in_tbl.ctx_id = %d\n", 520 bp->flow_stat->rx_fc_in_tbl.va, 521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 522 bp->flow_stat->rx_fc_in_tbl.ctx_id); 523 524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 525 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 526 if (rc) 527 return rc; 528 529 PMD_DRV_LOG(DEBUG, 530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 531 " rx_fc_out_tbl.ctx_id = %d\n", 532 bp->flow_stat->rx_fc_out_tbl.va, 533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 534 bp->flow_stat->rx_fc_out_tbl.ctx_id); 535 536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 537 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 538 if (rc) 539 return rc; 540 541 PMD_DRV_LOG(DEBUG, 542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 543 " tx_fc_in_tbl.ctx_id = %d\n", 544 bp->flow_stat->tx_fc_in_tbl.va, 545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 546 bp->flow_stat->tx_fc_in_tbl.ctx_id); 547 548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 549 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 550 if (rc) 551 return rc; 552 553 PMD_DRV_LOG(DEBUG, 554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 555 " tx_fc_out_tbl.ctx_id = %d\n", 556 bp->flow_stat->tx_fc_out_tbl.va, 557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 558 bp->flow_stat->tx_fc_out_tbl.ctx_id); 559 560 memset(bp->flow_stat->rx_fc_out_tbl.va, 561 0, 562 bp->flow_stat->rx_fc_out_tbl.size); 563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 565 bp->flow_stat->rx_fc_out_tbl.ctx_id, 566 bp->flow_stat->max_fc, 567 true); 568 if (rc) 569 return rc; 570 571 memset(bp->flow_stat->tx_fc_out_tbl.va, 572 0, 573 bp->flow_stat->tx_fc_out_tbl.size); 574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 576 bp->flow_stat->tx_fc_out_tbl.ctx_id, 577 bp->flow_stat->max_fc, 578 true); 579 580 return rc; 581 } 582 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size, 584 struct bnxt_ctx_mem_buf_info *ctx) 585 { 586 if (!ctx) 587 return -EINVAL; 588 589 ctx->va = rte_zmalloc_socket(type, size, 0, 590 bp->eth_dev->device->numa_node); 591 if (ctx->va == NULL) 592 return -ENOMEM; 593 rte_mem_lock_page(ctx->va); 594 ctx->size = size; 595 ctx->dma = rte_mem_virt2iova(ctx->va); 596 if (ctx->dma == RTE_BAD_IOVA) 597 return -ENOMEM; 598 599 return 0; 600 } 601 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 603 { 604 struct rte_pci_device *pdev = bp->pdev; 605 char type[RTE_MEMZONE_NAMESIZE]; 606 uint16_t max_fc; 607 int rc = 0; 608 609 max_fc = bp->flow_stat->max_fc; 610 611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 613 /* 4 bytes for each counter-id */ 614 rc = bnxt_alloc_ctx_mem_buf(bp, type, 615 max_fc * 4, 616 &bp->flow_stat->rx_fc_in_tbl); 617 if (rc) 618 return rc; 619 620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 623 rc = bnxt_alloc_ctx_mem_buf(bp, type, 624 max_fc * 16, 625 &bp->flow_stat->rx_fc_out_tbl); 626 if (rc) 627 return rc; 628 629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 631 /* 4 bytes for each counter-id */ 632 rc = bnxt_alloc_ctx_mem_buf(bp, type, 633 max_fc * 4, 634 &bp->flow_stat->tx_fc_in_tbl); 635 if (rc) 636 return rc; 637 638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 641 rc = bnxt_alloc_ctx_mem_buf(bp, type, 642 max_fc * 16, 643 &bp->flow_stat->tx_fc_out_tbl); 644 if (rc) 645 return rc; 646 647 rc = bnxt_register_fc_ctx_mem(bp); 648 649 return rc; 650 } 651 652 static int bnxt_init_ctx_mem(struct bnxt *bp) 653 { 654 int rc = 0; 655 656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 658 !BNXT_FLOW_XSTATS_EN(bp)) 659 return 0; 660 661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 662 if (rc) 663 return rc; 664 665 rc = bnxt_init_fc_ctx_mem(bp); 666 667 return rc; 668 } 669 670 static int bnxt_update_phy_setting(struct bnxt *bp) 671 { 672 struct rte_eth_link new; 673 int rc; 674 675 rc = bnxt_get_hwrm_link_config(bp, &new); 676 if (rc) { 677 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 678 return rc; 679 } 680 681 /* 682 * On BCM957508-N2100 adapters, FW will not allow any user other 683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 684 * always returns link up. Force phy update always in that case. 685 */ 686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 687 rc = bnxt_set_hwrm_link_config(bp, true); 688 if (rc) { 689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 690 return rc; 691 } 692 } 693 694 return rc; 695 } 696 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp) 698 { 699 rte_free(bp->prev_rx_ring_stats); 700 rte_free(bp->prev_tx_ring_stats); 701 702 bp->prev_rx_ring_stats = NULL; 703 bp->prev_tx_ring_stats = NULL; 704 } 705 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp) 707 { 708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats", 709 sizeof(struct bnxt_ring_stats) * 710 bp->rx_cp_nr_rings, 711 0); 712 if (bp->prev_rx_ring_stats == NULL) 713 return -ENOMEM; 714 715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats", 716 sizeof(struct bnxt_ring_stats) * 717 bp->tx_cp_nr_rings, 718 0); 719 if (bp->prev_tx_ring_stats == NULL) 720 goto error; 721 722 return 0; 723 724 error: 725 bnxt_free_prev_ring_stats(bp); 726 return -ENOMEM; 727 } 728 729 static int bnxt_start_nic(struct bnxt *bp) 730 { 731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 733 uint32_t intr_vector = 0; 734 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 735 uint32_t vec = BNXT_MISC_VEC_ID; 736 unsigned int i, j; 737 int rc; 738 739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 740 bp->eth_dev->data->dev_conf.rxmode.offloads |= 741 DEV_RX_OFFLOAD_JUMBO_FRAME; 742 bp->flags |= BNXT_FLAG_JUMBO; 743 } else { 744 bp->eth_dev->data->dev_conf.rxmode.offloads &= 745 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 746 bp->flags &= ~BNXT_FLAG_JUMBO; 747 } 748 749 /* THOR does not support ring groups. 750 * But we will use the array to save RSS context IDs. 751 */ 752 if (BNXT_CHIP_P5(bp)) 753 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 754 755 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 756 if (rc) { 757 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 758 goto err_out; 759 } 760 761 rc = bnxt_alloc_hwrm_rings(bp); 762 if (rc) { 763 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 764 goto err_out; 765 } 766 767 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 768 if (rc) { 769 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 770 goto err_out; 771 } 772 773 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 774 goto skip_cosq_cfg; 775 776 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 777 if (bp->rx_cos_queue[i].id != 0xff) { 778 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 779 780 if (!vnic) { 781 PMD_DRV_LOG(ERR, 782 "Num pools more than FW profile\n"); 783 rc = -EINVAL; 784 goto err_out; 785 } 786 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 787 bp->rx_cosq_cnt++; 788 } 789 } 790 791 skip_cosq_cfg: 792 rc = bnxt_mq_rx_configure(bp); 793 if (rc) { 794 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 795 goto err_out; 796 } 797 798 /* default vnic 0 */ 799 rc = bnxt_setup_one_vnic(bp, 0); 800 if (rc) 801 goto err_out; 802 /* VNIC configuration */ 803 if (BNXT_RFS_NEEDS_VNIC(bp)) { 804 for (i = 1; i < bp->nr_vnics; i++) { 805 rc = bnxt_setup_one_vnic(bp, i); 806 if (rc) 807 goto err_out; 808 } 809 } 810 811 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 812 if (rc) { 813 PMD_DRV_LOG(ERR, 814 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 815 goto err_out; 816 } 817 818 /* check and configure queue intr-vector mapping */ 819 if ((rte_intr_cap_multiple(intr_handle) || 820 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 821 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 822 intr_vector = bp->eth_dev->data->nb_rx_queues; 823 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 824 if (intr_vector > bp->rx_cp_nr_rings) { 825 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 826 bp->rx_cp_nr_rings); 827 return -ENOTSUP; 828 } 829 rc = rte_intr_efd_enable(intr_handle, intr_vector); 830 if (rc) 831 return rc; 832 } 833 834 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 835 intr_handle->intr_vec = 836 rte_zmalloc("intr_vec", 837 bp->eth_dev->data->nb_rx_queues * 838 sizeof(int), 0); 839 if (intr_handle->intr_vec == NULL) { 840 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 841 " intr_vec", bp->eth_dev->data->nb_rx_queues); 842 rc = -ENOMEM; 843 goto err_out; 844 } 845 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 846 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 847 intr_handle->intr_vec, intr_handle->nb_efd, 848 intr_handle->max_intr); 849 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 850 queue_id++) { 851 intr_handle->intr_vec[queue_id] = 852 vec + BNXT_RX_VEC_START; 853 if (vec < base + intr_handle->nb_efd - 1) 854 vec++; 855 } 856 } 857 858 /* enable uio/vfio intr/eventfd mapping */ 859 rc = rte_intr_enable(intr_handle); 860 #ifndef RTE_EXEC_ENV_FREEBSD 861 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 862 if (rc) 863 goto err_out; 864 #endif 865 866 rc = bnxt_update_phy_setting(bp); 867 if (rc) 868 goto err_out; 869 870 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 871 if (!bp->mark_table) 872 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 873 874 return 0; 875 876 err_out: 877 /* Some of the error status returned by FW may not be from errno.h */ 878 if (rc > 0) 879 rc = -EIO; 880 881 return rc; 882 } 883 884 static int bnxt_shutdown_nic(struct bnxt *bp) 885 { 886 bnxt_free_all_hwrm_resources(bp); 887 bnxt_free_all_filters(bp); 888 bnxt_free_all_vnics(bp); 889 return 0; 890 } 891 892 /* 893 * Device configuration and status function 894 */ 895 896 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 897 { 898 uint32_t link_speed = 0; 899 uint32_t speed_capa = 0; 900 901 if (bp->link_info == NULL) 902 return 0; 903 904 link_speed = bp->link_info->support_speeds; 905 906 /* If PAM4 is configured, use PAM4 supported speed */ 907 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 908 link_speed = bp->link_info->support_pam4_speeds; 909 910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 911 speed_capa |= ETH_LINK_SPEED_100M; 912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 913 speed_capa |= ETH_LINK_SPEED_100M_HD; 914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 915 speed_capa |= ETH_LINK_SPEED_1G; 916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 917 speed_capa |= ETH_LINK_SPEED_2_5G; 918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 919 speed_capa |= ETH_LINK_SPEED_10G; 920 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 921 speed_capa |= ETH_LINK_SPEED_20G; 922 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 923 speed_capa |= ETH_LINK_SPEED_25G; 924 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 925 speed_capa |= ETH_LINK_SPEED_40G; 926 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 927 speed_capa |= ETH_LINK_SPEED_50G; 928 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 929 speed_capa |= ETH_LINK_SPEED_100G; 930 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 931 speed_capa |= ETH_LINK_SPEED_50G; 932 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 933 speed_capa |= ETH_LINK_SPEED_100G; 934 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 935 speed_capa |= ETH_LINK_SPEED_200G; 936 937 if (bp->link_info->auto_mode == 938 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 939 speed_capa |= ETH_LINK_SPEED_FIXED; 940 941 return speed_capa; 942 } 943 944 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 945 struct rte_eth_dev_info *dev_info) 946 { 947 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 948 struct bnxt *bp = eth_dev->data->dev_private; 949 uint16_t max_vnics, i, j, vpool, vrxq; 950 unsigned int max_rx_rings; 951 int rc; 952 953 rc = is_bnxt_in_error(bp); 954 if (rc) 955 return rc; 956 957 /* MAC Specifics */ 958 dev_info->max_mac_addrs = bp->max_l2_ctx; 959 dev_info->max_hash_mac_addrs = 0; 960 961 /* PF/VF specifics */ 962 if (BNXT_PF(bp)) 963 dev_info->max_vfs = pdev->max_vfs; 964 965 max_rx_rings = bnxt_max_rings(bp); 966 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 967 dev_info->max_rx_queues = max_rx_rings; 968 dev_info->max_tx_queues = max_rx_rings; 969 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 970 dev_info->hash_key_size = HW_HASH_KEY_SIZE; 971 max_vnics = bp->max_vnics; 972 973 /* MTU specifics */ 974 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 975 dev_info->max_mtu = BNXT_MAX_MTU; 976 977 /* Fast path specifics */ 978 dev_info->min_rx_bufsize = 1; 979 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 980 981 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 982 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 983 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 984 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 985 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 986 dev_info->tx_queue_offload_capa; 987 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 988 989 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 990 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 991 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 992 993 dev_info->default_rxconf = (struct rte_eth_rxconf) { 994 .rx_thresh = { 995 .pthresh = 8, 996 .hthresh = 8, 997 .wthresh = 0, 998 }, 999 .rx_free_thresh = 32, 1000 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 1001 }; 1002 1003 dev_info->default_txconf = (struct rte_eth_txconf) { 1004 .tx_thresh = { 1005 .pthresh = 32, 1006 .hthresh = 0, 1007 .wthresh = 0, 1008 }, 1009 .tx_free_thresh = 32, 1010 .tx_rs_thresh = 32, 1011 }; 1012 eth_dev->data->dev_conf.intr_conf.lsc = 1; 1013 1014 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1015 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 1016 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1017 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 1018 1019 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 1020 dev_info->switch_info.name = eth_dev->device->name; 1021 dev_info->switch_info.domain_id = bp->switch_domain_id; 1022 dev_info->switch_info.port_id = 1023 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 1024 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 1025 } 1026 1027 /* 1028 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 1029 * need further investigation. 1030 */ 1031 1032 /* VMDq resources */ 1033 vpool = 64; /* ETH_64_POOLS */ 1034 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 1035 for (i = 0; i < 4; vpool >>= 1, i++) { 1036 if (max_vnics > vpool) { 1037 for (j = 0; j < 5; vrxq >>= 1, j++) { 1038 if (dev_info->max_rx_queues > vrxq) { 1039 if (vpool > vrxq) 1040 vpool = vrxq; 1041 goto found; 1042 } 1043 } 1044 /* Not enough resources to support VMDq */ 1045 break; 1046 } 1047 } 1048 /* Not enough resources to support VMDq */ 1049 vpool = 0; 1050 vrxq = 0; 1051 found: 1052 dev_info->max_vmdq_pools = vpool; 1053 dev_info->vmdq_queue_num = vrxq; 1054 1055 dev_info->vmdq_pool_base = 0; 1056 dev_info->vmdq_queue_base = 0; 1057 1058 return 0; 1059 } 1060 1061 /* Configure the device based on the configuration provided */ 1062 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1063 { 1064 struct bnxt *bp = eth_dev->data->dev_private; 1065 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1066 int rc; 1067 1068 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1069 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1070 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1071 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1072 1073 rc = is_bnxt_in_error(bp); 1074 if (rc) 1075 return rc; 1076 1077 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1078 rc = bnxt_hwrm_check_vf_rings(bp); 1079 if (rc) { 1080 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1081 return -ENOSPC; 1082 } 1083 1084 /* If a resource has already been allocated - in this case 1085 * it is the async completion ring, free it. Reallocate it after 1086 * resource reservation. This will ensure the resource counts 1087 * are calculated correctly. 1088 */ 1089 1090 pthread_mutex_lock(&bp->def_cp_lock); 1091 1092 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1093 bnxt_disable_int(bp); 1094 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1095 } 1096 1097 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1098 if (rc) { 1099 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1100 pthread_mutex_unlock(&bp->def_cp_lock); 1101 return -ENOSPC; 1102 } 1103 1104 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1105 rc = bnxt_alloc_async_cp_ring(bp); 1106 if (rc) { 1107 pthread_mutex_unlock(&bp->def_cp_lock); 1108 return rc; 1109 } 1110 bnxt_enable_int(bp); 1111 } 1112 1113 pthread_mutex_unlock(&bp->def_cp_lock); 1114 } 1115 1116 /* Inherit new configurations */ 1117 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1118 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1119 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1120 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1121 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1122 bp->max_stat_ctx) 1123 goto resource_error; 1124 1125 if (BNXT_HAS_RING_GRPS(bp) && 1126 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1127 goto resource_error; 1128 1129 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1130 bp->max_vnics < eth_dev->data->nb_rx_queues) 1131 goto resource_error; 1132 1133 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1134 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1135 1136 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1137 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1138 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1139 1140 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1141 eth_dev->data->mtu = 1142 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1143 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1144 BNXT_NUM_VLANS; 1145 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1146 } 1147 return 0; 1148 1149 resource_error: 1150 PMD_DRV_LOG(ERR, 1151 "Insufficient resources to support requested config\n"); 1152 PMD_DRV_LOG(ERR, 1153 "Num Queues Requested: Tx %d, Rx %d\n", 1154 eth_dev->data->nb_tx_queues, 1155 eth_dev->data->nb_rx_queues); 1156 PMD_DRV_LOG(ERR, 1157 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1158 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1159 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1160 return -ENOSPC; 1161 } 1162 1163 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1164 { 1165 struct rte_eth_link *link = ð_dev->data->dev_link; 1166 1167 if (link->link_status) 1168 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1169 eth_dev->data->port_id, 1170 (uint32_t)link->link_speed, 1171 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1172 ("full-duplex") : ("half-duplex\n")); 1173 else 1174 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1175 eth_dev->data->port_id); 1176 } 1177 1178 /* 1179 * Determine whether the current configuration requires support for scattered 1180 * receive; return 1 if scattered receive is required and 0 if not. 1181 */ 1182 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1183 { 1184 uint16_t buf_size; 1185 int i; 1186 1187 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1188 return 1; 1189 1190 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) 1191 return 1; 1192 1193 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1194 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1195 1196 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1197 RTE_PKTMBUF_HEADROOM); 1198 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1199 return 1; 1200 } 1201 return 0; 1202 } 1203 1204 static eth_rx_burst_t 1205 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1206 { 1207 struct bnxt *bp = eth_dev->data->dev_private; 1208 1209 /* Disable vector mode RX for Stingray2 for now */ 1210 if (BNXT_CHIP_SR2(bp)) { 1211 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1212 return bnxt_recv_pkts; 1213 } 1214 1215 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \ 1216 !defined(RTE_LIBRTE_IEEE1588) 1217 1218 /* Vector mode receive cannot be enabled if scattered rx is in use. */ 1219 if (eth_dev->data->scattered_rx) 1220 goto use_scalar_rx; 1221 1222 /* 1223 * Vector mode receive cannot be enabled if Truflow is enabled or if 1224 * asynchronous completions and receive completions can be placed in 1225 * the same completion ring. 1226 */ 1227 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp)) 1228 goto use_scalar_rx; 1229 1230 /* 1231 * Vector mode receive cannot be enabled if any receive offloads outside 1232 * a limited subset have been enabled. 1233 */ 1234 if (eth_dev->data->dev_conf.rxmode.offloads & 1235 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1236 DEV_RX_OFFLOAD_KEEP_CRC | 1237 DEV_RX_OFFLOAD_JUMBO_FRAME | 1238 DEV_RX_OFFLOAD_IPV4_CKSUM | 1239 DEV_RX_OFFLOAD_UDP_CKSUM | 1240 DEV_RX_OFFLOAD_TCP_CKSUM | 1241 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1242 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1243 DEV_RX_OFFLOAD_RSS_HASH | 1244 DEV_RX_OFFLOAD_VLAN_FILTER)) 1245 goto use_scalar_rx; 1246 1247 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1248 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1249 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1250 PMD_DRV_LOG(INFO, 1251 "Using AVX2 vector mode receive for port %d\n", 1252 eth_dev->data->port_id); 1253 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1254 return bnxt_recv_pkts_vec_avx2; 1255 } 1256 #endif 1257 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1258 PMD_DRV_LOG(INFO, 1259 "Using SSE vector mode receive for port %d\n", 1260 eth_dev->data->port_id); 1261 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1262 return bnxt_recv_pkts_vec; 1263 } 1264 1265 use_scalar_rx: 1266 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1267 eth_dev->data->port_id); 1268 PMD_DRV_LOG(INFO, 1269 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1270 eth_dev->data->port_id, 1271 eth_dev->data->scattered_rx, 1272 eth_dev->data->dev_conf.rxmode.offloads); 1273 #endif 1274 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1275 return bnxt_recv_pkts; 1276 } 1277 1278 static eth_tx_burst_t 1279 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1280 { 1281 struct bnxt *bp = eth_dev->data->dev_private; 1282 1283 /* Disable vector mode TX for Stingray2 for now */ 1284 if (BNXT_CHIP_SR2(bp)) 1285 return bnxt_xmit_pkts; 1286 1287 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \ 1288 !defined(RTE_LIBRTE_IEEE1588) 1289 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1290 1291 /* 1292 * Vector mode transmit can be enabled only if not using scatter rx 1293 * or tx offloads. 1294 */ 1295 if (eth_dev->data->scattered_rx || 1296 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) || 1297 BNXT_TRUFLOW_EN(bp)) 1298 goto use_scalar_tx; 1299 1300 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1301 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1302 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1303 PMD_DRV_LOG(INFO, 1304 "Using AVX2 vector mode transmit for port %d\n", 1305 eth_dev->data->port_id); 1306 return bnxt_xmit_pkts_vec_avx2; 1307 } 1308 #endif 1309 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1310 PMD_DRV_LOG(INFO, 1311 "Using SSE vector mode transmit for port %d\n", 1312 eth_dev->data->port_id); 1313 return bnxt_xmit_pkts_vec; 1314 } 1315 1316 use_scalar_tx: 1317 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1318 eth_dev->data->port_id); 1319 PMD_DRV_LOG(INFO, 1320 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1321 eth_dev->data->port_id, 1322 eth_dev->data->scattered_rx, 1323 offloads); 1324 #endif 1325 return bnxt_xmit_pkts; 1326 } 1327 1328 static int bnxt_handle_if_change_status(struct bnxt *bp) 1329 { 1330 int rc; 1331 1332 /* Since fw has undergone a reset and lost all contexts, 1333 * set fatal flag to not issue hwrm during cleanup 1334 */ 1335 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1336 bnxt_uninit_resources(bp, true); 1337 1338 /* clear fatal flag so that re-init happens */ 1339 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1340 rc = bnxt_init_resources(bp, true); 1341 1342 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1343 1344 return rc; 1345 } 1346 1347 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1348 { 1349 struct bnxt *bp = eth_dev->data->dev_private; 1350 int rc = 0; 1351 1352 if (!BNXT_SINGLE_PF(bp)) 1353 return -ENOTSUP; 1354 1355 if (!bp->link_info->link_up) 1356 rc = bnxt_set_hwrm_link_config(bp, true); 1357 if (!rc) 1358 eth_dev->data->dev_link.link_status = 1; 1359 1360 bnxt_print_link_info(eth_dev); 1361 return rc; 1362 } 1363 1364 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1365 { 1366 struct bnxt *bp = eth_dev->data->dev_private; 1367 1368 if (!BNXT_SINGLE_PF(bp)) 1369 return -ENOTSUP; 1370 1371 eth_dev->data->dev_link.link_status = 0; 1372 bnxt_set_hwrm_link_config(bp, false); 1373 bp->link_info->link_up = 0; 1374 1375 return 0; 1376 } 1377 1378 static void bnxt_free_switch_domain(struct bnxt *bp) 1379 { 1380 int rc = 0; 1381 1382 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) 1383 return; 1384 1385 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1386 if (rc) 1387 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1388 bp->switch_domain_id, rc); 1389 } 1390 1391 static void bnxt_ptp_get_current_time(void *arg) 1392 { 1393 struct bnxt *bp = arg; 1394 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1395 int rc; 1396 1397 rc = is_bnxt_in_error(bp); 1398 if (rc) 1399 return; 1400 1401 if (!ptp) 1402 return; 1403 1404 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1405 &ptp->current_time); 1406 1407 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1408 if (rc != 0) { 1409 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1410 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1411 } 1412 } 1413 1414 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1415 { 1416 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1417 int rc; 1418 1419 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1420 return 0; 1421 1422 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1423 &ptp->current_time); 1424 1425 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1426 return rc; 1427 } 1428 1429 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1430 { 1431 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1432 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1433 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1434 } 1435 } 1436 1437 static void bnxt_ptp_stop(struct bnxt *bp) 1438 { 1439 bnxt_cancel_ptp_alarm(bp); 1440 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1441 } 1442 1443 static int bnxt_ptp_start(struct bnxt *bp) 1444 { 1445 int rc; 1446 1447 rc = bnxt_schedule_ptp_alarm(bp); 1448 if (rc != 0) { 1449 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1450 } else { 1451 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1452 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1453 } 1454 1455 return rc; 1456 } 1457 1458 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1459 { 1460 struct bnxt *bp = eth_dev->data->dev_private; 1461 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1462 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1463 struct rte_eth_link link; 1464 int ret; 1465 1466 eth_dev->data->dev_started = 0; 1467 eth_dev->data->scattered_rx = 0; 1468 1469 /* Prevent crashes when queues are still in use */ 1470 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1471 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1472 1473 bnxt_disable_int(bp); 1474 1475 /* disable uio/vfio intr/eventfd mapping */ 1476 rte_intr_disable(intr_handle); 1477 1478 /* Stop the child representors for this device */ 1479 ret = bnxt_rep_stop_all(bp); 1480 if (ret != 0) 1481 return ret; 1482 1483 /* delete the bnxt ULP port details */ 1484 bnxt_ulp_port_deinit(bp); 1485 1486 bnxt_cancel_fw_health_check(bp); 1487 1488 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1489 bnxt_cancel_ptp_alarm(bp); 1490 1491 /* Do not bring link down during reset recovery */ 1492 if (!is_bnxt_in_error(bp)) { 1493 bnxt_dev_set_link_down_op(eth_dev); 1494 /* Wait for link to be reset */ 1495 if (BNXT_SINGLE_PF(bp)) 1496 rte_delay_ms(500); 1497 /* clear the recorded link status */ 1498 memset(&link, 0, sizeof(link)); 1499 rte_eth_linkstatus_set(eth_dev, &link); 1500 } 1501 1502 /* Clean queue intr-vector mapping */ 1503 rte_intr_efd_disable(intr_handle); 1504 if (intr_handle->intr_vec != NULL) { 1505 rte_free(intr_handle->intr_vec); 1506 intr_handle->intr_vec = NULL; 1507 } 1508 1509 bnxt_hwrm_port_clr_stats(bp); 1510 bnxt_free_tx_mbufs(bp); 1511 bnxt_free_rx_mbufs(bp); 1512 /* Process any remaining notifications in default completion queue */ 1513 bnxt_int_handler(eth_dev); 1514 bnxt_shutdown_nic(bp); 1515 bnxt_hwrm_if_change(bp, false); 1516 1517 bnxt_free_prev_ring_stats(bp); 1518 rte_free(bp->mark_table); 1519 bp->mark_table = NULL; 1520 1521 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1522 bp->rx_cosq_cnt = 0; 1523 /* All filters are deleted on a port stop. */ 1524 if (BNXT_FLOW_XSTATS_EN(bp)) 1525 bp->flow_stat->flow_count = 0; 1526 1527 return 0; 1528 } 1529 1530 /* Unload the driver, release resources */ 1531 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1532 { 1533 struct bnxt *bp = eth_dev->data->dev_private; 1534 1535 pthread_mutex_lock(&bp->err_recovery_lock); 1536 if (bp->flags & BNXT_FLAG_FW_RESET) { 1537 PMD_DRV_LOG(ERR, 1538 "Adapter recovering from error..Please retry\n"); 1539 pthread_mutex_unlock(&bp->err_recovery_lock); 1540 return -EAGAIN; 1541 } 1542 pthread_mutex_unlock(&bp->err_recovery_lock); 1543 1544 return bnxt_dev_stop(eth_dev); 1545 } 1546 1547 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1548 { 1549 struct bnxt *bp = eth_dev->data->dev_private; 1550 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1551 int vlan_mask = 0; 1552 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1553 1554 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1555 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1556 return -EINVAL; 1557 } 1558 1559 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1560 PMD_DRV_LOG(ERR, 1561 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1562 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1563 1564 do { 1565 rc = bnxt_hwrm_if_change(bp, true); 1566 if (rc == 0 || rc != -EAGAIN) 1567 break; 1568 1569 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1570 } while (retry_cnt--); 1571 1572 if (rc) 1573 return rc; 1574 1575 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1576 rc = bnxt_handle_if_change_status(bp); 1577 if (rc) 1578 return rc; 1579 } 1580 1581 bnxt_enable_int(bp); 1582 1583 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1584 1585 rc = bnxt_start_nic(bp); 1586 if (rc) 1587 goto error; 1588 1589 rc = bnxt_alloc_prev_ring_stats(bp); 1590 if (rc) 1591 goto error; 1592 1593 eth_dev->data->dev_started = 1; 1594 1595 bnxt_link_update_op(eth_dev, 1); 1596 1597 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1598 vlan_mask |= ETH_VLAN_FILTER_MASK; 1599 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1600 vlan_mask |= ETH_VLAN_STRIP_MASK; 1601 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1602 if (rc) 1603 goto error; 1604 1605 /* Initialize bnxt ULP port details */ 1606 rc = bnxt_ulp_port_init(bp); 1607 if (rc) 1608 goto error; 1609 1610 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1611 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1612 1613 bnxt_schedule_fw_health_check(bp); 1614 1615 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1616 bnxt_schedule_ptp_alarm(bp); 1617 1618 return 0; 1619 1620 error: 1621 bnxt_dev_stop(eth_dev); 1622 return rc; 1623 } 1624 1625 static void 1626 bnxt_uninit_locks(struct bnxt *bp) 1627 { 1628 pthread_mutex_destroy(&bp->flow_lock); 1629 pthread_mutex_destroy(&bp->def_cp_lock); 1630 pthread_mutex_destroy(&bp->health_check_lock); 1631 pthread_mutex_destroy(&bp->err_recovery_lock); 1632 if (bp->rep_info) { 1633 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1634 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1635 } 1636 } 1637 1638 static void bnxt_drv_uninit(struct bnxt *bp) 1639 { 1640 bnxt_free_leds_info(bp); 1641 bnxt_free_cos_queues(bp); 1642 bnxt_free_link_info(bp); 1643 bnxt_free_parent_info(bp); 1644 bnxt_uninit_locks(bp); 1645 1646 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1647 bp->tx_mem_zone = NULL; 1648 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1649 bp->rx_mem_zone = NULL; 1650 1651 bnxt_free_vf_info(bp); 1652 bnxt_free_pf_info(bp); 1653 1654 rte_free(bp->grp_info); 1655 bp->grp_info = NULL; 1656 } 1657 1658 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1659 { 1660 struct bnxt *bp = eth_dev->data->dev_private; 1661 int ret = 0; 1662 1663 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1664 return 0; 1665 1666 pthread_mutex_lock(&bp->err_recovery_lock); 1667 if (bp->flags & BNXT_FLAG_FW_RESET) { 1668 PMD_DRV_LOG(ERR, 1669 "Adapter recovering from error...Please retry\n"); 1670 pthread_mutex_unlock(&bp->err_recovery_lock); 1671 return -EAGAIN; 1672 } 1673 pthread_mutex_unlock(&bp->err_recovery_lock); 1674 1675 /* cancel the recovery handler before remove dev */ 1676 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1677 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1678 bnxt_cancel_fc_thread(bp); 1679 1680 if (eth_dev->data->dev_started) 1681 ret = bnxt_dev_stop(eth_dev); 1682 1683 bnxt_uninit_resources(bp, false); 1684 1685 bnxt_drv_uninit(bp); 1686 1687 return ret; 1688 } 1689 1690 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1691 uint32_t index) 1692 { 1693 struct bnxt *bp = eth_dev->data->dev_private; 1694 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1695 struct bnxt_vnic_info *vnic; 1696 struct bnxt_filter_info *filter, *temp_filter; 1697 uint32_t i; 1698 1699 if (is_bnxt_in_error(bp)) 1700 return; 1701 1702 /* 1703 * Loop through all VNICs from the specified filter flow pools to 1704 * remove the corresponding MAC addr filter 1705 */ 1706 for (i = 0; i < bp->nr_vnics; i++) { 1707 if (!(pool_mask & (1ULL << i))) 1708 continue; 1709 1710 vnic = &bp->vnic_info[i]; 1711 filter = STAILQ_FIRST(&vnic->filter); 1712 while (filter) { 1713 temp_filter = STAILQ_NEXT(filter, next); 1714 if (filter->mac_index == index) { 1715 STAILQ_REMOVE(&vnic->filter, filter, 1716 bnxt_filter_info, next); 1717 bnxt_hwrm_clear_l2_filter(bp, filter); 1718 bnxt_free_filter(bp, filter); 1719 } 1720 filter = temp_filter; 1721 } 1722 } 1723 } 1724 1725 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1726 struct rte_ether_addr *mac_addr, uint32_t index, 1727 uint32_t pool) 1728 { 1729 struct bnxt_filter_info *filter; 1730 int rc = 0; 1731 1732 /* Attach requested MAC address to the new l2_filter */ 1733 STAILQ_FOREACH(filter, &vnic->filter, next) { 1734 if (filter->mac_index == index) { 1735 PMD_DRV_LOG(DEBUG, 1736 "MAC addr already existed for pool %d\n", 1737 pool); 1738 return 0; 1739 } 1740 } 1741 1742 filter = bnxt_alloc_filter(bp); 1743 if (!filter) { 1744 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1745 return -ENODEV; 1746 } 1747 1748 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1749 * if the MAC that's been programmed now is a different one, then, 1750 * copy that addr to filter->l2_addr 1751 */ 1752 if (mac_addr) 1753 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1754 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1755 1756 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1757 if (!rc) { 1758 filter->mac_index = index; 1759 if (filter->mac_index == 0) 1760 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1761 else 1762 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1763 } else { 1764 bnxt_free_filter(bp, filter); 1765 } 1766 1767 return rc; 1768 } 1769 1770 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1771 struct rte_ether_addr *mac_addr, 1772 uint32_t index, uint32_t pool) 1773 { 1774 struct bnxt *bp = eth_dev->data->dev_private; 1775 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1776 int rc = 0; 1777 1778 rc = is_bnxt_in_error(bp); 1779 if (rc) 1780 return rc; 1781 1782 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1783 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1784 return -ENOTSUP; 1785 } 1786 1787 if (!vnic) { 1788 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1789 return -EINVAL; 1790 } 1791 1792 /* Filter settings will get applied when port is started */ 1793 if (!eth_dev->data->dev_started) 1794 return 0; 1795 1796 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1797 1798 return rc; 1799 } 1800 1801 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1802 { 1803 int rc = 0; 1804 struct bnxt *bp = eth_dev->data->dev_private; 1805 struct rte_eth_link new; 1806 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1807 BNXT_MIN_LINK_WAIT_CNT; 1808 1809 rc = is_bnxt_in_error(bp); 1810 if (rc) 1811 return rc; 1812 1813 memset(&new, 0, sizeof(new)); 1814 1815 if (bp->link_info == NULL) 1816 goto out; 1817 1818 do { 1819 /* Retrieve link info from hardware */ 1820 rc = bnxt_get_hwrm_link_config(bp, &new); 1821 if (rc) { 1822 new.link_speed = ETH_LINK_SPEED_100M; 1823 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1824 PMD_DRV_LOG(ERR, 1825 "Failed to retrieve link rc = 0x%x!\n", rc); 1826 goto out; 1827 } 1828 1829 if (!wait_to_complete || new.link_status) 1830 break; 1831 1832 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1833 } while (cnt--); 1834 1835 /* Only single function PF can bring phy down. 1836 * When port is stopped, report link down for VF/MH/NPAR functions. 1837 */ 1838 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1839 memset(&new, 0, sizeof(new)); 1840 1841 out: 1842 /* Timed out or success */ 1843 if (new.link_status != eth_dev->data->dev_link.link_status || 1844 new.link_speed != eth_dev->data->dev_link.link_speed) { 1845 rte_eth_linkstatus_set(eth_dev, &new); 1846 1847 rte_eth_dev_callback_process(eth_dev, 1848 RTE_ETH_EVENT_INTR_LSC, 1849 NULL); 1850 1851 bnxt_print_link_info(eth_dev); 1852 } 1853 1854 return rc; 1855 } 1856 1857 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1858 { 1859 struct bnxt *bp = eth_dev->data->dev_private; 1860 struct bnxt_vnic_info *vnic; 1861 uint32_t old_flags; 1862 int rc; 1863 1864 rc = is_bnxt_in_error(bp); 1865 if (rc) 1866 return rc; 1867 1868 /* Filter settings will get applied when port is started */ 1869 if (!eth_dev->data->dev_started) 1870 return 0; 1871 1872 if (bp->vnic_info == NULL) 1873 return 0; 1874 1875 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1876 1877 old_flags = vnic->flags; 1878 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1879 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1880 if (rc != 0) 1881 vnic->flags = old_flags; 1882 1883 return rc; 1884 } 1885 1886 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1887 { 1888 struct bnxt *bp = eth_dev->data->dev_private; 1889 struct bnxt_vnic_info *vnic; 1890 uint32_t old_flags; 1891 int rc; 1892 1893 rc = is_bnxt_in_error(bp); 1894 if (rc) 1895 return rc; 1896 1897 /* Filter settings will get applied when port is started */ 1898 if (!eth_dev->data->dev_started) 1899 return 0; 1900 1901 if (bp->vnic_info == NULL) 1902 return 0; 1903 1904 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1905 1906 old_flags = vnic->flags; 1907 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1908 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1909 if (rc != 0) 1910 vnic->flags = old_flags; 1911 1912 return rc; 1913 } 1914 1915 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1916 { 1917 struct bnxt *bp = eth_dev->data->dev_private; 1918 struct bnxt_vnic_info *vnic; 1919 uint32_t old_flags; 1920 int rc; 1921 1922 rc = is_bnxt_in_error(bp); 1923 if (rc) 1924 return rc; 1925 1926 /* Filter settings will get applied when port is started */ 1927 if (!eth_dev->data->dev_started) 1928 return 0; 1929 1930 if (bp->vnic_info == NULL) 1931 return 0; 1932 1933 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1934 1935 old_flags = vnic->flags; 1936 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1937 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1938 if (rc != 0) 1939 vnic->flags = old_flags; 1940 1941 return rc; 1942 } 1943 1944 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1945 { 1946 struct bnxt *bp = eth_dev->data->dev_private; 1947 struct bnxt_vnic_info *vnic; 1948 uint32_t old_flags; 1949 int rc; 1950 1951 rc = is_bnxt_in_error(bp); 1952 if (rc) 1953 return rc; 1954 1955 /* Filter settings will get applied when port is started */ 1956 if (!eth_dev->data->dev_started) 1957 return 0; 1958 1959 if (bp->vnic_info == NULL) 1960 return 0; 1961 1962 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1963 1964 old_flags = vnic->flags; 1965 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1966 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1967 if (rc != 0) 1968 vnic->flags = old_flags; 1969 1970 return rc; 1971 } 1972 1973 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1974 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1975 { 1976 if (qid >= bp->rx_nr_rings) 1977 return NULL; 1978 1979 return bp->eth_dev->data->rx_queues[qid]; 1980 } 1981 1982 /* Return rxq corresponding to a given rss table ring/group ID. */ 1983 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1984 { 1985 struct bnxt_rx_queue *rxq; 1986 unsigned int i; 1987 1988 if (!BNXT_HAS_RING_GRPS(bp)) { 1989 for (i = 0; i < bp->rx_nr_rings; i++) { 1990 rxq = bp->eth_dev->data->rx_queues[i]; 1991 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1992 return rxq->index; 1993 } 1994 } else { 1995 for (i = 0; i < bp->rx_nr_rings; i++) { 1996 if (bp->grp_info[i].fw_grp_id == fwr) 1997 return i; 1998 } 1999 } 2000 2001 return INVALID_HW_RING_ID; 2002 } 2003 2004 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 2005 struct rte_eth_rss_reta_entry64 *reta_conf, 2006 uint16_t reta_size) 2007 { 2008 struct bnxt *bp = eth_dev->data->dev_private; 2009 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2010 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2011 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2012 uint16_t idx, sft; 2013 int i, rc; 2014 2015 rc = is_bnxt_in_error(bp); 2016 if (rc) 2017 return rc; 2018 2019 if (!vnic->rss_table) 2020 return -EINVAL; 2021 2022 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 2023 return -EINVAL; 2024 2025 if (reta_size != tbl_size) { 2026 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2027 "(%d) must equal the size supported by the hardware " 2028 "(%d)\n", reta_size, tbl_size); 2029 return -EINVAL; 2030 } 2031 2032 for (i = 0; i < reta_size; i++) { 2033 struct bnxt_rx_queue *rxq; 2034 2035 idx = i / RTE_RETA_GROUP_SIZE; 2036 sft = i % RTE_RETA_GROUP_SIZE; 2037 2038 if (!(reta_conf[idx].mask & (1ULL << sft))) 2039 continue; 2040 2041 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 2042 if (!rxq) { 2043 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 2044 return -EINVAL; 2045 } 2046 2047 if (BNXT_CHIP_P5(bp)) { 2048 vnic->rss_table[i * 2] = 2049 rxq->rx_ring->rx_ring_struct->fw_ring_id; 2050 vnic->rss_table[i * 2 + 1] = 2051 rxq->cp_ring->cp_ring_struct->fw_ring_id; 2052 } else { 2053 vnic->rss_table[i] = 2054 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 2055 } 2056 } 2057 2058 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2059 return rc; 2060 } 2061 2062 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 2063 struct rte_eth_rss_reta_entry64 *reta_conf, 2064 uint16_t reta_size) 2065 { 2066 struct bnxt *bp = eth_dev->data->dev_private; 2067 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2068 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2069 uint16_t idx, sft, i; 2070 int rc; 2071 2072 rc = is_bnxt_in_error(bp); 2073 if (rc) 2074 return rc; 2075 2076 if (!vnic) 2077 return -EINVAL; 2078 if (!vnic->rss_table) 2079 return -EINVAL; 2080 2081 if (reta_size != tbl_size) { 2082 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2083 "(%d) must equal the size supported by the hardware " 2084 "(%d)\n", reta_size, tbl_size); 2085 return -EINVAL; 2086 } 2087 2088 for (idx = 0, i = 0; i < reta_size; i++) { 2089 idx = i / RTE_RETA_GROUP_SIZE; 2090 sft = i % RTE_RETA_GROUP_SIZE; 2091 2092 if (reta_conf[idx].mask & (1ULL << sft)) { 2093 uint16_t qid; 2094 2095 if (BNXT_CHIP_P5(bp)) 2096 qid = bnxt_rss_to_qid(bp, 2097 vnic->rss_table[i * 2]); 2098 else 2099 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2100 2101 if (qid == INVALID_HW_RING_ID) { 2102 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2103 return -EINVAL; 2104 } 2105 reta_conf[idx].reta[sft] = qid; 2106 } 2107 } 2108 2109 return 0; 2110 } 2111 2112 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2113 struct rte_eth_rss_conf *rss_conf) 2114 { 2115 struct bnxt *bp = eth_dev->data->dev_private; 2116 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2117 struct bnxt_vnic_info *vnic; 2118 int rc; 2119 2120 rc = is_bnxt_in_error(bp); 2121 if (rc) 2122 return rc; 2123 2124 /* 2125 * If RSS enablement were different than dev_configure, 2126 * then return -EINVAL 2127 */ 2128 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 2129 if (!rss_conf->rss_hf) 2130 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2131 } else { 2132 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2133 return -EINVAL; 2134 } 2135 2136 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2137 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2138 rss_conf, 2139 sizeof(*rss_conf)); 2140 2141 /* Update the default RSS VNIC(s) */ 2142 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2143 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2144 vnic->hash_mode = 2145 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2146 ETH_RSS_LEVEL(rss_conf->rss_hf)); 2147 2148 /* 2149 * If hashkey is not specified, use the previously configured 2150 * hashkey 2151 */ 2152 if (!rss_conf->rss_key) 2153 goto rss_config; 2154 2155 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2156 PMD_DRV_LOG(ERR, 2157 "Invalid hashkey length, should be %d bytes\n", 2158 HW_HASH_KEY_SIZE); 2159 return -EINVAL; 2160 } 2161 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2162 2163 rss_config: 2164 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2165 return rc; 2166 } 2167 2168 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2169 struct rte_eth_rss_conf *rss_conf) 2170 { 2171 struct bnxt *bp = eth_dev->data->dev_private; 2172 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2173 int len, rc; 2174 uint32_t hash_types; 2175 2176 rc = is_bnxt_in_error(bp); 2177 if (rc) 2178 return rc; 2179 2180 /* RSS configuration is the same for all VNICs */ 2181 if (vnic && vnic->rss_hash_key) { 2182 if (rss_conf->rss_key) { 2183 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2184 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2185 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2186 } 2187 2188 hash_types = vnic->hash_type; 2189 rss_conf->rss_hf = 0; 2190 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2191 rss_conf->rss_hf |= ETH_RSS_IPV4; 2192 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2193 } 2194 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2195 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2196 hash_types &= 2197 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2198 } 2199 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2200 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2201 hash_types &= 2202 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2203 } 2204 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2205 rss_conf->rss_hf |= ETH_RSS_IPV6; 2206 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2207 } 2208 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2209 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2210 hash_types &= 2211 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2212 } 2213 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2214 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2215 hash_types &= 2216 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2217 } 2218 2219 rss_conf->rss_hf |= 2220 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2221 2222 if (hash_types) { 2223 PMD_DRV_LOG(ERR, 2224 "Unknown RSS config from firmware (%08x), RSS disabled", 2225 vnic->hash_type); 2226 return -ENOTSUP; 2227 } 2228 } else { 2229 rss_conf->rss_hf = 0; 2230 } 2231 return 0; 2232 } 2233 2234 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2235 struct rte_eth_fc_conf *fc_conf) 2236 { 2237 struct bnxt *bp = dev->data->dev_private; 2238 struct rte_eth_link link_info; 2239 int rc; 2240 2241 rc = is_bnxt_in_error(bp); 2242 if (rc) 2243 return rc; 2244 2245 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2246 if (rc) 2247 return rc; 2248 2249 memset(fc_conf, 0, sizeof(*fc_conf)); 2250 if (bp->link_info->auto_pause) 2251 fc_conf->autoneg = 1; 2252 switch (bp->link_info->pause) { 2253 case 0: 2254 fc_conf->mode = RTE_FC_NONE; 2255 break; 2256 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2257 fc_conf->mode = RTE_FC_TX_PAUSE; 2258 break; 2259 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2260 fc_conf->mode = RTE_FC_RX_PAUSE; 2261 break; 2262 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2263 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2264 fc_conf->mode = RTE_FC_FULL; 2265 break; 2266 } 2267 return 0; 2268 } 2269 2270 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2271 struct rte_eth_fc_conf *fc_conf) 2272 { 2273 struct bnxt *bp = dev->data->dev_private; 2274 int rc; 2275 2276 rc = is_bnxt_in_error(bp); 2277 if (rc) 2278 return rc; 2279 2280 if (!BNXT_SINGLE_PF(bp)) { 2281 PMD_DRV_LOG(ERR, 2282 "Flow Control Settings cannot be modified on VF or on shared PF\n"); 2283 return -ENOTSUP; 2284 } 2285 2286 switch (fc_conf->mode) { 2287 case RTE_FC_NONE: 2288 bp->link_info->auto_pause = 0; 2289 bp->link_info->force_pause = 0; 2290 break; 2291 case RTE_FC_RX_PAUSE: 2292 if (fc_conf->autoneg) { 2293 bp->link_info->auto_pause = 2294 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2295 bp->link_info->force_pause = 0; 2296 } else { 2297 bp->link_info->auto_pause = 0; 2298 bp->link_info->force_pause = 2299 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2300 } 2301 break; 2302 case RTE_FC_TX_PAUSE: 2303 if (fc_conf->autoneg) { 2304 bp->link_info->auto_pause = 2305 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2306 bp->link_info->force_pause = 0; 2307 } else { 2308 bp->link_info->auto_pause = 0; 2309 bp->link_info->force_pause = 2310 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2311 } 2312 break; 2313 case RTE_FC_FULL: 2314 if (fc_conf->autoneg) { 2315 bp->link_info->auto_pause = 2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2317 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2318 bp->link_info->force_pause = 0; 2319 } else { 2320 bp->link_info->auto_pause = 0; 2321 bp->link_info->force_pause = 2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2323 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2324 } 2325 break; 2326 } 2327 return bnxt_set_hwrm_link_config(bp, true); 2328 } 2329 2330 /* Add UDP tunneling port */ 2331 static int 2332 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2333 struct rte_eth_udp_tunnel *udp_tunnel) 2334 { 2335 struct bnxt *bp = eth_dev->data->dev_private; 2336 uint16_t tunnel_type = 0; 2337 int rc = 0; 2338 2339 rc = is_bnxt_in_error(bp); 2340 if (rc) 2341 return rc; 2342 2343 switch (udp_tunnel->prot_type) { 2344 case RTE_TUNNEL_TYPE_VXLAN: 2345 if (bp->vxlan_port_cnt) { 2346 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2347 udp_tunnel->udp_port); 2348 if (bp->vxlan_port != udp_tunnel->udp_port) { 2349 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2350 return -ENOSPC; 2351 } 2352 bp->vxlan_port_cnt++; 2353 return 0; 2354 } 2355 tunnel_type = 2356 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2357 bp->vxlan_port_cnt++; 2358 break; 2359 case RTE_TUNNEL_TYPE_GENEVE: 2360 if (bp->geneve_port_cnt) { 2361 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2362 udp_tunnel->udp_port); 2363 if (bp->geneve_port != udp_tunnel->udp_port) { 2364 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2365 return -ENOSPC; 2366 } 2367 bp->geneve_port_cnt++; 2368 return 0; 2369 } 2370 tunnel_type = 2371 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2372 bp->geneve_port_cnt++; 2373 break; 2374 default: 2375 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2376 return -ENOTSUP; 2377 } 2378 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2379 tunnel_type); 2380 return rc; 2381 } 2382 2383 static int 2384 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2385 struct rte_eth_udp_tunnel *udp_tunnel) 2386 { 2387 struct bnxt *bp = eth_dev->data->dev_private; 2388 uint16_t tunnel_type = 0; 2389 uint16_t port = 0; 2390 int rc = 0; 2391 2392 rc = is_bnxt_in_error(bp); 2393 if (rc) 2394 return rc; 2395 2396 switch (udp_tunnel->prot_type) { 2397 case RTE_TUNNEL_TYPE_VXLAN: 2398 if (!bp->vxlan_port_cnt) { 2399 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2400 return -EINVAL; 2401 } 2402 if (bp->vxlan_port != udp_tunnel->udp_port) { 2403 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2404 udp_tunnel->udp_port, bp->vxlan_port); 2405 return -EINVAL; 2406 } 2407 if (--bp->vxlan_port_cnt) 2408 return 0; 2409 2410 tunnel_type = 2411 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2412 port = bp->vxlan_fw_dst_port_id; 2413 break; 2414 case RTE_TUNNEL_TYPE_GENEVE: 2415 if (!bp->geneve_port_cnt) { 2416 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2417 return -EINVAL; 2418 } 2419 if (bp->geneve_port != udp_tunnel->udp_port) { 2420 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2421 udp_tunnel->udp_port, bp->geneve_port); 2422 return -EINVAL; 2423 } 2424 if (--bp->geneve_port_cnt) 2425 return 0; 2426 2427 tunnel_type = 2428 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2429 port = bp->geneve_fw_dst_port_id; 2430 break; 2431 default: 2432 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2433 return -ENOTSUP; 2434 } 2435 2436 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2437 return rc; 2438 } 2439 2440 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2441 { 2442 struct bnxt_filter_info *filter; 2443 struct bnxt_vnic_info *vnic; 2444 int rc = 0; 2445 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2446 2447 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2448 filter = STAILQ_FIRST(&vnic->filter); 2449 while (filter) { 2450 /* Search for this matching MAC+VLAN filter */ 2451 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2452 /* Delete the filter */ 2453 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2454 if (rc) 2455 return rc; 2456 STAILQ_REMOVE(&vnic->filter, filter, 2457 bnxt_filter_info, next); 2458 bnxt_free_filter(bp, filter); 2459 PMD_DRV_LOG(INFO, 2460 "Deleted vlan filter for %d\n", 2461 vlan_id); 2462 return 0; 2463 } 2464 filter = STAILQ_NEXT(filter, next); 2465 } 2466 return -ENOENT; 2467 } 2468 2469 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2470 { 2471 struct bnxt_filter_info *filter; 2472 struct bnxt_vnic_info *vnic; 2473 int rc = 0; 2474 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2475 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2476 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2477 2478 /* Implementation notes on the use of VNIC in this command: 2479 * 2480 * By default, these filters belong to default vnic for the function. 2481 * Once these filters are set up, only destination VNIC can be modified. 2482 * If the destination VNIC is not specified in this command, 2483 * then the HWRM shall only create an l2 context id. 2484 */ 2485 2486 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2487 filter = STAILQ_FIRST(&vnic->filter); 2488 /* Check if the VLAN has already been added */ 2489 while (filter) { 2490 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2491 return -EEXIST; 2492 2493 filter = STAILQ_NEXT(filter, next); 2494 } 2495 2496 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2497 * command to create MAC+VLAN filter with the right flags, enables set. 2498 */ 2499 filter = bnxt_alloc_filter(bp); 2500 if (!filter) { 2501 PMD_DRV_LOG(ERR, 2502 "MAC/VLAN filter alloc failed\n"); 2503 return -ENOMEM; 2504 } 2505 /* MAC + VLAN ID filter */ 2506 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2507 * untagged packets are received 2508 * 2509 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2510 * packets and only the programmed vlan's packets are received 2511 */ 2512 filter->l2_ivlan = vlan_id; 2513 filter->l2_ivlan_mask = 0x0FFF; 2514 filter->enables |= en; 2515 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2516 2517 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2518 if (rc) { 2519 /* Free the newly allocated filter as we were 2520 * not able to create the filter in hardware. 2521 */ 2522 bnxt_free_filter(bp, filter); 2523 return rc; 2524 } 2525 2526 filter->mac_index = 0; 2527 /* Add this new filter to the list */ 2528 if (vlan_id == 0) 2529 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2530 else 2531 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2532 2533 PMD_DRV_LOG(INFO, 2534 "Added Vlan filter for %d\n", vlan_id); 2535 return rc; 2536 } 2537 2538 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2539 uint16_t vlan_id, int on) 2540 { 2541 struct bnxt *bp = eth_dev->data->dev_private; 2542 int rc; 2543 2544 rc = is_bnxt_in_error(bp); 2545 if (rc) 2546 return rc; 2547 2548 if (!eth_dev->data->dev_started) { 2549 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2550 return -EINVAL; 2551 } 2552 2553 /* These operations apply to ALL existing MAC/VLAN filters */ 2554 if (on) 2555 return bnxt_add_vlan_filter(bp, vlan_id); 2556 else 2557 return bnxt_del_vlan_filter(bp, vlan_id); 2558 } 2559 2560 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2561 struct bnxt_vnic_info *vnic) 2562 { 2563 struct bnxt_filter_info *filter; 2564 int rc; 2565 2566 filter = STAILQ_FIRST(&vnic->filter); 2567 while (filter) { 2568 if (filter->mac_index == 0 && 2569 !memcmp(filter->l2_addr, bp->mac_addr, 2570 RTE_ETHER_ADDR_LEN)) { 2571 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2572 if (!rc) { 2573 STAILQ_REMOVE(&vnic->filter, filter, 2574 bnxt_filter_info, next); 2575 bnxt_free_filter(bp, filter); 2576 } 2577 return rc; 2578 } 2579 filter = STAILQ_NEXT(filter, next); 2580 } 2581 return 0; 2582 } 2583 2584 static int 2585 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2586 { 2587 struct bnxt_vnic_info *vnic; 2588 unsigned int i; 2589 int rc; 2590 2591 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2592 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2593 /* Remove any VLAN filters programmed */ 2594 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2595 bnxt_del_vlan_filter(bp, i); 2596 2597 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2598 if (rc) 2599 return rc; 2600 } else { 2601 /* Default filter will allow packets that match the 2602 * dest mac. So, it has to be deleted, otherwise, we 2603 * will endup receiving vlan packets for which the 2604 * filter is not programmed, when hw-vlan-filter 2605 * configuration is ON 2606 */ 2607 bnxt_del_dflt_mac_filter(bp, vnic); 2608 /* This filter will allow only untagged packets */ 2609 bnxt_add_vlan_filter(bp, 0); 2610 } 2611 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2612 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2613 2614 return 0; 2615 } 2616 2617 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2618 { 2619 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2620 unsigned int i; 2621 int rc; 2622 2623 /* Destroy vnic filters and vnic */ 2624 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2625 DEV_RX_OFFLOAD_VLAN_FILTER) { 2626 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2627 bnxt_del_vlan_filter(bp, i); 2628 } 2629 bnxt_del_dflt_mac_filter(bp, vnic); 2630 2631 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2632 if (rc) 2633 return rc; 2634 2635 rc = bnxt_hwrm_vnic_free(bp, vnic); 2636 if (rc) 2637 return rc; 2638 2639 rte_free(vnic->fw_grp_ids); 2640 vnic->fw_grp_ids = NULL; 2641 2642 vnic->rx_queue_cnt = 0; 2643 2644 return 0; 2645 } 2646 2647 static int 2648 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2649 { 2650 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2651 int rc; 2652 2653 /* Destroy, recreate and reconfigure the default vnic */ 2654 rc = bnxt_free_one_vnic(bp, 0); 2655 if (rc) 2656 return rc; 2657 2658 /* default vnic 0 */ 2659 rc = bnxt_setup_one_vnic(bp, 0); 2660 if (rc) 2661 return rc; 2662 2663 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2664 DEV_RX_OFFLOAD_VLAN_FILTER) { 2665 rc = bnxt_add_vlan_filter(bp, 0); 2666 if (rc) 2667 return rc; 2668 rc = bnxt_restore_vlan_filters(bp); 2669 if (rc) 2670 return rc; 2671 } else { 2672 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2673 if (rc) 2674 return rc; 2675 } 2676 2677 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2678 if (rc) 2679 return rc; 2680 2681 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2682 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2683 2684 return rc; 2685 } 2686 2687 static int 2688 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2689 { 2690 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2691 struct bnxt *bp = dev->data->dev_private; 2692 int rc; 2693 2694 rc = is_bnxt_in_error(bp); 2695 if (rc) 2696 return rc; 2697 2698 /* Filter settings will get applied when port is started */ 2699 if (!dev->data->dev_started) 2700 return 0; 2701 2702 if (mask & ETH_VLAN_FILTER_MASK) { 2703 /* Enable or disable VLAN filtering */ 2704 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2705 if (rc) 2706 return rc; 2707 } 2708 2709 if (mask & ETH_VLAN_STRIP_MASK) { 2710 /* Enable or disable VLAN stripping */ 2711 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2712 if (rc) 2713 return rc; 2714 } 2715 2716 if (mask & ETH_VLAN_EXTEND_MASK) { 2717 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2718 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2719 else 2720 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2721 } 2722 2723 return 0; 2724 } 2725 2726 static int 2727 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2728 uint16_t tpid) 2729 { 2730 struct bnxt *bp = dev->data->dev_private; 2731 int qinq = dev->data->dev_conf.rxmode.offloads & 2732 DEV_RX_OFFLOAD_VLAN_EXTEND; 2733 2734 if (vlan_type != ETH_VLAN_TYPE_INNER && 2735 vlan_type != ETH_VLAN_TYPE_OUTER) { 2736 PMD_DRV_LOG(ERR, 2737 "Unsupported vlan type."); 2738 return -EINVAL; 2739 } 2740 if (!qinq) { 2741 PMD_DRV_LOG(ERR, 2742 "QinQ not enabled. Needs to be ON as we can " 2743 "accelerate only outer vlan\n"); 2744 return -EINVAL; 2745 } 2746 2747 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2748 switch (tpid) { 2749 case RTE_ETHER_TYPE_QINQ: 2750 bp->outer_tpid_bd = 2751 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2752 break; 2753 case RTE_ETHER_TYPE_VLAN: 2754 bp->outer_tpid_bd = 2755 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2756 break; 2757 case RTE_ETHER_TYPE_QINQ1: 2758 bp->outer_tpid_bd = 2759 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2760 break; 2761 case RTE_ETHER_TYPE_QINQ2: 2762 bp->outer_tpid_bd = 2763 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2764 break; 2765 case RTE_ETHER_TYPE_QINQ3: 2766 bp->outer_tpid_bd = 2767 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2768 break; 2769 default: 2770 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2771 return -EINVAL; 2772 } 2773 bp->outer_tpid_bd |= tpid; 2774 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2775 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2776 PMD_DRV_LOG(ERR, 2777 "Can accelerate only outer vlan in QinQ\n"); 2778 return -EINVAL; 2779 } 2780 2781 return 0; 2782 } 2783 2784 static int 2785 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2786 struct rte_ether_addr *addr) 2787 { 2788 struct bnxt *bp = dev->data->dev_private; 2789 /* Default Filter is tied to VNIC 0 */ 2790 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2791 int rc; 2792 2793 rc = is_bnxt_in_error(bp); 2794 if (rc) 2795 return rc; 2796 2797 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2798 return -EPERM; 2799 2800 if (rte_is_zero_ether_addr(addr)) 2801 return -EINVAL; 2802 2803 /* Filter settings will get applied when port is started */ 2804 if (!dev->data->dev_started) 2805 return 0; 2806 2807 /* Check if the requested MAC is already added */ 2808 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2809 return 0; 2810 2811 /* Destroy filter and re-create it */ 2812 bnxt_del_dflt_mac_filter(bp, vnic); 2813 2814 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2815 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2816 /* This filter will allow only untagged packets */ 2817 rc = bnxt_add_vlan_filter(bp, 0); 2818 } else { 2819 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2820 } 2821 2822 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2823 return rc; 2824 } 2825 2826 static int 2827 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2828 struct rte_ether_addr *mc_addr_set, 2829 uint32_t nb_mc_addr) 2830 { 2831 struct bnxt *bp = eth_dev->data->dev_private; 2832 char *mc_addr_list = (char *)mc_addr_set; 2833 struct bnxt_vnic_info *vnic; 2834 uint32_t off = 0, i = 0; 2835 int rc; 2836 2837 rc = is_bnxt_in_error(bp); 2838 if (rc) 2839 return rc; 2840 2841 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2842 2843 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2844 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2845 goto allmulti; 2846 } 2847 2848 /* TODO Check for Duplicate mcast addresses */ 2849 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2850 for (i = 0; i < nb_mc_addr; i++) { 2851 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2852 RTE_ETHER_ADDR_LEN); 2853 off += RTE_ETHER_ADDR_LEN; 2854 } 2855 2856 vnic->mc_addr_cnt = i; 2857 if (vnic->mc_addr_cnt) 2858 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2859 else 2860 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2861 2862 allmulti: 2863 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2864 } 2865 2866 static int 2867 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2868 { 2869 struct bnxt *bp = dev->data->dev_private; 2870 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2871 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2872 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2873 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2874 int ret; 2875 2876 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2877 fw_major, fw_minor, fw_updt, fw_rsvd); 2878 if (ret < 0) 2879 return -EINVAL; 2880 2881 ret += 1; /* add the size of '\0' */ 2882 if (fw_size < (size_t)ret) 2883 return ret; 2884 else 2885 return 0; 2886 } 2887 2888 static void 2889 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2890 struct rte_eth_rxq_info *qinfo) 2891 { 2892 struct bnxt *bp = dev->data->dev_private; 2893 struct bnxt_rx_queue *rxq; 2894 2895 if (is_bnxt_in_error(bp)) 2896 return; 2897 2898 rxq = dev->data->rx_queues[queue_id]; 2899 2900 qinfo->mp = rxq->mb_pool; 2901 qinfo->scattered_rx = dev->data->scattered_rx; 2902 qinfo->nb_desc = rxq->nb_rx_desc; 2903 2904 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2905 qinfo->conf.rx_drop_en = rxq->drop_en; 2906 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2907 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2908 } 2909 2910 static void 2911 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2912 struct rte_eth_txq_info *qinfo) 2913 { 2914 struct bnxt *bp = dev->data->dev_private; 2915 struct bnxt_tx_queue *txq; 2916 2917 if (is_bnxt_in_error(bp)) 2918 return; 2919 2920 txq = dev->data->tx_queues[queue_id]; 2921 2922 qinfo->nb_desc = txq->nb_tx_desc; 2923 2924 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2925 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2926 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2927 2928 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2929 qinfo->conf.tx_rs_thresh = 0; 2930 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2931 qinfo->conf.offloads = txq->offloads; 2932 } 2933 2934 static const struct { 2935 eth_rx_burst_t pkt_burst; 2936 const char *info; 2937 } bnxt_rx_burst_info[] = { 2938 {bnxt_recv_pkts, "Scalar"}, 2939 #if defined(RTE_ARCH_X86) 2940 {bnxt_recv_pkts_vec, "Vector SSE"}, 2941 #endif 2942 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2943 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"}, 2944 #endif 2945 #if defined(RTE_ARCH_ARM64) 2946 {bnxt_recv_pkts_vec, "Vector Neon"}, 2947 #endif 2948 }; 2949 2950 static int 2951 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2952 struct rte_eth_burst_mode *mode) 2953 { 2954 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2955 size_t i; 2956 2957 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2958 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2959 snprintf(mode->info, sizeof(mode->info), "%s", 2960 bnxt_rx_burst_info[i].info); 2961 return 0; 2962 } 2963 } 2964 2965 return -EINVAL; 2966 } 2967 2968 static const struct { 2969 eth_tx_burst_t pkt_burst; 2970 const char *info; 2971 } bnxt_tx_burst_info[] = { 2972 {bnxt_xmit_pkts, "Scalar"}, 2973 #if defined(RTE_ARCH_X86) 2974 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2975 #endif 2976 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2977 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"}, 2978 #endif 2979 #if defined(RTE_ARCH_ARM64) 2980 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2981 #endif 2982 }; 2983 2984 static int 2985 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2986 struct rte_eth_burst_mode *mode) 2987 { 2988 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2989 size_t i; 2990 2991 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2992 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2993 snprintf(mode->info, sizeof(mode->info), "%s", 2994 bnxt_tx_burst_info[i].info); 2995 return 0; 2996 } 2997 } 2998 2999 return -EINVAL; 3000 } 3001 3002 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 3003 { 3004 struct bnxt *bp = eth_dev->data->dev_private; 3005 uint32_t new_pkt_size; 3006 uint32_t rc = 0; 3007 uint32_t i; 3008 3009 rc = is_bnxt_in_error(bp); 3010 if (rc) 3011 return rc; 3012 3013 /* Exit if receive queues are not configured yet */ 3014 if (!eth_dev->data->nb_rx_queues) 3015 return rc; 3016 3017 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 3018 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 3019 3020 /* 3021 * Disallow any MTU change that would require scattered receive support 3022 * if it is not already enabled. 3023 */ 3024 if (eth_dev->data->dev_started && 3025 !eth_dev->data->scattered_rx && 3026 (new_pkt_size > 3027 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3028 PMD_DRV_LOG(ERR, 3029 "MTU change would require scattered rx support. "); 3030 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 3031 return -EINVAL; 3032 } 3033 3034 if (new_mtu > RTE_ETHER_MTU) { 3035 bp->flags |= BNXT_FLAG_JUMBO; 3036 bp->eth_dev->data->dev_conf.rxmode.offloads |= 3037 DEV_RX_OFFLOAD_JUMBO_FRAME; 3038 } else { 3039 bp->eth_dev->data->dev_conf.rxmode.offloads &= 3040 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3041 bp->flags &= ~BNXT_FLAG_JUMBO; 3042 } 3043 3044 /* Is there a change in mtu setting? */ 3045 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 3046 return rc; 3047 3048 for (i = 0; i < bp->nr_vnics; i++) { 3049 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3050 uint16_t size = 0; 3051 3052 vnic->mru = BNXT_VNIC_MRU(new_mtu); 3053 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 3054 if (rc) 3055 break; 3056 3057 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 3058 size -= RTE_PKTMBUF_HEADROOM; 3059 3060 if (size < new_mtu) { 3061 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 3062 if (rc) 3063 return rc; 3064 } 3065 } 3066 3067 if (!rc) 3068 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 3069 3070 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 3071 3072 return rc; 3073 } 3074 3075 static int 3076 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 3077 { 3078 struct bnxt *bp = dev->data->dev_private; 3079 uint16_t vlan = bp->vlan; 3080 int rc; 3081 3082 rc = is_bnxt_in_error(bp); 3083 if (rc) 3084 return rc; 3085 3086 if (!BNXT_SINGLE_PF(bp)) { 3087 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n"); 3088 return -ENOTSUP; 3089 } 3090 bp->vlan = on ? pvid : 0; 3091 3092 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 3093 if (rc) 3094 bp->vlan = vlan; 3095 return rc; 3096 } 3097 3098 static int 3099 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3100 { 3101 struct bnxt *bp = dev->data->dev_private; 3102 int rc; 3103 3104 rc = is_bnxt_in_error(bp); 3105 if (rc) 3106 return rc; 3107 3108 return bnxt_hwrm_port_led_cfg(bp, true); 3109 } 3110 3111 static int 3112 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3113 { 3114 struct bnxt *bp = dev->data->dev_private; 3115 int rc; 3116 3117 rc = is_bnxt_in_error(bp); 3118 if (rc) 3119 return rc; 3120 3121 return bnxt_hwrm_port_led_cfg(bp, false); 3122 } 3123 3124 static uint32_t 3125 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 3126 { 3127 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 3128 struct bnxt_cp_ring_info *cpr; 3129 uint32_t desc = 0, raw_cons; 3130 struct bnxt_rx_queue *rxq; 3131 struct rx_pkt_cmpl *rxcmp; 3132 int rc; 3133 3134 rc = is_bnxt_in_error(bp); 3135 if (rc) 3136 return rc; 3137 3138 rxq = dev->data->rx_queues[rx_queue_id]; 3139 cpr = rxq->cp_ring; 3140 raw_cons = cpr->cp_raw_cons; 3141 3142 while (1) { 3143 uint32_t agg_cnt, cons, cmpl_type; 3144 3145 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3146 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3147 3148 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3149 break; 3150 3151 cmpl_type = CMP_TYPE(rxcmp); 3152 3153 switch (cmpl_type) { 3154 case CMPL_BASE_TYPE_RX_L2: 3155 case CMPL_BASE_TYPE_RX_L2_V2: 3156 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3157 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3158 desc++; 3159 break; 3160 3161 case CMPL_BASE_TYPE_RX_TPA_END: 3162 if (BNXT_CHIP_P5(rxq->bp)) { 3163 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3164 3165 p5_tpa_end = (void *)rxcmp; 3166 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3167 } else { 3168 struct rx_tpa_end_cmpl *tpa_end; 3169 3170 tpa_end = (void *)rxcmp; 3171 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3172 } 3173 3174 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3175 desc++; 3176 break; 3177 3178 default: 3179 raw_cons += CMP_LEN(cmpl_type); 3180 } 3181 } 3182 3183 return desc; 3184 } 3185 3186 static int 3187 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3188 { 3189 struct bnxt_rx_queue *rxq = rx_queue; 3190 struct bnxt_cp_ring_info *cpr; 3191 struct bnxt_rx_ring_info *rxr; 3192 uint32_t desc, raw_cons; 3193 struct bnxt *bp = rxq->bp; 3194 struct rx_pkt_cmpl *rxcmp; 3195 int rc; 3196 3197 rc = is_bnxt_in_error(bp); 3198 if (rc) 3199 return rc; 3200 3201 if (offset >= rxq->nb_rx_desc) 3202 return -EINVAL; 3203 3204 rxr = rxq->rx_ring; 3205 cpr = rxq->cp_ring; 3206 3207 /* 3208 * For the vector receive case, the completion at the requested 3209 * offset can be indexed directly. 3210 */ 3211 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3212 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3213 struct rx_pkt_cmpl *rxcmp; 3214 uint32_t cons; 3215 3216 /* Check status of completion descriptor. */ 3217 raw_cons = cpr->cp_raw_cons + 3218 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3219 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3220 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3221 3222 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3223 return RTE_ETH_RX_DESC_DONE; 3224 3225 /* Check whether rx desc has an mbuf attached. */ 3226 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3227 if (cons >= rxq->rxrearm_start && 3228 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3229 return RTE_ETH_RX_DESC_UNAVAIL; 3230 } 3231 3232 return RTE_ETH_RX_DESC_AVAIL; 3233 } 3234 #endif 3235 3236 /* 3237 * For the non-vector receive case, scan the completion ring to 3238 * locate the completion descriptor for the requested offset. 3239 */ 3240 raw_cons = cpr->cp_raw_cons; 3241 desc = 0; 3242 while (1) { 3243 uint32_t agg_cnt, cons, cmpl_type; 3244 3245 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3246 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3247 3248 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3249 break; 3250 3251 cmpl_type = CMP_TYPE(rxcmp); 3252 3253 switch (cmpl_type) { 3254 case CMPL_BASE_TYPE_RX_L2: 3255 case CMPL_BASE_TYPE_RX_L2_V2: 3256 if (desc == offset) { 3257 cons = rxcmp->opaque; 3258 if (rxr->rx_buf_ring[cons]) 3259 return RTE_ETH_RX_DESC_DONE; 3260 else 3261 return RTE_ETH_RX_DESC_UNAVAIL; 3262 } 3263 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3264 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3265 desc++; 3266 break; 3267 3268 case CMPL_BASE_TYPE_RX_TPA_END: 3269 if (desc == offset) 3270 return RTE_ETH_RX_DESC_DONE; 3271 3272 if (BNXT_CHIP_P5(rxq->bp)) { 3273 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3274 3275 p5_tpa_end = (void *)rxcmp; 3276 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3277 } else { 3278 struct rx_tpa_end_cmpl *tpa_end; 3279 3280 tpa_end = (void *)rxcmp; 3281 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3282 } 3283 3284 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3285 desc++; 3286 break; 3287 3288 default: 3289 raw_cons += CMP_LEN(cmpl_type); 3290 } 3291 } 3292 3293 return RTE_ETH_RX_DESC_AVAIL; 3294 } 3295 3296 static int 3297 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3298 { 3299 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3300 struct bnxt_cp_ring_info *cpr = txq->cp_ring; 3301 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0; 3302 struct bnxt_ring *cp_ring_struct; 3303 struct cmpl_base *cp_desc_ring; 3304 int rc; 3305 3306 rc = is_bnxt_in_error(txq->bp); 3307 if (rc) 3308 return rc; 3309 3310 if (offset >= txq->nb_tx_desc) 3311 return -EINVAL; 3312 3313 /* Return "desc done" if descriptor is available for use. */ 3314 if (bnxt_tx_bds_in_hw(txq) <= offset) 3315 return RTE_ETH_TX_DESC_DONE; 3316 3317 raw_cons = cpr->cp_raw_cons; 3318 cp_desc_ring = cpr->cp_desc_ring; 3319 cp_ring_struct = cpr->cp_ring_struct; 3320 ring_mask = cpr->cp_ring_struct->ring_mask; 3321 3322 /* Check to see if hw has posted a completion for the descriptor. */ 3323 while (1) { 3324 struct tx_cmpl *txcmp; 3325 uint32_t cons; 3326 3327 cons = RING_CMPL(ring_mask, raw_cons); 3328 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons]; 3329 3330 if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct)) 3331 break; 3332 3333 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) 3334 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque); 3335 3336 if (nb_tx_pkts > offset) 3337 return RTE_ETH_TX_DESC_DONE; 3338 3339 raw_cons = NEXT_RAW_CMP(raw_cons); 3340 } 3341 3342 /* Descriptor is pending transmit, not yet completed by hardware. */ 3343 return RTE_ETH_TX_DESC_FULL; 3344 } 3345 3346 int 3347 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3348 const struct rte_flow_ops **ops) 3349 { 3350 struct bnxt *bp = dev->data->dev_private; 3351 int ret = 0; 3352 3353 if (!bp) 3354 return -EIO; 3355 3356 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3357 struct bnxt_representor *vfr = dev->data->dev_private; 3358 bp = vfr->parent_dev->data->dev_private; 3359 /* parent is deleted while children are still valid */ 3360 if (!bp) { 3361 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3362 dev->data->port_id); 3363 return -EIO; 3364 } 3365 } 3366 3367 ret = is_bnxt_in_error(bp); 3368 if (ret) 3369 return ret; 3370 3371 /* PMD supports thread-safe flow operations. rte_flow API 3372 * functions can avoid mutex for multi-thread safety. 3373 */ 3374 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3375 3376 if (BNXT_TRUFLOW_EN(bp)) 3377 *ops = &bnxt_ulp_rte_flow_ops; 3378 else 3379 *ops = &bnxt_flow_ops; 3380 3381 return ret; 3382 } 3383 3384 static const uint32_t * 3385 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3386 { 3387 static const uint32_t ptypes[] = { 3388 RTE_PTYPE_L2_ETHER_VLAN, 3389 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3390 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3391 RTE_PTYPE_L4_ICMP, 3392 RTE_PTYPE_L4_TCP, 3393 RTE_PTYPE_L4_UDP, 3394 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3395 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3396 RTE_PTYPE_INNER_L4_ICMP, 3397 RTE_PTYPE_INNER_L4_TCP, 3398 RTE_PTYPE_INNER_L4_UDP, 3399 RTE_PTYPE_UNKNOWN 3400 }; 3401 3402 if (!dev->rx_pkt_burst) 3403 return NULL; 3404 3405 return ptypes; 3406 } 3407 3408 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3409 int reg_win) 3410 { 3411 uint32_t reg_base = *reg_arr & 0xfffff000; 3412 uint32_t win_off; 3413 int i; 3414 3415 for (i = 0; i < count; i++) { 3416 if ((reg_arr[i] & 0xfffff000) != reg_base) 3417 return -ERANGE; 3418 } 3419 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3420 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3421 return 0; 3422 } 3423 3424 static int bnxt_map_ptp_regs(struct bnxt *bp) 3425 { 3426 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3427 uint32_t *reg_arr; 3428 int rc, i; 3429 3430 reg_arr = ptp->rx_regs; 3431 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3432 if (rc) 3433 return rc; 3434 3435 reg_arr = ptp->tx_regs; 3436 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3437 if (rc) 3438 return rc; 3439 3440 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3441 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3442 3443 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3444 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3445 3446 return 0; 3447 } 3448 3449 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3450 { 3451 rte_write32(0, (uint8_t *)bp->bar0 + 3452 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3453 rte_write32(0, (uint8_t *)bp->bar0 + 3454 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3455 } 3456 3457 static uint64_t bnxt_cc_read(struct bnxt *bp) 3458 { 3459 uint64_t ns; 3460 3461 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3462 BNXT_GRCPF_REG_SYNC_TIME)); 3463 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3464 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3465 return ns; 3466 } 3467 3468 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3469 { 3470 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3471 uint32_t fifo; 3472 3473 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3474 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3475 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3476 return -EAGAIN; 3477 3478 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3479 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3480 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3481 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3482 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3483 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3484 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3485 3486 return 0; 3487 } 3488 3489 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts) 3490 { 3491 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3492 struct bnxt_pf_info *pf = bp->pf; 3493 uint16_t port_id; 3494 int i = 0; 3495 uint32_t fifo; 3496 3497 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5)) 3498 return -EINVAL; 3499 3500 port_id = pf->port_id; 3501 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3502 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3503 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) { 3504 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3505 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3506 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3507 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3508 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3509 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3510 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3511 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3512 i++; 3513 } 3514 3515 if (i >= BNXT_PTP_RX_PND_CNT) 3516 return -EBUSY; 3517 3518 return 0; 3519 } 3520 3521 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3522 { 3523 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3524 struct bnxt_pf_info *pf = bp->pf; 3525 uint16_t port_id; 3526 uint32_t fifo; 3527 3528 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3529 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3530 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3531 return -EAGAIN; 3532 3533 port_id = pf->port_id; 3534 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3535 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3536 3537 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3538 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3539 if (fifo & BNXT_PTP_RX_FIFO_PENDING) 3540 return bnxt_clr_rx_ts(bp, ts); 3541 3542 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3543 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3544 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3545 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3546 3547 return 0; 3548 } 3549 3550 static int 3551 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3552 { 3553 uint64_t ns; 3554 struct bnxt *bp = dev->data->dev_private; 3555 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3556 3557 if (!ptp) 3558 return -ENOTSUP; 3559 3560 ns = rte_timespec_to_ns(ts); 3561 /* Set the timecounters to a new value. */ 3562 ptp->tc.nsec = ns; 3563 ptp->tx_tstamp_tc.nsec = ns; 3564 ptp->rx_tstamp_tc.nsec = ns; 3565 3566 return 0; 3567 } 3568 3569 static int 3570 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3571 { 3572 struct bnxt *bp = dev->data->dev_private; 3573 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3574 uint64_t ns, systime_cycles = 0; 3575 int rc = 0; 3576 3577 if (!ptp) 3578 return -ENOTSUP; 3579 3580 if (BNXT_CHIP_P5(bp)) 3581 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3582 &systime_cycles); 3583 else 3584 systime_cycles = bnxt_cc_read(bp); 3585 3586 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3587 *ts = rte_ns_to_timespec(ns); 3588 3589 return rc; 3590 } 3591 static int 3592 bnxt_timesync_enable(struct rte_eth_dev *dev) 3593 { 3594 struct bnxt *bp = dev->data->dev_private; 3595 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3596 uint32_t shift = 0; 3597 int rc; 3598 3599 if (!ptp) 3600 return -ENOTSUP; 3601 3602 ptp->rx_filter = 1; 3603 ptp->tx_tstamp_en = 1; 3604 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3605 3606 rc = bnxt_hwrm_ptp_cfg(bp); 3607 if (rc) 3608 return rc; 3609 3610 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3611 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3612 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3613 3614 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3615 ptp->tc.cc_shift = shift; 3616 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3617 3618 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3619 ptp->rx_tstamp_tc.cc_shift = shift; 3620 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3621 3622 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3623 ptp->tx_tstamp_tc.cc_shift = shift; 3624 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3625 3626 if (!BNXT_CHIP_P5(bp)) 3627 bnxt_map_ptp_regs(bp); 3628 else 3629 rc = bnxt_ptp_start(bp); 3630 3631 return rc; 3632 } 3633 3634 static int 3635 bnxt_timesync_disable(struct rte_eth_dev *dev) 3636 { 3637 struct bnxt *bp = dev->data->dev_private; 3638 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3639 3640 if (!ptp) 3641 return -ENOTSUP; 3642 3643 ptp->rx_filter = 0; 3644 ptp->tx_tstamp_en = 0; 3645 ptp->rxctl = 0; 3646 3647 bnxt_hwrm_ptp_cfg(bp); 3648 3649 if (!BNXT_CHIP_P5(bp)) 3650 bnxt_unmap_ptp_regs(bp); 3651 else 3652 bnxt_ptp_stop(bp); 3653 3654 return 0; 3655 } 3656 3657 static int 3658 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3659 struct timespec *timestamp, 3660 uint32_t flags __rte_unused) 3661 { 3662 struct bnxt *bp = dev->data->dev_private; 3663 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3664 uint64_t rx_tstamp_cycles = 0; 3665 uint64_t ns; 3666 3667 if (!ptp) 3668 return -ENOTSUP; 3669 3670 if (BNXT_CHIP_P5(bp)) 3671 rx_tstamp_cycles = ptp->rx_timestamp; 3672 else 3673 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3674 3675 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3676 *timestamp = rte_ns_to_timespec(ns); 3677 return 0; 3678 } 3679 3680 static int 3681 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3682 struct timespec *timestamp) 3683 { 3684 struct bnxt *bp = dev->data->dev_private; 3685 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3686 uint64_t tx_tstamp_cycles = 0; 3687 uint64_t ns; 3688 int rc = 0; 3689 3690 if (!ptp) 3691 return -ENOTSUP; 3692 3693 if (BNXT_CHIP_P5(bp)) 3694 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3695 &tx_tstamp_cycles); 3696 else 3697 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3698 3699 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3700 *timestamp = rte_ns_to_timespec(ns); 3701 3702 return rc; 3703 } 3704 3705 static int 3706 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3707 { 3708 struct bnxt *bp = dev->data->dev_private; 3709 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3710 3711 if (!ptp) 3712 return -ENOTSUP; 3713 3714 ptp->tc.nsec += delta; 3715 ptp->tx_tstamp_tc.nsec += delta; 3716 ptp->rx_tstamp_tc.nsec += delta; 3717 3718 return 0; 3719 } 3720 3721 static int 3722 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3723 { 3724 struct bnxt *bp = dev->data->dev_private; 3725 int rc; 3726 uint32_t dir_entries; 3727 uint32_t entry_length; 3728 3729 rc = is_bnxt_in_error(bp); 3730 if (rc) 3731 return rc; 3732 3733 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3734 bp->pdev->addr.domain, bp->pdev->addr.bus, 3735 bp->pdev->addr.devid, bp->pdev->addr.function); 3736 3737 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3738 if (rc != 0) 3739 return rc; 3740 3741 return dir_entries * entry_length; 3742 } 3743 3744 static int 3745 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3746 struct rte_dev_eeprom_info *in_eeprom) 3747 { 3748 struct bnxt *bp = dev->data->dev_private; 3749 uint32_t index; 3750 uint32_t offset; 3751 int rc; 3752 3753 rc = is_bnxt_in_error(bp); 3754 if (rc) 3755 return rc; 3756 3757 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3758 bp->pdev->addr.domain, bp->pdev->addr.bus, 3759 bp->pdev->addr.devid, bp->pdev->addr.function, 3760 in_eeprom->offset, in_eeprom->length); 3761 3762 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3763 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3764 in_eeprom->data); 3765 3766 index = in_eeprom->offset >> 24; 3767 offset = in_eeprom->offset & 0xffffff; 3768 3769 if (index != 0) 3770 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3771 in_eeprom->length, in_eeprom->data); 3772 3773 return 0; 3774 } 3775 3776 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3777 { 3778 switch (dir_type) { 3779 case BNX_DIR_TYPE_CHIMP_PATCH: 3780 case BNX_DIR_TYPE_BOOTCODE: 3781 case BNX_DIR_TYPE_BOOTCODE_2: 3782 case BNX_DIR_TYPE_APE_FW: 3783 case BNX_DIR_TYPE_APE_PATCH: 3784 case BNX_DIR_TYPE_KONG_FW: 3785 case BNX_DIR_TYPE_KONG_PATCH: 3786 case BNX_DIR_TYPE_BONO_FW: 3787 case BNX_DIR_TYPE_BONO_PATCH: 3788 /* FALLTHROUGH */ 3789 return true; 3790 } 3791 3792 return false; 3793 } 3794 3795 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3796 { 3797 switch (dir_type) { 3798 case BNX_DIR_TYPE_AVS: 3799 case BNX_DIR_TYPE_EXP_ROM_MBA: 3800 case BNX_DIR_TYPE_PCIE: 3801 case BNX_DIR_TYPE_TSCF_UCODE: 3802 case BNX_DIR_TYPE_EXT_PHY: 3803 case BNX_DIR_TYPE_CCM: 3804 case BNX_DIR_TYPE_ISCSI_BOOT: 3805 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3806 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3807 /* FALLTHROUGH */ 3808 return true; 3809 } 3810 3811 return false; 3812 } 3813 3814 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3815 { 3816 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3817 bnxt_dir_type_is_other_exec_format(dir_type); 3818 } 3819 3820 static int 3821 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3822 struct rte_dev_eeprom_info *in_eeprom) 3823 { 3824 struct bnxt *bp = dev->data->dev_private; 3825 uint8_t index, dir_op; 3826 uint16_t type, ext, ordinal, attr; 3827 int rc; 3828 3829 rc = is_bnxt_in_error(bp); 3830 if (rc) 3831 return rc; 3832 3833 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3834 bp->pdev->addr.domain, bp->pdev->addr.bus, 3835 bp->pdev->addr.devid, bp->pdev->addr.function, 3836 in_eeprom->offset, in_eeprom->length); 3837 3838 if (!BNXT_PF(bp)) { 3839 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3840 return -EINVAL; 3841 } 3842 3843 type = in_eeprom->magic >> 16; 3844 3845 if (type == 0xffff) { /* special value for directory operations */ 3846 index = in_eeprom->magic & 0xff; 3847 dir_op = in_eeprom->magic >> 8; 3848 if (index == 0) 3849 return -EINVAL; 3850 switch (dir_op) { 3851 case 0x0e: /* erase */ 3852 if (in_eeprom->offset != ~in_eeprom->magic) 3853 return -EINVAL; 3854 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3855 default: 3856 return -EINVAL; 3857 } 3858 } 3859 3860 /* Create or re-write an NVM item: */ 3861 if (bnxt_dir_type_is_executable(type) == true) 3862 return -EOPNOTSUPP; 3863 ext = in_eeprom->magic & 0xffff; 3864 ordinal = in_eeprom->offset >> 16; 3865 attr = in_eeprom->offset & 0xffff; 3866 3867 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3868 in_eeprom->data, in_eeprom->length); 3869 } 3870 3871 static int bnxt_get_module_info(struct rte_eth_dev *dev, 3872 struct rte_eth_dev_module_info *modinfo) 3873 { 3874 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3875 struct bnxt *bp = dev->data->dev_private; 3876 int rc; 3877 3878 /* No point in going further if phy status indicates 3879 * module is not inserted or if it is powered down or 3880 * if it is of type 10GBase-T 3881 */ 3882 if (bp->link_info->module_status > 3883 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) { 3884 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n", 3885 dev->data->port_id); 3886 return -ENOTSUP; 3887 } 3888 3889 /* This feature is not supported in older firmware versions */ 3890 if (bp->hwrm_spec_code < 0x10202) { 3891 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n", 3892 dev->data->port_id); 3893 return -ENOTSUP; 3894 } 3895 3896 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3897 SFF_DIAG_SUPPORT_OFFSET + 1, 3898 module_info); 3899 3900 if (rc) 3901 return rc; 3902 3903 switch (module_info[0]) { 3904 case SFF_MODULE_ID_SFP: 3905 modinfo->type = RTE_ETH_MODULE_SFF_8472; 3906 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 3907 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0) 3908 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3909 break; 3910 case SFF_MODULE_ID_QSFP: 3911 case SFF_MODULE_ID_QSFP_PLUS: 3912 modinfo->type = RTE_ETH_MODULE_SFF_8436; 3913 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3914 break; 3915 case SFF_MODULE_ID_QSFP28: 3916 modinfo->type = RTE_ETH_MODULE_SFF_8636; 3917 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 3918 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) 3919 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN; 3920 break; 3921 default: 3922 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id); 3923 return -ENOTSUP; 3924 } 3925 3926 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n", 3927 dev->data->port_id, modinfo->type, modinfo->eeprom_len); 3928 3929 return 0; 3930 } 3931 3932 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev, 3933 struct rte_dev_eeprom_info *info) 3934 { 3935 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 }; 3936 uint32_t offset = info->offset, length = info->length; 3937 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3938 struct bnxt *bp = dev->data->dev_private; 3939 uint8_t *data = info->data; 3940 uint8_t page = offset >> 7; 3941 uint8_t max_pages = 2; 3942 uint8_t opt_pages; 3943 int rc; 3944 3945 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3946 SFF_DIAG_SUPPORT_OFFSET + 1, 3947 module_info); 3948 if (rc) 3949 return rc; 3950 3951 switch (module_info[0]) { 3952 case SFF_MODULE_ID_SFP: 3953 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0; 3954 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) { 3955 pg_addr[2] = I2C_DEV_ADDR_A2; 3956 pg_addr[3] = I2C_DEV_ADDR_A2; 3957 max_pages = 4; 3958 } 3959 break; 3960 case SFF_MODULE_ID_QSFP28: 3961 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3962 SFF8636_OPT_PAGES_OFFSET, 3963 1, &opt_pages); 3964 if (rc) 3965 return rc; 3966 3967 if (opt_pages & SFF8636_PAGE1_MASK) { 3968 pg_addr[2] = I2C_DEV_ADDR_A0; 3969 max_pages = 3; 3970 } 3971 if (opt_pages & SFF8636_PAGE2_MASK) { 3972 pg_addr[3] = I2C_DEV_ADDR_A0; 3973 max_pages = 4; 3974 } 3975 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) { 3976 pg_addr[4] = I2C_DEV_ADDR_A0; 3977 max_pages = 5; 3978 } 3979 break; 3980 default: 3981 break; 3982 } 3983 3984 memset(data, 0, length); 3985 3986 offset &= 0xff; 3987 while (length && page < max_pages) { 3988 uint8_t raw_page = page ? page - 1 : 0; 3989 uint16_t chunk; 3990 3991 if (pg_addr[page] == I2C_DEV_ADDR_A2) 3992 raw_page = 0; 3993 else if (page) 3994 offset |= 0x80; 3995 chunk = RTE_MIN(length, 256 - offset); 3996 3997 if (pg_addr[page]) { 3998 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page], 3999 raw_page, offset, 4000 chunk, data); 4001 if (rc) 4002 return rc; 4003 } 4004 4005 data += chunk; 4006 length -= chunk; 4007 offset = 0; 4008 page += 1 + (chunk > 128); 4009 } 4010 4011 return length ? -EINVAL : 0; 4012 } 4013 4014 /* 4015 * Initialization 4016 */ 4017 4018 static const struct eth_dev_ops bnxt_dev_ops = { 4019 .dev_infos_get = bnxt_dev_info_get_op, 4020 .dev_close = bnxt_dev_close_op, 4021 .dev_configure = bnxt_dev_configure_op, 4022 .dev_start = bnxt_dev_start_op, 4023 .dev_stop = bnxt_dev_stop_op, 4024 .dev_set_link_up = bnxt_dev_set_link_up_op, 4025 .dev_set_link_down = bnxt_dev_set_link_down_op, 4026 .stats_get = bnxt_stats_get_op, 4027 .stats_reset = bnxt_stats_reset_op, 4028 .rx_queue_setup = bnxt_rx_queue_setup_op, 4029 .rx_queue_release = bnxt_rx_queue_release_op, 4030 .tx_queue_setup = bnxt_tx_queue_setup_op, 4031 .tx_queue_release = bnxt_tx_queue_release_op, 4032 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4033 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4034 .reta_update = bnxt_reta_update_op, 4035 .reta_query = bnxt_reta_query_op, 4036 .rss_hash_update = bnxt_rss_hash_update_op, 4037 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4038 .link_update = bnxt_link_update_op, 4039 .promiscuous_enable = bnxt_promiscuous_enable_op, 4040 .promiscuous_disable = bnxt_promiscuous_disable_op, 4041 .allmulticast_enable = bnxt_allmulticast_enable_op, 4042 .allmulticast_disable = bnxt_allmulticast_disable_op, 4043 .mac_addr_add = bnxt_mac_addr_add_op, 4044 .mac_addr_remove = bnxt_mac_addr_remove_op, 4045 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4046 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4047 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4048 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4049 .vlan_filter_set = bnxt_vlan_filter_set_op, 4050 .vlan_offload_set = bnxt_vlan_offload_set_op, 4051 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4052 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4053 .mtu_set = bnxt_mtu_set_op, 4054 .mac_addr_set = bnxt_set_default_mac_addr_op, 4055 .xstats_get = bnxt_dev_xstats_get_op, 4056 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4057 .xstats_reset = bnxt_dev_xstats_reset_op, 4058 .fw_version_get = bnxt_fw_version_get, 4059 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4060 .rxq_info_get = bnxt_rxq_info_get_op, 4061 .txq_info_get = bnxt_txq_info_get_op, 4062 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 4063 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 4064 .dev_led_on = bnxt_dev_led_on_op, 4065 .dev_led_off = bnxt_dev_led_off_op, 4066 .rx_queue_start = bnxt_rx_queue_start, 4067 .rx_queue_stop = bnxt_rx_queue_stop, 4068 .tx_queue_start = bnxt_tx_queue_start, 4069 .tx_queue_stop = bnxt_tx_queue_stop, 4070 .flow_ops_get = bnxt_flow_ops_get_op, 4071 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4072 .get_eeprom_length = bnxt_get_eeprom_length_op, 4073 .get_eeprom = bnxt_get_eeprom_op, 4074 .set_eeprom = bnxt_set_eeprom_op, 4075 .get_module_info = bnxt_get_module_info, 4076 .get_module_eeprom = bnxt_get_module_eeprom, 4077 .timesync_enable = bnxt_timesync_enable, 4078 .timesync_disable = bnxt_timesync_disable, 4079 .timesync_read_time = bnxt_timesync_read_time, 4080 .timesync_write_time = bnxt_timesync_write_time, 4081 .timesync_adjust_time = bnxt_timesync_adjust_time, 4082 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4083 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4084 }; 4085 4086 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4087 { 4088 uint32_t offset; 4089 4090 /* Only pre-map the reset GRC registers using window 3 */ 4091 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4092 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4093 4094 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4095 4096 return offset; 4097 } 4098 4099 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4100 { 4101 struct bnxt_error_recovery_info *info = bp->recovery_info; 4102 uint32_t reg_base = 0xffffffff; 4103 int i; 4104 4105 /* Only pre-map the monitoring GRC registers using window 2 */ 4106 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4107 uint32_t reg = info->status_regs[i]; 4108 4109 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4110 continue; 4111 4112 if (reg_base == 0xffffffff) 4113 reg_base = reg & 0xfffff000; 4114 if ((reg & 0xfffff000) != reg_base) 4115 return -ERANGE; 4116 4117 /* Use mask 0xffc as the Lower 2 bits indicates 4118 * address space location 4119 */ 4120 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4121 (reg & 0xffc); 4122 } 4123 4124 if (reg_base == 0xffffffff) 4125 return 0; 4126 4127 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4128 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4129 4130 return 0; 4131 } 4132 4133 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4134 { 4135 struct bnxt_error_recovery_info *info = bp->recovery_info; 4136 uint32_t delay = info->delay_after_reset[index]; 4137 uint32_t val = info->reset_reg_val[index]; 4138 uint32_t reg = info->reset_reg[index]; 4139 uint32_t type, offset; 4140 int ret; 4141 4142 type = BNXT_FW_STATUS_REG_TYPE(reg); 4143 offset = BNXT_FW_STATUS_REG_OFF(reg); 4144 4145 switch (type) { 4146 case BNXT_FW_STATUS_REG_TYPE_CFG: 4147 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4148 if (ret < 0) { 4149 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 4150 val, offset); 4151 return; 4152 } 4153 break; 4154 case BNXT_FW_STATUS_REG_TYPE_GRC: 4155 offset = bnxt_map_reset_regs(bp, offset); 4156 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4157 break; 4158 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4159 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4160 break; 4161 } 4162 /* wait on a specific interval of time until core reset is complete */ 4163 if (delay) 4164 rte_delay_ms(delay); 4165 } 4166 4167 static void bnxt_dev_cleanup(struct bnxt *bp) 4168 { 4169 bp->eth_dev->data->dev_link.link_status = 0; 4170 bp->link_info->link_up = 0; 4171 if (bp->eth_dev->data->dev_started) 4172 bnxt_dev_stop(bp->eth_dev); 4173 4174 bnxt_uninit_resources(bp, true); 4175 } 4176 4177 static int 4178 bnxt_check_fw_reset_done(struct bnxt *bp) 4179 { 4180 int timeout = bp->fw_reset_max_msecs; 4181 uint16_t val = 0; 4182 int rc; 4183 4184 do { 4185 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4186 if (rc < 0) { 4187 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4188 return rc; 4189 } 4190 if (val != 0xffff) 4191 break; 4192 rte_delay_ms(1); 4193 } while (timeout--); 4194 4195 if (val == 0xffff) { 4196 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 4197 return -1; 4198 } 4199 4200 return 0; 4201 } 4202 4203 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4204 { 4205 struct rte_eth_dev *dev = bp->eth_dev; 4206 struct rte_vlan_filter_conf *vfc; 4207 int vidx, vbit, rc; 4208 uint16_t vlan_id; 4209 4210 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4211 vfc = &dev->data->vlan_filter_conf; 4212 vidx = vlan_id / 64; 4213 vbit = vlan_id % 64; 4214 4215 /* Each bit corresponds to a VLAN id */ 4216 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4217 rc = bnxt_add_vlan_filter(bp, vlan_id); 4218 if (rc) 4219 return rc; 4220 } 4221 } 4222 4223 return 0; 4224 } 4225 4226 static int bnxt_restore_mac_filters(struct bnxt *bp) 4227 { 4228 struct rte_eth_dev *dev = bp->eth_dev; 4229 struct rte_eth_dev_info dev_info; 4230 struct rte_ether_addr *addr; 4231 uint64_t pool_mask; 4232 uint32_t pool = 0; 4233 uint32_t i; 4234 int rc; 4235 4236 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4237 return 0; 4238 4239 rc = bnxt_dev_info_get_op(dev, &dev_info); 4240 if (rc) 4241 return rc; 4242 4243 /* replay MAC address configuration */ 4244 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4245 addr = &dev->data->mac_addrs[i]; 4246 4247 /* skip zero address */ 4248 if (rte_is_zero_ether_addr(addr)) 4249 continue; 4250 4251 pool = 0; 4252 pool_mask = dev->data->mac_pool_sel[i]; 4253 4254 do { 4255 if (pool_mask & 1ULL) { 4256 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4257 if (rc) 4258 return rc; 4259 } 4260 pool_mask >>= 1; 4261 pool++; 4262 } while (pool_mask); 4263 } 4264 4265 return 0; 4266 } 4267 4268 static int bnxt_restore_filters(struct bnxt *bp) 4269 { 4270 struct rte_eth_dev *dev = bp->eth_dev; 4271 int ret = 0; 4272 4273 if (dev->data->all_multicast) { 4274 ret = bnxt_allmulticast_enable_op(dev); 4275 if (ret) 4276 return ret; 4277 } 4278 if (dev->data->promiscuous) { 4279 ret = bnxt_promiscuous_enable_op(dev); 4280 if (ret) 4281 return ret; 4282 } 4283 4284 ret = bnxt_restore_mac_filters(bp); 4285 if (ret) 4286 return ret; 4287 4288 ret = bnxt_restore_vlan_filters(bp); 4289 /* TODO restore other filters as well */ 4290 return ret; 4291 } 4292 4293 static int bnxt_check_fw_ready(struct bnxt *bp) 4294 { 4295 int timeout = bp->fw_reset_max_msecs; 4296 int rc = 0; 4297 4298 do { 4299 rc = bnxt_hwrm_poll_ver_get(bp); 4300 if (rc == 0) 4301 break; 4302 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4303 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4304 } while (rc && timeout > 0); 4305 4306 if (rc) 4307 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4308 4309 return rc; 4310 } 4311 4312 static void bnxt_dev_recover(void *arg) 4313 { 4314 struct bnxt *bp = arg; 4315 int rc = 0; 4316 4317 pthread_mutex_lock(&bp->err_recovery_lock); 4318 4319 if (!bp->fw_reset_min_msecs) { 4320 rc = bnxt_check_fw_reset_done(bp); 4321 if (rc) 4322 goto err; 4323 } 4324 4325 /* Clear Error flag so that device re-init should happen */ 4326 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4327 4328 rc = bnxt_check_fw_ready(bp); 4329 if (rc) 4330 goto err; 4331 4332 rc = bnxt_init_resources(bp, true); 4333 if (rc) { 4334 PMD_DRV_LOG(ERR, 4335 "Failed to initialize resources after reset\n"); 4336 goto err; 4337 } 4338 /* clear reset flag as the device is initialized now */ 4339 bp->flags &= ~BNXT_FLAG_FW_RESET; 4340 4341 rc = bnxt_dev_start_op(bp->eth_dev); 4342 if (rc) { 4343 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4344 goto err_start; 4345 } 4346 4347 rc = bnxt_restore_filters(bp); 4348 if (rc) 4349 goto err_start; 4350 4351 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4352 pthread_mutex_unlock(&bp->err_recovery_lock); 4353 4354 return; 4355 err_start: 4356 bnxt_dev_stop(bp->eth_dev); 4357 err: 4358 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4359 bnxt_uninit_resources(bp, false); 4360 if (bp->eth_dev->data->dev_conf.intr_conf.rmv) 4361 rte_eth_dev_callback_process(bp->eth_dev, 4362 RTE_ETH_EVENT_INTR_RMV, 4363 NULL); 4364 pthread_mutex_unlock(&bp->err_recovery_lock); 4365 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4366 } 4367 4368 void bnxt_dev_reset_and_resume(void *arg) 4369 { 4370 struct bnxt *bp = arg; 4371 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4372 uint16_t val = 0; 4373 int rc; 4374 4375 bnxt_dev_cleanup(bp); 4376 4377 bnxt_wait_for_device_shutdown(bp); 4378 4379 /* During some fatal firmware error conditions, the PCI config space 4380 * register 0x2e which normally contains the subsystem ID will become 4381 * 0xffff. This register will revert back to the normal value after 4382 * the chip has completed core reset. If we detect this condition, 4383 * we can poll this config register immediately for the value to revert. 4384 */ 4385 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4386 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4387 if (rc < 0) { 4388 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4389 return; 4390 } 4391 if (val == 0xffff) { 4392 bp->fw_reset_min_msecs = 0; 4393 us = 1; 4394 } 4395 } 4396 4397 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4398 if (rc) 4399 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4400 } 4401 4402 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4403 { 4404 struct bnxt_error_recovery_info *info = bp->recovery_info; 4405 uint32_t reg = info->status_regs[index]; 4406 uint32_t type, offset, val = 0; 4407 int ret = 0; 4408 4409 type = BNXT_FW_STATUS_REG_TYPE(reg); 4410 offset = BNXT_FW_STATUS_REG_OFF(reg); 4411 4412 switch (type) { 4413 case BNXT_FW_STATUS_REG_TYPE_CFG: 4414 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4415 if (ret < 0) 4416 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x", 4417 offset); 4418 break; 4419 case BNXT_FW_STATUS_REG_TYPE_GRC: 4420 offset = info->mapped_status_regs[index]; 4421 /* FALLTHROUGH */ 4422 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4423 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4424 offset)); 4425 break; 4426 } 4427 4428 return val; 4429 } 4430 4431 static int bnxt_fw_reset_all(struct bnxt *bp) 4432 { 4433 struct bnxt_error_recovery_info *info = bp->recovery_info; 4434 uint32_t i; 4435 int rc = 0; 4436 4437 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4438 /* Reset through master function driver */ 4439 for (i = 0; i < info->reg_array_cnt; i++) 4440 bnxt_write_fw_reset_reg(bp, i); 4441 /* Wait for time specified by FW after triggering reset */ 4442 rte_delay_ms(info->master_func_wait_period_after_reset); 4443 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4444 /* Reset with the help of Kong processor */ 4445 rc = bnxt_hwrm_fw_reset(bp); 4446 if (rc) 4447 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4448 } 4449 4450 return rc; 4451 } 4452 4453 static void bnxt_fw_reset_cb(void *arg) 4454 { 4455 struct bnxt *bp = arg; 4456 struct bnxt_error_recovery_info *info = bp->recovery_info; 4457 int rc = 0; 4458 4459 /* Only Master function can do FW reset */ 4460 if (bnxt_is_master_func(bp) && 4461 bnxt_is_recovery_enabled(bp)) { 4462 rc = bnxt_fw_reset_all(bp); 4463 if (rc) { 4464 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4465 return; 4466 } 4467 } 4468 4469 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4470 * EXCEPTION_FATAL_ASYNC event to all the functions 4471 * (including MASTER FUNC). After receiving this Async, all the active 4472 * drivers should treat this case as FW initiated recovery 4473 */ 4474 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4475 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4476 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4477 4478 /* To recover from error */ 4479 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4480 (void *)bp); 4481 } 4482 } 4483 4484 /* Driver should poll FW heartbeat, reset_counter with the frequency 4485 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4486 * When the driver detects heartbeat stop or change in reset_counter, 4487 * it has to trigger a reset to recover from the error condition. 4488 * A “master PF” is the function who will have the privilege to 4489 * initiate the chimp reset. The master PF will be elected by the 4490 * firmware and will be notified through async message. 4491 */ 4492 static void bnxt_check_fw_health(void *arg) 4493 { 4494 struct bnxt *bp = arg; 4495 struct bnxt_error_recovery_info *info = bp->recovery_info; 4496 uint32_t val = 0, wait_msec; 4497 4498 if (!info || !bnxt_is_recovery_enabled(bp) || 4499 is_bnxt_in_error(bp)) 4500 return; 4501 4502 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4503 if (val == info->last_heart_beat) 4504 goto reset; 4505 4506 info->last_heart_beat = val; 4507 4508 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4509 if (val != info->last_reset_counter) 4510 goto reset; 4511 4512 info->last_reset_counter = val; 4513 4514 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4515 bnxt_check_fw_health, (void *)bp); 4516 4517 return; 4518 reset: 4519 /* Stop DMA to/from device */ 4520 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4521 bp->flags |= BNXT_FLAG_FW_RESET; 4522 4523 bnxt_stop_rxtx(bp); 4524 4525 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4526 4527 if (bnxt_is_master_func(bp)) 4528 wait_msec = info->master_func_wait_period; 4529 else 4530 wait_msec = info->normal_func_wait_period; 4531 4532 rte_eal_alarm_set(US_PER_MS * wait_msec, 4533 bnxt_fw_reset_cb, (void *)bp); 4534 } 4535 4536 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4537 { 4538 uint32_t polling_freq; 4539 4540 pthread_mutex_lock(&bp->health_check_lock); 4541 4542 if (!bnxt_is_recovery_enabled(bp)) 4543 goto done; 4544 4545 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4546 goto done; 4547 4548 polling_freq = bp->recovery_info->driver_polling_freq; 4549 4550 rte_eal_alarm_set(US_PER_MS * polling_freq, 4551 bnxt_check_fw_health, (void *)bp); 4552 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4553 4554 done: 4555 pthread_mutex_unlock(&bp->health_check_lock); 4556 } 4557 4558 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4559 { 4560 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4561 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4562 } 4563 4564 static bool bnxt_vf_pciid(uint16_t device_id) 4565 { 4566 switch (device_id) { 4567 case BROADCOM_DEV_ID_57304_VF: 4568 case BROADCOM_DEV_ID_57406_VF: 4569 case BROADCOM_DEV_ID_5731X_VF: 4570 case BROADCOM_DEV_ID_5741X_VF: 4571 case BROADCOM_DEV_ID_57414_VF: 4572 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4573 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4574 case BROADCOM_DEV_ID_58802_VF: 4575 case BROADCOM_DEV_ID_57500_VF1: 4576 case BROADCOM_DEV_ID_57500_VF2: 4577 case BROADCOM_DEV_ID_58818_VF: 4578 /* FALLTHROUGH */ 4579 return true; 4580 default: 4581 return false; 4582 } 4583 } 4584 4585 /* Phase 5 device */ 4586 static bool bnxt_p5_device(uint16_t device_id) 4587 { 4588 switch (device_id) { 4589 case BROADCOM_DEV_ID_57508: 4590 case BROADCOM_DEV_ID_57504: 4591 case BROADCOM_DEV_ID_57502: 4592 case BROADCOM_DEV_ID_57508_MF1: 4593 case BROADCOM_DEV_ID_57504_MF1: 4594 case BROADCOM_DEV_ID_57502_MF1: 4595 case BROADCOM_DEV_ID_57508_MF2: 4596 case BROADCOM_DEV_ID_57504_MF2: 4597 case BROADCOM_DEV_ID_57502_MF2: 4598 case BROADCOM_DEV_ID_57500_VF1: 4599 case BROADCOM_DEV_ID_57500_VF2: 4600 case BROADCOM_DEV_ID_58812: 4601 case BROADCOM_DEV_ID_58814: 4602 case BROADCOM_DEV_ID_58818: 4603 case BROADCOM_DEV_ID_58818_VF: 4604 /* FALLTHROUGH */ 4605 return true; 4606 default: 4607 return false; 4608 } 4609 } 4610 4611 bool bnxt_stratus_device(struct bnxt *bp) 4612 { 4613 uint16_t device_id = bp->pdev->id.device_id; 4614 4615 switch (device_id) { 4616 case BROADCOM_DEV_ID_STRATUS_NIC: 4617 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4618 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4619 /* FALLTHROUGH */ 4620 return true; 4621 default: 4622 return false; 4623 } 4624 } 4625 4626 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4627 { 4628 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4629 struct bnxt *bp = eth_dev->data->dev_private; 4630 4631 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4632 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4633 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4634 if (!bp->bar0 || !bp->doorbell_base) { 4635 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4636 return -ENODEV; 4637 } 4638 4639 bp->eth_dev = eth_dev; 4640 bp->pdev = pci_dev; 4641 4642 return 0; 4643 } 4644 4645 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4646 struct bnxt_ctx_pg_info *ctx_pg, 4647 uint32_t mem_size, 4648 const char *suffix, 4649 uint16_t idx) 4650 { 4651 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4652 const struct rte_memzone *mz = NULL; 4653 char mz_name[RTE_MEMZONE_NAMESIZE]; 4654 rte_iova_t mz_phys_addr; 4655 uint64_t valid_bits = 0; 4656 uint32_t sz; 4657 int i; 4658 4659 if (!mem_size) 4660 return 0; 4661 4662 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4663 BNXT_PAGE_SIZE; 4664 rmem->page_size = BNXT_PAGE_SIZE; 4665 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4666 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4667 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4668 4669 valid_bits = PTU_PTE_VALID; 4670 4671 if (rmem->nr_pages > 1) { 4672 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4673 "bnxt_ctx_pg_tbl%s_%x_%d", 4674 suffix, idx, bp->eth_dev->data->port_id); 4675 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4676 mz = rte_memzone_lookup(mz_name); 4677 if (!mz) { 4678 mz = rte_memzone_reserve_aligned(mz_name, 4679 rmem->nr_pages * 8, 4680 bp->eth_dev->device->numa_node, 4681 RTE_MEMZONE_2MB | 4682 RTE_MEMZONE_SIZE_HINT_ONLY | 4683 RTE_MEMZONE_IOVA_CONTIG, 4684 BNXT_PAGE_SIZE); 4685 if (mz == NULL) 4686 return -ENOMEM; 4687 } 4688 4689 memset(mz->addr, 0, mz->len); 4690 mz_phys_addr = mz->iova; 4691 4692 rmem->pg_tbl = mz->addr; 4693 rmem->pg_tbl_map = mz_phys_addr; 4694 rmem->pg_tbl_mz = mz; 4695 } 4696 4697 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4698 suffix, idx, bp->eth_dev->data->port_id); 4699 mz = rte_memzone_lookup(mz_name); 4700 if (!mz) { 4701 mz = rte_memzone_reserve_aligned(mz_name, 4702 mem_size, 4703 bp->eth_dev->device->numa_node, 4704 RTE_MEMZONE_1GB | 4705 RTE_MEMZONE_SIZE_HINT_ONLY | 4706 RTE_MEMZONE_IOVA_CONTIG, 4707 BNXT_PAGE_SIZE); 4708 if (mz == NULL) 4709 return -ENOMEM; 4710 } 4711 4712 memset(mz->addr, 0, mz->len); 4713 mz_phys_addr = mz->iova; 4714 4715 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4716 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4717 rmem->dma_arr[i] = mz_phys_addr + sz; 4718 4719 if (rmem->nr_pages > 1) { 4720 if (i == rmem->nr_pages - 2 && 4721 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4722 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4723 else if (i == rmem->nr_pages - 1 && 4724 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4725 valid_bits |= PTU_PTE_LAST; 4726 4727 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4728 valid_bits); 4729 } 4730 } 4731 4732 rmem->mz = mz; 4733 if (rmem->vmem_size) 4734 rmem->vmem = (void **)mz->addr; 4735 rmem->dma_arr[0] = mz_phys_addr; 4736 return 0; 4737 } 4738 4739 static void bnxt_free_ctx_mem(struct bnxt *bp) 4740 { 4741 int i; 4742 4743 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4744 return; 4745 4746 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4747 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4748 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4749 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4750 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4751 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4752 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4753 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4754 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4755 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4756 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4757 4758 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4759 if (bp->ctx->tqm_mem[i]) 4760 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4761 } 4762 4763 rte_free(bp->ctx); 4764 bp->ctx = NULL; 4765 } 4766 4767 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4768 4769 #define min_t(type, x, y) ({ \ 4770 type __min1 = (x); \ 4771 type __min2 = (y); \ 4772 __min1 < __min2 ? __min1 : __min2; }) 4773 4774 #define max_t(type, x, y) ({ \ 4775 type __max1 = (x); \ 4776 type __max2 = (y); \ 4777 __max1 > __max2 ? __max1 : __max2; }) 4778 4779 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4780 4781 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4782 { 4783 struct bnxt_ctx_pg_info *ctx_pg; 4784 struct bnxt_ctx_mem_info *ctx; 4785 uint32_t mem_size, ena, entries; 4786 uint32_t entries_sp, min; 4787 int i, rc; 4788 4789 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4790 if (rc) { 4791 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4792 return rc; 4793 } 4794 ctx = bp->ctx; 4795 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4796 return 0; 4797 4798 ctx_pg = &ctx->qp_mem; 4799 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4800 if (ctx->qp_entry_size) { 4801 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4802 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4803 if (rc) 4804 return rc; 4805 } 4806 4807 ctx_pg = &ctx->srq_mem; 4808 ctx_pg->entries = ctx->srq_max_l2_entries; 4809 if (ctx->srq_entry_size) { 4810 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4811 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4812 if (rc) 4813 return rc; 4814 } 4815 4816 ctx_pg = &ctx->cq_mem; 4817 ctx_pg->entries = ctx->cq_max_l2_entries; 4818 if (ctx->cq_entry_size) { 4819 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4820 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4821 if (rc) 4822 return rc; 4823 } 4824 4825 ctx_pg = &ctx->vnic_mem; 4826 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4827 ctx->vnic_max_ring_table_entries; 4828 if (ctx->vnic_entry_size) { 4829 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4830 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4831 if (rc) 4832 return rc; 4833 } 4834 4835 ctx_pg = &ctx->stat_mem; 4836 ctx_pg->entries = ctx->stat_max_entries; 4837 if (ctx->stat_entry_size) { 4838 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4839 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4840 if (rc) 4841 return rc; 4842 } 4843 4844 min = ctx->tqm_min_entries_per_ring; 4845 4846 entries_sp = ctx->qp_max_l2_entries + 4847 ctx->vnic_max_vnic_entries + 4848 2 * ctx->qp_min_qp1_entries + min; 4849 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4850 4851 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4852 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4853 entries = clamp_t(uint32_t, entries, min, 4854 ctx->tqm_max_entries_per_ring); 4855 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4856 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4857 * i > 8 is other ext rings. 4858 */ 4859 ctx_pg = ctx->tqm_mem[i]; 4860 ctx_pg->entries = i ? entries : entries_sp; 4861 if (ctx->tqm_entry_size) { 4862 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4863 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4864 "tqm_mem", i); 4865 if (rc) 4866 return rc; 4867 } 4868 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4869 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4870 else 4871 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4872 } 4873 4874 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4875 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4876 if (rc) 4877 PMD_DRV_LOG(ERR, 4878 "Failed to configure context mem: rc = %d\n", rc); 4879 else 4880 ctx->flags |= BNXT_CTX_FLAG_INITED; 4881 4882 return rc; 4883 } 4884 4885 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4886 { 4887 struct rte_pci_device *pci_dev = bp->pdev; 4888 char mz_name[RTE_MEMZONE_NAMESIZE]; 4889 const struct rte_memzone *mz = NULL; 4890 uint32_t total_alloc_len; 4891 rte_iova_t mz_phys_addr; 4892 4893 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4894 return 0; 4895 4896 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4897 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4898 pci_dev->addr.bus, pci_dev->addr.devid, 4899 pci_dev->addr.function, "rx_port_stats"); 4900 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4901 mz = rte_memzone_lookup(mz_name); 4902 total_alloc_len = 4903 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4904 sizeof(struct rx_port_stats_ext) + 512); 4905 if (!mz) { 4906 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4907 SOCKET_ID_ANY, 4908 RTE_MEMZONE_2MB | 4909 RTE_MEMZONE_SIZE_HINT_ONLY | 4910 RTE_MEMZONE_IOVA_CONTIG); 4911 if (mz == NULL) 4912 return -ENOMEM; 4913 } 4914 memset(mz->addr, 0, mz->len); 4915 mz_phys_addr = mz->iova; 4916 4917 bp->rx_mem_zone = (const void *)mz; 4918 bp->hw_rx_port_stats = mz->addr; 4919 bp->hw_rx_port_stats_map = mz_phys_addr; 4920 4921 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4922 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4923 pci_dev->addr.bus, pci_dev->addr.devid, 4924 pci_dev->addr.function, "tx_port_stats"); 4925 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4926 mz = rte_memzone_lookup(mz_name); 4927 total_alloc_len = 4928 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4929 sizeof(struct tx_port_stats_ext) + 512); 4930 if (!mz) { 4931 mz = rte_memzone_reserve(mz_name, 4932 total_alloc_len, 4933 SOCKET_ID_ANY, 4934 RTE_MEMZONE_2MB | 4935 RTE_MEMZONE_SIZE_HINT_ONLY | 4936 RTE_MEMZONE_IOVA_CONTIG); 4937 if (mz == NULL) 4938 return -ENOMEM; 4939 } 4940 memset(mz->addr, 0, mz->len); 4941 mz_phys_addr = mz->iova; 4942 4943 bp->tx_mem_zone = (const void *)mz; 4944 bp->hw_tx_port_stats = mz->addr; 4945 bp->hw_tx_port_stats_map = mz_phys_addr; 4946 bp->flags |= BNXT_FLAG_PORT_STATS; 4947 4948 /* Display extended statistics if FW supports it */ 4949 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4950 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4951 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4952 return 0; 4953 4954 bp->hw_rx_port_stats_ext = (void *) 4955 ((uint8_t *)bp->hw_rx_port_stats + 4956 sizeof(struct rx_port_stats)); 4957 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4958 sizeof(struct rx_port_stats); 4959 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4960 4961 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4962 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4963 bp->hw_tx_port_stats_ext = (void *) 4964 ((uint8_t *)bp->hw_tx_port_stats + 4965 sizeof(struct tx_port_stats)); 4966 bp->hw_tx_port_stats_ext_map = 4967 bp->hw_tx_port_stats_map + 4968 sizeof(struct tx_port_stats); 4969 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4970 } 4971 4972 return 0; 4973 } 4974 4975 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4976 { 4977 struct bnxt *bp = eth_dev->data->dev_private; 4978 int rc = 0; 4979 4980 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4981 RTE_ETHER_ADDR_LEN * 4982 bp->max_l2_ctx, 4983 0); 4984 if (eth_dev->data->mac_addrs == NULL) { 4985 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4986 return -ENOMEM; 4987 } 4988 4989 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4990 if (BNXT_PF(bp)) 4991 return -EINVAL; 4992 4993 /* Generate a random MAC address, if none was assigned by PF */ 4994 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4995 bnxt_eth_hw_addr_random(bp->mac_addr); 4996 PMD_DRV_LOG(INFO, 4997 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4998 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4999 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 5000 5001 rc = bnxt_hwrm_set_mac(bp); 5002 if (rc) 5003 return rc; 5004 } 5005 5006 /* Copy the permanent MAC from the FUNC_QCAPS response */ 5007 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5008 5009 return rc; 5010 } 5011 5012 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5013 { 5014 int rc = 0; 5015 5016 /* MAC is already configured in FW */ 5017 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5018 return 0; 5019 5020 /* Restore the old MAC configured */ 5021 rc = bnxt_hwrm_set_mac(bp); 5022 if (rc) 5023 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5024 5025 return rc; 5026 } 5027 5028 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5029 { 5030 if (!BNXT_PF(bp)) 5031 return; 5032 5033 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5034 5035 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 5036 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 5037 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 5038 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 5039 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 5040 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 5041 } 5042 5043 struct bnxt * 5044 bnxt_get_bp(uint16_t port) 5045 { 5046 struct bnxt *bp; 5047 struct rte_eth_dev *dev; 5048 5049 if (!rte_eth_dev_is_valid_port(port)) { 5050 PMD_DRV_LOG(ERR, "Invalid port %d\n", port); 5051 return NULL; 5052 } 5053 5054 dev = &rte_eth_devices[port]; 5055 if (!is_bnxt_supported(dev)) { 5056 PMD_DRV_LOG(ERR, "Device %d not supported\n", port); 5057 return NULL; 5058 } 5059 5060 bp = (struct bnxt *)dev->data->dev_private; 5061 if (!BNXT_TRUFLOW_EN(bp)) { 5062 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); 5063 return NULL; 5064 } 5065 5066 return bp; 5067 } 5068 5069 uint16_t 5070 bnxt_get_svif(uint16_t port_id, bool func_svif, 5071 enum bnxt_ulp_intf_type type) 5072 { 5073 struct rte_eth_dev *eth_dev; 5074 struct bnxt *bp; 5075 5076 eth_dev = &rte_eth_devices[port_id]; 5077 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5078 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5079 if (!vfr) 5080 return 0; 5081 5082 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5083 return vfr->svif; 5084 5085 eth_dev = vfr->parent_dev; 5086 } 5087 5088 bp = eth_dev->data->dev_private; 5089 5090 return func_svif ? bp->func_svif : bp->port_svif; 5091 } 5092 5093 void 5094 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, 5095 uint8_t *mac, uint8_t *parent_mac) 5096 { 5097 struct rte_eth_dev *eth_dev; 5098 struct bnxt *bp; 5099 5100 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && 5101 type != BNXT_ULP_INTF_TYPE_PF) 5102 return; 5103 5104 eth_dev = &rte_eth_devices[port]; 5105 bp = eth_dev->data->dev_private; 5106 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); 5107 5108 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5109 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); 5110 } 5111 5112 uint16_t 5113 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5114 { 5115 struct rte_eth_dev *eth_dev; 5116 struct bnxt *bp; 5117 5118 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5119 return 0; 5120 5121 eth_dev = &rte_eth_devices[port]; 5122 bp = eth_dev->data->dev_private; 5123 5124 return bp->parent->vnic; 5125 } 5126 uint16_t 5127 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5128 { 5129 struct rte_eth_dev *eth_dev; 5130 struct bnxt_vnic_info *vnic; 5131 struct bnxt *bp; 5132 5133 eth_dev = &rte_eth_devices[port]; 5134 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5135 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5136 if (!vfr) 5137 return 0; 5138 5139 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5140 return vfr->dflt_vnic_id; 5141 5142 eth_dev = vfr->parent_dev; 5143 } 5144 5145 bp = eth_dev->data->dev_private; 5146 5147 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5148 5149 return vnic->fw_vnic_id; 5150 } 5151 5152 uint16_t 5153 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 5154 { 5155 struct rte_eth_dev *eth_dev; 5156 struct bnxt *bp; 5157 5158 eth_dev = &rte_eth_devices[port]; 5159 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5160 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5161 if (!vfr) 5162 return 0; 5163 5164 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5165 return vfr->fw_fid; 5166 5167 eth_dev = vfr->parent_dev; 5168 } 5169 5170 bp = eth_dev->data->dev_private; 5171 5172 return bp->fw_fid; 5173 } 5174 5175 enum bnxt_ulp_intf_type 5176 bnxt_get_interface_type(uint16_t port) 5177 { 5178 struct rte_eth_dev *eth_dev; 5179 struct bnxt *bp; 5180 5181 eth_dev = &rte_eth_devices[port]; 5182 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 5183 return BNXT_ULP_INTF_TYPE_VF_REP; 5184 5185 bp = eth_dev->data->dev_private; 5186 if (BNXT_PF(bp)) 5187 return BNXT_ULP_INTF_TYPE_PF; 5188 else if (BNXT_VF_IS_TRUSTED(bp)) 5189 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 5190 else if (BNXT_VF(bp)) 5191 return BNXT_ULP_INTF_TYPE_VF; 5192 5193 return BNXT_ULP_INTF_TYPE_INVALID; 5194 } 5195 5196 uint16_t 5197 bnxt_get_phy_port_id(uint16_t port_id) 5198 { 5199 struct bnxt_representor *vfr; 5200 struct rte_eth_dev *eth_dev; 5201 struct bnxt *bp; 5202 5203 eth_dev = &rte_eth_devices[port_id]; 5204 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5205 vfr = eth_dev->data->dev_private; 5206 if (!vfr) 5207 return 0; 5208 5209 eth_dev = vfr->parent_dev; 5210 } 5211 5212 bp = eth_dev->data->dev_private; 5213 5214 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 5215 } 5216 5217 uint16_t 5218 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 5219 { 5220 struct rte_eth_dev *eth_dev; 5221 struct bnxt *bp; 5222 5223 eth_dev = &rte_eth_devices[port_id]; 5224 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5225 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5226 if (!vfr) 5227 return 0; 5228 5229 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5230 return vfr->fw_fid - 1; 5231 5232 eth_dev = vfr->parent_dev; 5233 } 5234 5235 bp = eth_dev->data->dev_private; 5236 5237 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 5238 } 5239 5240 uint16_t 5241 bnxt_get_vport(uint16_t port_id) 5242 { 5243 return (1 << bnxt_get_phy_port_id(port_id)); 5244 } 5245 5246 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5247 { 5248 struct bnxt_error_recovery_info *info = bp->recovery_info; 5249 5250 if (info) { 5251 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5252 memset(info, 0, sizeof(*info)); 5253 return; 5254 } 5255 5256 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5257 return; 5258 5259 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5260 sizeof(*info), 0); 5261 if (!info) 5262 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5263 5264 bp->recovery_info = info; 5265 } 5266 5267 static void bnxt_check_fw_status(struct bnxt *bp) 5268 { 5269 uint32_t fw_status; 5270 5271 if (!(bp->recovery_info && 5272 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5273 return; 5274 5275 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5276 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5277 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5278 fw_status); 5279 } 5280 5281 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5282 { 5283 struct bnxt_error_recovery_info *info = bp->recovery_info; 5284 uint32_t status_loc; 5285 uint32_t sig_ver; 5286 5287 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5288 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5289 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5290 BNXT_GRCP_WINDOW_2_BASE + 5291 offsetof(struct hcomm_status, 5292 sig_ver))); 5293 /* If the signature is absent, then FW does not support this feature */ 5294 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5295 HCOMM_STATUS_SIGNATURE_VAL) 5296 return 0; 5297 5298 if (!info) { 5299 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5300 sizeof(*info), 0); 5301 if (!info) 5302 return -ENOMEM; 5303 bp->recovery_info = info; 5304 } else { 5305 memset(info, 0, sizeof(*info)); 5306 } 5307 5308 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5309 BNXT_GRCP_WINDOW_2_BASE + 5310 offsetof(struct hcomm_status, 5311 fw_status_loc))); 5312 5313 /* Only pre-map the FW health status GRC register */ 5314 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5315 return 0; 5316 5317 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5318 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5319 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5320 5321 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5322 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5323 5324 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5325 5326 return 0; 5327 } 5328 5329 /* This function gets the FW version along with the 5330 * capabilities(MAX and current) of the function, vnic, 5331 * error recovery, phy and other chip related info 5332 */ 5333 static int bnxt_get_config(struct bnxt *bp) 5334 { 5335 uint16_t mtu; 5336 int rc = 0; 5337 5338 bp->fw_cap = 0; 5339 5340 rc = bnxt_map_hcomm_fw_status_reg(bp); 5341 if (rc) 5342 return rc; 5343 5344 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5345 if (rc) { 5346 bnxt_check_fw_status(bp); 5347 return rc; 5348 } 5349 5350 rc = bnxt_hwrm_func_reset(bp); 5351 if (rc) 5352 return -EIO; 5353 5354 rc = bnxt_hwrm_vnic_qcaps(bp); 5355 if (rc) 5356 return rc; 5357 5358 rc = bnxt_hwrm_queue_qportcfg(bp); 5359 if (rc) 5360 return rc; 5361 5362 /* Get the MAX capabilities for this function. 5363 * This function also allocates context memory for TQM rings and 5364 * informs the firmware about this allocated backing store memory. 5365 */ 5366 rc = bnxt_hwrm_func_qcaps(bp); 5367 if (rc) 5368 return rc; 5369 5370 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5371 if (rc) 5372 return rc; 5373 5374 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5375 if (rc) 5376 return rc; 5377 5378 bnxt_hwrm_port_mac_qcfg(bp); 5379 5380 bnxt_hwrm_parent_pf_qcfg(bp); 5381 5382 bnxt_hwrm_port_phy_qcaps(bp); 5383 5384 bnxt_alloc_error_recovery_info(bp); 5385 /* Get the adapter error recovery support info */ 5386 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5387 if (rc) 5388 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5389 5390 bnxt_hwrm_port_led_qcaps(bp); 5391 5392 return 0; 5393 } 5394 5395 static int 5396 bnxt_init_locks(struct bnxt *bp) 5397 { 5398 int err; 5399 5400 err = pthread_mutex_init(&bp->flow_lock, NULL); 5401 if (err) { 5402 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5403 return err; 5404 } 5405 5406 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5407 if (err) { 5408 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5409 return err; 5410 } 5411 5412 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5413 if (err) { 5414 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5415 return err; 5416 } 5417 5418 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5419 if (err) 5420 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5421 5422 return err; 5423 } 5424 5425 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5426 { 5427 int rc = 0; 5428 5429 rc = bnxt_get_config(bp); 5430 if (rc) 5431 return rc; 5432 5433 if (!reconfig_dev) { 5434 rc = bnxt_setup_mac_addr(bp->eth_dev); 5435 if (rc) 5436 return rc; 5437 } else { 5438 rc = bnxt_restore_dflt_mac(bp); 5439 if (rc) 5440 return rc; 5441 } 5442 5443 bnxt_config_vf_req_fwd(bp); 5444 5445 rc = bnxt_hwrm_func_driver_register(bp); 5446 if (rc) { 5447 PMD_DRV_LOG(ERR, "Failed to register driver"); 5448 return -EBUSY; 5449 } 5450 5451 if (BNXT_PF(bp)) { 5452 if (bp->pdev->max_vfs) { 5453 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5454 if (rc) { 5455 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5456 return rc; 5457 } 5458 } else { 5459 rc = bnxt_hwrm_allocate_pf_only(bp); 5460 if (rc) { 5461 PMD_DRV_LOG(ERR, 5462 "Failed to allocate PF resources"); 5463 return rc; 5464 } 5465 } 5466 } 5467 5468 rc = bnxt_alloc_mem(bp, reconfig_dev); 5469 if (rc) 5470 return rc; 5471 5472 rc = bnxt_setup_int(bp); 5473 if (rc) 5474 return rc; 5475 5476 rc = bnxt_request_int(bp); 5477 if (rc) 5478 return rc; 5479 5480 rc = bnxt_init_ctx_mem(bp); 5481 if (rc) { 5482 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5483 return rc; 5484 } 5485 5486 return 0; 5487 } 5488 5489 static int 5490 bnxt_parse_devarg_accum_stats(__rte_unused const char *key, 5491 const char *value, void *opaque_arg) 5492 { 5493 struct bnxt *bp = opaque_arg; 5494 unsigned long accum_stats; 5495 char *end = NULL; 5496 5497 if (!value || !opaque_arg) { 5498 PMD_DRV_LOG(ERR, 5499 "Invalid parameter passed to accum-stats devargs.\n"); 5500 return -EINVAL; 5501 } 5502 5503 accum_stats = strtoul(value, &end, 10); 5504 if (end == NULL || *end != '\0' || 5505 (accum_stats == ULONG_MAX && errno == ERANGE)) { 5506 PMD_DRV_LOG(ERR, 5507 "Invalid parameter passed to accum-stats devargs.\n"); 5508 return -EINVAL; 5509 } 5510 5511 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { 5512 PMD_DRV_LOG(ERR, 5513 "Invalid value passed to accum-stats devargs.\n"); 5514 return -EINVAL; 5515 } 5516 5517 if (accum_stats) { 5518 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; 5519 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); 5520 } else { 5521 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; 5522 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); 5523 } 5524 5525 return 0; 5526 } 5527 5528 static int 5529 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5530 const char *value, void *opaque_arg) 5531 { 5532 struct bnxt *bp = opaque_arg; 5533 unsigned long flow_xstat; 5534 char *end = NULL; 5535 5536 if (!value || !opaque_arg) { 5537 PMD_DRV_LOG(ERR, 5538 "Invalid parameter passed to flow_xstat devarg.\n"); 5539 return -EINVAL; 5540 } 5541 5542 flow_xstat = strtoul(value, &end, 10); 5543 if (end == NULL || *end != '\0' || 5544 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5545 PMD_DRV_LOG(ERR, 5546 "Invalid parameter passed to flow_xstat devarg.\n"); 5547 return -EINVAL; 5548 } 5549 5550 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5551 PMD_DRV_LOG(ERR, 5552 "Invalid value passed to flow_xstat devarg.\n"); 5553 return -EINVAL; 5554 } 5555 5556 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5557 if (BNXT_FLOW_XSTATS_EN(bp)) 5558 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5559 5560 return 0; 5561 } 5562 5563 static int 5564 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5565 const char *value, void *opaque_arg) 5566 { 5567 struct bnxt *bp = opaque_arg; 5568 unsigned long max_num_kflows; 5569 char *end = NULL; 5570 5571 if (!value || !opaque_arg) { 5572 PMD_DRV_LOG(ERR, 5573 "Invalid parameter passed to max_num_kflows devarg.\n"); 5574 return -EINVAL; 5575 } 5576 5577 max_num_kflows = strtoul(value, &end, 10); 5578 if (end == NULL || *end != '\0' || 5579 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5580 PMD_DRV_LOG(ERR, 5581 "Invalid parameter passed to max_num_kflows devarg.\n"); 5582 return -EINVAL; 5583 } 5584 5585 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5586 PMD_DRV_LOG(ERR, 5587 "Invalid value passed to max_num_kflows devarg.\n"); 5588 return -EINVAL; 5589 } 5590 5591 bp->max_num_kflows = max_num_kflows; 5592 if (bp->max_num_kflows) 5593 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5594 max_num_kflows); 5595 5596 return 0; 5597 } 5598 5599 static int 5600 bnxt_parse_devarg_app_id(__rte_unused const char *key, 5601 const char *value, void *opaque_arg) 5602 { 5603 struct bnxt *bp = opaque_arg; 5604 unsigned long app_id; 5605 char *end = NULL; 5606 5607 if (!value || !opaque_arg) { 5608 PMD_DRV_LOG(ERR, 5609 "Invalid parameter passed to app-id " 5610 "devargs.\n"); 5611 return -EINVAL; 5612 } 5613 5614 app_id = strtoul(value, &end, 10); 5615 if (end == NULL || *end != '\0' || 5616 (app_id == ULONG_MAX && errno == ERANGE)) { 5617 PMD_DRV_LOG(ERR, 5618 "Invalid parameter passed to app_id " 5619 "devargs.\n"); 5620 return -EINVAL; 5621 } 5622 5623 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) { 5624 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n", 5625 (uint16_t)app_id); 5626 return -EINVAL; 5627 } 5628 5629 bp->app_id = app_id; 5630 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id); 5631 5632 return 0; 5633 } 5634 5635 static int 5636 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5637 const char *value, void *opaque_arg) 5638 { 5639 struct bnxt_representor *vfr_bp = opaque_arg; 5640 unsigned long rep_is_pf; 5641 char *end = NULL; 5642 5643 if (!value || !opaque_arg) { 5644 PMD_DRV_LOG(ERR, 5645 "Invalid parameter passed to rep_is_pf devargs.\n"); 5646 return -EINVAL; 5647 } 5648 5649 rep_is_pf = strtoul(value, &end, 10); 5650 if (end == NULL || *end != '\0' || 5651 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5652 PMD_DRV_LOG(ERR, 5653 "Invalid parameter passed to rep_is_pf devargs.\n"); 5654 return -EINVAL; 5655 } 5656 5657 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5658 PMD_DRV_LOG(ERR, 5659 "Invalid value passed to rep_is_pf devargs.\n"); 5660 return -EINVAL; 5661 } 5662 5663 vfr_bp->flags |= rep_is_pf; 5664 if (BNXT_REP_PF(vfr_bp)) 5665 PMD_DRV_LOG(INFO, "PF representor\n"); 5666 else 5667 PMD_DRV_LOG(INFO, "VF representor\n"); 5668 5669 return 0; 5670 } 5671 5672 static int 5673 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5674 const char *value, void *opaque_arg) 5675 { 5676 struct bnxt_representor *vfr_bp = opaque_arg; 5677 unsigned long rep_based_pf; 5678 char *end = NULL; 5679 5680 if (!value || !opaque_arg) { 5681 PMD_DRV_LOG(ERR, 5682 "Invalid parameter passed to rep_based_pf " 5683 "devargs.\n"); 5684 return -EINVAL; 5685 } 5686 5687 rep_based_pf = strtoul(value, &end, 10); 5688 if (end == NULL || *end != '\0' || 5689 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5690 PMD_DRV_LOG(ERR, 5691 "Invalid parameter passed to rep_based_pf " 5692 "devargs.\n"); 5693 return -EINVAL; 5694 } 5695 5696 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5697 PMD_DRV_LOG(ERR, 5698 "Invalid value passed to rep_based_pf devargs.\n"); 5699 return -EINVAL; 5700 } 5701 5702 vfr_bp->rep_based_pf = rep_based_pf; 5703 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5704 5705 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5706 5707 return 0; 5708 } 5709 5710 static int 5711 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5712 const char *value, void *opaque_arg) 5713 { 5714 struct bnxt_representor *vfr_bp = opaque_arg; 5715 unsigned long rep_q_r2f; 5716 char *end = NULL; 5717 5718 if (!value || !opaque_arg) { 5719 PMD_DRV_LOG(ERR, 5720 "Invalid parameter passed to rep_q_r2f " 5721 "devargs.\n"); 5722 return -EINVAL; 5723 } 5724 5725 rep_q_r2f = strtoul(value, &end, 10); 5726 if (end == NULL || *end != '\0' || 5727 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5728 PMD_DRV_LOG(ERR, 5729 "Invalid parameter passed to rep_q_r2f " 5730 "devargs.\n"); 5731 return -EINVAL; 5732 } 5733 5734 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5735 PMD_DRV_LOG(ERR, 5736 "Invalid value passed to rep_q_r2f devargs.\n"); 5737 return -EINVAL; 5738 } 5739 5740 vfr_bp->rep_q_r2f = rep_q_r2f; 5741 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5742 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5743 5744 return 0; 5745 } 5746 5747 static int 5748 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5749 const char *value, void *opaque_arg) 5750 { 5751 struct bnxt_representor *vfr_bp = opaque_arg; 5752 unsigned long rep_q_f2r; 5753 char *end = NULL; 5754 5755 if (!value || !opaque_arg) { 5756 PMD_DRV_LOG(ERR, 5757 "Invalid parameter passed to rep_q_f2r " 5758 "devargs.\n"); 5759 return -EINVAL; 5760 } 5761 5762 rep_q_f2r = strtoul(value, &end, 10); 5763 if (end == NULL || *end != '\0' || 5764 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5765 PMD_DRV_LOG(ERR, 5766 "Invalid parameter passed to rep_q_f2r " 5767 "devargs.\n"); 5768 return -EINVAL; 5769 } 5770 5771 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5772 PMD_DRV_LOG(ERR, 5773 "Invalid value passed to rep_q_f2r devargs.\n"); 5774 return -EINVAL; 5775 } 5776 5777 vfr_bp->rep_q_f2r = rep_q_f2r; 5778 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5779 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5780 5781 return 0; 5782 } 5783 5784 static int 5785 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5786 const char *value, void *opaque_arg) 5787 { 5788 struct bnxt_representor *vfr_bp = opaque_arg; 5789 unsigned long rep_fc_r2f; 5790 char *end = NULL; 5791 5792 if (!value || !opaque_arg) { 5793 PMD_DRV_LOG(ERR, 5794 "Invalid parameter passed to rep_fc_r2f " 5795 "devargs.\n"); 5796 return -EINVAL; 5797 } 5798 5799 rep_fc_r2f = strtoul(value, &end, 10); 5800 if (end == NULL || *end != '\0' || 5801 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5802 PMD_DRV_LOG(ERR, 5803 "Invalid parameter passed to rep_fc_r2f " 5804 "devargs.\n"); 5805 return -EINVAL; 5806 } 5807 5808 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5809 PMD_DRV_LOG(ERR, 5810 "Invalid value passed to rep_fc_r2f devargs.\n"); 5811 return -EINVAL; 5812 } 5813 5814 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5815 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5816 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5817 5818 return 0; 5819 } 5820 5821 static int 5822 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5823 const char *value, void *opaque_arg) 5824 { 5825 struct bnxt_representor *vfr_bp = opaque_arg; 5826 unsigned long rep_fc_f2r; 5827 char *end = NULL; 5828 5829 if (!value || !opaque_arg) { 5830 PMD_DRV_LOG(ERR, 5831 "Invalid parameter passed to rep_fc_f2r " 5832 "devargs.\n"); 5833 return -EINVAL; 5834 } 5835 5836 rep_fc_f2r = strtoul(value, &end, 10); 5837 if (end == NULL || *end != '\0' || 5838 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5839 PMD_DRV_LOG(ERR, 5840 "Invalid parameter passed to rep_fc_f2r " 5841 "devargs.\n"); 5842 return -EINVAL; 5843 } 5844 5845 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5846 PMD_DRV_LOG(ERR, 5847 "Invalid value passed to rep_fc_f2r devargs.\n"); 5848 return -EINVAL; 5849 } 5850 5851 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5852 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5853 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5854 5855 return 0; 5856 } 5857 5858 static int 5859 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5860 { 5861 struct rte_kvargs *kvlist; 5862 int ret; 5863 5864 if (devargs == NULL) 5865 return 0; 5866 5867 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5868 if (kvlist == NULL) 5869 return -EINVAL; 5870 5871 /* 5872 * Handler for "flow_xstat" devarg. 5873 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5874 */ 5875 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5876 bnxt_parse_devarg_flow_xstat, bp); 5877 if (ret) 5878 goto err; 5879 5880 /* 5881 * Handler for "accum-stats" devarg. 5882 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" 5883 */ 5884 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, 5885 bnxt_parse_devarg_accum_stats, bp); 5886 /* 5887 * Handler for "max_num_kflows" devarg. 5888 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5889 */ 5890 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5891 bnxt_parse_devarg_max_num_kflows, bp); 5892 if (ret) 5893 goto err; 5894 5895 err: 5896 /* 5897 * Handler for "app-id" devarg. 5898 * Invoked as for ex: "-a 000:00:0d.0,app-id=1" 5899 */ 5900 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID, 5901 bnxt_parse_devarg_app_id, bp); 5902 5903 rte_kvargs_free(kvlist); 5904 return ret; 5905 } 5906 5907 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5908 { 5909 int rc = 0; 5910 5911 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5912 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5913 if (rc) 5914 PMD_DRV_LOG(ERR, 5915 "Failed to alloc switch domain: %d\n", rc); 5916 else 5917 PMD_DRV_LOG(INFO, 5918 "Switch domain allocated %d\n", 5919 bp->switch_domain_id); 5920 } 5921 5922 return rc; 5923 } 5924 5925 /* Allocate and initialize various fields in bnxt struct that 5926 * need to be allocated/destroyed only once in the lifetime of the driver 5927 */ 5928 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5929 { 5930 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5931 struct bnxt *bp = eth_dev->data->dev_private; 5932 int rc = 0; 5933 5934 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5935 5936 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5937 bp->flags |= BNXT_FLAG_VF; 5938 5939 if (bnxt_p5_device(pci_dev->id.device_id)) 5940 bp->flags |= BNXT_FLAG_CHIP_P5; 5941 5942 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5943 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5944 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5945 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5946 bp->flags |= BNXT_FLAG_STINGRAY; 5947 5948 if (BNXT_TRUFLOW_EN(bp)) { 5949 /* extra mbuf field is required to store CFA code from mark */ 5950 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5951 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5952 .size = sizeof(bnxt_cfa_code_dynfield_t), 5953 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5954 }; 5955 bnxt_cfa_code_dynfield_offset = 5956 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5957 if (bnxt_cfa_code_dynfield_offset < 0) { 5958 PMD_DRV_LOG(ERR, 5959 "Failed to register mbuf field for TruFlow mark\n"); 5960 return -rte_errno; 5961 } 5962 } 5963 5964 rc = bnxt_map_pci_bars(eth_dev); 5965 if (rc) { 5966 PMD_DRV_LOG(ERR, 5967 "Failed to initialize board rc: %x\n", rc); 5968 return rc; 5969 } 5970 5971 rc = bnxt_alloc_pf_info(bp); 5972 if (rc) 5973 return rc; 5974 5975 rc = bnxt_alloc_link_info(bp); 5976 if (rc) 5977 return rc; 5978 5979 rc = bnxt_alloc_parent_info(bp); 5980 if (rc) 5981 return rc; 5982 5983 rc = bnxt_alloc_hwrm_resources(bp); 5984 if (rc) { 5985 PMD_DRV_LOG(ERR, 5986 "Failed to allocate response buffer rc: %x\n", rc); 5987 return rc; 5988 } 5989 rc = bnxt_alloc_leds_info(bp); 5990 if (rc) 5991 return rc; 5992 5993 rc = bnxt_alloc_cos_queues(bp); 5994 if (rc) 5995 return rc; 5996 5997 rc = bnxt_init_locks(bp); 5998 if (rc) 5999 return rc; 6000 6001 rc = bnxt_alloc_switch_domain(bp); 6002 if (rc) 6003 return rc; 6004 6005 return rc; 6006 } 6007 6008 static int 6009 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 6010 { 6011 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 6012 static int version_printed; 6013 struct bnxt *bp; 6014 int rc; 6015 6016 if (version_printed++ == 0) 6017 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 6018 6019 eth_dev->dev_ops = &bnxt_dev_ops; 6020 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 6021 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 6022 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 6023 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 6024 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 6025 6026 /* 6027 * For secondary processes, we don't initialise any further 6028 * as primary has already done this work. 6029 */ 6030 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6031 return 0; 6032 6033 rte_eth_copy_pci_info(eth_dev, pci_dev); 6034 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 6035 6036 bp = eth_dev->data->dev_private; 6037 6038 /* Parse dev arguments passed on when starting the DPDK application. */ 6039 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 6040 if (rc) 6041 goto error_free; 6042 6043 rc = bnxt_drv_init(eth_dev); 6044 if (rc) 6045 goto error_free; 6046 6047 rc = bnxt_init_resources(bp, false); 6048 if (rc) 6049 goto error_free; 6050 6051 rc = bnxt_alloc_stats_mem(bp); 6052 if (rc) 6053 goto error_free; 6054 6055 PMD_DRV_LOG(INFO, 6056 "Found %s device at mem %" PRIX64 ", node addr %pM\n", 6057 DRV_MODULE_NAME, 6058 pci_dev->mem_resource[0].phys_addr, 6059 pci_dev->mem_resource[0].addr); 6060 6061 return 0; 6062 6063 error_free: 6064 bnxt_dev_uninit(eth_dev); 6065 return rc; 6066 } 6067 6068 6069 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 6070 { 6071 if (!ctx) 6072 return; 6073 6074 if (ctx->va) 6075 rte_free(ctx->va); 6076 6077 ctx->va = NULL; 6078 ctx->dma = RTE_BAD_IOVA; 6079 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 6080 } 6081 6082 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 6083 { 6084 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 6085 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6086 bp->flow_stat->rx_fc_out_tbl.ctx_id, 6087 bp->flow_stat->max_fc, 6088 false); 6089 6090 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 6091 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6092 bp->flow_stat->tx_fc_out_tbl.ctx_id, 6093 bp->flow_stat->max_fc, 6094 false); 6095 6096 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6097 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 6098 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6099 6100 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6101 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 6102 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6103 6104 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6105 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 6106 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6107 6108 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6109 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 6110 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6111 } 6112 6113 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 6114 { 6115 bnxt_unregister_fc_ctx_mem(bp); 6116 6117 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 6118 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 6119 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 6120 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 6121 } 6122 6123 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 6124 { 6125 if (BNXT_FLOW_XSTATS_EN(bp)) 6126 bnxt_uninit_fc_ctx_mem(bp); 6127 } 6128 6129 static void 6130 bnxt_free_error_recovery_info(struct bnxt *bp) 6131 { 6132 rte_free(bp->recovery_info); 6133 bp->recovery_info = NULL; 6134 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 6135 } 6136 6137 static int 6138 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 6139 { 6140 int rc; 6141 6142 bnxt_free_int(bp); 6143 bnxt_free_mem(bp, reconfig_dev); 6144 6145 bnxt_hwrm_func_buf_unrgtr(bp); 6146 if (bp->pf != NULL) { 6147 rte_free(bp->pf->vf_req_buf); 6148 bp->pf->vf_req_buf = NULL; 6149 } 6150 6151 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 6152 bp->flags &= ~BNXT_FLAG_REGISTERED; 6153 bnxt_free_ctx_mem(bp); 6154 if (!reconfig_dev) { 6155 bnxt_free_hwrm_resources(bp); 6156 bnxt_free_error_recovery_info(bp); 6157 } 6158 6159 bnxt_uninit_ctx_mem(bp); 6160 6161 bnxt_free_flow_stats_info(bp); 6162 if (bp->rep_info != NULL) 6163 bnxt_free_switch_domain(bp); 6164 bnxt_free_rep_info(bp); 6165 rte_free(bp->ptp_cfg); 6166 bp->ptp_cfg = NULL; 6167 return rc; 6168 } 6169 6170 static int 6171 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 6172 { 6173 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6174 return -EPERM; 6175 6176 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 6177 6178 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 6179 bnxt_dev_close_op(eth_dev); 6180 6181 return 0; 6182 } 6183 6184 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 6185 { 6186 struct bnxt *bp = eth_dev->data->dev_private; 6187 struct rte_eth_dev *vf_rep_eth_dev; 6188 int ret = 0, i; 6189 6190 if (!bp) 6191 return -EINVAL; 6192 6193 for (i = 0; i < bp->num_reps; i++) { 6194 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 6195 if (!vf_rep_eth_dev) 6196 continue; 6197 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 6198 vf_rep_eth_dev->data->port_id); 6199 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 6200 } 6201 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 6202 eth_dev->data->port_id); 6203 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 6204 6205 return ret; 6206 } 6207 6208 static void bnxt_free_rep_info(struct bnxt *bp) 6209 { 6210 rte_free(bp->rep_info); 6211 bp->rep_info = NULL; 6212 rte_free(bp->cfa_code_map); 6213 bp->cfa_code_map = NULL; 6214 } 6215 6216 static int bnxt_init_rep_info(struct bnxt *bp) 6217 { 6218 int i = 0, rc; 6219 6220 if (bp->rep_info) 6221 return 0; 6222 6223 bp->rep_info = rte_zmalloc("bnxt_rep_info", 6224 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 6225 0); 6226 if (!bp->rep_info) { 6227 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 6228 return -ENOMEM; 6229 } 6230 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 6231 sizeof(*bp->cfa_code_map) * 6232 BNXT_MAX_CFA_CODE, 0); 6233 if (!bp->cfa_code_map) { 6234 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 6235 bnxt_free_rep_info(bp); 6236 return -ENOMEM; 6237 } 6238 6239 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 6240 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 6241 6242 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 6243 if (rc) { 6244 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 6245 bnxt_free_rep_info(bp); 6246 return rc; 6247 } 6248 6249 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 6250 if (rc) { 6251 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 6252 bnxt_free_rep_info(bp); 6253 return rc; 6254 } 6255 6256 return rc; 6257 } 6258 6259 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 6260 struct rte_eth_devargs *eth_da, 6261 struct rte_eth_dev *backing_eth_dev, 6262 const char *dev_args) 6263 { 6264 struct rte_eth_dev *vf_rep_eth_dev; 6265 char name[RTE_ETH_NAME_MAX_LEN]; 6266 struct bnxt *backing_bp; 6267 uint16_t num_rep; 6268 int i, ret = 0; 6269 struct rte_kvargs *kvlist = NULL; 6270 6271 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 6272 return 0; 6273 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 6274 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 6275 eth_da->type); 6276 return -ENOTSUP; 6277 } 6278 num_rep = eth_da->nb_representor_ports; 6279 if (num_rep > BNXT_MAX_VF_REPS) { 6280 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 6281 num_rep, BNXT_MAX_VF_REPS); 6282 return -EINVAL; 6283 } 6284 6285 if (num_rep >= RTE_MAX_ETHPORTS) { 6286 PMD_DRV_LOG(ERR, 6287 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 6288 num_rep, RTE_MAX_ETHPORTS); 6289 return -EINVAL; 6290 } 6291 6292 backing_bp = backing_eth_dev->data->dev_private; 6293 6294 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 6295 PMD_DRV_LOG(ERR, 6296 "Not a PF or trusted VF. No Representor support\n"); 6297 /* Returning an error is not an option. 6298 * Applications are not handling this correctly 6299 */ 6300 return 0; 6301 } 6302 6303 if (bnxt_init_rep_info(backing_bp)) 6304 return 0; 6305 6306 for (i = 0; i < num_rep; i++) { 6307 struct bnxt_representor representor = { 6308 .vf_id = eth_da->representor_ports[i], 6309 .switch_domain_id = backing_bp->switch_domain_id, 6310 .parent_dev = backing_eth_dev 6311 }; 6312 6313 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 6314 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 6315 representor.vf_id, BNXT_MAX_VF_REPS); 6316 continue; 6317 } 6318 6319 /* representor port net_bdf_port */ 6320 snprintf(name, sizeof(name), "net_%s_representor_%d", 6321 pci_dev->device.name, eth_da->representor_ports[i]); 6322 6323 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 6324 if (kvlist) { 6325 /* 6326 * Handler for "rep_is_pf" devarg. 6327 * Invoked as for ex: "-a 000:00:0d.0, 6328 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6329 */ 6330 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 6331 bnxt_parse_devarg_rep_is_pf, 6332 (void *)&representor); 6333 if (ret) { 6334 ret = -EINVAL; 6335 goto err; 6336 } 6337 /* 6338 * Handler for "rep_based_pf" devarg. 6339 * Invoked as for ex: "-a 000:00:0d.0, 6340 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6341 */ 6342 ret = rte_kvargs_process(kvlist, 6343 BNXT_DEVARG_REP_BASED_PF, 6344 bnxt_parse_devarg_rep_based_pf, 6345 (void *)&representor); 6346 if (ret) { 6347 ret = -EINVAL; 6348 goto err; 6349 } 6350 /* 6351 * Handler for "rep_based_pf" devarg. 6352 * Invoked as for ex: "-a 000:00:0d.0, 6353 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6354 */ 6355 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 6356 bnxt_parse_devarg_rep_q_r2f, 6357 (void *)&representor); 6358 if (ret) { 6359 ret = -EINVAL; 6360 goto err; 6361 } 6362 /* 6363 * Handler for "rep_based_pf" devarg. 6364 * Invoked as for ex: "-a 000:00:0d.0, 6365 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6366 */ 6367 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 6368 bnxt_parse_devarg_rep_q_f2r, 6369 (void *)&representor); 6370 if (ret) { 6371 ret = -EINVAL; 6372 goto err; 6373 } 6374 /* 6375 * Handler for "rep_based_pf" devarg. 6376 * Invoked as for ex: "-a 000:00:0d.0, 6377 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6378 */ 6379 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 6380 bnxt_parse_devarg_rep_fc_r2f, 6381 (void *)&representor); 6382 if (ret) { 6383 ret = -EINVAL; 6384 goto err; 6385 } 6386 /* 6387 * Handler for "rep_based_pf" devarg. 6388 * Invoked as for ex: "-a 000:00:0d.0, 6389 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6390 */ 6391 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 6392 bnxt_parse_devarg_rep_fc_f2r, 6393 (void *)&representor); 6394 if (ret) { 6395 ret = -EINVAL; 6396 goto err; 6397 } 6398 } 6399 6400 ret = rte_eth_dev_create(&pci_dev->device, name, 6401 sizeof(struct bnxt_representor), 6402 NULL, NULL, 6403 bnxt_representor_init, 6404 &representor); 6405 if (ret) { 6406 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6407 "representor %s.", name); 6408 goto err; 6409 } 6410 6411 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6412 if (!vf_rep_eth_dev) { 6413 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6414 " for VF-Rep: %s.", name); 6415 ret = -ENODEV; 6416 goto err; 6417 } 6418 6419 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6420 backing_eth_dev->data->port_id); 6421 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6422 vf_rep_eth_dev; 6423 backing_bp->num_reps++; 6424 6425 } 6426 6427 rte_kvargs_free(kvlist); 6428 return 0; 6429 6430 err: 6431 /* If num_rep > 1, then rollback already created 6432 * ports, since we'll be failing the probe anyway 6433 */ 6434 if (num_rep > 1) 6435 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6436 rte_errno = -ret; 6437 rte_kvargs_free(kvlist); 6438 6439 return ret; 6440 } 6441 6442 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6443 struct rte_pci_device *pci_dev) 6444 { 6445 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6446 struct rte_eth_dev *backing_eth_dev; 6447 uint16_t num_rep; 6448 int ret = 0; 6449 6450 if (pci_dev->device.devargs) { 6451 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6452 ð_da); 6453 if (ret) 6454 return ret; 6455 } 6456 6457 num_rep = eth_da.nb_representor_ports; 6458 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6459 num_rep); 6460 6461 /* We could come here after first level of probe is already invoked 6462 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6463 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6464 */ 6465 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6466 if (backing_eth_dev == NULL) { 6467 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6468 sizeof(struct bnxt), 6469 eth_dev_pci_specific_init, pci_dev, 6470 bnxt_dev_init, NULL); 6471 6472 if (ret || !num_rep) 6473 return ret; 6474 6475 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6476 } 6477 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6478 backing_eth_dev->data->port_id); 6479 6480 if (!num_rep) 6481 return ret; 6482 6483 /* probe representor ports now */ 6484 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6485 pci_dev->device.devargs->args); 6486 6487 return ret; 6488 } 6489 6490 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6491 { 6492 struct rte_eth_dev *eth_dev; 6493 6494 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6495 if (!eth_dev) 6496 return 0; /* Invoked typically only by OVS-DPDK, by the 6497 * time it comes here the eth_dev is already 6498 * deleted by rte_eth_dev_close(), so returning 6499 * +ve value will at least help in proper cleanup 6500 */ 6501 6502 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6503 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6504 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6505 return rte_eth_dev_destroy(eth_dev, 6506 bnxt_representor_uninit); 6507 else 6508 return rte_eth_dev_destroy(eth_dev, 6509 bnxt_dev_uninit); 6510 } else { 6511 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6512 } 6513 } 6514 6515 static struct rte_pci_driver bnxt_rte_pmd = { 6516 .id_table = bnxt_pci_id_map, 6517 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6518 RTE_PCI_DRV_INTR_RMV | 6519 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6520 * and OVS-DPDK 6521 */ 6522 .probe = bnxt_pci_probe, 6523 .remove = bnxt_pci_remove, 6524 }; 6525 6526 static bool 6527 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6528 { 6529 if (strcmp(dev->device->driver->name, drv->driver.name)) 6530 return false; 6531 6532 return true; 6533 } 6534 6535 bool is_bnxt_supported(struct rte_eth_dev *dev) 6536 { 6537 return is_device_supported(dev, &bnxt_rte_pmd); 6538 } 6539 6540 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE); 6541 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6542 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6543 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6544