1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 17 #include "bnxt.h" 18 #include "bnxt_filter.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_irq.h" 21 #include "bnxt_reps.h" 22 #include "bnxt_ring.h" 23 #include "bnxt_rxq.h" 24 #include "bnxt_rxr.h" 25 #include "bnxt_stats.h" 26 #include "bnxt_txq.h" 27 #include "bnxt_txr.h" 28 #include "bnxt_vnic.h" 29 #include "hsi_struct_def_dpdk.h" 30 #include "bnxt_nvm_defs.h" 31 #include "bnxt_tf_common.h" 32 #include "ulp_flow_db.h" 33 34 #define DRV_MODULE_NAME "bnxt" 35 static const char bnxt_version[] = 36 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 37 38 /* 39 * The set of PCI devices this driver supports 40 */ 41 static const struct rte_pci_id bnxt_pci_id_map[] = { 42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 95 { .vendor_id = 0, /* sentinel */ }, 96 }; 97 98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 101 #define BNXT_DEVARG_REPRESENTOR "representor" 102 103 static const char *const bnxt_dev_args[] = { 104 BNXT_DEVARG_REPRESENTOR, 105 BNXT_DEVARG_TRUFLOW, 106 BNXT_DEVARG_FLOW_XSTAT, 107 BNXT_DEVARG_MAX_NUM_KFLOWS, 108 NULL 109 }; 110 111 /* 112 * truflow == false to disable the feature 113 * truflow == true to enable the feature 114 */ 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 116 117 /* 118 * flow_xstat == false to disable the feature 119 * flow_xstat == true to enable the feature 120 */ 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 122 123 /* 124 * max_num_kflows must be >= 32 125 * and must be a power-of-2 supported value 126 * return: 1 -> invalid 127 * 0 -> valid 128 */ 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 130 { 131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 132 return 1; 133 return 0; 134 } 135 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 141 static int bnxt_restore_vlan_filters(struct bnxt *bp); 142 static void bnxt_dev_recover(void *arg); 143 static void bnxt_free_error_recovery_info(struct bnxt *bp); 144 static void bnxt_free_rep_info(struct bnxt *bp); 145 146 int is_bnxt_in_error(struct bnxt *bp) 147 { 148 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 149 return -EIO; 150 if (bp->flags & BNXT_FLAG_FW_RESET) 151 return -EBUSY; 152 153 return 0; 154 } 155 156 /***********************/ 157 158 /* 159 * High level utility functions 160 */ 161 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 163 { 164 if (!BNXT_CHIP_THOR(bp)) 165 return 1; 166 167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 168 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 169 BNXT_RSS_ENTRIES_PER_CTX_THOR; 170 } 171 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 173 { 174 if (!BNXT_CHIP_THOR(bp)) 175 return HW_HASH_INDEX_SIZE; 176 177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 178 } 179 180 static void bnxt_free_parent_info(struct bnxt *bp) 181 { 182 rte_free(bp->parent); 183 } 184 185 static void bnxt_free_pf_info(struct bnxt *bp) 186 { 187 rte_free(bp->pf); 188 } 189 190 static void bnxt_free_link_info(struct bnxt *bp) 191 { 192 rte_free(bp->link_info); 193 } 194 195 static void bnxt_free_leds_info(struct bnxt *bp) 196 { 197 if (BNXT_VF(bp)) 198 return; 199 200 rte_free(bp->leds); 201 bp->leds = NULL; 202 } 203 204 static void bnxt_free_flow_stats_info(struct bnxt *bp) 205 { 206 rte_free(bp->flow_stat); 207 bp->flow_stat = NULL; 208 } 209 210 static void bnxt_free_cos_queues(struct bnxt *bp) 211 { 212 rte_free(bp->rx_cos_queue); 213 rte_free(bp->tx_cos_queue); 214 } 215 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 217 { 218 bnxt_free_filter_mem(bp); 219 bnxt_free_vnic_attributes(bp); 220 bnxt_free_vnic_mem(bp); 221 222 /* tx/rx rings are configured as part of *_queue_setup callbacks. 223 * If the number of rings change across fw update, 224 * we don't have much choice except to warn the user. 225 */ 226 if (!reconfig) { 227 bnxt_free_stats(bp); 228 bnxt_free_tx_rings(bp); 229 bnxt_free_rx_rings(bp); 230 } 231 bnxt_free_async_cp_ring(bp); 232 bnxt_free_rxtx_nq_ring(bp); 233 234 rte_free(bp->grp_info); 235 bp->grp_info = NULL; 236 } 237 238 static int bnxt_alloc_parent_info(struct bnxt *bp) 239 { 240 bp->parent = rte_zmalloc("bnxt_parent_info", 241 sizeof(struct bnxt_parent_info), 0); 242 if (bp->parent == NULL) 243 return -ENOMEM; 244 245 return 0; 246 } 247 248 static int bnxt_alloc_pf_info(struct bnxt *bp) 249 { 250 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 251 if (bp->pf == NULL) 252 return -ENOMEM; 253 254 return 0; 255 } 256 257 static int bnxt_alloc_link_info(struct bnxt *bp) 258 { 259 bp->link_info = 260 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 261 if (bp->link_info == NULL) 262 return -ENOMEM; 263 264 return 0; 265 } 266 267 static int bnxt_alloc_leds_info(struct bnxt *bp) 268 { 269 if (BNXT_VF(bp)) 270 return 0; 271 272 bp->leds = rte_zmalloc("bnxt_leds", 273 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 274 0); 275 if (bp->leds == NULL) 276 return -ENOMEM; 277 278 return 0; 279 } 280 281 static int bnxt_alloc_cos_queues(struct bnxt *bp) 282 { 283 bp->rx_cos_queue = 284 rte_zmalloc("bnxt_rx_cosq", 285 BNXT_COS_QUEUE_COUNT * 286 sizeof(struct bnxt_cos_queue_info), 287 0); 288 if (bp->rx_cos_queue == NULL) 289 return -ENOMEM; 290 291 bp->tx_cos_queue = 292 rte_zmalloc("bnxt_tx_cosq", 293 BNXT_COS_QUEUE_COUNT * 294 sizeof(struct bnxt_cos_queue_info), 295 0); 296 if (bp->tx_cos_queue == NULL) 297 return -ENOMEM; 298 299 return 0; 300 } 301 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 303 { 304 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 305 sizeof(struct bnxt_flow_stat_info), 0); 306 if (bp->flow_stat == NULL) 307 return -ENOMEM; 308 309 return 0; 310 } 311 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 313 { 314 int rc; 315 316 rc = bnxt_alloc_ring_grps(bp); 317 if (rc) 318 goto alloc_mem_err; 319 320 rc = bnxt_alloc_async_ring_struct(bp); 321 if (rc) 322 goto alloc_mem_err; 323 324 rc = bnxt_alloc_vnic_mem(bp); 325 if (rc) 326 goto alloc_mem_err; 327 328 rc = bnxt_alloc_vnic_attributes(bp); 329 if (rc) 330 goto alloc_mem_err; 331 332 rc = bnxt_alloc_filter_mem(bp); 333 if (rc) 334 goto alloc_mem_err; 335 336 rc = bnxt_alloc_async_cp_ring(bp); 337 if (rc) 338 goto alloc_mem_err; 339 340 rc = bnxt_alloc_rxtx_nq_ring(bp); 341 if (rc) 342 goto alloc_mem_err; 343 344 if (BNXT_FLOW_XSTATS_EN(bp)) { 345 rc = bnxt_alloc_flow_stats_info(bp); 346 if (rc) 347 goto alloc_mem_err; 348 } 349 350 return 0; 351 352 alloc_mem_err: 353 bnxt_free_mem(bp, reconfig); 354 return rc; 355 } 356 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 358 { 359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 360 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 361 uint64_t rx_offloads = dev_conf->rxmode.offloads; 362 struct bnxt_rx_queue *rxq; 363 unsigned int j; 364 int rc; 365 366 rc = bnxt_vnic_grp_alloc(bp, vnic); 367 if (rc) 368 goto err_out; 369 370 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 371 vnic_id, vnic, vnic->fw_grp_ids); 372 373 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 374 if (rc) 375 goto err_out; 376 377 /* Alloc RSS context only if RSS mode is enabled */ 378 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 379 int j, nr_ctxs = bnxt_rss_ctxts(bp); 380 381 rc = 0; 382 for (j = 0; j < nr_ctxs; j++) { 383 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 384 if (rc) 385 break; 386 } 387 if (rc) { 388 PMD_DRV_LOG(ERR, 389 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 390 vnic_id, j, rc); 391 goto err_out; 392 } 393 vnic->num_lb_ctxts = nr_ctxs; 394 } 395 396 /* 397 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 398 * setting is not available at this time, it will not be 399 * configured correctly in the CFA. 400 */ 401 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 402 vnic->vlan_strip = true; 403 else 404 vnic->vlan_strip = false; 405 406 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 407 if (rc) 408 goto err_out; 409 410 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 411 if (rc) 412 goto err_out; 413 414 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 415 rxq = bp->eth_dev->data->rx_queues[j]; 416 417 PMD_DRV_LOG(DEBUG, 418 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 419 j, rxq->vnic, rxq->vnic->fw_grp_ids); 420 421 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 422 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 423 else 424 vnic->rx_queue_cnt++; 425 } 426 427 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 428 429 rc = bnxt_vnic_rss_configure(bp, vnic); 430 if (rc) 431 goto err_out; 432 433 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 434 435 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 436 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 437 else 438 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 439 440 return 0; 441 err_out: 442 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 443 vnic_id, rc); 444 return rc; 445 } 446 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 448 { 449 int rc = 0; 450 451 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 452 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 453 if (rc) 454 return rc; 455 456 PMD_DRV_LOG(DEBUG, 457 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 458 " rx_fc_in_tbl.ctx_id = %d\n", 459 bp->flow_stat->rx_fc_in_tbl.va, 460 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 461 bp->flow_stat->rx_fc_in_tbl.ctx_id); 462 463 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 464 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 465 if (rc) 466 return rc; 467 468 PMD_DRV_LOG(DEBUG, 469 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 470 " rx_fc_out_tbl.ctx_id = %d\n", 471 bp->flow_stat->rx_fc_out_tbl.va, 472 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 473 bp->flow_stat->rx_fc_out_tbl.ctx_id); 474 475 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 476 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 477 if (rc) 478 return rc; 479 480 PMD_DRV_LOG(DEBUG, 481 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 482 " tx_fc_in_tbl.ctx_id = %d\n", 483 bp->flow_stat->tx_fc_in_tbl.va, 484 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 485 bp->flow_stat->tx_fc_in_tbl.ctx_id); 486 487 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 488 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 489 if (rc) 490 return rc; 491 492 PMD_DRV_LOG(DEBUG, 493 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 494 " tx_fc_out_tbl.ctx_id = %d\n", 495 bp->flow_stat->tx_fc_out_tbl.va, 496 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 497 bp->flow_stat->tx_fc_out_tbl.ctx_id); 498 499 memset(bp->flow_stat->rx_fc_out_tbl.va, 500 0, 501 bp->flow_stat->rx_fc_out_tbl.size); 502 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 503 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 504 bp->flow_stat->rx_fc_out_tbl.ctx_id, 505 bp->flow_stat->max_fc, 506 true); 507 if (rc) 508 return rc; 509 510 memset(bp->flow_stat->tx_fc_out_tbl.va, 511 0, 512 bp->flow_stat->tx_fc_out_tbl.size); 513 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 514 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 515 bp->flow_stat->tx_fc_out_tbl.ctx_id, 516 bp->flow_stat->max_fc, 517 true); 518 519 return rc; 520 } 521 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 523 struct bnxt_ctx_mem_buf_info *ctx) 524 { 525 if (!ctx) 526 return -EINVAL; 527 528 ctx->va = rte_zmalloc(type, size, 0); 529 if (ctx->va == NULL) 530 return -ENOMEM; 531 rte_mem_lock_page(ctx->va); 532 ctx->size = size; 533 ctx->dma = rte_mem_virt2iova(ctx->va); 534 if (ctx->dma == RTE_BAD_IOVA) 535 return -ENOMEM; 536 537 return 0; 538 } 539 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 541 { 542 struct rte_pci_device *pdev = bp->pdev; 543 char type[RTE_MEMZONE_NAMESIZE]; 544 uint16_t max_fc; 545 int rc = 0; 546 547 max_fc = bp->flow_stat->max_fc; 548 549 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 551 /* 4 bytes for each counter-id */ 552 rc = bnxt_alloc_ctx_mem_buf(type, 553 max_fc * 4, 554 &bp->flow_stat->rx_fc_in_tbl); 555 if (rc) 556 return rc; 557 558 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 560 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 561 rc = bnxt_alloc_ctx_mem_buf(type, 562 max_fc * 16, 563 &bp->flow_stat->rx_fc_out_tbl); 564 if (rc) 565 return rc; 566 567 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 569 /* 4 bytes for each counter-id */ 570 rc = bnxt_alloc_ctx_mem_buf(type, 571 max_fc * 4, 572 &bp->flow_stat->tx_fc_in_tbl); 573 if (rc) 574 return rc; 575 576 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 578 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 579 rc = bnxt_alloc_ctx_mem_buf(type, 580 max_fc * 16, 581 &bp->flow_stat->tx_fc_out_tbl); 582 if (rc) 583 return rc; 584 585 rc = bnxt_register_fc_ctx_mem(bp); 586 587 return rc; 588 } 589 590 static int bnxt_init_ctx_mem(struct bnxt *bp) 591 { 592 int rc = 0; 593 594 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 595 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 596 !BNXT_FLOW_XSTATS_EN(bp)) 597 return 0; 598 599 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 600 if (rc) 601 return rc; 602 603 rc = bnxt_init_fc_ctx_mem(bp); 604 605 return rc; 606 } 607 608 static int bnxt_update_phy_setting(struct bnxt *bp) 609 { 610 struct rte_eth_link new; 611 int rc; 612 613 rc = bnxt_get_hwrm_link_config(bp, &new); 614 if (rc) { 615 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 616 return rc; 617 } 618 619 /* 620 * On BCM957508-N2100 adapters, FW will not allow any user other 621 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 622 * always returns link up. Force phy update always in that case. 623 */ 624 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 625 rc = bnxt_set_hwrm_link_config(bp, true); 626 if (rc) { 627 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 628 return rc; 629 } 630 } 631 632 return rc; 633 } 634 635 static int bnxt_init_chip(struct bnxt *bp) 636 { 637 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 638 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 639 uint32_t intr_vector = 0; 640 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 641 uint32_t vec = BNXT_MISC_VEC_ID; 642 unsigned int i, j; 643 int rc; 644 645 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 646 bp->eth_dev->data->dev_conf.rxmode.offloads |= 647 DEV_RX_OFFLOAD_JUMBO_FRAME; 648 bp->flags |= BNXT_FLAG_JUMBO; 649 } else { 650 bp->eth_dev->data->dev_conf.rxmode.offloads &= 651 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 652 bp->flags &= ~BNXT_FLAG_JUMBO; 653 } 654 655 /* THOR does not support ring groups. 656 * But we will use the array to save RSS context IDs. 657 */ 658 if (BNXT_CHIP_THOR(bp)) 659 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 660 661 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 662 if (rc) { 663 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 664 goto err_out; 665 } 666 667 rc = bnxt_alloc_hwrm_rings(bp); 668 if (rc) { 669 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 670 goto err_out; 671 } 672 673 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 674 if (rc) { 675 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 676 goto err_out; 677 } 678 679 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 680 goto skip_cosq_cfg; 681 682 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 683 if (bp->rx_cos_queue[i].id != 0xff) { 684 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 685 686 if (!vnic) { 687 PMD_DRV_LOG(ERR, 688 "Num pools more than FW profile\n"); 689 rc = -EINVAL; 690 goto err_out; 691 } 692 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 693 bp->rx_cosq_cnt++; 694 } 695 } 696 697 skip_cosq_cfg: 698 rc = bnxt_mq_rx_configure(bp); 699 if (rc) { 700 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 701 goto err_out; 702 } 703 704 /* VNIC configuration */ 705 for (i = 0; i < bp->nr_vnics; i++) { 706 rc = bnxt_setup_one_vnic(bp, i); 707 if (rc) 708 goto err_out; 709 } 710 711 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 712 if (rc) { 713 PMD_DRV_LOG(ERR, 714 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 715 goto err_out; 716 } 717 718 /* check and configure queue intr-vector mapping */ 719 if ((rte_intr_cap_multiple(intr_handle) || 720 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 721 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 722 intr_vector = bp->eth_dev->data->nb_rx_queues; 723 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 724 if (intr_vector > bp->rx_cp_nr_rings) { 725 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 726 bp->rx_cp_nr_rings); 727 return -ENOTSUP; 728 } 729 rc = rte_intr_efd_enable(intr_handle, intr_vector); 730 if (rc) 731 return rc; 732 } 733 734 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 735 intr_handle->intr_vec = 736 rte_zmalloc("intr_vec", 737 bp->eth_dev->data->nb_rx_queues * 738 sizeof(int), 0); 739 if (intr_handle->intr_vec == NULL) { 740 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 741 " intr_vec", bp->eth_dev->data->nb_rx_queues); 742 rc = -ENOMEM; 743 goto err_disable; 744 } 745 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 746 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 747 intr_handle->intr_vec, intr_handle->nb_efd, 748 intr_handle->max_intr); 749 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 750 queue_id++) { 751 intr_handle->intr_vec[queue_id] = 752 vec + BNXT_RX_VEC_START; 753 if (vec < base + intr_handle->nb_efd - 1) 754 vec++; 755 } 756 } 757 758 /* enable uio/vfio intr/eventfd mapping */ 759 rc = rte_intr_enable(intr_handle); 760 #ifndef RTE_EXEC_ENV_FREEBSD 761 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 762 if (rc) 763 goto err_free; 764 #endif 765 766 rc = bnxt_update_phy_setting(bp); 767 if (rc) 768 goto err_free; 769 770 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 771 if (!bp->mark_table) 772 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 773 774 return 0; 775 776 err_free: 777 rte_free(intr_handle->intr_vec); 778 err_disable: 779 rte_intr_efd_disable(intr_handle); 780 err_out: 781 /* Some of the error status returned by FW may not be from errno.h */ 782 if (rc > 0) 783 rc = -EIO; 784 785 return rc; 786 } 787 788 static int bnxt_shutdown_nic(struct bnxt *bp) 789 { 790 bnxt_free_all_hwrm_resources(bp); 791 bnxt_free_all_filters(bp); 792 bnxt_free_all_vnics(bp); 793 return 0; 794 } 795 796 /* 797 * Device configuration and status function 798 */ 799 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 801 { 802 uint32_t link_speed = bp->link_info->support_speeds; 803 uint32_t speed_capa = 0; 804 805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 806 speed_capa |= ETH_LINK_SPEED_100M; 807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 808 speed_capa |= ETH_LINK_SPEED_100M_HD; 809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 810 speed_capa |= ETH_LINK_SPEED_1G; 811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 812 speed_capa |= ETH_LINK_SPEED_2_5G; 813 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 814 speed_capa |= ETH_LINK_SPEED_10G; 815 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 816 speed_capa |= ETH_LINK_SPEED_20G; 817 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 818 speed_capa |= ETH_LINK_SPEED_25G; 819 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 820 speed_capa |= ETH_LINK_SPEED_40G; 821 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 822 speed_capa |= ETH_LINK_SPEED_50G; 823 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 824 speed_capa |= ETH_LINK_SPEED_100G; 825 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB) 826 speed_capa |= ETH_LINK_SPEED_200G; 827 828 if (bp->link_info->auto_mode == 829 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 830 speed_capa |= ETH_LINK_SPEED_FIXED; 831 else 832 speed_capa |= ETH_LINK_SPEED_AUTONEG; 833 834 return speed_capa; 835 } 836 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 838 struct rte_eth_dev_info *dev_info) 839 { 840 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 841 struct bnxt *bp = eth_dev->data->dev_private; 842 uint16_t max_vnics, i, j, vpool, vrxq; 843 unsigned int max_rx_rings; 844 int rc; 845 846 rc = is_bnxt_in_error(bp); 847 if (rc) 848 return rc; 849 850 /* MAC Specifics */ 851 dev_info->max_mac_addrs = bp->max_l2_ctx; 852 dev_info->max_hash_mac_addrs = 0; 853 854 /* PF/VF specifics */ 855 if (BNXT_PF(bp)) 856 dev_info->max_vfs = pdev->max_vfs; 857 858 max_rx_rings = BNXT_MAX_RINGS(bp); 859 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 860 dev_info->max_rx_queues = max_rx_rings; 861 dev_info->max_tx_queues = max_rx_rings; 862 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 863 dev_info->hash_key_size = 40; 864 max_vnics = bp->max_vnics; 865 866 /* MTU specifics */ 867 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 868 dev_info->max_mtu = BNXT_MAX_MTU; 869 870 /* Fast path specifics */ 871 dev_info->min_rx_bufsize = 1; 872 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 873 874 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 875 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 876 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 877 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 878 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 879 880 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 881 882 /* *INDENT-OFF* */ 883 dev_info->default_rxconf = (struct rte_eth_rxconf) { 884 .rx_thresh = { 885 .pthresh = 8, 886 .hthresh = 8, 887 .wthresh = 0, 888 }, 889 .rx_free_thresh = 32, 890 /* If no descriptors available, pkts are dropped by default */ 891 .rx_drop_en = 1, 892 }; 893 894 dev_info->default_txconf = (struct rte_eth_txconf) { 895 .tx_thresh = { 896 .pthresh = 32, 897 .hthresh = 0, 898 .wthresh = 0, 899 }, 900 .tx_free_thresh = 32, 901 .tx_rs_thresh = 32, 902 }; 903 eth_dev->data->dev_conf.intr_conf.lsc = 1; 904 905 eth_dev->data->dev_conf.intr_conf.rxq = 1; 906 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 907 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 908 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 909 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 910 911 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 912 dev_info->switch_info.name = eth_dev->device->name; 913 dev_info->switch_info.domain_id = bp->switch_domain_id; 914 dev_info->switch_info.port_id = 915 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 916 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 917 } 918 919 /* *INDENT-ON* */ 920 921 /* 922 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 923 * need further investigation. 924 */ 925 926 /* VMDq resources */ 927 vpool = 64; /* ETH_64_POOLS */ 928 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 929 for (i = 0; i < 4; vpool >>= 1, i++) { 930 if (max_vnics > vpool) { 931 for (j = 0; j < 5; vrxq >>= 1, j++) { 932 if (dev_info->max_rx_queues > vrxq) { 933 if (vpool > vrxq) 934 vpool = vrxq; 935 goto found; 936 } 937 } 938 /* Not enough resources to support VMDq */ 939 break; 940 } 941 } 942 /* Not enough resources to support VMDq */ 943 vpool = 0; 944 vrxq = 0; 945 found: 946 dev_info->max_vmdq_pools = vpool; 947 dev_info->vmdq_queue_num = vrxq; 948 949 dev_info->vmdq_pool_base = 0; 950 dev_info->vmdq_queue_base = 0; 951 952 return 0; 953 } 954 955 /* Configure the device based on the configuration provided */ 956 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 957 { 958 struct bnxt *bp = eth_dev->data->dev_private; 959 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 960 int rc; 961 962 bp->rx_queues = (void *)eth_dev->data->rx_queues; 963 bp->tx_queues = (void *)eth_dev->data->tx_queues; 964 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 965 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 966 967 rc = is_bnxt_in_error(bp); 968 if (rc) 969 return rc; 970 971 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 972 rc = bnxt_hwrm_check_vf_rings(bp); 973 if (rc) { 974 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 975 return -ENOSPC; 976 } 977 978 /* If a resource has already been allocated - in this case 979 * it is the async completion ring, free it. Reallocate it after 980 * resource reservation. This will ensure the resource counts 981 * are calculated correctly. 982 */ 983 984 pthread_mutex_lock(&bp->def_cp_lock); 985 986 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 987 bnxt_disable_int(bp); 988 bnxt_free_cp_ring(bp, bp->async_cp_ring); 989 } 990 991 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 992 if (rc) { 993 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 994 pthread_mutex_unlock(&bp->def_cp_lock); 995 return -ENOSPC; 996 } 997 998 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 999 rc = bnxt_alloc_async_cp_ring(bp); 1000 if (rc) { 1001 pthread_mutex_unlock(&bp->def_cp_lock); 1002 return rc; 1003 } 1004 bnxt_enable_int(bp); 1005 } 1006 1007 pthread_mutex_unlock(&bp->def_cp_lock); 1008 } else { 1009 /* legacy driver needs to get updated values */ 1010 rc = bnxt_hwrm_func_qcaps(bp); 1011 if (rc) { 1012 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 1013 return rc; 1014 } 1015 } 1016 1017 /* Inherit new configurations */ 1018 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1019 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1020 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1021 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1022 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1023 bp->max_stat_ctx) 1024 goto resource_error; 1025 1026 if (BNXT_HAS_RING_GRPS(bp) && 1027 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1028 goto resource_error; 1029 1030 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1031 bp->max_vnics < eth_dev->data->nb_rx_queues) 1032 goto resource_error; 1033 1034 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1035 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1036 1037 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1038 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1039 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1040 1041 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1042 eth_dev->data->mtu = 1043 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1044 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1045 BNXT_NUM_VLANS; 1046 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1047 } 1048 return 0; 1049 1050 resource_error: 1051 PMD_DRV_LOG(ERR, 1052 "Insufficient resources to support requested config\n"); 1053 PMD_DRV_LOG(ERR, 1054 "Num Queues Requested: Tx %d, Rx %d\n", 1055 eth_dev->data->nb_tx_queues, 1056 eth_dev->data->nb_rx_queues); 1057 PMD_DRV_LOG(ERR, 1058 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1059 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1060 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1061 return -ENOSPC; 1062 } 1063 1064 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1065 { 1066 struct rte_eth_link *link = ð_dev->data->dev_link; 1067 1068 if (link->link_status) 1069 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1070 eth_dev->data->port_id, 1071 (uint32_t)link->link_speed, 1072 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1073 ("full-duplex") : ("half-duplex\n")); 1074 else 1075 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1076 eth_dev->data->port_id); 1077 } 1078 1079 /* 1080 * Determine whether the current configuration requires support for scattered 1081 * receive; return 1 if scattered receive is required and 0 if not. 1082 */ 1083 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1084 { 1085 uint16_t buf_size; 1086 int i; 1087 1088 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1089 return 1; 1090 1091 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1092 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1093 1094 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1095 RTE_PKTMBUF_HEADROOM); 1096 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1097 return 1; 1098 } 1099 return 0; 1100 } 1101 1102 static eth_rx_burst_t 1103 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1104 { 1105 struct bnxt *bp = eth_dev->data->dev_private; 1106 1107 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1108 #ifndef RTE_LIBRTE_IEEE1588 1109 /* 1110 * Vector mode receive can be enabled only if scatter rx is not 1111 * in use and rx offloads are limited to VLAN stripping and 1112 * CRC stripping. 1113 */ 1114 if (!eth_dev->data->scattered_rx && 1115 !(eth_dev->data->dev_conf.rxmode.offloads & 1116 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1117 DEV_RX_OFFLOAD_KEEP_CRC | 1118 DEV_RX_OFFLOAD_JUMBO_FRAME | 1119 DEV_RX_OFFLOAD_IPV4_CKSUM | 1120 DEV_RX_OFFLOAD_UDP_CKSUM | 1121 DEV_RX_OFFLOAD_TCP_CKSUM | 1122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1123 DEV_RX_OFFLOAD_RSS_HASH | 1124 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1125 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) { 1126 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1127 eth_dev->data->port_id); 1128 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1129 return bnxt_recv_pkts_vec; 1130 } 1131 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1132 eth_dev->data->port_id); 1133 PMD_DRV_LOG(INFO, 1134 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1135 eth_dev->data->port_id, 1136 eth_dev->data->scattered_rx, 1137 eth_dev->data->dev_conf.rxmode.offloads); 1138 #endif 1139 #endif 1140 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1141 return bnxt_recv_pkts; 1142 } 1143 1144 static eth_tx_burst_t 1145 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 1146 { 1147 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1148 #ifndef RTE_LIBRTE_IEEE1588 1149 struct bnxt *bp = eth_dev->data->dev_private; 1150 1151 /* 1152 * Vector mode transmit can be enabled only if not using scatter rx 1153 * or tx offloads. 1154 */ 1155 if (!eth_dev->data->scattered_rx && 1156 !eth_dev->data->dev_conf.txmode.offloads && 1157 !BNXT_TRUFLOW_EN(bp)) { 1158 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1159 eth_dev->data->port_id); 1160 return bnxt_xmit_pkts_vec; 1161 } 1162 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1163 eth_dev->data->port_id); 1164 PMD_DRV_LOG(INFO, 1165 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1166 eth_dev->data->port_id, 1167 eth_dev->data->scattered_rx, 1168 eth_dev->data->dev_conf.txmode.offloads); 1169 #endif 1170 #endif 1171 return bnxt_xmit_pkts; 1172 } 1173 1174 static int bnxt_handle_if_change_status(struct bnxt *bp) 1175 { 1176 int rc; 1177 1178 /* Since fw has undergone a reset and lost all contexts, 1179 * set fatal flag to not issue hwrm during cleanup 1180 */ 1181 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1182 bnxt_uninit_resources(bp, true); 1183 1184 /* clear fatal flag so that re-init happens */ 1185 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1186 rc = bnxt_init_resources(bp, true); 1187 1188 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1189 1190 return rc; 1191 } 1192 1193 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1194 { 1195 struct bnxt *bp = eth_dev->data->dev_private; 1196 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1197 int vlan_mask = 0; 1198 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1199 1200 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1201 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1202 return -EINVAL; 1203 } 1204 1205 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 1206 PMD_DRV_LOG(ERR, 1207 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1208 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1209 } 1210 1211 do { 1212 rc = bnxt_hwrm_if_change(bp, true); 1213 if (rc == 0 || rc != -EAGAIN) 1214 break; 1215 1216 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1217 } while (retry_cnt--); 1218 1219 if (rc) 1220 return rc; 1221 1222 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1223 rc = bnxt_handle_if_change_status(bp); 1224 if (rc) 1225 return rc; 1226 } 1227 1228 bnxt_enable_int(bp); 1229 1230 rc = bnxt_init_chip(bp); 1231 if (rc) 1232 goto error; 1233 1234 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1235 eth_dev->data->dev_started = 1; 1236 1237 bnxt_link_update(eth_dev, 1, ETH_LINK_UP); 1238 1239 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1240 vlan_mask |= ETH_VLAN_FILTER_MASK; 1241 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1242 vlan_mask |= ETH_VLAN_STRIP_MASK; 1243 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1244 if (rc) 1245 goto error; 1246 1247 /* Initialize bnxt ULP port details */ 1248 rc = bnxt_ulp_port_init(bp); 1249 if (rc) 1250 goto error; 1251 1252 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1253 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1254 1255 bnxt_schedule_fw_health_check(bp); 1256 1257 return 0; 1258 1259 error: 1260 bnxt_shutdown_nic(bp); 1261 bnxt_free_tx_mbufs(bp); 1262 bnxt_free_rx_mbufs(bp); 1263 bnxt_hwrm_if_change(bp, false); 1264 eth_dev->data->dev_started = 0; 1265 return rc; 1266 } 1267 1268 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1269 { 1270 struct bnxt *bp = eth_dev->data->dev_private; 1271 int rc = 0; 1272 1273 if (!bp->link_info->link_up) 1274 rc = bnxt_set_hwrm_link_config(bp, true); 1275 if (!rc) 1276 eth_dev->data->dev_link.link_status = 1; 1277 1278 bnxt_print_link_info(eth_dev); 1279 return rc; 1280 } 1281 1282 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1283 { 1284 struct bnxt *bp = eth_dev->data->dev_private; 1285 1286 eth_dev->data->dev_link.link_status = 0; 1287 bnxt_set_hwrm_link_config(bp, false); 1288 bp->link_info->link_up = 0; 1289 1290 return 0; 1291 } 1292 1293 static void bnxt_free_switch_domain(struct bnxt *bp) 1294 { 1295 if (bp->switch_domain_id) 1296 rte_eth_switch_domain_free(bp->switch_domain_id); 1297 } 1298 1299 /* Unload the driver, release resources */ 1300 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1301 { 1302 struct bnxt *bp = eth_dev->data->dev_private; 1303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1305 1306 eth_dev->data->dev_started = 0; 1307 eth_dev->data->scattered_rx = 0; 1308 1309 /* Prevent crashes when queues are still in use */ 1310 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1311 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1312 1313 bnxt_disable_int(bp); 1314 1315 /* disable uio/vfio intr/eventfd mapping */ 1316 rte_intr_disable(intr_handle); 1317 1318 /* Stop the child representors for this device */ 1319 bnxt_vf_rep_stop_all(bp); 1320 1321 /* delete the bnxt ULP port details */ 1322 bnxt_ulp_port_deinit(bp); 1323 1324 bnxt_cancel_fw_health_check(bp); 1325 1326 bnxt_dev_set_link_down_op(eth_dev); 1327 1328 /* Wait for link to be reset and the async notification to process. 1329 * During reset recovery, there is no need to wait and 1330 * VF/NPAR functions do not have privilege to change PHY config. 1331 */ 1332 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp)) 1333 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN); 1334 1335 /* Clean queue intr-vector mapping */ 1336 rte_intr_efd_disable(intr_handle); 1337 if (intr_handle->intr_vec != NULL) { 1338 rte_free(intr_handle->intr_vec); 1339 intr_handle->intr_vec = NULL; 1340 } 1341 1342 bnxt_hwrm_port_clr_stats(bp); 1343 bnxt_free_tx_mbufs(bp); 1344 bnxt_free_rx_mbufs(bp); 1345 /* Process any remaining notifications in default completion queue */ 1346 bnxt_int_handler(eth_dev); 1347 bnxt_shutdown_nic(bp); 1348 bnxt_hwrm_if_change(bp, false); 1349 1350 rte_free(bp->mark_table); 1351 bp->mark_table = NULL; 1352 1353 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1354 bp->rx_cosq_cnt = 0; 1355 /* All filters are deleted on a port stop. */ 1356 if (BNXT_FLOW_XSTATS_EN(bp)) 1357 bp->flow_stat->flow_count = 0; 1358 } 1359 1360 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1361 { 1362 struct bnxt *bp = eth_dev->data->dev_private; 1363 1364 /* cancel the recovery handler before remove dev */ 1365 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1366 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1367 bnxt_cancel_fc_thread(bp); 1368 1369 if (eth_dev->data->dev_started) 1370 bnxt_dev_stop_op(eth_dev); 1371 1372 bnxt_free_switch_domain(bp); 1373 1374 bnxt_uninit_resources(bp, false); 1375 1376 bnxt_free_leds_info(bp); 1377 bnxt_free_cos_queues(bp); 1378 bnxt_free_link_info(bp); 1379 bnxt_free_pf_info(bp); 1380 bnxt_free_parent_info(bp); 1381 1382 eth_dev->dev_ops = NULL; 1383 eth_dev->rx_pkt_burst = NULL; 1384 eth_dev->tx_pkt_burst = NULL; 1385 1386 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1387 bp->tx_mem_zone = NULL; 1388 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1389 bp->rx_mem_zone = NULL; 1390 1391 bnxt_hwrm_free_vf_info(bp); 1392 1393 rte_free(bp->grp_info); 1394 bp->grp_info = NULL; 1395 } 1396 1397 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1398 uint32_t index) 1399 { 1400 struct bnxt *bp = eth_dev->data->dev_private; 1401 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1402 struct bnxt_vnic_info *vnic; 1403 struct bnxt_filter_info *filter, *temp_filter; 1404 uint32_t i; 1405 1406 if (is_bnxt_in_error(bp)) 1407 return; 1408 1409 /* 1410 * Loop through all VNICs from the specified filter flow pools to 1411 * remove the corresponding MAC addr filter 1412 */ 1413 for (i = 0; i < bp->nr_vnics; i++) { 1414 if (!(pool_mask & (1ULL << i))) 1415 continue; 1416 1417 vnic = &bp->vnic_info[i]; 1418 filter = STAILQ_FIRST(&vnic->filter); 1419 while (filter) { 1420 temp_filter = STAILQ_NEXT(filter, next); 1421 if (filter->mac_index == index) { 1422 STAILQ_REMOVE(&vnic->filter, filter, 1423 bnxt_filter_info, next); 1424 bnxt_hwrm_clear_l2_filter(bp, filter); 1425 bnxt_free_filter(bp, filter); 1426 } 1427 filter = temp_filter; 1428 } 1429 } 1430 } 1431 1432 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1433 struct rte_ether_addr *mac_addr, uint32_t index, 1434 uint32_t pool) 1435 { 1436 struct bnxt_filter_info *filter; 1437 int rc = 0; 1438 1439 /* Attach requested MAC address to the new l2_filter */ 1440 STAILQ_FOREACH(filter, &vnic->filter, next) { 1441 if (filter->mac_index == index) { 1442 PMD_DRV_LOG(DEBUG, 1443 "MAC addr already existed for pool %d\n", 1444 pool); 1445 return 0; 1446 } 1447 } 1448 1449 filter = bnxt_alloc_filter(bp); 1450 if (!filter) { 1451 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1452 return -ENODEV; 1453 } 1454 1455 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1456 * if the MAC that's been programmed now is a different one, then, 1457 * copy that addr to filter->l2_addr 1458 */ 1459 if (mac_addr) 1460 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1461 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1462 1463 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1464 if (!rc) { 1465 filter->mac_index = index; 1466 if (filter->mac_index == 0) 1467 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1468 else 1469 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1470 } else { 1471 bnxt_free_filter(bp, filter); 1472 } 1473 1474 return rc; 1475 } 1476 1477 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1478 struct rte_ether_addr *mac_addr, 1479 uint32_t index, uint32_t pool) 1480 { 1481 struct bnxt *bp = eth_dev->data->dev_private; 1482 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1483 int rc = 0; 1484 1485 rc = is_bnxt_in_error(bp); 1486 if (rc) 1487 return rc; 1488 1489 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1490 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1491 return -ENOTSUP; 1492 } 1493 1494 if (!vnic) { 1495 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1496 return -EINVAL; 1497 } 1498 1499 /* Filter settings will get applied when port is started */ 1500 if (!eth_dev->data->dev_started) 1501 return 0; 1502 1503 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1504 1505 return rc; 1506 } 1507 1508 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1509 bool exp_link_status) 1510 { 1511 int rc = 0; 1512 struct bnxt *bp = eth_dev->data->dev_private; 1513 struct rte_eth_link new; 1514 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT : 1515 BNXT_LINK_DOWN_WAIT_CNT; 1516 1517 rc = is_bnxt_in_error(bp); 1518 if (rc) 1519 return rc; 1520 1521 memset(&new, 0, sizeof(new)); 1522 do { 1523 /* Retrieve link info from hardware */ 1524 rc = bnxt_get_hwrm_link_config(bp, &new); 1525 if (rc) { 1526 new.link_speed = ETH_LINK_SPEED_100M; 1527 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1528 PMD_DRV_LOG(ERR, 1529 "Failed to retrieve link rc = 0x%x!\n", rc); 1530 goto out; 1531 } 1532 1533 if (!wait_to_complete || new.link_status == exp_link_status) 1534 break; 1535 1536 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1537 } while (cnt--); 1538 1539 out: 1540 /* Timed out or success */ 1541 if (new.link_status != eth_dev->data->dev_link.link_status || 1542 new.link_speed != eth_dev->data->dev_link.link_speed) { 1543 rte_eth_linkstatus_set(eth_dev, &new); 1544 1545 rte_eth_dev_callback_process(eth_dev, 1546 RTE_ETH_EVENT_INTR_LSC, 1547 NULL); 1548 1549 bnxt_print_link_info(eth_dev); 1550 } 1551 1552 return rc; 1553 } 1554 1555 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1556 int wait_to_complete) 1557 { 1558 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP); 1559 } 1560 1561 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1562 { 1563 struct bnxt *bp = eth_dev->data->dev_private; 1564 struct bnxt_vnic_info *vnic; 1565 uint32_t old_flags; 1566 int rc; 1567 1568 rc = is_bnxt_in_error(bp); 1569 if (rc) 1570 return rc; 1571 1572 /* Filter settings will get applied when port is started */ 1573 if (!eth_dev->data->dev_started) 1574 return 0; 1575 1576 if (bp->vnic_info == NULL) 1577 return 0; 1578 1579 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1580 1581 old_flags = vnic->flags; 1582 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1583 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1584 if (rc != 0) 1585 vnic->flags = old_flags; 1586 1587 return rc; 1588 } 1589 1590 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1591 { 1592 struct bnxt *bp = eth_dev->data->dev_private; 1593 struct bnxt_vnic_info *vnic; 1594 uint32_t old_flags; 1595 int rc; 1596 1597 rc = is_bnxt_in_error(bp); 1598 if (rc) 1599 return rc; 1600 1601 /* Filter settings will get applied when port is started */ 1602 if (!eth_dev->data->dev_started) 1603 return 0; 1604 1605 if (bp->vnic_info == NULL) 1606 return 0; 1607 1608 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1609 1610 old_flags = vnic->flags; 1611 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1612 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1613 if (rc != 0) 1614 vnic->flags = old_flags; 1615 1616 return rc; 1617 } 1618 1619 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1620 { 1621 struct bnxt *bp = eth_dev->data->dev_private; 1622 struct bnxt_vnic_info *vnic; 1623 uint32_t old_flags; 1624 int rc; 1625 1626 rc = is_bnxt_in_error(bp); 1627 if (rc) 1628 return rc; 1629 1630 /* Filter settings will get applied when port is started */ 1631 if (!eth_dev->data->dev_started) 1632 return 0; 1633 1634 if (bp->vnic_info == NULL) 1635 return 0; 1636 1637 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1638 1639 old_flags = vnic->flags; 1640 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1641 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1642 if (rc != 0) 1643 vnic->flags = old_flags; 1644 1645 return rc; 1646 } 1647 1648 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1649 { 1650 struct bnxt *bp = eth_dev->data->dev_private; 1651 struct bnxt_vnic_info *vnic; 1652 uint32_t old_flags; 1653 int rc; 1654 1655 rc = is_bnxt_in_error(bp); 1656 if (rc) 1657 return rc; 1658 1659 /* Filter settings will get applied when port is started */ 1660 if (!eth_dev->data->dev_started) 1661 return 0; 1662 1663 if (bp->vnic_info == NULL) 1664 return 0; 1665 1666 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1667 1668 old_flags = vnic->flags; 1669 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1670 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1671 if (rc != 0) 1672 vnic->flags = old_flags; 1673 1674 return rc; 1675 } 1676 1677 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1678 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1679 { 1680 if (qid >= bp->rx_nr_rings) 1681 return NULL; 1682 1683 return bp->eth_dev->data->rx_queues[qid]; 1684 } 1685 1686 /* Return rxq corresponding to a given rss table ring/group ID. */ 1687 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1688 { 1689 struct bnxt_rx_queue *rxq; 1690 unsigned int i; 1691 1692 if (!BNXT_HAS_RING_GRPS(bp)) { 1693 for (i = 0; i < bp->rx_nr_rings; i++) { 1694 rxq = bp->eth_dev->data->rx_queues[i]; 1695 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1696 return rxq->index; 1697 } 1698 } else { 1699 for (i = 0; i < bp->rx_nr_rings; i++) { 1700 if (bp->grp_info[i].fw_grp_id == fwr) 1701 return i; 1702 } 1703 } 1704 1705 return INVALID_HW_RING_ID; 1706 } 1707 1708 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1709 struct rte_eth_rss_reta_entry64 *reta_conf, 1710 uint16_t reta_size) 1711 { 1712 struct bnxt *bp = eth_dev->data->dev_private; 1713 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1714 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1715 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1716 uint16_t idx, sft; 1717 int i, rc; 1718 1719 rc = is_bnxt_in_error(bp); 1720 if (rc) 1721 return rc; 1722 1723 if (!vnic->rss_table) 1724 return -EINVAL; 1725 1726 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1727 return -EINVAL; 1728 1729 if (reta_size != tbl_size) { 1730 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1731 "(%d) must equal the size supported by the hardware " 1732 "(%d)\n", reta_size, tbl_size); 1733 return -EINVAL; 1734 } 1735 1736 for (i = 0; i < reta_size; i++) { 1737 struct bnxt_rx_queue *rxq; 1738 1739 idx = i / RTE_RETA_GROUP_SIZE; 1740 sft = i % RTE_RETA_GROUP_SIZE; 1741 1742 if (!(reta_conf[idx].mask & (1ULL << sft))) 1743 continue; 1744 1745 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1746 if (!rxq) { 1747 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1748 return -EINVAL; 1749 } 1750 1751 if (BNXT_CHIP_THOR(bp)) { 1752 vnic->rss_table[i * 2] = 1753 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1754 vnic->rss_table[i * 2 + 1] = 1755 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1756 } else { 1757 vnic->rss_table[i] = 1758 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1759 } 1760 } 1761 1762 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1763 return 0; 1764 } 1765 1766 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1767 struct rte_eth_rss_reta_entry64 *reta_conf, 1768 uint16_t reta_size) 1769 { 1770 struct bnxt *bp = eth_dev->data->dev_private; 1771 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1772 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1773 uint16_t idx, sft, i; 1774 int rc; 1775 1776 rc = is_bnxt_in_error(bp); 1777 if (rc) 1778 return rc; 1779 1780 /* Retrieve from the default VNIC */ 1781 if (!vnic) 1782 return -EINVAL; 1783 if (!vnic->rss_table) 1784 return -EINVAL; 1785 1786 if (reta_size != tbl_size) { 1787 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1788 "(%d) must equal the size supported by the hardware " 1789 "(%d)\n", reta_size, tbl_size); 1790 return -EINVAL; 1791 } 1792 1793 for (idx = 0, i = 0; i < reta_size; i++) { 1794 idx = i / RTE_RETA_GROUP_SIZE; 1795 sft = i % RTE_RETA_GROUP_SIZE; 1796 1797 if (reta_conf[idx].mask & (1ULL << sft)) { 1798 uint16_t qid; 1799 1800 if (BNXT_CHIP_THOR(bp)) 1801 qid = bnxt_rss_to_qid(bp, 1802 vnic->rss_table[i * 2]); 1803 else 1804 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1805 1806 if (qid == INVALID_HW_RING_ID) { 1807 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1808 return -EINVAL; 1809 } 1810 reta_conf[idx].reta[sft] = qid; 1811 } 1812 } 1813 1814 return 0; 1815 } 1816 1817 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1818 struct rte_eth_rss_conf *rss_conf) 1819 { 1820 struct bnxt *bp = eth_dev->data->dev_private; 1821 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1822 struct bnxt_vnic_info *vnic; 1823 int rc; 1824 1825 rc = is_bnxt_in_error(bp); 1826 if (rc) 1827 return rc; 1828 1829 /* 1830 * If RSS enablement were different than dev_configure, 1831 * then return -EINVAL 1832 */ 1833 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1834 if (!rss_conf->rss_hf) 1835 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1836 } else { 1837 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1838 return -EINVAL; 1839 } 1840 1841 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1842 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 1843 rss_conf, 1844 sizeof(*rss_conf)); 1845 1846 /* Update the default RSS VNIC(s) */ 1847 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1848 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1849 1850 /* 1851 * If hashkey is not specified, use the previously configured 1852 * hashkey 1853 */ 1854 if (!rss_conf->rss_key) 1855 goto rss_config; 1856 1857 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1858 PMD_DRV_LOG(ERR, 1859 "Invalid hashkey length, should be 16 bytes\n"); 1860 return -EINVAL; 1861 } 1862 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1863 1864 rss_config: 1865 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1866 return 0; 1867 } 1868 1869 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1870 struct rte_eth_rss_conf *rss_conf) 1871 { 1872 struct bnxt *bp = eth_dev->data->dev_private; 1873 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1874 int len, rc; 1875 uint32_t hash_types; 1876 1877 rc = is_bnxt_in_error(bp); 1878 if (rc) 1879 return rc; 1880 1881 /* RSS configuration is the same for all VNICs */ 1882 if (vnic && vnic->rss_hash_key) { 1883 if (rss_conf->rss_key) { 1884 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1885 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1886 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1887 } 1888 1889 hash_types = vnic->hash_type; 1890 rss_conf->rss_hf = 0; 1891 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1892 rss_conf->rss_hf |= ETH_RSS_IPV4; 1893 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1894 } 1895 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1896 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1897 hash_types &= 1898 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1899 } 1900 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1901 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1902 hash_types &= 1903 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1904 } 1905 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1906 rss_conf->rss_hf |= ETH_RSS_IPV6; 1907 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1908 } 1909 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1910 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1911 hash_types &= 1912 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1913 } 1914 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1915 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1916 hash_types &= 1917 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1918 } 1919 if (hash_types) { 1920 PMD_DRV_LOG(ERR, 1921 "Unknown RSS config from firmware (%08x), RSS disabled", 1922 vnic->hash_type); 1923 return -ENOTSUP; 1924 } 1925 } else { 1926 rss_conf->rss_hf = 0; 1927 } 1928 return 0; 1929 } 1930 1931 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1932 struct rte_eth_fc_conf *fc_conf) 1933 { 1934 struct bnxt *bp = dev->data->dev_private; 1935 struct rte_eth_link link_info; 1936 int rc; 1937 1938 rc = is_bnxt_in_error(bp); 1939 if (rc) 1940 return rc; 1941 1942 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1943 if (rc) 1944 return rc; 1945 1946 memset(fc_conf, 0, sizeof(*fc_conf)); 1947 if (bp->link_info->auto_pause) 1948 fc_conf->autoneg = 1; 1949 switch (bp->link_info->pause) { 1950 case 0: 1951 fc_conf->mode = RTE_FC_NONE; 1952 break; 1953 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1954 fc_conf->mode = RTE_FC_TX_PAUSE; 1955 break; 1956 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1957 fc_conf->mode = RTE_FC_RX_PAUSE; 1958 break; 1959 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1960 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1961 fc_conf->mode = RTE_FC_FULL; 1962 break; 1963 } 1964 return 0; 1965 } 1966 1967 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1968 struct rte_eth_fc_conf *fc_conf) 1969 { 1970 struct bnxt *bp = dev->data->dev_private; 1971 int rc; 1972 1973 rc = is_bnxt_in_error(bp); 1974 if (rc) 1975 return rc; 1976 1977 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1978 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1979 return -ENOTSUP; 1980 } 1981 1982 switch (fc_conf->mode) { 1983 case RTE_FC_NONE: 1984 bp->link_info->auto_pause = 0; 1985 bp->link_info->force_pause = 0; 1986 break; 1987 case RTE_FC_RX_PAUSE: 1988 if (fc_conf->autoneg) { 1989 bp->link_info->auto_pause = 1990 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1991 bp->link_info->force_pause = 0; 1992 } else { 1993 bp->link_info->auto_pause = 0; 1994 bp->link_info->force_pause = 1995 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1996 } 1997 break; 1998 case RTE_FC_TX_PAUSE: 1999 if (fc_conf->autoneg) { 2000 bp->link_info->auto_pause = 2001 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2002 bp->link_info->force_pause = 0; 2003 } else { 2004 bp->link_info->auto_pause = 0; 2005 bp->link_info->force_pause = 2006 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2007 } 2008 break; 2009 case RTE_FC_FULL: 2010 if (fc_conf->autoneg) { 2011 bp->link_info->auto_pause = 2012 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2013 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2014 bp->link_info->force_pause = 0; 2015 } else { 2016 bp->link_info->auto_pause = 0; 2017 bp->link_info->force_pause = 2018 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2019 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2020 } 2021 break; 2022 } 2023 return bnxt_set_hwrm_link_config(bp, true); 2024 } 2025 2026 /* Add UDP tunneling port */ 2027 static int 2028 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2029 struct rte_eth_udp_tunnel *udp_tunnel) 2030 { 2031 struct bnxt *bp = eth_dev->data->dev_private; 2032 uint16_t tunnel_type = 0; 2033 int rc = 0; 2034 2035 rc = is_bnxt_in_error(bp); 2036 if (rc) 2037 return rc; 2038 2039 switch (udp_tunnel->prot_type) { 2040 case RTE_TUNNEL_TYPE_VXLAN: 2041 if (bp->vxlan_port_cnt) { 2042 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2043 udp_tunnel->udp_port); 2044 if (bp->vxlan_port != udp_tunnel->udp_port) { 2045 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2046 return -ENOSPC; 2047 } 2048 bp->vxlan_port_cnt++; 2049 return 0; 2050 } 2051 tunnel_type = 2052 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2053 bp->vxlan_port_cnt++; 2054 break; 2055 case RTE_TUNNEL_TYPE_GENEVE: 2056 if (bp->geneve_port_cnt) { 2057 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2058 udp_tunnel->udp_port); 2059 if (bp->geneve_port != udp_tunnel->udp_port) { 2060 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2061 return -ENOSPC; 2062 } 2063 bp->geneve_port_cnt++; 2064 return 0; 2065 } 2066 tunnel_type = 2067 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2068 bp->geneve_port_cnt++; 2069 break; 2070 default: 2071 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2072 return -ENOTSUP; 2073 } 2074 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2075 tunnel_type); 2076 return rc; 2077 } 2078 2079 static int 2080 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2081 struct rte_eth_udp_tunnel *udp_tunnel) 2082 { 2083 struct bnxt *bp = eth_dev->data->dev_private; 2084 uint16_t tunnel_type = 0; 2085 uint16_t port = 0; 2086 int rc = 0; 2087 2088 rc = is_bnxt_in_error(bp); 2089 if (rc) 2090 return rc; 2091 2092 switch (udp_tunnel->prot_type) { 2093 case RTE_TUNNEL_TYPE_VXLAN: 2094 if (!bp->vxlan_port_cnt) { 2095 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2096 return -EINVAL; 2097 } 2098 if (bp->vxlan_port != udp_tunnel->udp_port) { 2099 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2100 udp_tunnel->udp_port, bp->vxlan_port); 2101 return -EINVAL; 2102 } 2103 if (--bp->vxlan_port_cnt) 2104 return 0; 2105 2106 tunnel_type = 2107 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2108 port = bp->vxlan_fw_dst_port_id; 2109 break; 2110 case RTE_TUNNEL_TYPE_GENEVE: 2111 if (!bp->geneve_port_cnt) { 2112 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2113 return -EINVAL; 2114 } 2115 if (bp->geneve_port != udp_tunnel->udp_port) { 2116 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2117 udp_tunnel->udp_port, bp->geneve_port); 2118 return -EINVAL; 2119 } 2120 if (--bp->geneve_port_cnt) 2121 return 0; 2122 2123 tunnel_type = 2124 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2125 port = bp->geneve_fw_dst_port_id; 2126 break; 2127 default: 2128 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2129 return -ENOTSUP; 2130 } 2131 2132 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2133 if (!rc) { 2134 if (tunnel_type == 2135 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 2136 bp->vxlan_port = 0; 2137 if (tunnel_type == 2138 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 2139 bp->geneve_port = 0; 2140 } 2141 return rc; 2142 } 2143 2144 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2145 { 2146 struct bnxt_filter_info *filter; 2147 struct bnxt_vnic_info *vnic; 2148 int rc = 0; 2149 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2150 2151 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2152 filter = STAILQ_FIRST(&vnic->filter); 2153 while (filter) { 2154 /* Search for this matching MAC+VLAN filter */ 2155 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2156 /* Delete the filter */ 2157 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2158 if (rc) 2159 return rc; 2160 STAILQ_REMOVE(&vnic->filter, filter, 2161 bnxt_filter_info, next); 2162 bnxt_free_filter(bp, filter); 2163 PMD_DRV_LOG(INFO, 2164 "Deleted vlan filter for %d\n", 2165 vlan_id); 2166 return 0; 2167 } 2168 filter = STAILQ_NEXT(filter, next); 2169 } 2170 return -ENOENT; 2171 } 2172 2173 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2174 { 2175 struct bnxt_filter_info *filter; 2176 struct bnxt_vnic_info *vnic; 2177 int rc = 0; 2178 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2179 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2180 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2181 2182 /* Implementation notes on the use of VNIC in this command: 2183 * 2184 * By default, these filters belong to default vnic for the function. 2185 * Once these filters are set up, only destination VNIC can be modified. 2186 * If the destination VNIC is not specified in this command, 2187 * then the HWRM shall only create an l2 context id. 2188 */ 2189 2190 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2191 filter = STAILQ_FIRST(&vnic->filter); 2192 /* Check if the VLAN has already been added */ 2193 while (filter) { 2194 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2195 return -EEXIST; 2196 2197 filter = STAILQ_NEXT(filter, next); 2198 } 2199 2200 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2201 * command to create MAC+VLAN filter with the right flags, enables set. 2202 */ 2203 filter = bnxt_alloc_filter(bp); 2204 if (!filter) { 2205 PMD_DRV_LOG(ERR, 2206 "MAC/VLAN filter alloc failed\n"); 2207 return -ENOMEM; 2208 } 2209 /* MAC + VLAN ID filter */ 2210 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2211 * untagged packets are received 2212 * 2213 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2214 * packets and only the programmed vlan's packets are received 2215 */ 2216 filter->l2_ivlan = vlan_id; 2217 filter->l2_ivlan_mask = 0x0FFF; 2218 filter->enables |= en; 2219 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2220 2221 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2222 if (rc) { 2223 /* Free the newly allocated filter as we were 2224 * not able to create the filter in hardware. 2225 */ 2226 bnxt_free_filter(bp, filter); 2227 return rc; 2228 } 2229 2230 filter->mac_index = 0; 2231 /* Add this new filter to the list */ 2232 if (vlan_id == 0) 2233 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2234 else 2235 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2236 2237 PMD_DRV_LOG(INFO, 2238 "Added Vlan filter for %d\n", vlan_id); 2239 return rc; 2240 } 2241 2242 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2243 uint16_t vlan_id, int on) 2244 { 2245 struct bnxt *bp = eth_dev->data->dev_private; 2246 int rc; 2247 2248 rc = is_bnxt_in_error(bp); 2249 if (rc) 2250 return rc; 2251 2252 if (!eth_dev->data->dev_started) { 2253 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2254 return -EINVAL; 2255 } 2256 2257 /* These operations apply to ALL existing MAC/VLAN filters */ 2258 if (on) 2259 return bnxt_add_vlan_filter(bp, vlan_id); 2260 else 2261 return bnxt_del_vlan_filter(bp, vlan_id); 2262 } 2263 2264 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2265 struct bnxt_vnic_info *vnic) 2266 { 2267 struct bnxt_filter_info *filter; 2268 int rc; 2269 2270 filter = STAILQ_FIRST(&vnic->filter); 2271 while (filter) { 2272 if (filter->mac_index == 0 && 2273 !memcmp(filter->l2_addr, bp->mac_addr, 2274 RTE_ETHER_ADDR_LEN)) { 2275 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2276 if (!rc) { 2277 STAILQ_REMOVE(&vnic->filter, filter, 2278 bnxt_filter_info, next); 2279 bnxt_free_filter(bp, filter); 2280 } 2281 return rc; 2282 } 2283 filter = STAILQ_NEXT(filter, next); 2284 } 2285 return 0; 2286 } 2287 2288 static int 2289 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2290 { 2291 struct bnxt_vnic_info *vnic; 2292 unsigned int i; 2293 int rc; 2294 2295 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2296 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2297 /* Remove any VLAN filters programmed */ 2298 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2299 bnxt_del_vlan_filter(bp, i); 2300 2301 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2302 if (rc) 2303 return rc; 2304 } else { 2305 /* Default filter will allow packets that match the 2306 * dest mac. So, it has to be deleted, otherwise, we 2307 * will endup receiving vlan packets for which the 2308 * filter is not programmed, when hw-vlan-filter 2309 * configuration is ON 2310 */ 2311 bnxt_del_dflt_mac_filter(bp, vnic); 2312 /* This filter will allow only untagged packets */ 2313 bnxt_add_vlan_filter(bp, 0); 2314 } 2315 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2316 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2317 2318 return 0; 2319 } 2320 2321 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2322 { 2323 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2324 unsigned int i; 2325 int rc; 2326 2327 /* Destroy vnic filters and vnic */ 2328 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2329 DEV_RX_OFFLOAD_VLAN_FILTER) { 2330 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2331 bnxt_del_vlan_filter(bp, i); 2332 } 2333 bnxt_del_dflt_mac_filter(bp, vnic); 2334 2335 rc = bnxt_hwrm_vnic_free(bp, vnic); 2336 if (rc) 2337 return rc; 2338 2339 rte_free(vnic->fw_grp_ids); 2340 vnic->fw_grp_ids = NULL; 2341 2342 vnic->rx_queue_cnt = 0; 2343 2344 return 0; 2345 } 2346 2347 static int 2348 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2349 { 2350 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2351 int rc; 2352 2353 /* Destroy, recreate and reconfigure the default vnic */ 2354 rc = bnxt_free_one_vnic(bp, 0); 2355 if (rc) 2356 return rc; 2357 2358 /* default vnic 0 */ 2359 rc = bnxt_setup_one_vnic(bp, 0); 2360 if (rc) 2361 return rc; 2362 2363 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2364 DEV_RX_OFFLOAD_VLAN_FILTER) { 2365 rc = bnxt_add_vlan_filter(bp, 0); 2366 if (rc) 2367 return rc; 2368 rc = bnxt_restore_vlan_filters(bp); 2369 if (rc) 2370 return rc; 2371 } else { 2372 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2373 if (rc) 2374 return rc; 2375 } 2376 2377 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2378 if (rc) 2379 return rc; 2380 2381 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2382 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2383 2384 return rc; 2385 } 2386 2387 static int 2388 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2389 { 2390 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2391 struct bnxt *bp = dev->data->dev_private; 2392 int rc; 2393 2394 rc = is_bnxt_in_error(bp); 2395 if (rc) 2396 return rc; 2397 2398 /* Filter settings will get applied when port is started */ 2399 if (!dev->data->dev_started) 2400 return 0; 2401 2402 if (mask & ETH_VLAN_FILTER_MASK) { 2403 /* Enable or disable VLAN filtering */ 2404 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2405 if (rc) 2406 return rc; 2407 } 2408 2409 if (mask & ETH_VLAN_STRIP_MASK) { 2410 /* Enable or disable VLAN stripping */ 2411 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2412 if (rc) 2413 return rc; 2414 } 2415 2416 if (mask & ETH_VLAN_EXTEND_MASK) { 2417 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2418 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2419 else 2420 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int 2427 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2428 uint16_t tpid) 2429 { 2430 struct bnxt *bp = dev->data->dev_private; 2431 int qinq = dev->data->dev_conf.rxmode.offloads & 2432 DEV_RX_OFFLOAD_VLAN_EXTEND; 2433 2434 if (vlan_type != ETH_VLAN_TYPE_INNER && 2435 vlan_type != ETH_VLAN_TYPE_OUTER) { 2436 PMD_DRV_LOG(ERR, 2437 "Unsupported vlan type."); 2438 return -EINVAL; 2439 } 2440 if (!qinq) { 2441 PMD_DRV_LOG(ERR, 2442 "QinQ not enabled. Needs to be ON as we can " 2443 "accelerate only outer vlan\n"); 2444 return -EINVAL; 2445 } 2446 2447 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2448 switch (tpid) { 2449 case RTE_ETHER_TYPE_QINQ: 2450 bp->outer_tpid_bd = 2451 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2452 break; 2453 case RTE_ETHER_TYPE_VLAN: 2454 bp->outer_tpid_bd = 2455 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2456 break; 2457 case RTE_ETHER_TYPE_QINQ1: 2458 bp->outer_tpid_bd = 2459 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2460 break; 2461 case RTE_ETHER_TYPE_QINQ2: 2462 bp->outer_tpid_bd = 2463 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2464 break; 2465 case RTE_ETHER_TYPE_QINQ3: 2466 bp->outer_tpid_bd = 2467 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2468 break; 2469 default: 2470 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2471 return -EINVAL; 2472 } 2473 bp->outer_tpid_bd |= tpid; 2474 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2475 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2476 PMD_DRV_LOG(ERR, 2477 "Can accelerate only outer vlan in QinQ\n"); 2478 return -EINVAL; 2479 } 2480 2481 return 0; 2482 } 2483 2484 static int 2485 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2486 struct rte_ether_addr *addr) 2487 { 2488 struct bnxt *bp = dev->data->dev_private; 2489 /* Default Filter is tied to VNIC 0 */ 2490 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2491 int rc; 2492 2493 rc = is_bnxt_in_error(bp); 2494 if (rc) 2495 return rc; 2496 2497 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2498 return -EPERM; 2499 2500 if (rte_is_zero_ether_addr(addr)) 2501 return -EINVAL; 2502 2503 /* Filter settings will get applied when port is started */ 2504 if (!dev->data->dev_started) 2505 return 0; 2506 2507 /* Check if the requested MAC is already added */ 2508 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2509 return 0; 2510 2511 /* Destroy filter and re-create it */ 2512 bnxt_del_dflt_mac_filter(bp, vnic); 2513 2514 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2515 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2516 /* This filter will allow only untagged packets */ 2517 rc = bnxt_add_vlan_filter(bp, 0); 2518 } else { 2519 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2520 } 2521 2522 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2523 return rc; 2524 } 2525 2526 static int 2527 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2528 struct rte_ether_addr *mc_addr_set, 2529 uint32_t nb_mc_addr) 2530 { 2531 struct bnxt *bp = eth_dev->data->dev_private; 2532 char *mc_addr_list = (char *)mc_addr_set; 2533 struct bnxt_vnic_info *vnic; 2534 uint32_t off = 0, i = 0; 2535 int rc; 2536 2537 rc = is_bnxt_in_error(bp); 2538 if (rc) 2539 return rc; 2540 2541 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2542 2543 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2544 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2545 goto allmulti; 2546 } 2547 2548 /* TODO Check for Duplicate mcast addresses */ 2549 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2550 for (i = 0; i < nb_mc_addr; i++) { 2551 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2552 RTE_ETHER_ADDR_LEN); 2553 off += RTE_ETHER_ADDR_LEN; 2554 } 2555 2556 vnic->mc_addr_cnt = i; 2557 if (vnic->mc_addr_cnt) 2558 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2559 else 2560 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2561 2562 allmulti: 2563 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2564 } 2565 2566 static int 2567 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2568 { 2569 struct bnxt *bp = dev->data->dev_private; 2570 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2571 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2572 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2573 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2574 int ret; 2575 2576 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2577 fw_major, fw_minor, fw_updt, fw_rsvd); 2578 2579 ret += 1; /* add the size of '\0' */ 2580 if (fw_size < (uint32_t)ret) 2581 return ret; 2582 else 2583 return 0; 2584 } 2585 2586 static void 2587 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2588 struct rte_eth_rxq_info *qinfo) 2589 { 2590 struct bnxt *bp = dev->data->dev_private; 2591 struct bnxt_rx_queue *rxq; 2592 2593 if (is_bnxt_in_error(bp)) 2594 return; 2595 2596 rxq = dev->data->rx_queues[queue_id]; 2597 2598 qinfo->mp = rxq->mb_pool; 2599 qinfo->scattered_rx = dev->data->scattered_rx; 2600 qinfo->nb_desc = rxq->nb_rx_desc; 2601 2602 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2603 qinfo->conf.rx_drop_en = 0; 2604 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2605 } 2606 2607 static void 2608 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2609 struct rte_eth_txq_info *qinfo) 2610 { 2611 struct bnxt *bp = dev->data->dev_private; 2612 struct bnxt_tx_queue *txq; 2613 2614 if (is_bnxt_in_error(bp)) 2615 return; 2616 2617 txq = dev->data->tx_queues[queue_id]; 2618 2619 qinfo->nb_desc = txq->nb_tx_desc; 2620 2621 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2622 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2623 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2624 2625 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2626 qinfo->conf.tx_rs_thresh = 0; 2627 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2628 } 2629 2630 static const struct { 2631 eth_rx_burst_t pkt_burst; 2632 const char *info; 2633 } bnxt_rx_burst_info[] = { 2634 {bnxt_recv_pkts, "Scalar"}, 2635 #if defined(RTE_ARCH_X86) 2636 {bnxt_recv_pkts_vec, "Vector SSE"}, 2637 #elif defined(RTE_ARCH_ARM64) 2638 {bnxt_recv_pkts_vec, "Vector Neon"}, 2639 #endif 2640 }; 2641 2642 static int 2643 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2644 struct rte_eth_burst_mode *mode) 2645 { 2646 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2647 size_t i; 2648 2649 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2650 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2651 snprintf(mode->info, sizeof(mode->info), "%s", 2652 bnxt_rx_burst_info[i].info); 2653 return 0; 2654 } 2655 } 2656 2657 return -EINVAL; 2658 } 2659 2660 static const struct { 2661 eth_tx_burst_t pkt_burst; 2662 const char *info; 2663 } bnxt_tx_burst_info[] = { 2664 {bnxt_xmit_pkts, "Scalar"}, 2665 #if defined(RTE_ARCH_X86) 2666 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2667 #elif defined(RTE_ARCH_ARM64) 2668 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2669 #endif 2670 }; 2671 2672 static int 2673 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2674 struct rte_eth_burst_mode *mode) 2675 { 2676 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2677 size_t i; 2678 2679 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2680 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2681 snprintf(mode->info, sizeof(mode->info), "%s", 2682 bnxt_tx_burst_info[i].info); 2683 return 0; 2684 } 2685 } 2686 2687 return -EINVAL; 2688 } 2689 2690 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2691 { 2692 struct bnxt *bp = eth_dev->data->dev_private; 2693 uint32_t new_pkt_size; 2694 uint32_t rc = 0; 2695 uint32_t i; 2696 2697 rc = is_bnxt_in_error(bp); 2698 if (rc) 2699 return rc; 2700 2701 /* Exit if receive queues are not configured yet */ 2702 if (!eth_dev->data->nb_rx_queues) 2703 return rc; 2704 2705 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2706 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2707 2708 /* 2709 * Disallow any MTU change that would require scattered receive support 2710 * if it is not already enabled. 2711 */ 2712 if (eth_dev->data->dev_started && 2713 !eth_dev->data->scattered_rx && 2714 (new_pkt_size > 2715 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2716 PMD_DRV_LOG(ERR, 2717 "MTU change would require scattered rx support. "); 2718 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2719 return -EINVAL; 2720 } 2721 2722 if (new_mtu > RTE_ETHER_MTU) { 2723 bp->flags |= BNXT_FLAG_JUMBO; 2724 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2725 DEV_RX_OFFLOAD_JUMBO_FRAME; 2726 } else { 2727 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2728 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2729 bp->flags &= ~BNXT_FLAG_JUMBO; 2730 } 2731 2732 /* Is there a change in mtu setting? */ 2733 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2734 return rc; 2735 2736 for (i = 0; i < bp->nr_vnics; i++) { 2737 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2738 uint16_t size = 0; 2739 2740 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2741 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2742 if (rc) 2743 break; 2744 2745 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2746 size -= RTE_PKTMBUF_HEADROOM; 2747 2748 if (size < new_mtu) { 2749 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2750 if (rc) 2751 return rc; 2752 } 2753 } 2754 2755 if (!rc) 2756 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2757 2758 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2759 2760 return rc; 2761 } 2762 2763 static int 2764 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2765 { 2766 struct bnxt *bp = dev->data->dev_private; 2767 uint16_t vlan = bp->vlan; 2768 int rc; 2769 2770 rc = is_bnxt_in_error(bp); 2771 if (rc) 2772 return rc; 2773 2774 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2775 PMD_DRV_LOG(ERR, 2776 "PVID cannot be modified for this function\n"); 2777 return -ENOTSUP; 2778 } 2779 bp->vlan = on ? pvid : 0; 2780 2781 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2782 if (rc) 2783 bp->vlan = vlan; 2784 return rc; 2785 } 2786 2787 static int 2788 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2789 { 2790 struct bnxt *bp = dev->data->dev_private; 2791 int rc; 2792 2793 rc = is_bnxt_in_error(bp); 2794 if (rc) 2795 return rc; 2796 2797 return bnxt_hwrm_port_led_cfg(bp, true); 2798 } 2799 2800 static int 2801 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2802 { 2803 struct bnxt *bp = dev->data->dev_private; 2804 int rc; 2805 2806 rc = is_bnxt_in_error(bp); 2807 if (rc) 2808 return rc; 2809 2810 return bnxt_hwrm_port_led_cfg(bp, false); 2811 } 2812 2813 static uint32_t 2814 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2815 { 2816 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2817 uint32_t desc = 0, raw_cons = 0, cons; 2818 struct bnxt_cp_ring_info *cpr; 2819 struct bnxt_rx_queue *rxq; 2820 struct rx_pkt_cmpl *rxcmp; 2821 int rc; 2822 2823 rc = is_bnxt_in_error(bp); 2824 if (rc) 2825 return rc; 2826 2827 rxq = dev->data->rx_queues[rx_queue_id]; 2828 cpr = rxq->cp_ring; 2829 raw_cons = cpr->cp_raw_cons; 2830 2831 while (1) { 2832 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2833 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2834 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2835 2836 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2837 break; 2838 } else { 2839 raw_cons++; 2840 desc++; 2841 } 2842 } 2843 2844 return desc; 2845 } 2846 2847 static int 2848 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2849 { 2850 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2851 struct bnxt_rx_ring_info *rxr; 2852 struct bnxt_cp_ring_info *cpr; 2853 struct rte_mbuf *rx_buf; 2854 struct rx_pkt_cmpl *rxcmp; 2855 uint32_t cons, cp_cons; 2856 int rc; 2857 2858 if (!rxq) 2859 return -EINVAL; 2860 2861 rc = is_bnxt_in_error(rxq->bp); 2862 if (rc) 2863 return rc; 2864 2865 cpr = rxq->cp_ring; 2866 rxr = rxq->rx_ring; 2867 2868 if (offset >= rxq->nb_rx_desc) 2869 return -EINVAL; 2870 2871 cons = RING_CMP(cpr->cp_ring_struct, offset); 2872 cp_cons = cpr->cp_raw_cons; 2873 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2874 2875 if (cons > cp_cons) { 2876 if (CMPL_VALID(rxcmp, cpr->valid)) 2877 return RTE_ETH_RX_DESC_DONE; 2878 } else { 2879 if (CMPL_VALID(rxcmp, !cpr->valid)) 2880 return RTE_ETH_RX_DESC_DONE; 2881 } 2882 rx_buf = rxr->rx_buf_ring[cons]; 2883 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) 2884 return RTE_ETH_RX_DESC_UNAVAIL; 2885 2886 2887 return RTE_ETH_RX_DESC_AVAIL; 2888 } 2889 2890 static int 2891 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2892 { 2893 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2894 struct bnxt_tx_ring_info *txr; 2895 struct bnxt_cp_ring_info *cpr; 2896 struct bnxt_sw_tx_bd *tx_buf; 2897 struct tx_pkt_cmpl *txcmp; 2898 uint32_t cons, cp_cons; 2899 int rc; 2900 2901 if (!txq) 2902 return -EINVAL; 2903 2904 rc = is_bnxt_in_error(txq->bp); 2905 if (rc) 2906 return rc; 2907 2908 cpr = txq->cp_ring; 2909 txr = txq->tx_ring; 2910 2911 if (offset >= txq->nb_tx_desc) 2912 return -EINVAL; 2913 2914 cons = RING_CMP(cpr->cp_ring_struct, offset); 2915 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2916 cp_cons = cpr->cp_raw_cons; 2917 2918 if (cons > cp_cons) { 2919 if (CMPL_VALID(txcmp, cpr->valid)) 2920 return RTE_ETH_TX_DESC_UNAVAIL; 2921 } else { 2922 if (CMPL_VALID(txcmp, !cpr->valid)) 2923 return RTE_ETH_TX_DESC_UNAVAIL; 2924 } 2925 tx_buf = &txr->tx_buf_ring[cons]; 2926 if (tx_buf->mbuf == NULL) 2927 return RTE_ETH_TX_DESC_DONE; 2928 2929 return RTE_ETH_TX_DESC_FULL; 2930 } 2931 2932 static struct bnxt_filter_info * 2933 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2934 struct rte_eth_ethertype_filter *efilter, 2935 struct bnxt_vnic_info *vnic0, 2936 struct bnxt_vnic_info *vnic, 2937 int *ret) 2938 { 2939 struct bnxt_filter_info *mfilter = NULL; 2940 int match = 0; 2941 *ret = 0; 2942 2943 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2944 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2945 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2946 " ethertype filter.", efilter->ether_type); 2947 *ret = -EINVAL; 2948 goto exit; 2949 } 2950 if (efilter->queue >= bp->rx_nr_rings) { 2951 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2952 *ret = -EINVAL; 2953 goto exit; 2954 } 2955 2956 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2957 vnic = &bp->vnic_info[efilter->queue]; 2958 if (vnic == NULL) { 2959 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2960 *ret = -EINVAL; 2961 goto exit; 2962 } 2963 2964 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2965 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2966 if ((!memcmp(efilter->mac_addr.addr_bytes, 2967 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2968 mfilter->flags == 2969 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2970 mfilter->ethertype == efilter->ether_type)) { 2971 match = 1; 2972 break; 2973 } 2974 } 2975 } else { 2976 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2977 if ((!memcmp(efilter->mac_addr.addr_bytes, 2978 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2979 mfilter->ethertype == efilter->ether_type && 2980 mfilter->flags == 2981 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2982 match = 1; 2983 break; 2984 } 2985 } 2986 2987 if (match) 2988 *ret = -EEXIST; 2989 2990 exit: 2991 return mfilter; 2992 } 2993 2994 static int 2995 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2996 enum rte_filter_op filter_op, 2997 void *arg) 2998 { 2999 struct bnxt *bp = dev->data->dev_private; 3000 struct rte_eth_ethertype_filter *efilter = 3001 (struct rte_eth_ethertype_filter *)arg; 3002 struct bnxt_filter_info *bfilter, *filter1; 3003 struct bnxt_vnic_info *vnic, *vnic0; 3004 int ret; 3005 3006 if (filter_op == RTE_ETH_FILTER_NOP) 3007 return 0; 3008 3009 if (arg == NULL) { 3010 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 3011 filter_op); 3012 return -EINVAL; 3013 } 3014 3015 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3016 vnic = &bp->vnic_info[efilter->queue]; 3017 3018 switch (filter_op) { 3019 case RTE_ETH_FILTER_ADD: 3020 bnxt_match_and_validate_ether_filter(bp, efilter, 3021 vnic0, vnic, &ret); 3022 if (ret < 0) 3023 return ret; 3024 3025 bfilter = bnxt_get_unused_filter(bp); 3026 if (bfilter == NULL) { 3027 PMD_DRV_LOG(ERR, 3028 "Not enough resources for a new filter.\n"); 3029 return -ENOMEM; 3030 } 3031 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3032 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 3033 RTE_ETHER_ADDR_LEN); 3034 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 3035 RTE_ETHER_ADDR_LEN); 3036 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 3037 bfilter->ethertype = efilter->ether_type; 3038 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3039 3040 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 3041 if (filter1 == NULL) { 3042 ret = -EINVAL; 3043 goto cleanup; 3044 } 3045 bfilter->enables |= 3046 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3047 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3048 3049 bfilter->dst_id = vnic->fw_vnic_id; 3050 3051 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 3052 bfilter->flags = 3053 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 3054 } 3055 3056 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 3057 if (ret) 3058 goto cleanup; 3059 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 3060 break; 3061 case RTE_ETH_FILTER_DELETE: 3062 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 3063 vnic0, vnic, &ret); 3064 if (ret == -EEXIST) { 3065 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 3066 3067 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 3068 next); 3069 bnxt_free_filter(bp, filter1); 3070 } else if (ret == 0) { 3071 PMD_DRV_LOG(ERR, "No matching filter found\n"); 3072 } 3073 break; 3074 default: 3075 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 3076 ret = -EINVAL; 3077 goto error; 3078 } 3079 return ret; 3080 cleanup: 3081 bnxt_free_filter(bp, bfilter); 3082 error: 3083 return ret; 3084 } 3085 3086 static inline int 3087 parse_ntuple_filter(struct bnxt *bp, 3088 struct rte_eth_ntuple_filter *nfilter, 3089 struct bnxt_filter_info *bfilter) 3090 { 3091 uint32_t en = 0; 3092 3093 if (nfilter->queue >= bp->rx_nr_rings) { 3094 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 3095 return -EINVAL; 3096 } 3097 3098 switch (nfilter->dst_port_mask) { 3099 case UINT16_MAX: 3100 bfilter->dst_port_mask = -1; 3101 bfilter->dst_port = nfilter->dst_port; 3102 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 3103 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3104 break; 3105 default: 3106 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 3107 return -EINVAL; 3108 } 3109 3110 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3111 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3112 3113 switch (nfilter->proto_mask) { 3114 case UINT8_MAX: 3115 if (nfilter->proto == 17) /* IPPROTO_UDP */ 3116 bfilter->ip_protocol = 17; 3117 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 3118 bfilter->ip_protocol = 6; 3119 else 3120 return -EINVAL; 3121 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3122 break; 3123 default: 3124 PMD_DRV_LOG(ERR, "invalid protocol mask."); 3125 return -EINVAL; 3126 } 3127 3128 switch (nfilter->dst_ip_mask) { 3129 case UINT32_MAX: 3130 bfilter->dst_ipaddr_mask[0] = -1; 3131 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 3132 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 3133 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3134 break; 3135 default: 3136 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3137 return -EINVAL; 3138 } 3139 3140 switch (nfilter->src_ip_mask) { 3141 case UINT32_MAX: 3142 bfilter->src_ipaddr_mask[0] = -1; 3143 bfilter->src_ipaddr[0] = nfilter->src_ip; 3144 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 3145 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3146 break; 3147 default: 3148 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 3149 return -EINVAL; 3150 } 3151 3152 switch (nfilter->src_port_mask) { 3153 case UINT16_MAX: 3154 bfilter->src_port_mask = -1; 3155 bfilter->src_port = nfilter->src_port; 3156 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 3157 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3158 break; 3159 default: 3160 PMD_DRV_LOG(ERR, "invalid src_port mask."); 3161 return -EINVAL; 3162 } 3163 3164 bfilter->enables = en; 3165 return 0; 3166 } 3167 3168 static struct bnxt_filter_info* 3169 bnxt_match_ntuple_filter(struct bnxt *bp, 3170 struct bnxt_filter_info *bfilter, 3171 struct bnxt_vnic_info **mvnic) 3172 { 3173 struct bnxt_filter_info *mfilter = NULL; 3174 int i; 3175 3176 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3177 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3178 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 3179 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 3180 bfilter->src_ipaddr_mask[0] == 3181 mfilter->src_ipaddr_mask[0] && 3182 bfilter->src_port == mfilter->src_port && 3183 bfilter->src_port_mask == mfilter->src_port_mask && 3184 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 3185 bfilter->dst_ipaddr_mask[0] == 3186 mfilter->dst_ipaddr_mask[0] && 3187 bfilter->dst_port == mfilter->dst_port && 3188 bfilter->dst_port_mask == mfilter->dst_port_mask && 3189 bfilter->flags == mfilter->flags && 3190 bfilter->enables == mfilter->enables) { 3191 if (mvnic) 3192 *mvnic = vnic; 3193 return mfilter; 3194 } 3195 } 3196 } 3197 return NULL; 3198 } 3199 3200 static int 3201 bnxt_cfg_ntuple_filter(struct bnxt *bp, 3202 struct rte_eth_ntuple_filter *nfilter, 3203 enum rte_filter_op filter_op) 3204 { 3205 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 3206 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 3207 int ret; 3208 3209 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 3210 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 3211 return -EINVAL; 3212 } 3213 3214 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 3215 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 3216 return -EINVAL; 3217 } 3218 3219 bfilter = bnxt_get_unused_filter(bp); 3220 if (bfilter == NULL) { 3221 PMD_DRV_LOG(ERR, 3222 "Not enough resources for a new filter.\n"); 3223 return -ENOMEM; 3224 } 3225 ret = parse_ntuple_filter(bp, nfilter, bfilter); 3226 if (ret < 0) 3227 goto free_filter; 3228 3229 vnic = &bp->vnic_info[nfilter->queue]; 3230 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3231 filter1 = STAILQ_FIRST(&vnic0->filter); 3232 if (filter1 == NULL) { 3233 ret = -EINVAL; 3234 goto free_filter; 3235 } 3236 3237 bfilter->dst_id = vnic->fw_vnic_id; 3238 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3239 bfilter->enables |= 3240 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3241 bfilter->ethertype = 0x800; 3242 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3243 3244 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 3245 3246 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 3247 bfilter->dst_id == mfilter->dst_id) { 3248 PMD_DRV_LOG(ERR, "filter exists.\n"); 3249 ret = -EEXIST; 3250 goto free_filter; 3251 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 3252 bfilter->dst_id != mfilter->dst_id) { 3253 mfilter->dst_id = vnic->fw_vnic_id; 3254 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 3255 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 3256 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 3257 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 3258 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 3259 goto free_filter; 3260 } 3261 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3262 PMD_DRV_LOG(ERR, "filter doesn't exist."); 3263 ret = -ENOENT; 3264 goto free_filter; 3265 } 3266 3267 if (filter_op == RTE_ETH_FILTER_ADD) { 3268 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3269 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 3270 if (ret) 3271 goto free_filter; 3272 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 3273 } else { 3274 if (mfilter == NULL) { 3275 /* This should not happen. But for Coverity! */ 3276 ret = -ENOENT; 3277 goto free_filter; 3278 } 3279 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 3280 3281 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 3282 bnxt_free_filter(bp, mfilter); 3283 bnxt_free_filter(bp, bfilter); 3284 } 3285 3286 return 0; 3287 free_filter: 3288 bnxt_free_filter(bp, bfilter); 3289 return ret; 3290 } 3291 3292 static int 3293 bnxt_ntuple_filter(struct rte_eth_dev *dev, 3294 enum rte_filter_op filter_op, 3295 void *arg) 3296 { 3297 struct bnxt *bp = dev->data->dev_private; 3298 int ret; 3299 3300 if (filter_op == RTE_ETH_FILTER_NOP) 3301 return 0; 3302 3303 if (arg == NULL) { 3304 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 3305 filter_op); 3306 return -EINVAL; 3307 } 3308 3309 switch (filter_op) { 3310 case RTE_ETH_FILTER_ADD: 3311 ret = bnxt_cfg_ntuple_filter(bp, 3312 (struct rte_eth_ntuple_filter *)arg, 3313 filter_op); 3314 break; 3315 case RTE_ETH_FILTER_DELETE: 3316 ret = bnxt_cfg_ntuple_filter(bp, 3317 (struct rte_eth_ntuple_filter *)arg, 3318 filter_op); 3319 break; 3320 default: 3321 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 3322 ret = -EINVAL; 3323 break; 3324 } 3325 return ret; 3326 } 3327 3328 static int 3329 bnxt_parse_fdir_filter(struct bnxt *bp, 3330 struct rte_eth_fdir_filter *fdir, 3331 struct bnxt_filter_info *filter) 3332 { 3333 enum rte_fdir_mode fdir_mode = 3334 bp->eth_dev->data->dev_conf.fdir_conf.mode; 3335 struct bnxt_vnic_info *vnic0, *vnic; 3336 struct bnxt_filter_info *filter1; 3337 uint32_t en = 0; 3338 int i; 3339 3340 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 3341 return -EINVAL; 3342 3343 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 3344 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 3345 3346 switch (fdir->input.flow_type) { 3347 case RTE_ETH_FLOW_IPV4: 3348 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3349 /* FALLTHROUGH */ 3350 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 3351 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3352 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 3353 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3354 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 3355 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3356 filter->ip_addr_type = 3357 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3358 filter->src_ipaddr_mask[0] = 0xffffffff; 3359 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3360 filter->dst_ipaddr_mask[0] = 0xffffffff; 3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3362 filter->ethertype = 0x800; 3363 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3364 break; 3365 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3366 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 3367 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3368 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 3369 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3370 filter->dst_port_mask = 0xffff; 3371 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3372 filter->src_port_mask = 0xffff; 3373 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3374 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 3375 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3376 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 3377 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3378 filter->ip_protocol = 6; 3379 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3380 filter->ip_addr_type = 3381 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3382 filter->src_ipaddr_mask[0] = 0xffffffff; 3383 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3384 filter->dst_ipaddr_mask[0] = 0xffffffff; 3385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3386 filter->ethertype = 0x800; 3387 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3388 break; 3389 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3390 filter->src_port = fdir->input.flow.udp4_flow.src_port; 3391 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3392 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 3393 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3394 filter->dst_port_mask = 0xffff; 3395 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3396 filter->src_port_mask = 0xffff; 3397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3398 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 3399 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3400 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 3401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3402 filter->ip_protocol = 17; 3403 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3404 filter->ip_addr_type = 3405 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3406 filter->src_ipaddr_mask[0] = 0xffffffff; 3407 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3408 filter->dst_ipaddr_mask[0] = 0xffffffff; 3409 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3410 filter->ethertype = 0x800; 3411 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3412 break; 3413 case RTE_ETH_FLOW_IPV6: 3414 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3415 /* FALLTHROUGH */ 3416 filter->ip_addr_type = 3417 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3418 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 3419 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3420 rte_memcpy(filter->src_ipaddr, 3421 fdir->input.flow.ipv6_flow.src_ip, 16); 3422 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3423 rte_memcpy(filter->dst_ipaddr, 3424 fdir->input.flow.ipv6_flow.dst_ip, 16); 3425 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3426 memset(filter->dst_ipaddr_mask, 0xff, 16); 3427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3428 memset(filter->src_ipaddr_mask, 0xff, 16); 3429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3430 filter->ethertype = 0x86dd; 3431 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3432 break; 3433 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3434 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 3435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3436 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 3437 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3438 filter->dst_port_mask = 0xffff; 3439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3440 filter->src_port_mask = 0xffff; 3441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3442 filter->ip_addr_type = 3443 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3444 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 3445 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3446 rte_memcpy(filter->src_ipaddr, 3447 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 3448 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3449 rte_memcpy(filter->dst_ipaddr, 3450 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 3451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3452 memset(filter->dst_ipaddr_mask, 0xff, 16); 3453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3454 memset(filter->src_ipaddr_mask, 0xff, 16); 3455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3456 filter->ethertype = 0x86dd; 3457 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3458 break; 3459 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3460 filter->src_port = fdir->input.flow.udp6_flow.src_port; 3461 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3462 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 3463 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3464 filter->dst_port_mask = 0xffff; 3465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3466 filter->src_port_mask = 0xffff; 3467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3468 filter->ip_addr_type = 3469 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3470 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 3471 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3472 rte_memcpy(filter->src_ipaddr, 3473 fdir->input.flow.udp6_flow.ip.src_ip, 16); 3474 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3475 rte_memcpy(filter->dst_ipaddr, 3476 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 3477 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3478 memset(filter->dst_ipaddr_mask, 0xff, 16); 3479 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3480 memset(filter->src_ipaddr_mask, 0xff, 16); 3481 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3482 filter->ethertype = 0x86dd; 3483 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3484 break; 3485 case RTE_ETH_FLOW_L2_PAYLOAD: 3486 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 3487 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3488 break; 3489 case RTE_ETH_FLOW_VXLAN: 3490 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3491 return -EINVAL; 3492 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3493 filter->tunnel_type = 3494 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 3495 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3496 break; 3497 case RTE_ETH_FLOW_NVGRE: 3498 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3499 return -EINVAL; 3500 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3501 filter->tunnel_type = 3502 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 3503 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3504 break; 3505 case RTE_ETH_FLOW_UNKNOWN: 3506 case RTE_ETH_FLOW_RAW: 3507 case RTE_ETH_FLOW_FRAG_IPV4: 3508 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 3509 case RTE_ETH_FLOW_FRAG_IPV6: 3510 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 3511 case RTE_ETH_FLOW_IPV6_EX: 3512 case RTE_ETH_FLOW_IPV6_TCP_EX: 3513 case RTE_ETH_FLOW_IPV6_UDP_EX: 3514 case RTE_ETH_FLOW_GENEVE: 3515 /* FALLTHROUGH */ 3516 default: 3517 return -EINVAL; 3518 } 3519 3520 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3521 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3522 if (vnic == NULL) { 3523 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 3524 return -EINVAL; 3525 } 3526 3527 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3528 rte_memcpy(filter->dst_macaddr, 3529 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 3530 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 3531 } 3532 3533 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 3534 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 3535 filter1 = STAILQ_FIRST(&vnic0->filter); 3536 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 3537 } else { 3538 filter->dst_id = vnic->fw_vnic_id; 3539 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3540 if (filter->dst_macaddr[i] == 0x00) 3541 filter1 = STAILQ_FIRST(&vnic0->filter); 3542 else 3543 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 3544 } 3545 3546 if (filter1 == NULL) 3547 return -EINVAL; 3548 3549 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3550 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3551 3552 filter->enables = en; 3553 3554 return 0; 3555 } 3556 3557 static struct bnxt_filter_info * 3558 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 3559 struct bnxt_vnic_info **mvnic) 3560 { 3561 struct bnxt_filter_info *mf = NULL; 3562 int i; 3563 3564 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3565 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3566 3567 STAILQ_FOREACH(mf, &vnic->filter, next) { 3568 if (mf->filter_type == nf->filter_type && 3569 mf->flags == nf->flags && 3570 mf->src_port == nf->src_port && 3571 mf->src_port_mask == nf->src_port_mask && 3572 mf->dst_port == nf->dst_port && 3573 mf->dst_port_mask == nf->dst_port_mask && 3574 mf->ip_protocol == nf->ip_protocol && 3575 mf->ip_addr_type == nf->ip_addr_type && 3576 mf->ethertype == nf->ethertype && 3577 mf->vni == nf->vni && 3578 mf->tunnel_type == nf->tunnel_type && 3579 mf->l2_ovlan == nf->l2_ovlan && 3580 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 3581 mf->l2_ivlan == nf->l2_ivlan && 3582 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 3583 !memcmp(mf->l2_addr, nf->l2_addr, 3584 RTE_ETHER_ADDR_LEN) && 3585 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 3586 RTE_ETHER_ADDR_LEN) && 3587 !memcmp(mf->src_macaddr, nf->src_macaddr, 3588 RTE_ETHER_ADDR_LEN) && 3589 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 3590 RTE_ETHER_ADDR_LEN) && 3591 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 3592 sizeof(nf->src_ipaddr)) && 3593 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 3594 sizeof(nf->src_ipaddr_mask)) && 3595 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 3596 sizeof(nf->dst_ipaddr)) && 3597 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 3598 sizeof(nf->dst_ipaddr_mask))) { 3599 if (mvnic) 3600 *mvnic = vnic; 3601 return mf; 3602 } 3603 } 3604 } 3605 return NULL; 3606 } 3607 3608 static int 3609 bnxt_fdir_filter(struct rte_eth_dev *dev, 3610 enum rte_filter_op filter_op, 3611 void *arg) 3612 { 3613 struct bnxt *bp = dev->data->dev_private; 3614 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 3615 struct bnxt_filter_info *filter, *match; 3616 struct bnxt_vnic_info *vnic, *mvnic; 3617 int ret = 0, i; 3618 3619 if (filter_op == RTE_ETH_FILTER_NOP) 3620 return 0; 3621 3622 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 3623 return -EINVAL; 3624 3625 switch (filter_op) { 3626 case RTE_ETH_FILTER_ADD: 3627 case RTE_ETH_FILTER_DELETE: 3628 /* FALLTHROUGH */ 3629 filter = bnxt_get_unused_filter(bp); 3630 if (filter == NULL) { 3631 PMD_DRV_LOG(ERR, 3632 "Not enough resources for a new flow.\n"); 3633 return -ENOMEM; 3634 } 3635 3636 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 3637 if (ret != 0) 3638 goto free_filter; 3639 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3640 3641 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3642 vnic = &bp->vnic_info[0]; 3643 else 3644 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3645 3646 match = bnxt_match_fdir(bp, filter, &mvnic); 3647 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 3648 if (match->dst_id == vnic->fw_vnic_id) { 3649 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 3650 ret = -EEXIST; 3651 goto free_filter; 3652 } else { 3653 match->dst_id = vnic->fw_vnic_id; 3654 ret = bnxt_hwrm_set_ntuple_filter(bp, 3655 match->dst_id, 3656 match); 3657 STAILQ_REMOVE(&mvnic->filter, match, 3658 bnxt_filter_info, next); 3659 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 3660 PMD_DRV_LOG(ERR, 3661 "Filter with matching pattern exist\n"); 3662 PMD_DRV_LOG(ERR, 3663 "Updated it to new destination q\n"); 3664 goto free_filter; 3665 } 3666 } 3667 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3668 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 3669 ret = -ENOENT; 3670 goto free_filter; 3671 } 3672 3673 if (filter_op == RTE_ETH_FILTER_ADD) { 3674 ret = bnxt_hwrm_set_ntuple_filter(bp, 3675 filter->dst_id, 3676 filter); 3677 if (ret) 3678 goto free_filter; 3679 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 3680 } else { 3681 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 3682 STAILQ_REMOVE(&vnic->filter, match, 3683 bnxt_filter_info, next); 3684 bnxt_free_filter(bp, match); 3685 bnxt_free_filter(bp, filter); 3686 } 3687 break; 3688 case RTE_ETH_FILTER_FLUSH: 3689 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3690 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3691 3692 STAILQ_FOREACH(filter, &vnic->filter, next) { 3693 if (filter->filter_type == 3694 HWRM_CFA_NTUPLE_FILTER) { 3695 ret = 3696 bnxt_hwrm_clear_ntuple_filter(bp, 3697 filter); 3698 STAILQ_REMOVE(&vnic->filter, filter, 3699 bnxt_filter_info, next); 3700 } 3701 } 3702 } 3703 return ret; 3704 case RTE_ETH_FILTER_UPDATE: 3705 case RTE_ETH_FILTER_STATS: 3706 case RTE_ETH_FILTER_INFO: 3707 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 3708 break; 3709 default: 3710 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 3711 ret = -EINVAL; 3712 break; 3713 } 3714 return ret; 3715 3716 free_filter: 3717 bnxt_free_filter(bp, filter); 3718 return ret; 3719 } 3720 3721 int 3722 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3723 enum rte_filter_type filter_type, 3724 enum rte_filter_op filter_op, void *arg) 3725 { 3726 struct bnxt *bp = dev->data->dev_private; 3727 int ret = 0; 3728 3729 if (!bp) 3730 return -EIO; 3731 3732 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3733 struct bnxt_vf_representor *vfr = dev->data->dev_private; 3734 bp = vfr->parent_dev->data->dev_private; 3735 /* parent is deleted while children are still valid */ 3736 if (!bp) { 3737 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n", 3738 dev->data->port_id, 3739 filter_type, 3740 filter_op); 3741 return -EIO; 3742 } 3743 } 3744 3745 ret = is_bnxt_in_error(bp); 3746 if (ret) 3747 return ret; 3748 3749 switch (filter_type) { 3750 case RTE_ETH_FILTER_TUNNEL: 3751 PMD_DRV_LOG(ERR, 3752 "filter type: %d: To be implemented\n", filter_type); 3753 break; 3754 case RTE_ETH_FILTER_FDIR: 3755 ret = bnxt_fdir_filter(dev, filter_op, arg); 3756 break; 3757 case RTE_ETH_FILTER_NTUPLE: 3758 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3759 break; 3760 case RTE_ETH_FILTER_ETHERTYPE: 3761 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3762 break; 3763 case RTE_ETH_FILTER_GENERIC: 3764 if (filter_op != RTE_ETH_FILTER_GET) 3765 return -EINVAL; 3766 if (BNXT_TRUFLOW_EN(bp)) 3767 *(const void **)arg = &bnxt_ulp_rte_flow_ops; 3768 else 3769 *(const void **)arg = &bnxt_flow_ops; 3770 break; 3771 default: 3772 PMD_DRV_LOG(ERR, 3773 "Filter type (%d) not supported", filter_type); 3774 ret = -EINVAL; 3775 break; 3776 } 3777 return ret; 3778 } 3779 3780 static const uint32_t * 3781 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3782 { 3783 static const uint32_t ptypes[] = { 3784 RTE_PTYPE_L2_ETHER_VLAN, 3785 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3786 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3787 RTE_PTYPE_L4_ICMP, 3788 RTE_PTYPE_L4_TCP, 3789 RTE_PTYPE_L4_UDP, 3790 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3791 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3792 RTE_PTYPE_INNER_L4_ICMP, 3793 RTE_PTYPE_INNER_L4_TCP, 3794 RTE_PTYPE_INNER_L4_UDP, 3795 RTE_PTYPE_UNKNOWN 3796 }; 3797 3798 if (!dev->rx_pkt_burst) 3799 return NULL; 3800 3801 return ptypes; 3802 } 3803 3804 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3805 int reg_win) 3806 { 3807 uint32_t reg_base = *reg_arr & 0xfffff000; 3808 uint32_t win_off; 3809 int i; 3810 3811 for (i = 0; i < count; i++) { 3812 if ((reg_arr[i] & 0xfffff000) != reg_base) 3813 return -ERANGE; 3814 } 3815 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3816 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3817 return 0; 3818 } 3819 3820 static int bnxt_map_ptp_regs(struct bnxt *bp) 3821 { 3822 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3823 uint32_t *reg_arr; 3824 int rc, i; 3825 3826 reg_arr = ptp->rx_regs; 3827 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3828 if (rc) 3829 return rc; 3830 3831 reg_arr = ptp->tx_regs; 3832 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3833 if (rc) 3834 return rc; 3835 3836 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3837 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3838 3839 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3840 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3841 3842 return 0; 3843 } 3844 3845 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3846 { 3847 rte_write32(0, (uint8_t *)bp->bar0 + 3848 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3849 rte_write32(0, (uint8_t *)bp->bar0 + 3850 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3851 } 3852 3853 static uint64_t bnxt_cc_read(struct bnxt *bp) 3854 { 3855 uint64_t ns; 3856 3857 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3858 BNXT_GRCPF_REG_SYNC_TIME)); 3859 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3860 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3861 return ns; 3862 } 3863 3864 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3865 { 3866 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3867 uint32_t fifo; 3868 3869 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3870 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3871 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3872 return -EAGAIN; 3873 3874 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3875 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3876 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3877 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3878 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3879 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3880 3881 return 0; 3882 } 3883 3884 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3885 { 3886 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3887 struct bnxt_pf_info *pf = bp->pf; 3888 uint16_t port_id; 3889 uint32_t fifo; 3890 3891 if (!ptp) 3892 return -ENODEV; 3893 3894 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3895 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3896 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3897 return -EAGAIN; 3898 3899 port_id = pf->port_id; 3900 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3901 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3902 3903 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3904 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3905 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3906 /* bnxt_clr_rx_ts(bp); TBD */ 3907 return -EBUSY; 3908 } 3909 3910 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3911 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3912 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3913 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3914 3915 return 0; 3916 } 3917 3918 static int 3919 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3920 { 3921 uint64_t ns; 3922 struct bnxt *bp = dev->data->dev_private; 3923 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3924 3925 if (!ptp) 3926 return 0; 3927 3928 ns = rte_timespec_to_ns(ts); 3929 /* Set the timecounters to a new value. */ 3930 ptp->tc.nsec = ns; 3931 3932 return 0; 3933 } 3934 3935 static int 3936 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3937 { 3938 struct bnxt *bp = dev->data->dev_private; 3939 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3940 uint64_t ns, systime_cycles = 0; 3941 int rc = 0; 3942 3943 if (!ptp) 3944 return 0; 3945 3946 if (BNXT_CHIP_THOR(bp)) 3947 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3948 &systime_cycles); 3949 else 3950 systime_cycles = bnxt_cc_read(bp); 3951 3952 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3953 *ts = rte_ns_to_timespec(ns); 3954 3955 return rc; 3956 } 3957 static int 3958 bnxt_timesync_enable(struct rte_eth_dev *dev) 3959 { 3960 struct bnxt *bp = dev->data->dev_private; 3961 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3962 uint32_t shift = 0; 3963 int rc; 3964 3965 if (!ptp) 3966 return 0; 3967 3968 ptp->rx_filter = 1; 3969 ptp->tx_tstamp_en = 1; 3970 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3971 3972 rc = bnxt_hwrm_ptp_cfg(bp); 3973 if (rc) 3974 return rc; 3975 3976 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3977 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3978 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3979 3980 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3981 ptp->tc.cc_shift = shift; 3982 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3983 3984 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3985 ptp->rx_tstamp_tc.cc_shift = shift; 3986 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3987 3988 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3989 ptp->tx_tstamp_tc.cc_shift = shift; 3990 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3991 3992 if (!BNXT_CHIP_THOR(bp)) 3993 bnxt_map_ptp_regs(bp); 3994 3995 return 0; 3996 } 3997 3998 static int 3999 bnxt_timesync_disable(struct rte_eth_dev *dev) 4000 { 4001 struct bnxt *bp = dev->data->dev_private; 4002 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 4003 4004 if (!ptp) 4005 return 0; 4006 4007 ptp->rx_filter = 0; 4008 ptp->tx_tstamp_en = 0; 4009 ptp->rxctl = 0; 4010 4011 bnxt_hwrm_ptp_cfg(bp); 4012 4013 if (!BNXT_CHIP_THOR(bp)) 4014 bnxt_unmap_ptp_regs(bp); 4015 4016 return 0; 4017 } 4018 4019 static int 4020 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 4021 struct timespec *timestamp, 4022 uint32_t flags __rte_unused) 4023 { 4024 struct bnxt *bp = dev->data->dev_private; 4025 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 4026 uint64_t rx_tstamp_cycles = 0; 4027 uint64_t ns; 4028 4029 if (!ptp) 4030 return 0; 4031 4032 if (BNXT_CHIP_THOR(bp)) 4033 rx_tstamp_cycles = ptp->rx_timestamp; 4034 else 4035 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 4036 4037 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 4038 *timestamp = rte_ns_to_timespec(ns); 4039 return 0; 4040 } 4041 4042 static int 4043 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4044 struct timespec *timestamp) 4045 { 4046 struct bnxt *bp = dev->data->dev_private; 4047 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 4048 uint64_t tx_tstamp_cycles = 0; 4049 uint64_t ns; 4050 int rc = 0; 4051 4052 if (!ptp) 4053 return 0; 4054 4055 if (BNXT_CHIP_THOR(bp)) 4056 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 4057 &tx_tstamp_cycles); 4058 else 4059 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 4060 4061 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 4062 *timestamp = rte_ns_to_timespec(ns); 4063 4064 return rc; 4065 } 4066 4067 static int 4068 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4069 { 4070 struct bnxt *bp = dev->data->dev_private; 4071 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 4072 4073 if (!ptp) 4074 return 0; 4075 4076 ptp->tc.nsec += delta; 4077 4078 return 0; 4079 } 4080 4081 static int 4082 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 4083 { 4084 struct bnxt *bp = dev->data->dev_private; 4085 int rc; 4086 uint32_t dir_entries; 4087 uint32_t entry_length; 4088 4089 rc = is_bnxt_in_error(bp); 4090 if (rc) 4091 return rc; 4092 4093 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 4094 bp->pdev->addr.domain, bp->pdev->addr.bus, 4095 bp->pdev->addr.devid, bp->pdev->addr.function); 4096 4097 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 4098 if (rc != 0) 4099 return rc; 4100 4101 return dir_entries * entry_length; 4102 } 4103 4104 static int 4105 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 4106 struct rte_dev_eeprom_info *in_eeprom) 4107 { 4108 struct bnxt *bp = dev->data->dev_private; 4109 uint32_t index; 4110 uint32_t offset; 4111 int rc; 4112 4113 rc = is_bnxt_in_error(bp); 4114 if (rc) 4115 return rc; 4116 4117 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 4118 bp->pdev->addr.domain, bp->pdev->addr.bus, 4119 bp->pdev->addr.devid, bp->pdev->addr.function, 4120 in_eeprom->offset, in_eeprom->length); 4121 4122 if (in_eeprom->offset == 0) /* special offset value to get directory */ 4123 return bnxt_get_nvram_directory(bp, in_eeprom->length, 4124 in_eeprom->data); 4125 4126 index = in_eeprom->offset >> 24; 4127 offset = in_eeprom->offset & 0xffffff; 4128 4129 if (index != 0) 4130 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 4131 in_eeprom->length, in_eeprom->data); 4132 4133 return 0; 4134 } 4135 4136 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 4137 { 4138 switch (dir_type) { 4139 case BNX_DIR_TYPE_CHIMP_PATCH: 4140 case BNX_DIR_TYPE_BOOTCODE: 4141 case BNX_DIR_TYPE_BOOTCODE_2: 4142 case BNX_DIR_TYPE_APE_FW: 4143 case BNX_DIR_TYPE_APE_PATCH: 4144 case BNX_DIR_TYPE_KONG_FW: 4145 case BNX_DIR_TYPE_KONG_PATCH: 4146 case BNX_DIR_TYPE_BONO_FW: 4147 case BNX_DIR_TYPE_BONO_PATCH: 4148 /* FALLTHROUGH */ 4149 return true; 4150 } 4151 4152 return false; 4153 } 4154 4155 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 4156 { 4157 switch (dir_type) { 4158 case BNX_DIR_TYPE_AVS: 4159 case BNX_DIR_TYPE_EXP_ROM_MBA: 4160 case BNX_DIR_TYPE_PCIE: 4161 case BNX_DIR_TYPE_TSCF_UCODE: 4162 case BNX_DIR_TYPE_EXT_PHY: 4163 case BNX_DIR_TYPE_CCM: 4164 case BNX_DIR_TYPE_ISCSI_BOOT: 4165 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 4166 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 4167 /* FALLTHROUGH */ 4168 return true; 4169 } 4170 4171 return false; 4172 } 4173 4174 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 4175 { 4176 return bnxt_dir_type_is_ape_bin_format(dir_type) || 4177 bnxt_dir_type_is_other_exec_format(dir_type); 4178 } 4179 4180 static int 4181 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 4182 struct rte_dev_eeprom_info *in_eeprom) 4183 { 4184 struct bnxt *bp = dev->data->dev_private; 4185 uint8_t index, dir_op; 4186 uint16_t type, ext, ordinal, attr; 4187 int rc; 4188 4189 rc = is_bnxt_in_error(bp); 4190 if (rc) 4191 return rc; 4192 4193 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 4194 bp->pdev->addr.domain, bp->pdev->addr.bus, 4195 bp->pdev->addr.devid, bp->pdev->addr.function, 4196 in_eeprom->offset, in_eeprom->length); 4197 4198 if (!BNXT_PF(bp)) { 4199 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 4200 return -EINVAL; 4201 } 4202 4203 type = in_eeprom->magic >> 16; 4204 4205 if (type == 0xffff) { /* special value for directory operations */ 4206 index = in_eeprom->magic & 0xff; 4207 dir_op = in_eeprom->magic >> 8; 4208 if (index == 0) 4209 return -EINVAL; 4210 switch (dir_op) { 4211 case 0x0e: /* erase */ 4212 if (in_eeprom->offset != ~in_eeprom->magic) 4213 return -EINVAL; 4214 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 4215 default: 4216 return -EINVAL; 4217 } 4218 } 4219 4220 /* Create or re-write an NVM item: */ 4221 if (bnxt_dir_type_is_executable(type) == true) 4222 return -EOPNOTSUPP; 4223 ext = in_eeprom->magic & 0xffff; 4224 ordinal = in_eeprom->offset >> 16; 4225 attr = in_eeprom->offset & 0xffff; 4226 4227 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 4228 in_eeprom->data, in_eeprom->length); 4229 } 4230 4231 /* 4232 * Initialization 4233 */ 4234 4235 static const struct eth_dev_ops bnxt_dev_ops = { 4236 .dev_infos_get = bnxt_dev_info_get_op, 4237 .dev_close = bnxt_dev_close_op, 4238 .dev_configure = bnxt_dev_configure_op, 4239 .dev_start = bnxt_dev_start_op, 4240 .dev_stop = bnxt_dev_stop_op, 4241 .dev_set_link_up = bnxt_dev_set_link_up_op, 4242 .dev_set_link_down = bnxt_dev_set_link_down_op, 4243 .stats_get = bnxt_stats_get_op, 4244 .stats_reset = bnxt_stats_reset_op, 4245 .rx_queue_setup = bnxt_rx_queue_setup_op, 4246 .rx_queue_release = bnxt_rx_queue_release_op, 4247 .tx_queue_setup = bnxt_tx_queue_setup_op, 4248 .tx_queue_release = bnxt_tx_queue_release_op, 4249 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4250 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4251 .reta_update = bnxt_reta_update_op, 4252 .reta_query = bnxt_reta_query_op, 4253 .rss_hash_update = bnxt_rss_hash_update_op, 4254 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4255 .link_update = bnxt_link_update_op, 4256 .promiscuous_enable = bnxt_promiscuous_enable_op, 4257 .promiscuous_disable = bnxt_promiscuous_disable_op, 4258 .allmulticast_enable = bnxt_allmulticast_enable_op, 4259 .allmulticast_disable = bnxt_allmulticast_disable_op, 4260 .mac_addr_add = bnxt_mac_addr_add_op, 4261 .mac_addr_remove = bnxt_mac_addr_remove_op, 4262 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4263 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4264 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4265 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4266 .vlan_filter_set = bnxt_vlan_filter_set_op, 4267 .vlan_offload_set = bnxt_vlan_offload_set_op, 4268 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4269 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4270 .mtu_set = bnxt_mtu_set_op, 4271 .mac_addr_set = bnxt_set_default_mac_addr_op, 4272 .xstats_get = bnxt_dev_xstats_get_op, 4273 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4274 .xstats_reset = bnxt_dev_xstats_reset_op, 4275 .fw_version_get = bnxt_fw_version_get, 4276 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4277 .rxq_info_get = bnxt_rxq_info_get_op, 4278 .txq_info_get = bnxt_txq_info_get_op, 4279 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 4280 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 4281 .dev_led_on = bnxt_dev_led_on_op, 4282 .dev_led_off = bnxt_dev_led_off_op, 4283 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 4284 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 4285 .rx_queue_start = bnxt_rx_queue_start, 4286 .rx_queue_stop = bnxt_rx_queue_stop, 4287 .tx_queue_start = bnxt_tx_queue_start, 4288 .tx_queue_stop = bnxt_tx_queue_stop, 4289 .filter_ctrl = bnxt_filter_ctrl_op, 4290 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4291 .get_eeprom_length = bnxt_get_eeprom_length_op, 4292 .get_eeprom = bnxt_get_eeprom_op, 4293 .set_eeprom = bnxt_set_eeprom_op, 4294 .timesync_enable = bnxt_timesync_enable, 4295 .timesync_disable = bnxt_timesync_disable, 4296 .timesync_read_time = bnxt_timesync_read_time, 4297 .timesync_write_time = bnxt_timesync_write_time, 4298 .timesync_adjust_time = bnxt_timesync_adjust_time, 4299 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4300 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4301 }; 4302 4303 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4304 { 4305 uint32_t offset; 4306 4307 /* Only pre-map the reset GRC registers using window 3 */ 4308 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4309 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4310 4311 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4312 4313 return offset; 4314 } 4315 4316 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4317 { 4318 struct bnxt_error_recovery_info *info = bp->recovery_info; 4319 uint32_t reg_base = 0xffffffff; 4320 int i; 4321 4322 /* Only pre-map the monitoring GRC registers using window 2 */ 4323 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4324 uint32_t reg = info->status_regs[i]; 4325 4326 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4327 continue; 4328 4329 if (reg_base == 0xffffffff) 4330 reg_base = reg & 0xfffff000; 4331 if ((reg & 0xfffff000) != reg_base) 4332 return -ERANGE; 4333 4334 /* Use mask 0xffc as the Lower 2 bits indicates 4335 * address space location 4336 */ 4337 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4338 (reg & 0xffc); 4339 } 4340 4341 if (reg_base == 0xffffffff) 4342 return 0; 4343 4344 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4345 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4346 4347 return 0; 4348 } 4349 4350 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4351 { 4352 struct bnxt_error_recovery_info *info = bp->recovery_info; 4353 uint32_t delay = info->delay_after_reset[index]; 4354 uint32_t val = info->reset_reg_val[index]; 4355 uint32_t reg = info->reset_reg[index]; 4356 uint32_t type, offset; 4357 4358 type = BNXT_FW_STATUS_REG_TYPE(reg); 4359 offset = BNXT_FW_STATUS_REG_OFF(reg); 4360 4361 switch (type) { 4362 case BNXT_FW_STATUS_REG_TYPE_CFG: 4363 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4364 break; 4365 case BNXT_FW_STATUS_REG_TYPE_GRC: 4366 offset = bnxt_map_reset_regs(bp, offset); 4367 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4368 break; 4369 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4370 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4371 break; 4372 } 4373 /* wait on a specific interval of time until core reset is complete */ 4374 if (delay) 4375 rte_delay_ms(delay); 4376 } 4377 4378 static void bnxt_dev_cleanup(struct bnxt *bp) 4379 { 4380 bnxt_set_hwrm_link_config(bp, false); 4381 bp->link_info->link_up = 0; 4382 if (bp->eth_dev->data->dev_started) 4383 bnxt_dev_stop_op(bp->eth_dev); 4384 4385 bnxt_uninit_resources(bp, true); 4386 } 4387 4388 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4389 { 4390 struct rte_eth_dev *dev = bp->eth_dev; 4391 struct rte_vlan_filter_conf *vfc; 4392 int vidx, vbit, rc; 4393 uint16_t vlan_id; 4394 4395 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4396 vfc = &dev->data->vlan_filter_conf; 4397 vidx = vlan_id / 64; 4398 vbit = vlan_id % 64; 4399 4400 /* Each bit corresponds to a VLAN id */ 4401 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4402 rc = bnxt_add_vlan_filter(bp, vlan_id); 4403 if (rc) 4404 return rc; 4405 } 4406 } 4407 4408 return 0; 4409 } 4410 4411 static int bnxt_restore_mac_filters(struct bnxt *bp) 4412 { 4413 struct rte_eth_dev *dev = bp->eth_dev; 4414 struct rte_eth_dev_info dev_info; 4415 struct rte_ether_addr *addr; 4416 uint64_t pool_mask; 4417 uint32_t pool = 0; 4418 uint16_t i; 4419 int rc; 4420 4421 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4422 return 0; 4423 4424 rc = bnxt_dev_info_get_op(dev, &dev_info); 4425 if (rc) 4426 return rc; 4427 4428 /* replay MAC address configuration */ 4429 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4430 addr = &dev->data->mac_addrs[i]; 4431 4432 /* skip zero address */ 4433 if (rte_is_zero_ether_addr(addr)) 4434 continue; 4435 4436 pool = 0; 4437 pool_mask = dev->data->mac_pool_sel[i]; 4438 4439 do { 4440 if (pool_mask & 1ULL) { 4441 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4442 if (rc) 4443 return rc; 4444 } 4445 pool_mask >>= 1; 4446 pool++; 4447 } while (pool_mask); 4448 } 4449 4450 return 0; 4451 } 4452 4453 static int bnxt_restore_filters(struct bnxt *bp) 4454 { 4455 struct rte_eth_dev *dev = bp->eth_dev; 4456 int ret = 0; 4457 4458 if (dev->data->all_multicast) { 4459 ret = bnxt_allmulticast_enable_op(dev); 4460 if (ret) 4461 return ret; 4462 } 4463 if (dev->data->promiscuous) { 4464 ret = bnxt_promiscuous_enable_op(dev); 4465 if (ret) 4466 return ret; 4467 } 4468 4469 ret = bnxt_restore_mac_filters(bp); 4470 if (ret) 4471 return ret; 4472 4473 ret = bnxt_restore_vlan_filters(bp); 4474 /* TODO restore other filters as well */ 4475 return ret; 4476 } 4477 4478 static void bnxt_dev_recover(void *arg) 4479 { 4480 struct bnxt *bp = arg; 4481 int timeout = bp->fw_reset_max_msecs; 4482 int rc = 0; 4483 4484 /* Clear Error flag so that device re-init should happen */ 4485 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4486 4487 do { 4488 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); 4489 if (rc == 0) 4490 break; 4491 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4492 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4493 } while (rc && timeout); 4494 4495 if (rc) { 4496 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4497 goto err; 4498 } 4499 4500 rc = bnxt_init_resources(bp, true); 4501 if (rc) { 4502 PMD_DRV_LOG(ERR, 4503 "Failed to initialize resources after reset\n"); 4504 goto err; 4505 } 4506 /* clear reset flag as the device is initialized now */ 4507 bp->flags &= ~BNXT_FLAG_FW_RESET; 4508 4509 rc = bnxt_dev_start_op(bp->eth_dev); 4510 if (rc) { 4511 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4512 goto err_start; 4513 } 4514 4515 rc = bnxt_restore_filters(bp); 4516 if (rc) 4517 goto err_start; 4518 4519 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4520 return; 4521 err_start: 4522 bnxt_dev_stop_op(bp->eth_dev); 4523 err: 4524 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4525 bnxt_uninit_resources(bp, false); 4526 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4527 } 4528 4529 void bnxt_dev_reset_and_resume(void *arg) 4530 { 4531 struct bnxt *bp = arg; 4532 int rc; 4533 4534 bnxt_dev_cleanup(bp); 4535 4536 bnxt_wait_for_device_shutdown(bp); 4537 4538 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 4539 bnxt_dev_recover, (void *)bp); 4540 if (rc) 4541 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4542 } 4543 4544 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4545 { 4546 struct bnxt_error_recovery_info *info = bp->recovery_info; 4547 uint32_t reg = info->status_regs[index]; 4548 uint32_t type, offset, val = 0; 4549 4550 type = BNXT_FW_STATUS_REG_TYPE(reg); 4551 offset = BNXT_FW_STATUS_REG_OFF(reg); 4552 4553 switch (type) { 4554 case BNXT_FW_STATUS_REG_TYPE_CFG: 4555 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4556 break; 4557 case BNXT_FW_STATUS_REG_TYPE_GRC: 4558 offset = info->mapped_status_regs[index]; 4559 /* FALLTHROUGH */ 4560 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4561 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4562 offset)); 4563 break; 4564 } 4565 4566 return val; 4567 } 4568 4569 static int bnxt_fw_reset_all(struct bnxt *bp) 4570 { 4571 struct bnxt_error_recovery_info *info = bp->recovery_info; 4572 uint32_t i; 4573 int rc = 0; 4574 4575 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4576 /* Reset through master function driver */ 4577 for (i = 0; i < info->reg_array_cnt; i++) 4578 bnxt_write_fw_reset_reg(bp, i); 4579 /* Wait for time specified by FW after triggering reset */ 4580 rte_delay_ms(info->master_func_wait_period_after_reset); 4581 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4582 /* Reset with the help of Kong processor */ 4583 rc = bnxt_hwrm_fw_reset(bp); 4584 if (rc) 4585 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4586 } 4587 4588 return rc; 4589 } 4590 4591 static void bnxt_fw_reset_cb(void *arg) 4592 { 4593 struct bnxt *bp = arg; 4594 struct bnxt_error_recovery_info *info = bp->recovery_info; 4595 int rc = 0; 4596 4597 /* Only Master function can do FW reset */ 4598 if (bnxt_is_master_func(bp) && 4599 bnxt_is_recovery_enabled(bp)) { 4600 rc = bnxt_fw_reset_all(bp); 4601 if (rc) { 4602 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4603 return; 4604 } 4605 } 4606 4607 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4608 * EXCEPTION_FATAL_ASYNC event to all the functions 4609 * (including MASTER FUNC). After receiving this Async, all the active 4610 * drivers should treat this case as FW initiated recovery 4611 */ 4612 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4613 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4614 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4615 4616 /* To recover from error */ 4617 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4618 (void *)bp); 4619 } 4620 } 4621 4622 /* Driver should poll FW heartbeat, reset_counter with the frequency 4623 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4624 * When the driver detects heartbeat stop or change in reset_counter, 4625 * it has to trigger a reset to recover from the error condition. 4626 * A “master PF” is the function who will have the privilege to 4627 * initiate the chimp reset. The master PF will be elected by the 4628 * firmware and will be notified through async message. 4629 */ 4630 static void bnxt_check_fw_health(void *arg) 4631 { 4632 struct bnxt *bp = arg; 4633 struct bnxt_error_recovery_info *info = bp->recovery_info; 4634 uint32_t val = 0, wait_msec; 4635 4636 if (!info || !bnxt_is_recovery_enabled(bp) || 4637 is_bnxt_in_error(bp)) 4638 return; 4639 4640 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4641 if (val == info->last_heart_beat) 4642 goto reset; 4643 4644 info->last_heart_beat = val; 4645 4646 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4647 if (val != info->last_reset_counter) 4648 goto reset; 4649 4650 info->last_reset_counter = val; 4651 4652 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4653 bnxt_check_fw_health, (void *)bp); 4654 4655 return; 4656 reset: 4657 /* Stop DMA to/from device */ 4658 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4659 bp->flags |= BNXT_FLAG_FW_RESET; 4660 4661 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4662 4663 if (bnxt_is_master_func(bp)) 4664 wait_msec = info->master_func_wait_period; 4665 else 4666 wait_msec = info->normal_func_wait_period; 4667 4668 rte_eal_alarm_set(US_PER_MS * wait_msec, 4669 bnxt_fw_reset_cb, (void *)bp); 4670 } 4671 4672 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4673 { 4674 uint32_t polling_freq; 4675 4676 pthread_mutex_lock(&bp->health_check_lock); 4677 4678 if (!bnxt_is_recovery_enabled(bp)) 4679 goto done; 4680 4681 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4682 goto done; 4683 4684 polling_freq = bp->recovery_info->driver_polling_freq; 4685 4686 rte_eal_alarm_set(US_PER_MS * polling_freq, 4687 bnxt_check_fw_health, (void *)bp); 4688 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4689 4690 done: 4691 pthread_mutex_unlock(&bp->health_check_lock); 4692 } 4693 4694 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4695 { 4696 if (!bnxt_is_recovery_enabled(bp)) 4697 return; 4698 4699 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4700 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4701 } 4702 4703 static bool bnxt_vf_pciid(uint16_t device_id) 4704 { 4705 switch (device_id) { 4706 case BROADCOM_DEV_ID_57304_VF: 4707 case BROADCOM_DEV_ID_57406_VF: 4708 case BROADCOM_DEV_ID_5731X_VF: 4709 case BROADCOM_DEV_ID_5741X_VF: 4710 case BROADCOM_DEV_ID_57414_VF: 4711 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4712 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4713 case BROADCOM_DEV_ID_58802_VF: 4714 case BROADCOM_DEV_ID_57500_VF1: 4715 case BROADCOM_DEV_ID_57500_VF2: 4716 /* FALLTHROUGH */ 4717 return true; 4718 default: 4719 return false; 4720 } 4721 } 4722 4723 static bool bnxt_thor_device(uint16_t device_id) 4724 { 4725 switch (device_id) { 4726 case BROADCOM_DEV_ID_57508: 4727 case BROADCOM_DEV_ID_57504: 4728 case BROADCOM_DEV_ID_57502: 4729 case BROADCOM_DEV_ID_57508_MF1: 4730 case BROADCOM_DEV_ID_57504_MF1: 4731 case BROADCOM_DEV_ID_57502_MF1: 4732 case BROADCOM_DEV_ID_57508_MF2: 4733 case BROADCOM_DEV_ID_57504_MF2: 4734 case BROADCOM_DEV_ID_57502_MF2: 4735 case BROADCOM_DEV_ID_57500_VF1: 4736 case BROADCOM_DEV_ID_57500_VF2: 4737 /* FALLTHROUGH */ 4738 return true; 4739 default: 4740 return false; 4741 } 4742 } 4743 4744 bool bnxt_stratus_device(struct bnxt *bp) 4745 { 4746 uint16_t device_id = bp->pdev->id.device_id; 4747 4748 switch (device_id) { 4749 case BROADCOM_DEV_ID_STRATUS_NIC: 4750 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4751 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4752 /* FALLTHROUGH */ 4753 return true; 4754 default: 4755 return false; 4756 } 4757 } 4758 4759 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4760 { 4761 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4762 struct bnxt *bp = eth_dev->data->dev_private; 4763 4764 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4765 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4766 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4767 if (!bp->bar0 || !bp->doorbell_base) { 4768 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4769 return -ENODEV; 4770 } 4771 4772 bp->eth_dev = eth_dev; 4773 bp->pdev = pci_dev; 4774 4775 return 0; 4776 } 4777 4778 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4779 struct bnxt_ctx_pg_info *ctx_pg, 4780 uint32_t mem_size, 4781 const char *suffix, 4782 uint16_t idx) 4783 { 4784 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4785 const struct rte_memzone *mz = NULL; 4786 char mz_name[RTE_MEMZONE_NAMESIZE]; 4787 rte_iova_t mz_phys_addr; 4788 uint64_t valid_bits = 0; 4789 uint32_t sz; 4790 int i; 4791 4792 if (!mem_size) 4793 return 0; 4794 4795 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4796 BNXT_PAGE_SIZE; 4797 rmem->page_size = BNXT_PAGE_SIZE; 4798 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4799 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4800 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4801 4802 valid_bits = PTU_PTE_VALID; 4803 4804 if (rmem->nr_pages > 1) { 4805 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4806 "bnxt_ctx_pg_tbl%s_%x_%d", 4807 suffix, idx, bp->eth_dev->data->port_id); 4808 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4809 mz = rte_memzone_lookup(mz_name); 4810 if (!mz) { 4811 mz = rte_memzone_reserve_aligned(mz_name, 4812 rmem->nr_pages * 8, 4813 SOCKET_ID_ANY, 4814 RTE_MEMZONE_2MB | 4815 RTE_MEMZONE_SIZE_HINT_ONLY | 4816 RTE_MEMZONE_IOVA_CONTIG, 4817 BNXT_PAGE_SIZE); 4818 if (mz == NULL) 4819 return -ENOMEM; 4820 } 4821 4822 memset(mz->addr, 0, mz->len); 4823 mz_phys_addr = mz->iova; 4824 4825 rmem->pg_tbl = mz->addr; 4826 rmem->pg_tbl_map = mz_phys_addr; 4827 rmem->pg_tbl_mz = mz; 4828 } 4829 4830 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4831 suffix, idx, bp->eth_dev->data->port_id); 4832 mz = rte_memzone_lookup(mz_name); 4833 if (!mz) { 4834 mz = rte_memzone_reserve_aligned(mz_name, 4835 mem_size, 4836 SOCKET_ID_ANY, 4837 RTE_MEMZONE_1GB | 4838 RTE_MEMZONE_SIZE_HINT_ONLY | 4839 RTE_MEMZONE_IOVA_CONTIG, 4840 BNXT_PAGE_SIZE); 4841 if (mz == NULL) 4842 return -ENOMEM; 4843 } 4844 4845 memset(mz->addr, 0, mz->len); 4846 mz_phys_addr = mz->iova; 4847 4848 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4849 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4850 rmem->dma_arr[i] = mz_phys_addr + sz; 4851 4852 if (rmem->nr_pages > 1) { 4853 if (i == rmem->nr_pages - 2 && 4854 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4855 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4856 else if (i == rmem->nr_pages - 1 && 4857 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4858 valid_bits |= PTU_PTE_LAST; 4859 4860 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4861 valid_bits); 4862 } 4863 } 4864 4865 rmem->mz = mz; 4866 if (rmem->vmem_size) 4867 rmem->vmem = (void **)mz->addr; 4868 rmem->dma_arr[0] = mz_phys_addr; 4869 return 0; 4870 } 4871 4872 static void bnxt_free_ctx_mem(struct bnxt *bp) 4873 { 4874 int i; 4875 4876 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4877 return; 4878 4879 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4880 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4881 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4882 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4883 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4884 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4885 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4886 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4887 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4888 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4889 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4890 4891 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4892 if (bp->ctx->tqm_mem[i]) 4893 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4894 } 4895 4896 rte_free(bp->ctx); 4897 bp->ctx = NULL; 4898 } 4899 4900 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4901 4902 #define min_t(type, x, y) ({ \ 4903 type __min1 = (x); \ 4904 type __min2 = (y); \ 4905 __min1 < __min2 ? __min1 : __min2; }) 4906 4907 #define max_t(type, x, y) ({ \ 4908 type __max1 = (x); \ 4909 type __max2 = (y); \ 4910 __max1 > __max2 ? __max1 : __max2; }) 4911 4912 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4913 4914 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4915 { 4916 struct bnxt_ctx_pg_info *ctx_pg; 4917 struct bnxt_ctx_mem_info *ctx; 4918 uint32_t mem_size, ena, entries; 4919 uint32_t entries_sp, min; 4920 int i, rc; 4921 4922 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4923 if (rc) { 4924 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4925 return rc; 4926 } 4927 ctx = bp->ctx; 4928 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4929 return 0; 4930 4931 ctx_pg = &ctx->qp_mem; 4932 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4933 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4934 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4935 if (rc) 4936 return rc; 4937 4938 ctx_pg = &ctx->srq_mem; 4939 ctx_pg->entries = ctx->srq_max_l2_entries; 4940 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4941 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4942 if (rc) 4943 return rc; 4944 4945 ctx_pg = &ctx->cq_mem; 4946 ctx_pg->entries = ctx->cq_max_l2_entries; 4947 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4948 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4949 if (rc) 4950 return rc; 4951 4952 ctx_pg = &ctx->vnic_mem; 4953 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4954 ctx->vnic_max_ring_table_entries; 4955 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4956 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4957 if (rc) 4958 return rc; 4959 4960 ctx_pg = &ctx->stat_mem; 4961 ctx_pg->entries = ctx->stat_max_entries; 4962 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4963 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4964 if (rc) 4965 return rc; 4966 4967 min = ctx->tqm_min_entries_per_ring; 4968 4969 entries_sp = ctx->qp_max_l2_entries + 4970 ctx->vnic_max_vnic_entries + 4971 2 * ctx->qp_min_qp1_entries + min; 4972 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4973 4974 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4975 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4976 entries = clamp_t(uint32_t, entries, min, 4977 ctx->tqm_max_entries_per_ring); 4978 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4979 ctx_pg = ctx->tqm_mem[i]; 4980 ctx_pg->entries = i ? entries : entries_sp; 4981 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4982 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4983 if (rc) 4984 return rc; 4985 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4986 } 4987 4988 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4989 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4990 if (rc) 4991 PMD_DRV_LOG(ERR, 4992 "Failed to configure context mem: rc = %d\n", rc); 4993 else 4994 ctx->flags |= BNXT_CTX_FLAG_INITED; 4995 4996 return rc; 4997 } 4998 4999 static int bnxt_alloc_stats_mem(struct bnxt *bp) 5000 { 5001 struct rte_pci_device *pci_dev = bp->pdev; 5002 char mz_name[RTE_MEMZONE_NAMESIZE]; 5003 const struct rte_memzone *mz = NULL; 5004 uint32_t total_alloc_len; 5005 rte_iova_t mz_phys_addr; 5006 5007 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 5008 return 0; 5009 5010 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 5011 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 5012 pci_dev->addr.bus, pci_dev->addr.devid, 5013 pci_dev->addr.function, "rx_port_stats"); 5014 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 5015 mz = rte_memzone_lookup(mz_name); 5016 total_alloc_len = 5017 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 5018 sizeof(struct rx_port_stats_ext) + 512); 5019 if (!mz) { 5020 mz = rte_memzone_reserve(mz_name, total_alloc_len, 5021 SOCKET_ID_ANY, 5022 RTE_MEMZONE_2MB | 5023 RTE_MEMZONE_SIZE_HINT_ONLY | 5024 RTE_MEMZONE_IOVA_CONTIG); 5025 if (mz == NULL) 5026 return -ENOMEM; 5027 } 5028 memset(mz->addr, 0, mz->len); 5029 mz_phys_addr = mz->iova; 5030 5031 bp->rx_mem_zone = (const void *)mz; 5032 bp->hw_rx_port_stats = mz->addr; 5033 bp->hw_rx_port_stats_map = mz_phys_addr; 5034 5035 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 5036 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 5037 pci_dev->addr.bus, pci_dev->addr.devid, 5038 pci_dev->addr.function, "tx_port_stats"); 5039 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 5040 mz = rte_memzone_lookup(mz_name); 5041 total_alloc_len = 5042 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 5043 sizeof(struct tx_port_stats_ext) + 512); 5044 if (!mz) { 5045 mz = rte_memzone_reserve(mz_name, 5046 total_alloc_len, 5047 SOCKET_ID_ANY, 5048 RTE_MEMZONE_2MB | 5049 RTE_MEMZONE_SIZE_HINT_ONLY | 5050 RTE_MEMZONE_IOVA_CONTIG); 5051 if (mz == NULL) 5052 return -ENOMEM; 5053 } 5054 memset(mz->addr, 0, mz->len); 5055 mz_phys_addr = mz->iova; 5056 5057 bp->tx_mem_zone = (const void *)mz; 5058 bp->hw_tx_port_stats = mz->addr; 5059 bp->hw_tx_port_stats_map = mz_phys_addr; 5060 bp->flags |= BNXT_FLAG_PORT_STATS; 5061 5062 /* Display extended statistics if FW supports it */ 5063 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 5064 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 5065 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 5066 return 0; 5067 5068 bp->hw_rx_port_stats_ext = (void *) 5069 ((uint8_t *)bp->hw_rx_port_stats + 5070 sizeof(struct rx_port_stats)); 5071 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 5072 sizeof(struct rx_port_stats); 5073 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 5074 5075 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 5076 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 5077 bp->hw_tx_port_stats_ext = (void *) 5078 ((uint8_t *)bp->hw_tx_port_stats + 5079 sizeof(struct tx_port_stats)); 5080 bp->hw_tx_port_stats_ext_map = 5081 bp->hw_tx_port_stats_map + 5082 sizeof(struct tx_port_stats); 5083 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 5084 } 5085 5086 return 0; 5087 } 5088 5089 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 5090 { 5091 struct bnxt *bp = eth_dev->data->dev_private; 5092 int rc = 0; 5093 5094 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 5095 RTE_ETHER_ADDR_LEN * 5096 bp->max_l2_ctx, 5097 0); 5098 if (eth_dev->data->mac_addrs == NULL) { 5099 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 5100 return -ENOMEM; 5101 } 5102 5103 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 5104 if (BNXT_PF(bp)) 5105 return -EINVAL; 5106 5107 /* Generate a random MAC address, if none was assigned by PF */ 5108 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 5109 bnxt_eth_hw_addr_random(bp->mac_addr); 5110 PMD_DRV_LOG(INFO, 5111 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 5112 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 5113 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 5114 5115 rc = bnxt_hwrm_set_mac(bp); 5116 if (rc) 5117 return rc; 5118 } 5119 5120 /* Copy the permanent MAC from the FUNC_QCAPS response */ 5121 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5122 5123 return rc; 5124 } 5125 5126 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5127 { 5128 int rc = 0; 5129 5130 /* MAC is already configured in FW */ 5131 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5132 return 0; 5133 5134 /* Restore the old MAC configured */ 5135 rc = bnxt_hwrm_set_mac(bp); 5136 if (rc) 5137 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5138 5139 return rc; 5140 } 5141 5142 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5143 { 5144 if (!BNXT_PF(bp)) 5145 return; 5146 5147 #define ALLOW_FUNC(x) \ 5148 { \ 5149 uint32_t arg = (x); \ 5150 bp->pf->vf_req_fwd[((arg) >> 5)] &= \ 5151 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 5152 } 5153 5154 /* Forward all requests if firmware is new enough */ 5155 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 5156 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 5157 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 5158 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd)); 5159 } else { 5160 PMD_DRV_LOG(WARNING, 5161 "Firmware too old for VF mailbox functionality\n"); 5162 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5163 } 5164 5165 /* 5166 * The following are used for driver cleanup. If we disallow these, 5167 * VF drivers can't clean up cleanly. 5168 */ 5169 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 5170 ALLOW_FUNC(HWRM_VNIC_FREE); 5171 ALLOW_FUNC(HWRM_RING_FREE); 5172 ALLOW_FUNC(HWRM_RING_GRP_FREE); 5173 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 5174 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 5175 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 5176 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 5177 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 5178 } 5179 5180 uint16_t 5181 bnxt_get_svif(uint16_t port_id, bool func_svif, 5182 enum bnxt_ulp_intf_type type) 5183 { 5184 struct rte_eth_dev *eth_dev; 5185 struct bnxt *bp; 5186 5187 eth_dev = &rte_eth_devices[port_id]; 5188 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5189 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5190 if (!vfr) 5191 return 0; 5192 5193 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5194 return vfr->svif; 5195 5196 eth_dev = vfr->parent_dev; 5197 } 5198 5199 bp = eth_dev->data->dev_private; 5200 5201 return func_svif ? bp->func_svif : bp->port_svif; 5202 } 5203 5204 uint16_t 5205 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5206 { 5207 struct rte_eth_dev *eth_dev; 5208 struct bnxt_vnic_info *vnic; 5209 struct bnxt *bp; 5210 5211 eth_dev = &rte_eth_devices[port]; 5212 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5213 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5214 if (!vfr) 5215 return 0; 5216 5217 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5218 return vfr->dflt_vnic_id; 5219 5220 eth_dev = vfr->parent_dev; 5221 } 5222 5223 bp = eth_dev->data->dev_private; 5224 5225 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5226 5227 return vnic->fw_vnic_id; 5228 } 5229 5230 uint16_t 5231 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 5232 { 5233 struct rte_eth_dev *eth_dev; 5234 struct bnxt *bp; 5235 5236 eth_dev = &rte_eth_devices[port]; 5237 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5238 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5239 if (!vfr) 5240 return 0; 5241 5242 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5243 return vfr->fw_fid; 5244 5245 eth_dev = vfr->parent_dev; 5246 } 5247 5248 bp = eth_dev->data->dev_private; 5249 5250 return bp->fw_fid; 5251 } 5252 5253 enum bnxt_ulp_intf_type 5254 bnxt_get_interface_type(uint16_t port) 5255 { 5256 struct rte_eth_dev *eth_dev; 5257 struct bnxt *bp; 5258 5259 eth_dev = &rte_eth_devices[port]; 5260 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 5261 return BNXT_ULP_INTF_TYPE_VF_REP; 5262 5263 bp = eth_dev->data->dev_private; 5264 if (BNXT_PF(bp)) 5265 return BNXT_ULP_INTF_TYPE_PF; 5266 else if (BNXT_VF_IS_TRUSTED(bp)) 5267 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 5268 else if (BNXT_VF(bp)) 5269 return BNXT_ULP_INTF_TYPE_VF; 5270 5271 return BNXT_ULP_INTF_TYPE_INVALID; 5272 } 5273 5274 uint16_t 5275 bnxt_get_phy_port_id(uint16_t port_id) 5276 { 5277 struct bnxt_vf_representor *vfr; 5278 struct rte_eth_dev *eth_dev; 5279 struct bnxt *bp; 5280 5281 eth_dev = &rte_eth_devices[port_id]; 5282 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5283 vfr = eth_dev->data->dev_private; 5284 if (!vfr) 5285 return 0; 5286 5287 eth_dev = vfr->parent_dev; 5288 } 5289 5290 bp = eth_dev->data->dev_private; 5291 5292 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 5293 } 5294 5295 uint16_t 5296 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 5297 { 5298 struct rte_eth_dev *eth_dev; 5299 struct bnxt *bp; 5300 5301 eth_dev = &rte_eth_devices[port_id]; 5302 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5303 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5304 if (!vfr) 5305 return 0; 5306 5307 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5308 return vfr->fw_fid - 1; 5309 5310 eth_dev = vfr->parent_dev; 5311 } 5312 5313 bp = eth_dev->data->dev_private; 5314 5315 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 5316 } 5317 5318 uint16_t 5319 bnxt_get_vport(uint16_t port_id) 5320 { 5321 return (1 << bnxt_get_phy_port_id(port_id)); 5322 } 5323 5324 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5325 { 5326 struct bnxt_error_recovery_info *info = bp->recovery_info; 5327 5328 if (info) { 5329 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5330 memset(info, 0, sizeof(*info)); 5331 return; 5332 } 5333 5334 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5335 return; 5336 5337 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5338 sizeof(*info), 0); 5339 if (!info) 5340 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5341 5342 bp->recovery_info = info; 5343 } 5344 5345 static void bnxt_check_fw_status(struct bnxt *bp) 5346 { 5347 uint32_t fw_status; 5348 5349 if (!(bp->recovery_info && 5350 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5351 return; 5352 5353 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5354 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5355 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5356 fw_status); 5357 } 5358 5359 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5360 { 5361 struct bnxt_error_recovery_info *info = bp->recovery_info; 5362 uint32_t status_loc; 5363 uint32_t sig_ver; 5364 5365 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5366 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5367 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5368 BNXT_GRCP_WINDOW_2_BASE + 5369 offsetof(struct hcomm_status, 5370 sig_ver))); 5371 /* If the signature is absent, then FW does not support this feature */ 5372 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5373 HCOMM_STATUS_SIGNATURE_VAL) 5374 return 0; 5375 5376 if (!info) { 5377 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5378 sizeof(*info), 0); 5379 if (!info) 5380 return -ENOMEM; 5381 bp->recovery_info = info; 5382 } else { 5383 memset(info, 0, sizeof(*info)); 5384 } 5385 5386 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5387 BNXT_GRCP_WINDOW_2_BASE + 5388 offsetof(struct hcomm_status, 5389 fw_status_loc))); 5390 5391 /* Only pre-map the FW health status GRC register */ 5392 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5393 return 0; 5394 5395 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5396 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5397 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5398 5399 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5400 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5401 5402 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5403 5404 return 0; 5405 } 5406 5407 static int bnxt_init_fw(struct bnxt *bp) 5408 { 5409 uint16_t mtu; 5410 int rc = 0; 5411 5412 bp->fw_cap = 0; 5413 5414 rc = bnxt_map_hcomm_fw_status_reg(bp); 5415 if (rc) 5416 return rc; 5417 5418 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5419 if (rc) { 5420 bnxt_check_fw_status(bp); 5421 return rc; 5422 } 5423 5424 rc = bnxt_hwrm_func_reset(bp); 5425 if (rc) 5426 return -EIO; 5427 5428 rc = bnxt_hwrm_vnic_qcaps(bp); 5429 if (rc) 5430 return rc; 5431 5432 rc = bnxt_hwrm_queue_qportcfg(bp); 5433 if (rc) 5434 return rc; 5435 5436 /* Get the MAX capabilities for this function. 5437 * This function also allocates context memory for TQM rings and 5438 * informs the firmware about this allocated backing store memory. 5439 */ 5440 rc = bnxt_hwrm_func_qcaps(bp); 5441 if (rc) 5442 return rc; 5443 5444 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5445 if (rc) 5446 return rc; 5447 5448 bnxt_hwrm_port_mac_qcfg(bp); 5449 5450 bnxt_hwrm_parent_pf_qcfg(bp); 5451 5452 bnxt_hwrm_port_phy_qcaps(bp); 5453 5454 bnxt_alloc_error_recovery_info(bp); 5455 /* Get the adapter error recovery support info */ 5456 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5457 if (rc) 5458 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5459 5460 bnxt_hwrm_port_led_qcaps(bp); 5461 5462 return 0; 5463 } 5464 5465 static int 5466 bnxt_init_locks(struct bnxt *bp) 5467 { 5468 int err; 5469 5470 err = pthread_mutex_init(&bp->flow_lock, NULL); 5471 if (err) { 5472 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5473 return err; 5474 } 5475 5476 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5477 if (err) 5478 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5479 5480 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5481 if (err) 5482 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5483 return err; 5484 } 5485 5486 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5487 { 5488 int rc = 0; 5489 5490 rc = bnxt_init_fw(bp); 5491 if (rc) 5492 return rc; 5493 5494 if (!reconfig_dev) { 5495 rc = bnxt_setup_mac_addr(bp->eth_dev); 5496 if (rc) 5497 return rc; 5498 } else { 5499 rc = bnxt_restore_dflt_mac(bp); 5500 if (rc) 5501 return rc; 5502 } 5503 5504 bnxt_config_vf_req_fwd(bp); 5505 5506 rc = bnxt_hwrm_func_driver_register(bp); 5507 if (rc) { 5508 PMD_DRV_LOG(ERR, "Failed to register driver"); 5509 return -EBUSY; 5510 } 5511 5512 if (BNXT_PF(bp)) { 5513 if (bp->pdev->max_vfs) { 5514 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5515 if (rc) { 5516 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5517 return rc; 5518 } 5519 } else { 5520 rc = bnxt_hwrm_allocate_pf_only(bp); 5521 if (rc) { 5522 PMD_DRV_LOG(ERR, 5523 "Failed to allocate PF resources"); 5524 return rc; 5525 } 5526 } 5527 } 5528 5529 rc = bnxt_alloc_mem(bp, reconfig_dev); 5530 if (rc) 5531 return rc; 5532 5533 rc = bnxt_setup_int(bp); 5534 if (rc) 5535 return rc; 5536 5537 rc = bnxt_request_int(bp); 5538 if (rc) 5539 return rc; 5540 5541 rc = bnxt_init_ctx_mem(bp); 5542 if (rc) { 5543 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5544 return rc; 5545 } 5546 5547 rc = bnxt_init_locks(bp); 5548 if (rc) 5549 return rc; 5550 5551 return 0; 5552 } 5553 5554 static int 5555 bnxt_parse_devarg_truflow(__rte_unused const char *key, 5556 const char *value, void *opaque_arg) 5557 { 5558 struct bnxt *bp = opaque_arg; 5559 unsigned long truflow; 5560 char *end = NULL; 5561 5562 if (!value || !opaque_arg) { 5563 PMD_DRV_LOG(ERR, 5564 "Invalid parameter passed to truflow devargs.\n"); 5565 return -EINVAL; 5566 } 5567 5568 truflow = strtoul(value, &end, 10); 5569 if (end == NULL || *end != '\0' || 5570 (truflow == ULONG_MAX && errno == ERANGE)) { 5571 PMD_DRV_LOG(ERR, 5572 "Invalid parameter passed to truflow devargs.\n"); 5573 return -EINVAL; 5574 } 5575 5576 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 5577 PMD_DRV_LOG(ERR, 5578 "Invalid value passed to truflow devargs.\n"); 5579 return -EINVAL; 5580 } 5581 5582 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 5583 if (BNXT_TRUFLOW_EN(bp)) 5584 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 5585 5586 return 0; 5587 } 5588 5589 static int 5590 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5591 const char *value, void *opaque_arg) 5592 { 5593 struct bnxt *bp = opaque_arg; 5594 unsigned long flow_xstat; 5595 char *end = NULL; 5596 5597 if (!value || !opaque_arg) { 5598 PMD_DRV_LOG(ERR, 5599 "Invalid parameter passed to flow_xstat devarg.\n"); 5600 return -EINVAL; 5601 } 5602 5603 flow_xstat = strtoul(value, &end, 10); 5604 if (end == NULL || *end != '\0' || 5605 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5606 PMD_DRV_LOG(ERR, 5607 "Invalid parameter passed to flow_xstat devarg.\n"); 5608 return -EINVAL; 5609 } 5610 5611 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5612 PMD_DRV_LOG(ERR, 5613 "Invalid value passed to flow_xstat devarg.\n"); 5614 return -EINVAL; 5615 } 5616 5617 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5618 if (BNXT_FLOW_XSTATS_EN(bp)) 5619 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5620 5621 return 0; 5622 } 5623 5624 static int 5625 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5626 const char *value, void *opaque_arg) 5627 { 5628 struct bnxt *bp = opaque_arg; 5629 unsigned long max_num_kflows; 5630 char *end = NULL; 5631 5632 if (!value || !opaque_arg) { 5633 PMD_DRV_LOG(ERR, 5634 "Invalid parameter passed to max_num_kflows devarg.\n"); 5635 return -EINVAL; 5636 } 5637 5638 max_num_kflows = strtoul(value, &end, 10); 5639 if (end == NULL || *end != '\0' || 5640 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5641 PMD_DRV_LOG(ERR, 5642 "Invalid parameter passed to max_num_kflows devarg.\n"); 5643 return -EINVAL; 5644 } 5645 5646 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5647 PMD_DRV_LOG(ERR, 5648 "Invalid value passed to max_num_kflows devarg.\n"); 5649 return -EINVAL; 5650 } 5651 5652 bp->max_num_kflows = max_num_kflows; 5653 if (bp->max_num_kflows) 5654 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5655 max_num_kflows); 5656 5657 return 0; 5658 } 5659 5660 static void 5661 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5662 { 5663 struct rte_kvargs *kvlist; 5664 5665 if (devargs == NULL) 5666 return; 5667 5668 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5669 if (kvlist == NULL) 5670 return; 5671 5672 /* 5673 * Handler for "truflow" devarg. 5674 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1" 5675 */ 5676 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5677 bnxt_parse_devarg_truflow, bp); 5678 5679 /* 5680 * Handler for "flow_xstat" devarg. 5681 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1" 5682 */ 5683 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5684 bnxt_parse_devarg_flow_xstat, bp); 5685 5686 /* 5687 * Handler for "max_num_kflows" devarg. 5688 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32" 5689 */ 5690 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5691 bnxt_parse_devarg_max_num_kflows, bp); 5692 5693 rte_kvargs_free(kvlist); 5694 } 5695 5696 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5697 { 5698 int rc = 0; 5699 5700 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5701 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5702 if (rc) 5703 PMD_DRV_LOG(ERR, 5704 "Failed to alloc switch domain: %d\n", rc); 5705 else 5706 PMD_DRV_LOG(INFO, 5707 "Switch domain allocated %d\n", 5708 bp->switch_domain_id); 5709 } 5710 5711 return rc; 5712 } 5713 5714 static int 5715 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5716 { 5717 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5718 static int version_printed; 5719 struct bnxt *bp; 5720 int rc; 5721 5722 if (version_printed++ == 0) 5723 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5724 5725 eth_dev->dev_ops = &bnxt_dev_ops; 5726 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 5727 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 5728 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 5729 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5730 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5731 5732 /* 5733 * For secondary processes, we don't initialise any further 5734 * as primary has already done this work. 5735 */ 5736 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5737 return 0; 5738 5739 rte_eth_copy_pci_info(eth_dev, pci_dev); 5740 5741 bp = eth_dev->data->dev_private; 5742 5743 /* Parse dev arguments passed on when starting the DPDK application. */ 5744 bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5745 5746 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5747 5748 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5749 bp->flags |= BNXT_FLAG_VF; 5750 5751 if (bnxt_thor_device(pci_dev->id.device_id)) 5752 bp->flags |= BNXT_FLAG_THOR_CHIP; 5753 5754 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5755 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5756 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5757 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5758 bp->flags |= BNXT_FLAG_STINGRAY; 5759 5760 rc = bnxt_init_board(eth_dev); 5761 if (rc) { 5762 PMD_DRV_LOG(ERR, 5763 "Failed to initialize board rc: %x\n", rc); 5764 return rc; 5765 } 5766 5767 rc = bnxt_alloc_pf_info(bp); 5768 if (rc) 5769 goto error_free; 5770 5771 rc = bnxt_alloc_link_info(bp); 5772 if (rc) 5773 goto error_free; 5774 5775 rc = bnxt_alloc_parent_info(bp); 5776 if (rc) 5777 goto error_free; 5778 5779 rc = bnxt_alloc_hwrm_resources(bp); 5780 if (rc) { 5781 PMD_DRV_LOG(ERR, 5782 "Failed to allocate hwrm resource rc: %x\n", rc); 5783 goto error_free; 5784 } 5785 rc = bnxt_alloc_leds_info(bp); 5786 if (rc) 5787 goto error_free; 5788 5789 rc = bnxt_alloc_cos_queues(bp); 5790 if (rc) 5791 goto error_free; 5792 5793 rc = bnxt_init_resources(bp, false); 5794 if (rc) 5795 goto error_free; 5796 5797 rc = bnxt_alloc_stats_mem(bp); 5798 if (rc) 5799 goto error_free; 5800 5801 bnxt_alloc_switch_domain(bp); 5802 5803 /* Pass the information to the rte_eth_dev_close() that it should also 5804 * release the private port resources. 5805 */ 5806 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 5807 5808 PMD_DRV_LOG(INFO, 5809 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5810 pci_dev->mem_resource[0].phys_addr, 5811 pci_dev->mem_resource[0].addr); 5812 5813 return 0; 5814 5815 error_free: 5816 bnxt_dev_uninit(eth_dev); 5817 return rc; 5818 } 5819 5820 5821 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5822 { 5823 if (!ctx) 5824 return; 5825 5826 if (ctx->va) 5827 rte_free(ctx->va); 5828 5829 ctx->va = NULL; 5830 ctx->dma = RTE_BAD_IOVA; 5831 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5832 } 5833 5834 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5835 { 5836 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5837 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5838 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5839 bp->flow_stat->max_fc, 5840 false); 5841 5842 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5843 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5844 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5845 bp->flow_stat->max_fc, 5846 false); 5847 5848 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5849 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5850 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5851 5852 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5853 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5854 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5855 5856 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5857 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5858 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5859 5860 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5861 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5862 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5863 } 5864 5865 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5866 { 5867 bnxt_unregister_fc_ctx_mem(bp); 5868 5869 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5870 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5871 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5872 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5873 } 5874 5875 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5876 { 5877 if (BNXT_FLOW_XSTATS_EN(bp)) 5878 bnxt_uninit_fc_ctx_mem(bp); 5879 } 5880 5881 static void 5882 bnxt_free_error_recovery_info(struct bnxt *bp) 5883 { 5884 rte_free(bp->recovery_info); 5885 bp->recovery_info = NULL; 5886 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5887 } 5888 5889 static void 5890 bnxt_uninit_locks(struct bnxt *bp) 5891 { 5892 pthread_mutex_destroy(&bp->flow_lock); 5893 pthread_mutex_destroy(&bp->def_cp_lock); 5894 pthread_mutex_destroy(&bp->health_check_lock); 5895 if (bp->rep_info) { 5896 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 5897 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 5898 } 5899 } 5900 5901 static int 5902 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5903 { 5904 int rc; 5905 5906 bnxt_free_int(bp); 5907 bnxt_free_mem(bp, reconfig_dev); 5908 bnxt_hwrm_func_buf_unrgtr(bp); 5909 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5910 bp->flags &= ~BNXT_FLAG_REGISTERED; 5911 bnxt_free_ctx_mem(bp); 5912 if (!reconfig_dev) { 5913 bnxt_free_hwrm_resources(bp); 5914 bnxt_free_error_recovery_info(bp); 5915 } 5916 5917 bnxt_uninit_ctx_mem(bp); 5918 5919 bnxt_uninit_locks(bp); 5920 bnxt_free_flow_stats_info(bp); 5921 bnxt_free_rep_info(bp); 5922 rte_free(bp->ptp_cfg); 5923 bp->ptp_cfg = NULL; 5924 return rc; 5925 } 5926 5927 static int 5928 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5929 { 5930 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5931 return -EPERM; 5932 5933 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5934 5935 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5936 bnxt_dev_close_op(eth_dev); 5937 5938 return 0; 5939 } 5940 5941 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5942 { 5943 struct bnxt *bp = eth_dev->data->dev_private; 5944 struct rte_eth_dev *vf_rep_eth_dev; 5945 int ret = 0, i; 5946 5947 if (!bp) 5948 return -EINVAL; 5949 5950 for (i = 0; i < bp->num_reps; i++) { 5951 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5952 if (!vf_rep_eth_dev) 5953 continue; 5954 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 5955 vf_rep_eth_dev->data->port_id); 5956 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit); 5957 } 5958 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 5959 eth_dev->data->port_id); 5960 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5961 5962 return ret; 5963 } 5964 5965 static void bnxt_free_rep_info(struct bnxt *bp) 5966 { 5967 rte_free(bp->rep_info); 5968 bp->rep_info = NULL; 5969 rte_free(bp->cfa_code_map); 5970 bp->cfa_code_map = NULL; 5971 } 5972 5973 static int bnxt_init_rep_info(struct bnxt *bp) 5974 { 5975 int i = 0, rc; 5976 5977 if (bp->rep_info) 5978 return 0; 5979 5980 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5981 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5982 0); 5983 if (!bp->rep_info) { 5984 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5985 return -ENOMEM; 5986 } 5987 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5988 sizeof(*bp->cfa_code_map) * 5989 BNXT_MAX_CFA_CODE, 0); 5990 if (!bp->cfa_code_map) { 5991 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5992 bnxt_free_rep_info(bp); 5993 return -ENOMEM; 5994 } 5995 5996 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5997 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5998 5999 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 6000 if (rc) { 6001 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 6002 bnxt_free_rep_info(bp); 6003 return rc; 6004 } 6005 6006 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 6007 if (rc) { 6008 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 6009 bnxt_free_rep_info(bp); 6010 return rc; 6011 } 6012 6013 return rc; 6014 } 6015 6016 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 6017 struct rte_eth_devargs eth_da, 6018 struct rte_eth_dev *backing_eth_dev) 6019 { 6020 struct rte_eth_dev *vf_rep_eth_dev; 6021 char name[RTE_ETH_NAME_MAX_LEN]; 6022 struct bnxt *backing_bp; 6023 uint16_t num_rep; 6024 int i, ret = 0; 6025 6026 num_rep = eth_da.nb_representor_ports; 6027 if (num_rep > BNXT_MAX_VF_REPS) { 6028 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 6029 num_rep, BNXT_MAX_VF_REPS); 6030 return -EINVAL; 6031 } 6032 6033 if (num_rep >= RTE_MAX_ETHPORTS) { 6034 PMD_DRV_LOG(ERR, 6035 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 6036 num_rep, RTE_MAX_ETHPORTS); 6037 return -EINVAL; 6038 } 6039 6040 backing_bp = backing_eth_dev->data->dev_private; 6041 6042 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 6043 PMD_DRV_LOG(ERR, 6044 "Not a PF or trusted VF. No Representor support\n"); 6045 /* Returning an error is not an option. 6046 * Applications are not handling this correctly 6047 */ 6048 return 0; 6049 } 6050 6051 if (bnxt_init_rep_info(backing_bp)) 6052 return 0; 6053 6054 for (i = 0; i < num_rep; i++) { 6055 struct bnxt_vf_representor representor = { 6056 .vf_id = eth_da.representor_ports[i], 6057 .switch_domain_id = backing_bp->switch_domain_id, 6058 .parent_dev = backing_eth_dev 6059 }; 6060 6061 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 6062 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 6063 representor.vf_id, BNXT_MAX_VF_REPS); 6064 continue; 6065 } 6066 6067 /* representor port net_bdf_port */ 6068 snprintf(name, sizeof(name), "net_%s_representor_%d", 6069 pci_dev->device.name, eth_da.representor_ports[i]); 6070 6071 ret = rte_eth_dev_create(&pci_dev->device, name, 6072 sizeof(struct bnxt_vf_representor), 6073 NULL, NULL, 6074 bnxt_vf_representor_init, 6075 &representor); 6076 if (ret) { 6077 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6078 "representor %s.", name); 6079 goto err; 6080 } 6081 6082 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6083 if (!vf_rep_eth_dev) { 6084 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6085 " for VF-Rep: %s.", name); 6086 ret = -ENODEV; 6087 goto err; 6088 } 6089 6090 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6091 backing_eth_dev->data->port_id); 6092 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6093 vf_rep_eth_dev; 6094 backing_bp->num_reps++; 6095 } 6096 6097 return 0; 6098 6099 err: 6100 /* If num_rep > 1, then rollback already created 6101 * ports, since we'll be failing the probe anyway 6102 */ 6103 if (num_rep > 1) 6104 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6105 6106 return ret; 6107 } 6108 6109 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6110 struct rte_pci_device *pci_dev) 6111 { 6112 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6113 struct rte_eth_dev *backing_eth_dev; 6114 uint16_t num_rep; 6115 int ret = 0; 6116 6117 if (pci_dev->device.devargs) { 6118 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6119 ð_da); 6120 if (ret) 6121 return ret; 6122 } 6123 6124 num_rep = eth_da.nb_representor_ports; 6125 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6126 num_rep); 6127 6128 /* We could come here after first level of probe is already invoked 6129 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6130 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6131 */ 6132 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6133 if (backing_eth_dev == NULL) { 6134 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6135 sizeof(struct bnxt), 6136 eth_dev_pci_specific_init, pci_dev, 6137 bnxt_dev_init, NULL); 6138 6139 if (ret || !num_rep) 6140 return ret; 6141 6142 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6143 } 6144 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6145 backing_eth_dev->data->port_id); 6146 /* probe representor ports now */ 6147 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev); 6148 6149 return ret; 6150 } 6151 6152 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6153 { 6154 struct rte_eth_dev *eth_dev; 6155 6156 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6157 if (!eth_dev) 6158 return 0; /* Invoked typically only by OVS-DPDK, by the 6159 * time it comes here the eth_dev is already 6160 * deleted by rte_eth_dev_close(), so returning 6161 * +ve value will at least help in proper cleanup 6162 */ 6163 6164 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6165 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6166 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6167 return rte_eth_dev_destroy(eth_dev, 6168 bnxt_vf_representor_uninit); 6169 else 6170 return rte_eth_dev_destroy(eth_dev, 6171 bnxt_dev_uninit); 6172 } else { 6173 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6174 } 6175 } 6176 6177 static struct rte_pci_driver bnxt_rte_pmd = { 6178 .id_table = bnxt_pci_id_map, 6179 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6180 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6181 * and OVS-DPDK 6182 */ 6183 .probe = bnxt_pci_probe, 6184 .remove = bnxt_pci_remove, 6185 }; 6186 6187 static bool 6188 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6189 { 6190 if (strcmp(dev->device->driver->name, drv->driver.name)) 6191 return false; 6192 6193 return true; 6194 } 6195 6196 bool is_bnxt_supported(struct rte_eth_dev *dev) 6197 { 6198 return is_device_supported(dev, &bnxt_rte_pmd); 6199 } 6200 6201 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 6202 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6203 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6204 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6205