1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 101 static const char *const bnxt_dev_args[] = { 102 BNXT_DEVARG_REPRESENTOR, 103 BNXT_DEVARG_TRUFLOW, 104 BNXT_DEVARG_FLOW_XSTAT, 105 BNXT_DEVARG_MAX_NUM_KFLOWS, 106 BNXT_DEVARG_REP_BASED_PF, 107 BNXT_DEVARG_REP_IS_PF, 108 BNXT_DEVARG_REP_Q_R2F, 109 BNXT_DEVARG_REP_Q_F2R, 110 BNXT_DEVARG_REP_FC_R2F, 111 BNXT_DEVARG_REP_FC_F2R, 112 NULL 113 }; 114 115 /* 116 * truflow == false to disable the feature 117 * truflow == true to enable the feature 118 */ 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 120 121 /* 122 * flow_xstat == false to disable the feature 123 * flow_xstat == true to enable the feature 124 */ 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 126 127 /* 128 * rep_is_pf == false to indicate VF representor 129 * rep_is_pf == true to indicate PF representor 130 */ 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 132 133 /* 134 * rep_based_pf == Physical index of the PF 135 */ 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 137 /* 138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 139 */ 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 141 142 /* 143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 144 */ 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 146 147 /* 148 * rep_fc_r2f == Flow control for the representor to endpoint direction 149 */ 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 151 152 /* 153 * rep_fc_f2r == Flow control for the endpoint to representor direction 154 */ 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 156 157 int bnxt_cfa_code_dynfield_offset = -1; 158 159 /* 160 * max_num_kflows must be >= 32 161 * and must be a power-of-2 supported value 162 * return: 1 -> invalid 163 * 0 -> valid 164 */ 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 166 { 167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 168 return 1; 169 return 0; 170 } 171 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 177 static int bnxt_restore_vlan_filters(struct bnxt *bp); 178 static void bnxt_dev_recover(void *arg); 179 static void bnxt_free_error_recovery_info(struct bnxt *bp); 180 static void bnxt_free_rep_info(struct bnxt *bp); 181 182 int is_bnxt_in_error(struct bnxt *bp) 183 { 184 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 185 return -EIO; 186 if (bp->flags & BNXT_FLAG_FW_RESET) 187 return -EBUSY; 188 189 return 0; 190 } 191 192 /***********************/ 193 194 /* 195 * High level utility functions 196 */ 197 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 199 { 200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 201 BNXT_RSS_TBL_SIZE_P5); 202 203 if (!BNXT_CHIP_P5(bp)) 204 return 1; 205 206 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 207 BNXT_RSS_ENTRIES_PER_CTX_P5) / 208 BNXT_RSS_ENTRIES_PER_CTX_P5; 209 } 210 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 212 { 213 if (!BNXT_CHIP_P5(bp)) 214 return HW_HASH_INDEX_SIZE; 215 216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 217 } 218 219 static void bnxt_free_parent_info(struct bnxt *bp) 220 { 221 rte_free(bp->parent); 222 } 223 224 static void bnxt_free_pf_info(struct bnxt *bp) 225 { 226 rte_free(bp->pf); 227 } 228 229 static void bnxt_free_link_info(struct bnxt *bp) 230 { 231 rte_free(bp->link_info); 232 } 233 234 static void bnxt_free_leds_info(struct bnxt *bp) 235 { 236 if (BNXT_VF(bp)) 237 return; 238 239 rte_free(bp->leds); 240 bp->leds = NULL; 241 } 242 243 static void bnxt_free_flow_stats_info(struct bnxt *bp) 244 { 245 rte_free(bp->flow_stat); 246 bp->flow_stat = NULL; 247 } 248 249 static void bnxt_free_cos_queues(struct bnxt *bp) 250 { 251 rte_free(bp->rx_cos_queue); 252 rte_free(bp->tx_cos_queue); 253 } 254 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 256 { 257 bnxt_free_filter_mem(bp); 258 bnxt_free_vnic_attributes(bp); 259 bnxt_free_vnic_mem(bp); 260 261 /* tx/rx rings are configured as part of *_queue_setup callbacks. 262 * If the number of rings change across fw update, 263 * we don't have much choice except to warn the user. 264 */ 265 if (!reconfig) { 266 bnxt_free_stats(bp); 267 bnxt_free_tx_rings(bp); 268 bnxt_free_rx_rings(bp); 269 } 270 bnxt_free_async_cp_ring(bp); 271 bnxt_free_rxtx_nq_ring(bp); 272 273 rte_free(bp->grp_info); 274 bp->grp_info = NULL; 275 } 276 277 static int bnxt_alloc_parent_info(struct bnxt *bp) 278 { 279 bp->parent = rte_zmalloc("bnxt_parent_info", 280 sizeof(struct bnxt_parent_info), 0); 281 if (bp->parent == NULL) 282 return -ENOMEM; 283 284 return 0; 285 } 286 287 static int bnxt_alloc_pf_info(struct bnxt *bp) 288 { 289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 290 if (bp->pf == NULL) 291 return -ENOMEM; 292 293 return 0; 294 } 295 296 static int bnxt_alloc_link_info(struct bnxt *bp) 297 { 298 bp->link_info = 299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 300 if (bp->link_info == NULL) 301 return -ENOMEM; 302 303 return 0; 304 } 305 306 static int bnxt_alloc_leds_info(struct bnxt *bp) 307 { 308 if (BNXT_VF(bp)) 309 return 0; 310 311 bp->leds = rte_zmalloc("bnxt_leds", 312 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 313 0); 314 if (bp->leds == NULL) 315 return -ENOMEM; 316 317 return 0; 318 } 319 320 static int bnxt_alloc_cos_queues(struct bnxt *bp) 321 { 322 bp->rx_cos_queue = 323 rte_zmalloc("bnxt_rx_cosq", 324 BNXT_COS_QUEUE_COUNT * 325 sizeof(struct bnxt_cos_queue_info), 326 0); 327 if (bp->rx_cos_queue == NULL) 328 return -ENOMEM; 329 330 bp->tx_cos_queue = 331 rte_zmalloc("bnxt_tx_cosq", 332 BNXT_COS_QUEUE_COUNT * 333 sizeof(struct bnxt_cos_queue_info), 334 0); 335 if (bp->tx_cos_queue == NULL) 336 return -ENOMEM; 337 338 return 0; 339 } 340 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 342 { 343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 344 sizeof(struct bnxt_flow_stat_info), 0); 345 if (bp->flow_stat == NULL) 346 return -ENOMEM; 347 348 return 0; 349 } 350 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 352 { 353 int rc; 354 355 rc = bnxt_alloc_ring_grps(bp); 356 if (rc) 357 goto alloc_mem_err; 358 359 rc = bnxt_alloc_async_ring_struct(bp); 360 if (rc) 361 goto alloc_mem_err; 362 363 rc = bnxt_alloc_vnic_mem(bp); 364 if (rc) 365 goto alloc_mem_err; 366 367 rc = bnxt_alloc_vnic_attributes(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_filter_mem(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_async_cp_ring(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_rxtx_nq_ring(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 if (BNXT_FLOW_XSTATS_EN(bp)) { 384 rc = bnxt_alloc_flow_stats_info(bp); 385 if (rc) 386 goto alloc_mem_err; 387 } 388 389 return 0; 390 391 alloc_mem_err: 392 bnxt_free_mem(bp, reconfig); 393 return rc; 394 } 395 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 397 { 398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 400 uint64_t rx_offloads = dev_conf->rxmode.offloads; 401 struct bnxt_rx_queue *rxq; 402 unsigned int j; 403 int rc; 404 405 rc = bnxt_vnic_grp_alloc(bp, vnic); 406 if (rc) 407 goto err_out; 408 409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 410 vnic_id, vnic, vnic->fw_grp_ids); 411 412 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 413 if (rc) 414 goto err_out; 415 416 /* Alloc RSS context only if RSS mode is enabled */ 417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 418 int j, nr_ctxs = bnxt_rss_ctxts(bp); 419 420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 423 PMD_DRV_LOG(ERR, 424 "Only queues 0-%d will be in RSS table\n", 425 BNXT_RSS_TBL_SIZE_P5 - 1); 426 } 427 428 rc = 0; 429 for (j = 0; j < nr_ctxs; j++) { 430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 431 if (rc) 432 break; 433 } 434 if (rc) { 435 PMD_DRV_LOG(ERR, 436 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 437 vnic_id, j, rc); 438 goto err_out; 439 } 440 vnic->num_lb_ctxts = nr_ctxs; 441 } 442 443 /* 444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 445 * setting is not available at this time, it will not be 446 * configured correctly in the CFA. 447 */ 448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 449 vnic->vlan_strip = true; 450 else 451 vnic->vlan_strip = false; 452 453 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 454 if (rc) 455 goto err_out; 456 457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 458 if (rc) 459 goto err_out; 460 461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 462 rxq = bp->eth_dev->data->rx_queues[j]; 463 464 PMD_DRV_LOG(DEBUG, 465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 466 j, rxq->vnic, rxq->vnic->fw_grp_ids); 467 468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 470 else 471 vnic->rx_queue_cnt++; 472 } 473 474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 475 476 rc = bnxt_vnic_rss_configure(bp, vnic); 477 if (rc) 478 goto err_out; 479 480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 481 482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 484 else 485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 486 487 return 0; 488 err_out: 489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 490 vnic_id, rc); 491 return rc; 492 } 493 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 495 { 496 int rc = 0; 497 498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 499 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 500 if (rc) 501 return rc; 502 503 PMD_DRV_LOG(DEBUG, 504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 505 " rx_fc_in_tbl.ctx_id = %d\n", 506 bp->flow_stat->rx_fc_in_tbl.va, 507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 508 bp->flow_stat->rx_fc_in_tbl.ctx_id); 509 510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 511 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 512 if (rc) 513 return rc; 514 515 PMD_DRV_LOG(DEBUG, 516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 517 " rx_fc_out_tbl.ctx_id = %d\n", 518 bp->flow_stat->rx_fc_out_tbl.va, 519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 520 bp->flow_stat->rx_fc_out_tbl.ctx_id); 521 522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 523 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 524 if (rc) 525 return rc; 526 527 PMD_DRV_LOG(DEBUG, 528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 529 " tx_fc_in_tbl.ctx_id = %d\n", 530 bp->flow_stat->tx_fc_in_tbl.va, 531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 532 bp->flow_stat->tx_fc_in_tbl.ctx_id); 533 534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 535 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 536 if (rc) 537 return rc; 538 539 PMD_DRV_LOG(DEBUG, 540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 541 " tx_fc_out_tbl.ctx_id = %d\n", 542 bp->flow_stat->tx_fc_out_tbl.va, 543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 544 bp->flow_stat->tx_fc_out_tbl.ctx_id); 545 546 memset(bp->flow_stat->rx_fc_out_tbl.va, 547 0, 548 bp->flow_stat->rx_fc_out_tbl.size); 549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 551 bp->flow_stat->rx_fc_out_tbl.ctx_id, 552 bp->flow_stat->max_fc, 553 true); 554 if (rc) 555 return rc; 556 557 memset(bp->flow_stat->tx_fc_out_tbl.va, 558 0, 559 bp->flow_stat->tx_fc_out_tbl.size); 560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 562 bp->flow_stat->tx_fc_out_tbl.ctx_id, 563 bp->flow_stat->max_fc, 564 true); 565 566 return rc; 567 } 568 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 570 struct bnxt_ctx_mem_buf_info *ctx) 571 { 572 if (!ctx) 573 return -EINVAL; 574 575 ctx->va = rte_zmalloc(type, size, 0); 576 if (ctx->va == NULL) 577 return -ENOMEM; 578 rte_mem_lock_page(ctx->va); 579 ctx->size = size; 580 ctx->dma = rte_mem_virt2iova(ctx->va); 581 if (ctx->dma == RTE_BAD_IOVA) 582 return -ENOMEM; 583 584 return 0; 585 } 586 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 588 { 589 struct rte_pci_device *pdev = bp->pdev; 590 char type[RTE_MEMZONE_NAMESIZE]; 591 uint16_t max_fc; 592 int rc = 0; 593 594 max_fc = bp->flow_stat->max_fc; 595 596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 598 /* 4 bytes for each counter-id */ 599 rc = bnxt_alloc_ctx_mem_buf(type, 600 max_fc * 4, 601 &bp->flow_stat->rx_fc_in_tbl); 602 if (rc) 603 return rc; 604 605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 608 rc = bnxt_alloc_ctx_mem_buf(type, 609 max_fc * 16, 610 &bp->flow_stat->rx_fc_out_tbl); 611 if (rc) 612 return rc; 613 614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 616 /* 4 bytes for each counter-id */ 617 rc = bnxt_alloc_ctx_mem_buf(type, 618 max_fc * 4, 619 &bp->flow_stat->tx_fc_in_tbl); 620 if (rc) 621 return rc; 622 623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 626 rc = bnxt_alloc_ctx_mem_buf(type, 627 max_fc * 16, 628 &bp->flow_stat->tx_fc_out_tbl); 629 if (rc) 630 return rc; 631 632 rc = bnxt_register_fc_ctx_mem(bp); 633 634 return rc; 635 } 636 637 static int bnxt_init_ctx_mem(struct bnxt *bp) 638 { 639 int rc = 0; 640 641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 643 !BNXT_FLOW_XSTATS_EN(bp)) 644 return 0; 645 646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 647 if (rc) 648 return rc; 649 650 rc = bnxt_init_fc_ctx_mem(bp); 651 652 return rc; 653 } 654 655 static int bnxt_update_phy_setting(struct bnxt *bp) 656 { 657 struct rte_eth_link new; 658 int rc; 659 660 rc = bnxt_get_hwrm_link_config(bp, &new); 661 if (rc) { 662 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 663 return rc; 664 } 665 666 /* 667 * On BCM957508-N2100 adapters, FW will not allow any user other 668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 669 * always returns link up. Force phy update always in that case. 670 */ 671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 672 rc = bnxt_set_hwrm_link_config(bp, true); 673 if (rc) { 674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 675 return rc; 676 } 677 } 678 679 return rc; 680 } 681 682 static int bnxt_init_chip(struct bnxt *bp) 683 { 684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 686 uint32_t intr_vector = 0; 687 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 688 uint32_t vec = BNXT_MISC_VEC_ID; 689 unsigned int i, j; 690 int rc; 691 692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 693 bp->eth_dev->data->dev_conf.rxmode.offloads |= 694 DEV_RX_OFFLOAD_JUMBO_FRAME; 695 bp->flags |= BNXT_FLAG_JUMBO; 696 } else { 697 bp->eth_dev->data->dev_conf.rxmode.offloads &= 698 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 699 bp->flags &= ~BNXT_FLAG_JUMBO; 700 } 701 702 /* THOR does not support ring groups. 703 * But we will use the array to save RSS context IDs. 704 */ 705 if (BNXT_CHIP_P5(bp)) 706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 707 708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 709 if (rc) { 710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 711 goto err_out; 712 } 713 714 rc = bnxt_alloc_hwrm_rings(bp); 715 if (rc) { 716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 717 goto err_out; 718 } 719 720 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 721 if (rc) { 722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 723 goto err_out; 724 } 725 726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 727 goto skip_cosq_cfg; 728 729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 730 if (bp->rx_cos_queue[i].id != 0xff) { 731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 732 733 if (!vnic) { 734 PMD_DRV_LOG(ERR, 735 "Num pools more than FW profile\n"); 736 rc = -EINVAL; 737 goto err_out; 738 } 739 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 740 bp->rx_cosq_cnt++; 741 } 742 } 743 744 skip_cosq_cfg: 745 rc = bnxt_mq_rx_configure(bp); 746 if (rc) { 747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 748 goto err_out; 749 } 750 751 /* default vnic 0 */ 752 rc = bnxt_setup_one_vnic(bp, 0); 753 if (rc) 754 goto err_out; 755 /* VNIC configuration */ 756 if (BNXT_RFS_NEEDS_VNIC(bp)) { 757 for (i = 1; i < bp->nr_vnics; i++) { 758 rc = bnxt_setup_one_vnic(bp, i); 759 if (rc) 760 goto err_out; 761 } 762 } 763 764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 765 if (rc) { 766 PMD_DRV_LOG(ERR, 767 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 768 goto err_out; 769 } 770 771 /* check and configure queue intr-vector mapping */ 772 if ((rte_intr_cap_multiple(intr_handle) || 773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 775 intr_vector = bp->eth_dev->data->nb_rx_queues; 776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 777 if (intr_vector > bp->rx_cp_nr_rings) { 778 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 779 bp->rx_cp_nr_rings); 780 return -ENOTSUP; 781 } 782 rc = rte_intr_efd_enable(intr_handle, intr_vector); 783 if (rc) 784 return rc; 785 } 786 787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 788 intr_handle->intr_vec = 789 rte_zmalloc("intr_vec", 790 bp->eth_dev->data->nb_rx_queues * 791 sizeof(int), 0); 792 if (intr_handle->intr_vec == NULL) { 793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 794 " intr_vec", bp->eth_dev->data->nb_rx_queues); 795 rc = -ENOMEM; 796 goto err_disable; 797 } 798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 800 intr_handle->intr_vec, intr_handle->nb_efd, 801 intr_handle->max_intr); 802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 803 queue_id++) { 804 intr_handle->intr_vec[queue_id] = 805 vec + BNXT_RX_VEC_START; 806 if (vec < base + intr_handle->nb_efd - 1) 807 vec++; 808 } 809 } 810 811 /* enable uio/vfio intr/eventfd mapping */ 812 rc = rte_intr_enable(intr_handle); 813 #ifndef RTE_EXEC_ENV_FREEBSD 814 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 815 if (rc) 816 goto err_free; 817 #endif 818 819 rc = bnxt_update_phy_setting(bp); 820 if (rc) 821 goto err_free; 822 823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 824 if (!bp->mark_table) 825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 826 827 return 0; 828 829 err_free: 830 rte_free(intr_handle->intr_vec); 831 err_disable: 832 rte_intr_efd_disable(intr_handle); 833 err_out: 834 /* Some of the error status returned by FW may not be from errno.h */ 835 if (rc > 0) 836 rc = -EIO; 837 838 return rc; 839 } 840 841 static int bnxt_shutdown_nic(struct bnxt *bp) 842 { 843 bnxt_free_all_hwrm_resources(bp); 844 bnxt_free_all_filters(bp); 845 bnxt_free_all_vnics(bp); 846 return 0; 847 } 848 849 /* 850 * Device configuration and status function 851 */ 852 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 854 { 855 uint32_t link_speed = bp->link_info->support_speeds; 856 uint32_t speed_capa = 0; 857 858 /* If PAM4 is configured, use PAM4 supported speed */ 859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 860 link_speed = bp->link_info->support_pam4_speeds; 861 862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 863 speed_capa |= ETH_LINK_SPEED_100M; 864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 865 speed_capa |= ETH_LINK_SPEED_100M_HD; 866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 867 speed_capa |= ETH_LINK_SPEED_1G; 868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 869 speed_capa |= ETH_LINK_SPEED_2_5G; 870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 871 speed_capa |= ETH_LINK_SPEED_10G; 872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 873 speed_capa |= ETH_LINK_SPEED_20G; 874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 875 speed_capa |= ETH_LINK_SPEED_25G; 876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 877 speed_capa |= ETH_LINK_SPEED_40G; 878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 879 speed_capa |= ETH_LINK_SPEED_50G; 880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 881 speed_capa |= ETH_LINK_SPEED_100G; 882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 883 speed_capa |= ETH_LINK_SPEED_50G; 884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 885 speed_capa |= ETH_LINK_SPEED_100G; 886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 887 speed_capa |= ETH_LINK_SPEED_200G; 888 889 if (bp->link_info->auto_mode == 890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 891 speed_capa |= ETH_LINK_SPEED_FIXED; 892 else 893 speed_capa |= ETH_LINK_SPEED_AUTONEG; 894 895 return speed_capa; 896 } 897 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 899 struct rte_eth_dev_info *dev_info) 900 { 901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 902 struct bnxt *bp = eth_dev->data->dev_private; 903 uint16_t max_vnics, i, j, vpool, vrxq; 904 unsigned int max_rx_rings; 905 int rc; 906 907 rc = is_bnxt_in_error(bp); 908 if (rc) 909 return rc; 910 911 /* MAC Specifics */ 912 dev_info->max_mac_addrs = bp->max_l2_ctx; 913 dev_info->max_hash_mac_addrs = 0; 914 915 /* PF/VF specifics */ 916 if (BNXT_PF(bp)) 917 dev_info->max_vfs = pdev->max_vfs; 918 919 max_rx_rings = bnxt_max_rings(bp); 920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 921 dev_info->max_rx_queues = max_rx_rings; 922 dev_info->max_tx_queues = max_rx_rings; 923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 924 dev_info->hash_key_size = 40; 925 max_vnics = bp->max_vnics; 926 927 /* MTU specifics */ 928 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 929 dev_info->max_mtu = BNXT_MAX_MTU; 930 931 /* Fast path specifics */ 932 dev_info->min_rx_bufsize = 1; 933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 934 935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 940 dev_info->tx_queue_offload_capa; 941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 942 943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 944 945 /* *INDENT-OFF* */ 946 dev_info->default_rxconf = (struct rte_eth_rxconf) { 947 .rx_thresh = { 948 .pthresh = 8, 949 .hthresh = 8, 950 .wthresh = 0, 951 }, 952 .rx_free_thresh = 32, 953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 954 }; 955 956 dev_info->default_txconf = (struct rte_eth_txconf) { 957 .tx_thresh = { 958 .pthresh = 32, 959 .hthresh = 0, 960 .wthresh = 0, 961 }, 962 .tx_free_thresh = 32, 963 .tx_rs_thresh = 32, 964 }; 965 eth_dev->data->dev_conf.intr_conf.lsc = 1; 966 967 eth_dev->data->dev_conf.intr_conf.rxq = 1; 968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 972 973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 974 dev_info->switch_info.name = eth_dev->device->name; 975 dev_info->switch_info.domain_id = bp->switch_domain_id; 976 dev_info->switch_info.port_id = 977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 978 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 979 } 980 981 /* *INDENT-ON* */ 982 983 /* 984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 985 * need further investigation. 986 */ 987 988 /* VMDq resources */ 989 vpool = 64; /* ETH_64_POOLS */ 990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 991 for (i = 0; i < 4; vpool >>= 1, i++) { 992 if (max_vnics > vpool) { 993 for (j = 0; j < 5; vrxq >>= 1, j++) { 994 if (dev_info->max_rx_queues > vrxq) { 995 if (vpool > vrxq) 996 vpool = vrxq; 997 goto found; 998 } 999 } 1000 /* Not enough resources to support VMDq */ 1001 break; 1002 } 1003 } 1004 /* Not enough resources to support VMDq */ 1005 vpool = 0; 1006 vrxq = 0; 1007 found: 1008 dev_info->max_vmdq_pools = vpool; 1009 dev_info->vmdq_queue_num = vrxq; 1010 1011 dev_info->vmdq_pool_base = 0; 1012 dev_info->vmdq_queue_base = 0; 1013 1014 return 0; 1015 } 1016 1017 /* Configure the device based on the configuration provided */ 1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1019 { 1020 struct bnxt *bp = eth_dev->data->dev_private; 1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1022 int rc; 1023 1024 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1025 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1028 1029 rc = is_bnxt_in_error(bp); 1030 if (rc) 1031 return rc; 1032 1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1034 rc = bnxt_hwrm_check_vf_rings(bp); 1035 if (rc) { 1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1037 return -ENOSPC; 1038 } 1039 1040 /* If a resource has already been allocated - in this case 1041 * it is the async completion ring, free it. Reallocate it after 1042 * resource reservation. This will ensure the resource counts 1043 * are calculated correctly. 1044 */ 1045 1046 pthread_mutex_lock(&bp->def_cp_lock); 1047 1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1049 bnxt_disable_int(bp); 1050 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1051 } 1052 1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1054 if (rc) { 1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1056 pthread_mutex_unlock(&bp->def_cp_lock); 1057 return -ENOSPC; 1058 } 1059 1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1061 rc = bnxt_alloc_async_cp_ring(bp); 1062 if (rc) { 1063 pthread_mutex_unlock(&bp->def_cp_lock); 1064 return rc; 1065 } 1066 bnxt_enable_int(bp); 1067 } 1068 1069 pthread_mutex_unlock(&bp->def_cp_lock); 1070 } 1071 1072 /* Inherit new configurations */ 1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1078 bp->max_stat_ctx) 1079 goto resource_error; 1080 1081 if (BNXT_HAS_RING_GRPS(bp) && 1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1083 goto resource_error; 1084 1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1086 bp->max_vnics < eth_dev->data->nb_rx_queues) 1087 goto resource_error; 1088 1089 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1090 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1091 1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1095 1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1097 eth_dev->data->mtu = 1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1100 BNXT_NUM_VLANS; 1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1102 } 1103 return 0; 1104 1105 resource_error: 1106 PMD_DRV_LOG(ERR, 1107 "Insufficient resources to support requested config\n"); 1108 PMD_DRV_LOG(ERR, 1109 "Num Queues Requested: Tx %d, Rx %d\n", 1110 eth_dev->data->nb_tx_queues, 1111 eth_dev->data->nb_rx_queues); 1112 PMD_DRV_LOG(ERR, 1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1116 return -ENOSPC; 1117 } 1118 1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1120 { 1121 struct rte_eth_link *link = ð_dev->data->dev_link; 1122 1123 if (link->link_status) 1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1125 eth_dev->data->port_id, 1126 (uint32_t)link->link_speed, 1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1128 ("full-duplex") : ("half-duplex\n")); 1129 else 1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1131 eth_dev->data->port_id); 1132 } 1133 1134 /* 1135 * Determine whether the current configuration requires support for scattered 1136 * receive; return 1 if scattered receive is required and 0 if not. 1137 */ 1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1139 { 1140 uint16_t buf_size; 1141 int i; 1142 1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1144 return 1; 1145 1146 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1147 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1148 1149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1150 RTE_PKTMBUF_HEADROOM); 1151 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1152 return 1; 1153 } 1154 return 0; 1155 } 1156 1157 static eth_rx_burst_t 1158 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1159 { 1160 struct bnxt *bp = eth_dev->data->dev_private; 1161 1162 /* Disable vector mode RX for Stingray2 for now */ 1163 if (BNXT_CHIP_SR2(bp)) { 1164 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1165 return bnxt_recv_pkts; 1166 } 1167 1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1169 #ifndef RTE_LIBRTE_IEEE1588 1170 /* 1171 * Vector mode receive can be enabled only if scatter rx is not 1172 * in use and rx offloads are limited to VLAN stripping and 1173 * CRC stripping. 1174 */ 1175 if (!eth_dev->data->scattered_rx && 1176 !(eth_dev->data->dev_conf.rxmode.offloads & 1177 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1178 DEV_RX_OFFLOAD_KEEP_CRC | 1179 DEV_RX_OFFLOAD_JUMBO_FRAME | 1180 DEV_RX_OFFLOAD_IPV4_CKSUM | 1181 DEV_RX_OFFLOAD_UDP_CKSUM | 1182 DEV_RX_OFFLOAD_TCP_CKSUM | 1183 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1184 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1185 DEV_RX_OFFLOAD_RSS_HASH | 1186 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1187 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && 1188 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1189 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1190 eth_dev->data->port_id); 1191 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1192 return bnxt_recv_pkts_vec; 1193 } 1194 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1195 eth_dev->data->port_id); 1196 PMD_DRV_LOG(INFO, 1197 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1198 eth_dev->data->port_id, 1199 eth_dev->data->scattered_rx, 1200 eth_dev->data->dev_conf.rxmode.offloads); 1201 #endif 1202 #endif 1203 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1204 return bnxt_recv_pkts; 1205 } 1206 1207 static eth_tx_burst_t 1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1209 { 1210 struct bnxt *bp = eth_dev->data->dev_private; 1211 1212 /* Disable vector mode TX for Stingray2 for now */ 1213 if (BNXT_CHIP_SR2(bp)) 1214 return bnxt_xmit_pkts; 1215 1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1217 #ifndef RTE_LIBRTE_IEEE1588 1218 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1219 1220 /* 1221 * Vector mode transmit can be enabled only if not using scatter rx 1222 * or tx offloads. 1223 */ 1224 if (!eth_dev->data->scattered_rx && 1225 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && 1226 !BNXT_TRUFLOW_EN(bp) && 1227 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1228 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1229 eth_dev->data->port_id); 1230 return bnxt_xmit_pkts_vec; 1231 } 1232 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1233 eth_dev->data->port_id); 1234 PMD_DRV_LOG(INFO, 1235 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1236 eth_dev->data->port_id, 1237 eth_dev->data->scattered_rx, 1238 offloads); 1239 #endif 1240 #endif 1241 return bnxt_xmit_pkts; 1242 } 1243 1244 static int bnxt_handle_if_change_status(struct bnxt *bp) 1245 { 1246 int rc; 1247 1248 /* Since fw has undergone a reset and lost all contexts, 1249 * set fatal flag to not issue hwrm during cleanup 1250 */ 1251 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1252 bnxt_uninit_resources(bp, true); 1253 1254 /* clear fatal flag so that re-init happens */ 1255 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1256 rc = bnxt_init_resources(bp, true); 1257 1258 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1259 1260 return rc; 1261 } 1262 1263 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1264 { 1265 struct bnxt *bp = eth_dev->data->dev_private; 1266 int rc = 0; 1267 1268 if (!bp->link_info->link_up) 1269 rc = bnxt_set_hwrm_link_config(bp, true); 1270 if (!rc) 1271 eth_dev->data->dev_link.link_status = 1; 1272 1273 bnxt_print_link_info(eth_dev); 1274 return rc; 1275 } 1276 1277 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1278 { 1279 struct bnxt *bp = eth_dev->data->dev_private; 1280 1281 eth_dev->data->dev_link.link_status = 0; 1282 bnxt_set_hwrm_link_config(bp, false); 1283 bp->link_info->link_up = 0; 1284 1285 return 0; 1286 } 1287 1288 static void bnxt_free_switch_domain(struct bnxt *bp) 1289 { 1290 int rc = 0; 1291 1292 if (bp->switch_domain_id) { 1293 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1294 if (rc) 1295 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1296 bp->switch_domain_id, rc); 1297 } 1298 } 1299 1300 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1301 { 1302 struct bnxt *bp = eth_dev->data->dev_private; 1303 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1304 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1305 struct rte_eth_link link; 1306 int ret; 1307 1308 eth_dev->data->dev_started = 0; 1309 eth_dev->data->scattered_rx = 0; 1310 1311 /* Prevent crashes when queues are still in use */ 1312 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1313 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1314 1315 bnxt_disable_int(bp); 1316 1317 /* disable uio/vfio intr/eventfd mapping */ 1318 rte_intr_disable(intr_handle); 1319 1320 /* Stop the child representors for this device */ 1321 ret = bnxt_rep_stop_all(bp); 1322 if (ret != 0) 1323 return ret; 1324 1325 /* delete the bnxt ULP port details */ 1326 bnxt_ulp_port_deinit(bp); 1327 1328 bnxt_cancel_fw_health_check(bp); 1329 1330 /* Do not bring link down during reset recovery */ 1331 if (!is_bnxt_in_error(bp)) { 1332 bnxt_dev_set_link_down_op(eth_dev); 1333 /* Wait for link to be reset */ 1334 if (BNXT_SINGLE_PF(bp)) 1335 rte_delay_ms(500); 1336 /* clear the recorded link status */ 1337 memset(&link, 0, sizeof(link)); 1338 rte_eth_linkstatus_set(eth_dev, &link); 1339 } 1340 1341 /* Clean queue intr-vector mapping */ 1342 rte_intr_efd_disable(intr_handle); 1343 if (intr_handle->intr_vec != NULL) { 1344 rte_free(intr_handle->intr_vec); 1345 intr_handle->intr_vec = NULL; 1346 } 1347 1348 bnxt_hwrm_port_clr_stats(bp); 1349 bnxt_free_tx_mbufs(bp); 1350 bnxt_free_rx_mbufs(bp); 1351 /* Process any remaining notifications in default completion queue */ 1352 bnxt_int_handler(eth_dev); 1353 bnxt_shutdown_nic(bp); 1354 bnxt_hwrm_if_change(bp, false); 1355 1356 rte_free(bp->mark_table); 1357 bp->mark_table = NULL; 1358 1359 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1360 bp->rx_cosq_cnt = 0; 1361 /* All filters are deleted on a port stop. */ 1362 if (BNXT_FLOW_XSTATS_EN(bp)) 1363 bp->flow_stat->flow_count = 0; 1364 1365 return 0; 1366 } 1367 1368 /* Unload the driver, release resources */ 1369 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1370 { 1371 struct bnxt *bp = eth_dev->data->dev_private; 1372 1373 pthread_mutex_lock(&bp->err_recovery_lock); 1374 if (bp->flags & BNXT_FLAG_FW_RESET) { 1375 PMD_DRV_LOG(ERR, 1376 "Adapter recovering from error..Please retry\n"); 1377 return -EAGAIN; 1378 } 1379 pthread_mutex_unlock(&bp->err_recovery_lock); 1380 1381 return bnxt_dev_stop(eth_dev); 1382 } 1383 1384 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1385 { 1386 struct bnxt *bp = eth_dev->data->dev_private; 1387 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1388 int vlan_mask = 0; 1389 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1390 1391 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1392 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1393 return -EINVAL; 1394 } 1395 1396 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1397 PMD_DRV_LOG(ERR, 1398 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1399 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1400 1401 do { 1402 rc = bnxt_hwrm_if_change(bp, true); 1403 if (rc == 0 || rc != -EAGAIN) 1404 break; 1405 1406 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1407 } while (retry_cnt--); 1408 1409 if (rc) 1410 return rc; 1411 1412 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1413 rc = bnxt_handle_if_change_status(bp); 1414 if (rc) 1415 return rc; 1416 } 1417 1418 bnxt_enable_int(bp); 1419 1420 rc = bnxt_init_chip(bp); 1421 if (rc) 1422 goto error; 1423 1424 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1425 eth_dev->data->dev_started = 1; 1426 1427 bnxt_link_update_op(eth_dev, 1); 1428 1429 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1430 vlan_mask |= ETH_VLAN_FILTER_MASK; 1431 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1432 vlan_mask |= ETH_VLAN_STRIP_MASK; 1433 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1434 if (rc) 1435 goto error; 1436 1437 /* Initialize bnxt ULP port details */ 1438 rc = bnxt_ulp_port_init(bp); 1439 if (rc) 1440 goto error; 1441 1442 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1443 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1444 1445 bnxt_schedule_fw_health_check(bp); 1446 1447 return 0; 1448 1449 error: 1450 bnxt_dev_stop(eth_dev); 1451 return rc; 1452 } 1453 1454 static void 1455 bnxt_uninit_locks(struct bnxt *bp) 1456 { 1457 pthread_mutex_destroy(&bp->flow_lock); 1458 pthread_mutex_destroy(&bp->def_cp_lock); 1459 pthread_mutex_destroy(&bp->health_check_lock); 1460 pthread_mutex_destroy(&bp->err_recovery_lock); 1461 if (bp->rep_info) { 1462 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1463 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1464 } 1465 } 1466 1467 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1468 { 1469 struct bnxt *bp = eth_dev->data->dev_private; 1470 int ret = 0; 1471 1472 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1473 return 0; 1474 1475 pthread_mutex_lock(&bp->err_recovery_lock); 1476 if (bp->flags & BNXT_FLAG_FW_RESET) { 1477 PMD_DRV_LOG(ERR, 1478 "Adapter recovering from error...Please retry\n"); 1479 return -EAGAIN; 1480 } 1481 pthread_mutex_unlock(&bp->err_recovery_lock); 1482 1483 /* cancel the recovery handler before remove dev */ 1484 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1485 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1486 bnxt_cancel_fc_thread(bp); 1487 1488 if (eth_dev->data->dev_started) 1489 ret = bnxt_dev_stop(eth_dev); 1490 1491 bnxt_free_switch_domain(bp); 1492 1493 bnxt_uninit_resources(bp, false); 1494 1495 bnxt_free_leds_info(bp); 1496 bnxt_free_cos_queues(bp); 1497 bnxt_free_link_info(bp); 1498 bnxt_free_pf_info(bp); 1499 bnxt_free_parent_info(bp); 1500 bnxt_uninit_locks(bp); 1501 1502 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1503 bp->tx_mem_zone = NULL; 1504 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1505 bp->rx_mem_zone = NULL; 1506 1507 bnxt_hwrm_free_vf_info(bp); 1508 1509 rte_free(bp->grp_info); 1510 bp->grp_info = NULL; 1511 1512 return ret; 1513 } 1514 1515 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1516 uint32_t index) 1517 { 1518 struct bnxt *bp = eth_dev->data->dev_private; 1519 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1520 struct bnxt_vnic_info *vnic; 1521 struct bnxt_filter_info *filter, *temp_filter; 1522 uint32_t i; 1523 1524 if (is_bnxt_in_error(bp)) 1525 return; 1526 1527 /* 1528 * Loop through all VNICs from the specified filter flow pools to 1529 * remove the corresponding MAC addr filter 1530 */ 1531 for (i = 0; i < bp->nr_vnics; i++) { 1532 if (!(pool_mask & (1ULL << i))) 1533 continue; 1534 1535 vnic = &bp->vnic_info[i]; 1536 filter = STAILQ_FIRST(&vnic->filter); 1537 while (filter) { 1538 temp_filter = STAILQ_NEXT(filter, next); 1539 if (filter->mac_index == index) { 1540 STAILQ_REMOVE(&vnic->filter, filter, 1541 bnxt_filter_info, next); 1542 bnxt_hwrm_clear_l2_filter(bp, filter); 1543 bnxt_free_filter(bp, filter); 1544 } 1545 filter = temp_filter; 1546 } 1547 } 1548 } 1549 1550 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1551 struct rte_ether_addr *mac_addr, uint32_t index, 1552 uint32_t pool) 1553 { 1554 struct bnxt_filter_info *filter; 1555 int rc = 0; 1556 1557 /* Attach requested MAC address to the new l2_filter */ 1558 STAILQ_FOREACH(filter, &vnic->filter, next) { 1559 if (filter->mac_index == index) { 1560 PMD_DRV_LOG(DEBUG, 1561 "MAC addr already existed for pool %d\n", 1562 pool); 1563 return 0; 1564 } 1565 } 1566 1567 filter = bnxt_alloc_filter(bp); 1568 if (!filter) { 1569 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1570 return -ENODEV; 1571 } 1572 1573 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1574 * if the MAC that's been programmed now is a different one, then, 1575 * copy that addr to filter->l2_addr 1576 */ 1577 if (mac_addr) 1578 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1579 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1580 1581 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1582 if (!rc) { 1583 filter->mac_index = index; 1584 if (filter->mac_index == 0) 1585 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1586 else 1587 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1588 } else { 1589 bnxt_free_filter(bp, filter); 1590 } 1591 1592 return rc; 1593 } 1594 1595 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1596 struct rte_ether_addr *mac_addr, 1597 uint32_t index, uint32_t pool) 1598 { 1599 struct bnxt *bp = eth_dev->data->dev_private; 1600 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1601 int rc = 0; 1602 1603 rc = is_bnxt_in_error(bp); 1604 if (rc) 1605 return rc; 1606 1607 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1608 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1609 return -ENOTSUP; 1610 } 1611 1612 if (!vnic) { 1613 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1614 return -EINVAL; 1615 } 1616 1617 /* Filter settings will get applied when port is started */ 1618 if (!eth_dev->data->dev_started) 1619 return 0; 1620 1621 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1622 1623 return rc; 1624 } 1625 1626 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1627 { 1628 int rc = 0; 1629 struct bnxt *bp = eth_dev->data->dev_private; 1630 struct rte_eth_link new; 1631 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1632 BNXT_MIN_LINK_WAIT_CNT; 1633 1634 rc = is_bnxt_in_error(bp); 1635 if (rc) 1636 return rc; 1637 1638 memset(&new, 0, sizeof(new)); 1639 do { 1640 /* Retrieve link info from hardware */ 1641 rc = bnxt_get_hwrm_link_config(bp, &new); 1642 if (rc) { 1643 new.link_speed = ETH_LINK_SPEED_100M; 1644 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1645 PMD_DRV_LOG(ERR, 1646 "Failed to retrieve link rc = 0x%x!\n", rc); 1647 goto out; 1648 } 1649 1650 if (!wait_to_complete || new.link_status) 1651 break; 1652 1653 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1654 } while (cnt--); 1655 1656 /* Only single function PF can bring phy down. 1657 * When port is stopped, report link down for VF/MH/NPAR functions. 1658 */ 1659 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1660 memset(&new, 0, sizeof(new)); 1661 1662 out: 1663 /* Timed out or success */ 1664 if (new.link_status != eth_dev->data->dev_link.link_status || 1665 new.link_speed != eth_dev->data->dev_link.link_speed) { 1666 rte_eth_linkstatus_set(eth_dev, &new); 1667 1668 rte_eth_dev_callback_process(eth_dev, 1669 RTE_ETH_EVENT_INTR_LSC, 1670 NULL); 1671 1672 bnxt_print_link_info(eth_dev); 1673 } 1674 1675 return rc; 1676 } 1677 1678 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1679 { 1680 struct bnxt *bp = eth_dev->data->dev_private; 1681 struct bnxt_vnic_info *vnic; 1682 uint32_t old_flags; 1683 int rc; 1684 1685 rc = is_bnxt_in_error(bp); 1686 if (rc) 1687 return rc; 1688 1689 /* Filter settings will get applied when port is started */ 1690 if (!eth_dev->data->dev_started) 1691 return 0; 1692 1693 if (bp->vnic_info == NULL) 1694 return 0; 1695 1696 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1697 1698 old_flags = vnic->flags; 1699 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1700 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1701 if (rc != 0) 1702 vnic->flags = old_flags; 1703 1704 return rc; 1705 } 1706 1707 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1708 { 1709 struct bnxt *bp = eth_dev->data->dev_private; 1710 struct bnxt_vnic_info *vnic; 1711 uint32_t old_flags; 1712 int rc; 1713 1714 rc = is_bnxt_in_error(bp); 1715 if (rc) 1716 return rc; 1717 1718 /* Filter settings will get applied when port is started */ 1719 if (!eth_dev->data->dev_started) 1720 return 0; 1721 1722 if (bp->vnic_info == NULL) 1723 return 0; 1724 1725 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1726 1727 old_flags = vnic->flags; 1728 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1729 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1730 if (rc != 0) 1731 vnic->flags = old_flags; 1732 1733 return rc; 1734 } 1735 1736 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1737 { 1738 struct bnxt *bp = eth_dev->data->dev_private; 1739 struct bnxt_vnic_info *vnic; 1740 uint32_t old_flags; 1741 int rc; 1742 1743 rc = is_bnxt_in_error(bp); 1744 if (rc) 1745 return rc; 1746 1747 /* Filter settings will get applied when port is started */ 1748 if (!eth_dev->data->dev_started) 1749 return 0; 1750 1751 if (bp->vnic_info == NULL) 1752 return 0; 1753 1754 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1755 1756 old_flags = vnic->flags; 1757 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1758 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1759 if (rc != 0) 1760 vnic->flags = old_flags; 1761 1762 return rc; 1763 } 1764 1765 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1766 { 1767 struct bnxt *bp = eth_dev->data->dev_private; 1768 struct bnxt_vnic_info *vnic; 1769 uint32_t old_flags; 1770 int rc; 1771 1772 rc = is_bnxt_in_error(bp); 1773 if (rc) 1774 return rc; 1775 1776 /* Filter settings will get applied when port is started */ 1777 if (!eth_dev->data->dev_started) 1778 return 0; 1779 1780 if (bp->vnic_info == NULL) 1781 return 0; 1782 1783 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1784 1785 old_flags = vnic->flags; 1786 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1787 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1788 if (rc != 0) 1789 vnic->flags = old_flags; 1790 1791 return rc; 1792 } 1793 1794 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1795 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1796 { 1797 if (qid >= bp->rx_nr_rings) 1798 return NULL; 1799 1800 return bp->eth_dev->data->rx_queues[qid]; 1801 } 1802 1803 /* Return rxq corresponding to a given rss table ring/group ID. */ 1804 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1805 { 1806 struct bnxt_rx_queue *rxq; 1807 unsigned int i; 1808 1809 if (!BNXT_HAS_RING_GRPS(bp)) { 1810 for (i = 0; i < bp->rx_nr_rings; i++) { 1811 rxq = bp->eth_dev->data->rx_queues[i]; 1812 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1813 return rxq->index; 1814 } 1815 } else { 1816 for (i = 0; i < bp->rx_nr_rings; i++) { 1817 if (bp->grp_info[i].fw_grp_id == fwr) 1818 return i; 1819 } 1820 } 1821 1822 return INVALID_HW_RING_ID; 1823 } 1824 1825 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1826 struct rte_eth_rss_reta_entry64 *reta_conf, 1827 uint16_t reta_size) 1828 { 1829 struct bnxt *bp = eth_dev->data->dev_private; 1830 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1831 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1832 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1833 uint16_t idx, sft; 1834 int i, rc; 1835 1836 rc = is_bnxt_in_error(bp); 1837 if (rc) 1838 return rc; 1839 1840 if (!vnic->rss_table) 1841 return -EINVAL; 1842 1843 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1844 return -EINVAL; 1845 1846 if (reta_size != tbl_size) { 1847 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1848 "(%d) must equal the size supported by the hardware " 1849 "(%d)\n", reta_size, tbl_size); 1850 return -EINVAL; 1851 } 1852 1853 for (i = 0; i < reta_size; i++) { 1854 struct bnxt_rx_queue *rxq; 1855 1856 idx = i / RTE_RETA_GROUP_SIZE; 1857 sft = i % RTE_RETA_GROUP_SIZE; 1858 1859 if (!(reta_conf[idx].mask & (1ULL << sft))) 1860 continue; 1861 1862 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1863 if (!rxq) { 1864 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1865 return -EINVAL; 1866 } 1867 1868 if (BNXT_CHIP_P5(bp)) { 1869 vnic->rss_table[i * 2] = 1870 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1871 vnic->rss_table[i * 2 + 1] = 1872 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1873 } else { 1874 vnic->rss_table[i] = 1875 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1876 } 1877 } 1878 1879 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1880 return rc; 1881 } 1882 1883 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1884 struct rte_eth_rss_reta_entry64 *reta_conf, 1885 uint16_t reta_size) 1886 { 1887 struct bnxt *bp = eth_dev->data->dev_private; 1888 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1889 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1890 uint16_t idx, sft, i; 1891 int rc; 1892 1893 rc = is_bnxt_in_error(bp); 1894 if (rc) 1895 return rc; 1896 1897 /* Retrieve from the default VNIC */ 1898 if (!vnic) 1899 return -EINVAL; 1900 if (!vnic->rss_table) 1901 return -EINVAL; 1902 1903 if (reta_size != tbl_size) { 1904 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1905 "(%d) must equal the size supported by the hardware " 1906 "(%d)\n", reta_size, tbl_size); 1907 return -EINVAL; 1908 } 1909 1910 for (idx = 0, i = 0; i < reta_size; i++) { 1911 idx = i / RTE_RETA_GROUP_SIZE; 1912 sft = i % RTE_RETA_GROUP_SIZE; 1913 1914 if (reta_conf[idx].mask & (1ULL << sft)) { 1915 uint16_t qid; 1916 1917 if (BNXT_CHIP_P5(bp)) 1918 qid = bnxt_rss_to_qid(bp, 1919 vnic->rss_table[i * 2]); 1920 else 1921 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1922 1923 if (qid == INVALID_HW_RING_ID) { 1924 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1925 return -EINVAL; 1926 } 1927 reta_conf[idx].reta[sft] = qid; 1928 } 1929 } 1930 1931 return 0; 1932 } 1933 1934 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1935 struct rte_eth_rss_conf *rss_conf) 1936 { 1937 struct bnxt *bp = eth_dev->data->dev_private; 1938 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1939 struct bnxt_vnic_info *vnic; 1940 int rc; 1941 1942 rc = is_bnxt_in_error(bp); 1943 if (rc) 1944 return rc; 1945 1946 /* 1947 * If RSS enablement were different than dev_configure, 1948 * then return -EINVAL 1949 */ 1950 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1951 if (!rss_conf->rss_hf) 1952 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1953 } else { 1954 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1955 return -EINVAL; 1956 } 1957 1958 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1959 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 1960 rss_conf, 1961 sizeof(*rss_conf)); 1962 1963 /* Update the default RSS VNIC(s) */ 1964 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1965 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1966 vnic->hash_mode = 1967 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 1968 ETH_RSS_LEVEL(rss_conf->rss_hf)); 1969 1970 /* 1971 * If hashkey is not specified, use the previously configured 1972 * hashkey 1973 */ 1974 if (!rss_conf->rss_key) 1975 goto rss_config; 1976 1977 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1978 PMD_DRV_LOG(ERR, 1979 "Invalid hashkey length, should be 16 bytes\n"); 1980 return -EINVAL; 1981 } 1982 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1983 1984 rss_config: 1985 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1986 return rc; 1987 } 1988 1989 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1990 struct rte_eth_rss_conf *rss_conf) 1991 { 1992 struct bnxt *bp = eth_dev->data->dev_private; 1993 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1994 int len, rc; 1995 uint32_t hash_types; 1996 1997 rc = is_bnxt_in_error(bp); 1998 if (rc) 1999 return rc; 2000 2001 /* RSS configuration is the same for all VNICs */ 2002 if (vnic && vnic->rss_hash_key) { 2003 if (rss_conf->rss_key) { 2004 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2005 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2006 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2007 } 2008 2009 hash_types = vnic->hash_type; 2010 rss_conf->rss_hf = 0; 2011 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2012 rss_conf->rss_hf |= ETH_RSS_IPV4; 2013 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2014 } 2015 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2016 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2017 hash_types &= 2018 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2019 } 2020 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2021 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2022 hash_types &= 2023 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2024 } 2025 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2026 rss_conf->rss_hf |= ETH_RSS_IPV6; 2027 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2028 } 2029 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2030 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2031 hash_types &= 2032 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2033 } 2034 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2035 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2036 hash_types &= 2037 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2038 } 2039 2040 rss_conf->rss_hf |= 2041 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2042 2043 if (hash_types) { 2044 PMD_DRV_LOG(ERR, 2045 "Unknown RSS config from firmware (%08x), RSS disabled", 2046 vnic->hash_type); 2047 return -ENOTSUP; 2048 } 2049 } else { 2050 rss_conf->rss_hf = 0; 2051 } 2052 return 0; 2053 } 2054 2055 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2056 struct rte_eth_fc_conf *fc_conf) 2057 { 2058 struct bnxt *bp = dev->data->dev_private; 2059 struct rte_eth_link link_info; 2060 int rc; 2061 2062 rc = is_bnxt_in_error(bp); 2063 if (rc) 2064 return rc; 2065 2066 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2067 if (rc) 2068 return rc; 2069 2070 memset(fc_conf, 0, sizeof(*fc_conf)); 2071 if (bp->link_info->auto_pause) 2072 fc_conf->autoneg = 1; 2073 switch (bp->link_info->pause) { 2074 case 0: 2075 fc_conf->mode = RTE_FC_NONE; 2076 break; 2077 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2078 fc_conf->mode = RTE_FC_TX_PAUSE; 2079 break; 2080 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2081 fc_conf->mode = RTE_FC_RX_PAUSE; 2082 break; 2083 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2084 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2085 fc_conf->mode = RTE_FC_FULL; 2086 break; 2087 } 2088 return 0; 2089 } 2090 2091 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2092 struct rte_eth_fc_conf *fc_conf) 2093 { 2094 struct bnxt *bp = dev->data->dev_private; 2095 int rc; 2096 2097 rc = is_bnxt_in_error(bp); 2098 if (rc) 2099 return rc; 2100 2101 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2102 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 2103 return -ENOTSUP; 2104 } 2105 2106 switch (fc_conf->mode) { 2107 case RTE_FC_NONE: 2108 bp->link_info->auto_pause = 0; 2109 bp->link_info->force_pause = 0; 2110 break; 2111 case RTE_FC_RX_PAUSE: 2112 if (fc_conf->autoneg) { 2113 bp->link_info->auto_pause = 2114 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2115 bp->link_info->force_pause = 0; 2116 } else { 2117 bp->link_info->auto_pause = 0; 2118 bp->link_info->force_pause = 2119 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2120 } 2121 break; 2122 case RTE_FC_TX_PAUSE: 2123 if (fc_conf->autoneg) { 2124 bp->link_info->auto_pause = 2125 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2126 bp->link_info->force_pause = 0; 2127 } else { 2128 bp->link_info->auto_pause = 0; 2129 bp->link_info->force_pause = 2130 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2131 } 2132 break; 2133 case RTE_FC_FULL: 2134 if (fc_conf->autoneg) { 2135 bp->link_info->auto_pause = 2136 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2137 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2138 bp->link_info->force_pause = 0; 2139 } else { 2140 bp->link_info->auto_pause = 0; 2141 bp->link_info->force_pause = 2142 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2143 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2144 } 2145 break; 2146 } 2147 return bnxt_set_hwrm_link_config(bp, true); 2148 } 2149 2150 /* Add UDP tunneling port */ 2151 static int 2152 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2153 struct rte_eth_udp_tunnel *udp_tunnel) 2154 { 2155 struct bnxt *bp = eth_dev->data->dev_private; 2156 uint16_t tunnel_type = 0; 2157 int rc = 0; 2158 2159 rc = is_bnxt_in_error(bp); 2160 if (rc) 2161 return rc; 2162 2163 switch (udp_tunnel->prot_type) { 2164 case RTE_TUNNEL_TYPE_VXLAN: 2165 if (bp->vxlan_port_cnt) { 2166 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2167 udp_tunnel->udp_port); 2168 if (bp->vxlan_port != udp_tunnel->udp_port) { 2169 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2170 return -ENOSPC; 2171 } 2172 bp->vxlan_port_cnt++; 2173 return 0; 2174 } 2175 tunnel_type = 2176 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2177 bp->vxlan_port_cnt++; 2178 break; 2179 case RTE_TUNNEL_TYPE_GENEVE: 2180 if (bp->geneve_port_cnt) { 2181 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2182 udp_tunnel->udp_port); 2183 if (bp->geneve_port != udp_tunnel->udp_port) { 2184 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2185 return -ENOSPC; 2186 } 2187 bp->geneve_port_cnt++; 2188 return 0; 2189 } 2190 tunnel_type = 2191 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2192 bp->geneve_port_cnt++; 2193 break; 2194 default: 2195 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2196 return -ENOTSUP; 2197 } 2198 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2199 tunnel_type); 2200 return rc; 2201 } 2202 2203 static int 2204 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2205 struct rte_eth_udp_tunnel *udp_tunnel) 2206 { 2207 struct bnxt *bp = eth_dev->data->dev_private; 2208 uint16_t tunnel_type = 0; 2209 uint16_t port = 0; 2210 int rc = 0; 2211 2212 rc = is_bnxt_in_error(bp); 2213 if (rc) 2214 return rc; 2215 2216 switch (udp_tunnel->prot_type) { 2217 case RTE_TUNNEL_TYPE_VXLAN: 2218 if (!bp->vxlan_port_cnt) { 2219 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2220 return -EINVAL; 2221 } 2222 if (bp->vxlan_port != udp_tunnel->udp_port) { 2223 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2224 udp_tunnel->udp_port, bp->vxlan_port); 2225 return -EINVAL; 2226 } 2227 if (--bp->vxlan_port_cnt) 2228 return 0; 2229 2230 tunnel_type = 2231 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2232 port = bp->vxlan_fw_dst_port_id; 2233 break; 2234 case RTE_TUNNEL_TYPE_GENEVE: 2235 if (!bp->geneve_port_cnt) { 2236 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2237 return -EINVAL; 2238 } 2239 if (bp->geneve_port != udp_tunnel->udp_port) { 2240 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2241 udp_tunnel->udp_port, bp->geneve_port); 2242 return -EINVAL; 2243 } 2244 if (--bp->geneve_port_cnt) 2245 return 0; 2246 2247 tunnel_type = 2248 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2249 port = bp->geneve_fw_dst_port_id; 2250 break; 2251 default: 2252 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2253 return -ENOTSUP; 2254 } 2255 2256 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2257 return rc; 2258 } 2259 2260 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2261 { 2262 struct bnxt_filter_info *filter; 2263 struct bnxt_vnic_info *vnic; 2264 int rc = 0; 2265 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2266 2267 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2268 filter = STAILQ_FIRST(&vnic->filter); 2269 while (filter) { 2270 /* Search for this matching MAC+VLAN filter */ 2271 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2272 /* Delete the filter */ 2273 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2274 if (rc) 2275 return rc; 2276 STAILQ_REMOVE(&vnic->filter, filter, 2277 bnxt_filter_info, next); 2278 bnxt_free_filter(bp, filter); 2279 PMD_DRV_LOG(INFO, 2280 "Deleted vlan filter for %d\n", 2281 vlan_id); 2282 return 0; 2283 } 2284 filter = STAILQ_NEXT(filter, next); 2285 } 2286 return -ENOENT; 2287 } 2288 2289 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2290 { 2291 struct bnxt_filter_info *filter; 2292 struct bnxt_vnic_info *vnic; 2293 int rc = 0; 2294 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2295 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2296 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2297 2298 /* Implementation notes on the use of VNIC in this command: 2299 * 2300 * By default, these filters belong to default vnic for the function. 2301 * Once these filters are set up, only destination VNIC can be modified. 2302 * If the destination VNIC is not specified in this command, 2303 * then the HWRM shall only create an l2 context id. 2304 */ 2305 2306 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2307 filter = STAILQ_FIRST(&vnic->filter); 2308 /* Check if the VLAN has already been added */ 2309 while (filter) { 2310 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2311 return -EEXIST; 2312 2313 filter = STAILQ_NEXT(filter, next); 2314 } 2315 2316 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2317 * command to create MAC+VLAN filter with the right flags, enables set. 2318 */ 2319 filter = bnxt_alloc_filter(bp); 2320 if (!filter) { 2321 PMD_DRV_LOG(ERR, 2322 "MAC/VLAN filter alloc failed\n"); 2323 return -ENOMEM; 2324 } 2325 /* MAC + VLAN ID filter */ 2326 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2327 * untagged packets are received 2328 * 2329 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2330 * packets and only the programmed vlan's packets are received 2331 */ 2332 filter->l2_ivlan = vlan_id; 2333 filter->l2_ivlan_mask = 0x0FFF; 2334 filter->enables |= en; 2335 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2336 2337 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2338 if (rc) { 2339 /* Free the newly allocated filter as we were 2340 * not able to create the filter in hardware. 2341 */ 2342 bnxt_free_filter(bp, filter); 2343 return rc; 2344 } 2345 2346 filter->mac_index = 0; 2347 /* Add this new filter to the list */ 2348 if (vlan_id == 0) 2349 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2350 else 2351 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2352 2353 PMD_DRV_LOG(INFO, 2354 "Added Vlan filter for %d\n", vlan_id); 2355 return rc; 2356 } 2357 2358 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2359 uint16_t vlan_id, int on) 2360 { 2361 struct bnxt *bp = eth_dev->data->dev_private; 2362 int rc; 2363 2364 rc = is_bnxt_in_error(bp); 2365 if (rc) 2366 return rc; 2367 2368 if (!eth_dev->data->dev_started) { 2369 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2370 return -EINVAL; 2371 } 2372 2373 /* These operations apply to ALL existing MAC/VLAN filters */ 2374 if (on) 2375 return bnxt_add_vlan_filter(bp, vlan_id); 2376 else 2377 return bnxt_del_vlan_filter(bp, vlan_id); 2378 } 2379 2380 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2381 struct bnxt_vnic_info *vnic) 2382 { 2383 struct bnxt_filter_info *filter; 2384 int rc; 2385 2386 filter = STAILQ_FIRST(&vnic->filter); 2387 while (filter) { 2388 if (filter->mac_index == 0 && 2389 !memcmp(filter->l2_addr, bp->mac_addr, 2390 RTE_ETHER_ADDR_LEN)) { 2391 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2392 if (!rc) { 2393 STAILQ_REMOVE(&vnic->filter, filter, 2394 bnxt_filter_info, next); 2395 bnxt_free_filter(bp, filter); 2396 } 2397 return rc; 2398 } 2399 filter = STAILQ_NEXT(filter, next); 2400 } 2401 return 0; 2402 } 2403 2404 static int 2405 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2406 { 2407 struct bnxt_vnic_info *vnic; 2408 unsigned int i; 2409 int rc; 2410 2411 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2412 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2413 /* Remove any VLAN filters programmed */ 2414 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2415 bnxt_del_vlan_filter(bp, i); 2416 2417 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2418 if (rc) 2419 return rc; 2420 } else { 2421 /* Default filter will allow packets that match the 2422 * dest mac. So, it has to be deleted, otherwise, we 2423 * will endup receiving vlan packets for which the 2424 * filter is not programmed, when hw-vlan-filter 2425 * configuration is ON 2426 */ 2427 bnxt_del_dflt_mac_filter(bp, vnic); 2428 /* This filter will allow only untagged packets */ 2429 bnxt_add_vlan_filter(bp, 0); 2430 } 2431 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2432 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2433 2434 return 0; 2435 } 2436 2437 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2438 { 2439 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2440 unsigned int i; 2441 int rc; 2442 2443 /* Destroy vnic filters and vnic */ 2444 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2445 DEV_RX_OFFLOAD_VLAN_FILTER) { 2446 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2447 bnxt_del_vlan_filter(bp, i); 2448 } 2449 bnxt_del_dflt_mac_filter(bp, vnic); 2450 2451 rc = bnxt_hwrm_vnic_free(bp, vnic); 2452 if (rc) 2453 return rc; 2454 2455 rte_free(vnic->fw_grp_ids); 2456 vnic->fw_grp_ids = NULL; 2457 2458 vnic->rx_queue_cnt = 0; 2459 2460 return 0; 2461 } 2462 2463 static int 2464 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2465 { 2466 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2467 int rc; 2468 2469 /* Destroy, recreate and reconfigure the default vnic */ 2470 rc = bnxt_free_one_vnic(bp, 0); 2471 if (rc) 2472 return rc; 2473 2474 /* default vnic 0 */ 2475 rc = bnxt_setup_one_vnic(bp, 0); 2476 if (rc) 2477 return rc; 2478 2479 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2480 DEV_RX_OFFLOAD_VLAN_FILTER) { 2481 rc = bnxt_add_vlan_filter(bp, 0); 2482 if (rc) 2483 return rc; 2484 rc = bnxt_restore_vlan_filters(bp); 2485 if (rc) 2486 return rc; 2487 } else { 2488 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2489 if (rc) 2490 return rc; 2491 } 2492 2493 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2494 if (rc) 2495 return rc; 2496 2497 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2498 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2499 2500 return rc; 2501 } 2502 2503 static int 2504 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2505 { 2506 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2507 struct bnxt *bp = dev->data->dev_private; 2508 int rc; 2509 2510 rc = is_bnxt_in_error(bp); 2511 if (rc) 2512 return rc; 2513 2514 /* Filter settings will get applied when port is started */ 2515 if (!dev->data->dev_started) 2516 return 0; 2517 2518 if (mask & ETH_VLAN_FILTER_MASK) { 2519 /* Enable or disable VLAN filtering */ 2520 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2521 if (rc) 2522 return rc; 2523 } 2524 2525 if (mask & ETH_VLAN_STRIP_MASK) { 2526 /* Enable or disable VLAN stripping */ 2527 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2528 if (rc) 2529 return rc; 2530 } 2531 2532 if (mask & ETH_VLAN_EXTEND_MASK) { 2533 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2534 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2535 else 2536 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2537 } 2538 2539 return 0; 2540 } 2541 2542 static int 2543 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2544 uint16_t tpid) 2545 { 2546 struct bnxt *bp = dev->data->dev_private; 2547 int qinq = dev->data->dev_conf.rxmode.offloads & 2548 DEV_RX_OFFLOAD_VLAN_EXTEND; 2549 2550 if (vlan_type != ETH_VLAN_TYPE_INNER && 2551 vlan_type != ETH_VLAN_TYPE_OUTER) { 2552 PMD_DRV_LOG(ERR, 2553 "Unsupported vlan type."); 2554 return -EINVAL; 2555 } 2556 if (!qinq) { 2557 PMD_DRV_LOG(ERR, 2558 "QinQ not enabled. Needs to be ON as we can " 2559 "accelerate only outer vlan\n"); 2560 return -EINVAL; 2561 } 2562 2563 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2564 switch (tpid) { 2565 case RTE_ETHER_TYPE_QINQ: 2566 bp->outer_tpid_bd = 2567 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2568 break; 2569 case RTE_ETHER_TYPE_VLAN: 2570 bp->outer_tpid_bd = 2571 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2572 break; 2573 case RTE_ETHER_TYPE_QINQ1: 2574 bp->outer_tpid_bd = 2575 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2576 break; 2577 case RTE_ETHER_TYPE_QINQ2: 2578 bp->outer_tpid_bd = 2579 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2580 break; 2581 case RTE_ETHER_TYPE_QINQ3: 2582 bp->outer_tpid_bd = 2583 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2584 break; 2585 default: 2586 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2587 return -EINVAL; 2588 } 2589 bp->outer_tpid_bd |= tpid; 2590 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2591 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2592 PMD_DRV_LOG(ERR, 2593 "Can accelerate only outer vlan in QinQ\n"); 2594 return -EINVAL; 2595 } 2596 2597 return 0; 2598 } 2599 2600 static int 2601 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2602 struct rte_ether_addr *addr) 2603 { 2604 struct bnxt *bp = dev->data->dev_private; 2605 /* Default Filter is tied to VNIC 0 */ 2606 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2607 int rc; 2608 2609 rc = is_bnxt_in_error(bp); 2610 if (rc) 2611 return rc; 2612 2613 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2614 return -EPERM; 2615 2616 if (rte_is_zero_ether_addr(addr)) 2617 return -EINVAL; 2618 2619 /* Filter settings will get applied when port is started */ 2620 if (!dev->data->dev_started) 2621 return 0; 2622 2623 /* Check if the requested MAC is already added */ 2624 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2625 return 0; 2626 2627 /* Destroy filter and re-create it */ 2628 bnxt_del_dflt_mac_filter(bp, vnic); 2629 2630 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2631 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2632 /* This filter will allow only untagged packets */ 2633 rc = bnxt_add_vlan_filter(bp, 0); 2634 } else { 2635 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2636 } 2637 2638 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2639 return rc; 2640 } 2641 2642 static int 2643 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2644 struct rte_ether_addr *mc_addr_set, 2645 uint32_t nb_mc_addr) 2646 { 2647 struct bnxt *bp = eth_dev->data->dev_private; 2648 char *mc_addr_list = (char *)mc_addr_set; 2649 struct bnxt_vnic_info *vnic; 2650 uint32_t off = 0, i = 0; 2651 int rc; 2652 2653 rc = is_bnxt_in_error(bp); 2654 if (rc) 2655 return rc; 2656 2657 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2658 2659 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2660 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2661 goto allmulti; 2662 } 2663 2664 /* TODO Check for Duplicate mcast addresses */ 2665 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2666 for (i = 0; i < nb_mc_addr; i++) { 2667 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2668 RTE_ETHER_ADDR_LEN); 2669 off += RTE_ETHER_ADDR_LEN; 2670 } 2671 2672 vnic->mc_addr_cnt = i; 2673 if (vnic->mc_addr_cnt) 2674 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2675 else 2676 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2677 2678 allmulti: 2679 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2680 } 2681 2682 static int 2683 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2684 { 2685 struct bnxt *bp = dev->data->dev_private; 2686 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2687 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2688 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2689 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2690 int ret; 2691 2692 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2693 fw_major, fw_minor, fw_updt, fw_rsvd); 2694 2695 ret += 1; /* add the size of '\0' */ 2696 if (fw_size < (uint32_t)ret) 2697 return ret; 2698 else 2699 return 0; 2700 } 2701 2702 static void 2703 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2704 struct rte_eth_rxq_info *qinfo) 2705 { 2706 struct bnxt *bp = dev->data->dev_private; 2707 struct bnxt_rx_queue *rxq; 2708 2709 if (is_bnxt_in_error(bp)) 2710 return; 2711 2712 rxq = dev->data->rx_queues[queue_id]; 2713 2714 qinfo->mp = rxq->mb_pool; 2715 qinfo->scattered_rx = dev->data->scattered_rx; 2716 qinfo->nb_desc = rxq->nb_rx_desc; 2717 2718 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2719 qinfo->conf.rx_drop_en = rxq->drop_en; 2720 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2721 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2722 } 2723 2724 static void 2725 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2726 struct rte_eth_txq_info *qinfo) 2727 { 2728 struct bnxt *bp = dev->data->dev_private; 2729 struct bnxt_tx_queue *txq; 2730 2731 if (is_bnxt_in_error(bp)) 2732 return; 2733 2734 txq = dev->data->tx_queues[queue_id]; 2735 2736 qinfo->nb_desc = txq->nb_tx_desc; 2737 2738 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2739 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2740 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2741 2742 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2743 qinfo->conf.tx_rs_thresh = 0; 2744 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2745 qinfo->conf.offloads = txq->offloads; 2746 } 2747 2748 static const struct { 2749 eth_rx_burst_t pkt_burst; 2750 const char *info; 2751 } bnxt_rx_burst_info[] = { 2752 {bnxt_recv_pkts, "Scalar"}, 2753 #if defined(RTE_ARCH_X86) 2754 {bnxt_recv_pkts_vec, "Vector SSE"}, 2755 #elif defined(RTE_ARCH_ARM64) 2756 {bnxt_recv_pkts_vec, "Vector Neon"}, 2757 #endif 2758 }; 2759 2760 static int 2761 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2762 struct rte_eth_burst_mode *mode) 2763 { 2764 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2765 size_t i; 2766 2767 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2768 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2769 snprintf(mode->info, sizeof(mode->info), "%s", 2770 bnxt_rx_burst_info[i].info); 2771 return 0; 2772 } 2773 } 2774 2775 return -EINVAL; 2776 } 2777 2778 static const struct { 2779 eth_tx_burst_t pkt_burst; 2780 const char *info; 2781 } bnxt_tx_burst_info[] = { 2782 {bnxt_xmit_pkts, "Scalar"}, 2783 #if defined(RTE_ARCH_X86) 2784 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2785 #elif defined(RTE_ARCH_ARM64) 2786 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2787 #endif 2788 }; 2789 2790 static int 2791 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2792 struct rte_eth_burst_mode *mode) 2793 { 2794 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2795 size_t i; 2796 2797 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2798 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2799 snprintf(mode->info, sizeof(mode->info), "%s", 2800 bnxt_tx_burst_info[i].info); 2801 return 0; 2802 } 2803 } 2804 2805 return -EINVAL; 2806 } 2807 2808 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2809 { 2810 struct bnxt *bp = eth_dev->data->dev_private; 2811 uint32_t new_pkt_size; 2812 uint32_t rc = 0; 2813 uint32_t i; 2814 2815 rc = is_bnxt_in_error(bp); 2816 if (rc) 2817 return rc; 2818 2819 /* Exit if receive queues are not configured yet */ 2820 if (!eth_dev->data->nb_rx_queues) 2821 return rc; 2822 2823 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2824 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2825 2826 /* 2827 * Disallow any MTU change that would require scattered receive support 2828 * if it is not already enabled. 2829 */ 2830 if (eth_dev->data->dev_started && 2831 !eth_dev->data->scattered_rx && 2832 (new_pkt_size > 2833 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2834 PMD_DRV_LOG(ERR, 2835 "MTU change would require scattered rx support. "); 2836 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2837 return -EINVAL; 2838 } 2839 2840 if (new_mtu > RTE_ETHER_MTU) { 2841 bp->flags |= BNXT_FLAG_JUMBO; 2842 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2843 DEV_RX_OFFLOAD_JUMBO_FRAME; 2844 } else { 2845 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2846 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2847 bp->flags &= ~BNXT_FLAG_JUMBO; 2848 } 2849 2850 /* Is there a change in mtu setting? */ 2851 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2852 return rc; 2853 2854 for (i = 0; i < bp->nr_vnics; i++) { 2855 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2856 uint16_t size = 0; 2857 2858 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2859 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2860 if (rc) 2861 break; 2862 2863 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2864 size -= RTE_PKTMBUF_HEADROOM; 2865 2866 if (size < new_mtu) { 2867 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2868 if (rc) 2869 return rc; 2870 } 2871 } 2872 2873 if (!rc) 2874 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2875 2876 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2877 2878 return rc; 2879 } 2880 2881 static int 2882 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2883 { 2884 struct bnxt *bp = dev->data->dev_private; 2885 uint16_t vlan = bp->vlan; 2886 int rc; 2887 2888 rc = is_bnxt_in_error(bp); 2889 if (rc) 2890 return rc; 2891 2892 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2893 PMD_DRV_LOG(ERR, 2894 "PVID cannot be modified for this function\n"); 2895 return -ENOTSUP; 2896 } 2897 bp->vlan = on ? pvid : 0; 2898 2899 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2900 if (rc) 2901 bp->vlan = vlan; 2902 return rc; 2903 } 2904 2905 static int 2906 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2907 { 2908 struct bnxt *bp = dev->data->dev_private; 2909 int rc; 2910 2911 rc = is_bnxt_in_error(bp); 2912 if (rc) 2913 return rc; 2914 2915 return bnxt_hwrm_port_led_cfg(bp, true); 2916 } 2917 2918 static int 2919 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2920 { 2921 struct bnxt *bp = dev->data->dev_private; 2922 int rc; 2923 2924 rc = is_bnxt_in_error(bp); 2925 if (rc) 2926 return rc; 2927 2928 return bnxt_hwrm_port_led_cfg(bp, false); 2929 } 2930 2931 static uint32_t 2932 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2933 { 2934 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2935 uint32_t desc = 0, raw_cons = 0, cons; 2936 struct bnxt_cp_ring_info *cpr; 2937 struct bnxt_rx_queue *rxq; 2938 struct rx_pkt_cmpl *rxcmp; 2939 int rc; 2940 2941 rc = is_bnxt_in_error(bp); 2942 if (rc) 2943 return rc; 2944 2945 rxq = dev->data->rx_queues[rx_queue_id]; 2946 cpr = rxq->cp_ring; 2947 raw_cons = cpr->cp_raw_cons; 2948 2949 while (1) { 2950 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2951 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2952 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2953 2954 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2955 break; 2956 } else { 2957 raw_cons++; 2958 desc++; 2959 } 2960 } 2961 2962 return desc; 2963 } 2964 2965 static int 2966 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2967 { 2968 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2969 struct bnxt_rx_ring_info *rxr; 2970 struct bnxt_cp_ring_info *cpr; 2971 struct rte_mbuf *rx_buf; 2972 struct rx_pkt_cmpl *rxcmp; 2973 uint32_t cons, cp_cons; 2974 int rc; 2975 2976 if (!rxq) 2977 return -EINVAL; 2978 2979 rc = is_bnxt_in_error(rxq->bp); 2980 if (rc) 2981 return rc; 2982 2983 cpr = rxq->cp_ring; 2984 rxr = rxq->rx_ring; 2985 2986 if (offset >= rxq->nb_rx_desc) 2987 return -EINVAL; 2988 2989 cons = RING_CMP(cpr->cp_ring_struct, offset); 2990 cp_cons = cpr->cp_raw_cons; 2991 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2992 2993 if (cons > cp_cons) { 2994 if (CMPL_VALID(rxcmp, cpr->valid)) 2995 return RTE_ETH_RX_DESC_DONE; 2996 } else { 2997 if (CMPL_VALID(rxcmp, !cpr->valid)) 2998 return RTE_ETH_RX_DESC_DONE; 2999 } 3000 rx_buf = rxr->rx_buf_ring[cons]; 3001 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) 3002 return RTE_ETH_RX_DESC_UNAVAIL; 3003 3004 3005 return RTE_ETH_RX_DESC_AVAIL; 3006 } 3007 3008 static int 3009 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3010 { 3011 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3012 struct bnxt_tx_ring_info *txr; 3013 struct bnxt_cp_ring_info *cpr; 3014 struct bnxt_sw_tx_bd *tx_buf; 3015 struct tx_pkt_cmpl *txcmp; 3016 uint32_t cons, cp_cons; 3017 int rc; 3018 3019 if (!txq) 3020 return -EINVAL; 3021 3022 rc = is_bnxt_in_error(txq->bp); 3023 if (rc) 3024 return rc; 3025 3026 cpr = txq->cp_ring; 3027 txr = txq->tx_ring; 3028 3029 if (offset >= txq->nb_tx_desc) 3030 return -EINVAL; 3031 3032 cons = RING_CMP(cpr->cp_ring_struct, offset); 3033 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3034 cp_cons = cpr->cp_raw_cons; 3035 3036 if (cons > cp_cons) { 3037 if (CMPL_VALID(txcmp, cpr->valid)) 3038 return RTE_ETH_TX_DESC_UNAVAIL; 3039 } else { 3040 if (CMPL_VALID(txcmp, !cpr->valid)) 3041 return RTE_ETH_TX_DESC_UNAVAIL; 3042 } 3043 tx_buf = &txr->tx_buf_ring[cons]; 3044 if (tx_buf->mbuf == NULL) 3045 return RTE_ETH_TX_DESC_DONE; 3046 3047 return RTE_ETH_TX_DESC_FULL; 3048 } 3049 3050 int 3051 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3052 enum rte_filter_type filter_type, 3053 enum rte_filter_op filter_op, void *arg) 3054 { 3055 struct bnxt *bp = dev->data->dev_private; 3056 int ret = 0; 3057 3058 if (!bp) 3059 return -EIO; 3060 3061 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3062 struct bnxt_representor *vfr = dev->data->dev_private; 3063 bp = vfr->parent_dev->data->dev_private; 3064 /* parent is deleted while children are still valid */ 3065 if (!bp) { 3066 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n", 3067 dev->data->port_id, 3068 filter_type, 3069 filter_op); 3070 return -EIO; 3071 } 3072 } 3073 3074 ret = is_bnxt_in_error(bp); 3075 if (ret) 3076 return ret; 3077 3078 switch (filter_type) { 3079 case RTE_ETH_FILTER_GENERIC: 3080 if (filter_op != RTE_ETH_FILTER_GET) 3081 return -EINVAL; 3082 3083 /* PMD supports thread-safe flow operations. rte_flow API 3084 * functions can avoid mutex for multi-thread safety. 3085 */ 3086 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3087 3088 if (BNXT_TRUFLOW_EN(bp)) 3089 *(const void **)arg = &bnxt_ulp_rte_flow_ops; 3090 else 3091 *(const void **)arg = &bnxt_flow_ops; 3092 break; 3093 default: 3094 PMD_DRV_LOG(ERR, 3095 "Filter type (%d) not supported", filter_type); 3096 ret = -EINVAL; 3097 break; 3098 } 3099 return ret; 3100 } 3101 3102 static const uint32_t * 3103 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3104 { 3105 static const uint32_t ptypes[] = { 3106 RTE_PTYPE_L2_ETHER_VLAN, 3107 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3108 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3109 RTE_PTYPE_L4_ICMP, 3110 RTE_PTYPE_L4_TCP, 3111 RTE_PTYPE_L4_UDP, 3112 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3113 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3114 RTE_PTYPE_INNER_L4_ICMP, 3115 RTE_PTYPE_INNER_L4_TCP, 3116 RTE_PTYPE_INNER_L4_UDP, 3117 RTE_PTYPE_UNKNOWN 3118 }; 3119 3120 if (!dev->rx_pkt_burst) 3121 return NULL; 3122 3123 return ptypes; 3124 } 3125 3126 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3127 int reg_win) 3128 { 3129 uint32_t reg_base = *reg_arr & 0xfffff000; 3130 uint32_t win_off; 3131 int i; 3132 3133 for (i = 0; i < count; i++) { 3134 if ((reg_arr[i] & 0xfffff000) != reg_base) 3135 return -ERANGE; 3136 } 3137 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3138 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3139 return 0; 3140 } 3141 3142 static int bnxt_map_ptp_regs(struct bnxt *bp) 3143 { 3144 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3145 uint32_t *reg_arr; 3146 int rc, i; 3147 3148 reg_arr = ptp->rx_regs; 3149 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3150 if (rc) 3151 return rc; 3152 3153 reg_arr = ptp->tx_regs; 3154 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3155 if (rc) 3156 return rc; 3157 3158 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3159 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3160 3161 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3162 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3163 3164 return 0; 3165 } 3166 3167 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3168 { 3169 rte_write32(0, (uint8_t *)bp->bar0 + 3170 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3171 rte_write32(0, (uint8_t *)bp->bar0 + 3172 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3173 } 3174 3175 static uint64_t bnxt_cc_read(struct bnxt *bp) 3176 { 3177 uint64_t ns; 3178 3179 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3180 BNXT_GRCPF_REG_SYNC_TIME)); 3181 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3182 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3183 return ns; 3184 } 3185 3186 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3187 { 3188 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3189 uint32_t fifo; 3190 3191 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3192 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3193 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3194 return -EAGAIN; 3195 3196 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3197 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3198 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3199 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3200 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3201 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3202 3203 return 0; 3204 } 3205 3206 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3207 { 3208 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3209 struct bnxt_pf_info *pf = bp->pf; 3210 uint16_t port_id; 3211 uint32_t fifo; 3212 3213 if (!ptp) 3214 return -ENODEV; 3215 3216 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3217 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3218 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3219 return -EAGAIN; 3220 3221 port_id = pf->port_id; 3222 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3223 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3224 3225 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3226 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3227 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3228 /* bnxt_clr_rx_ts(bp); TBD */ 3229 return -EBUSY; 3230 } 3231 3232 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3233 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3234 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3235 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3236 3237 return 0; 3238 } 3239 3240 static int 3241 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3242 { 3243 uint64_t ns; 3244 struct bnxt *bp = dev->data->dev_private; 3245 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3246 3247 if (!ptp) 3248 return 0; 3249 3250 ns = rte_timespec_to_ns(ts); 3251 /* Set the timecounters to a new value. */ 3252 ptp->tc.nsec = ns; 3253 3254 return 0; 3255 } 3256 3257 static int 3258 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3259 { 3260 struct bnxt *bp = dev->data->dev_private; 3261 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3262 uint64_t ns, systime_cycles = 0; 3263 int rc = 0; 3264 3265 if (!ptp) 3266 return 0; 3267 3268 if (BNXT_CHIP_P5(bp)) 3269 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3270 &systime_cycles); 3271 else 3272 systime_cycles = bnxt_cc_read(bp); 3273 3274 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3275 *ts = rte_ns_to_timespec(ns); 3276 3277 return rc; 3278 } 3279 static int 3280 bnxt_timesync_enable(struct rte_eth_dev *dev) 3281 { 3282 struct bnxt *bp = dev->data->dev_private; 3283 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3284 uint32_t shift = 0; 3285 int rc; 3286 3287 if (!ptp) 3288 return 0; 3289 3290 ptp->rx_filter = 1; 3291 ptp->tx_tstamp_en = 1; 3292 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3293 3294 rc = bnxt_hwrm_ptp_cfg(bp); 3295 if (rc) 3296 return rc; 3297 3298 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3299 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3300 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3301 3302 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3303 ptp->tc.cc_shift = shift; 3304 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3305 3306 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3307 ptp->rx_tstamp_tc.cc_shift = shift; 3308 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3309 3310 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3311 ptp->tx_tstamp_tc.cc_shift = shift; 3312 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3313 3314 if (!BNXT_CHIP_P5(bp)) 3315 bnxt_map_ptp_regs(bp); 3316 3317 return 0; 3318 } 3319 3320 static int 3321 bnxt_timesync_disable(struct rte_eth_dev *dev) 3322 { 3323 struct bnxt *bp = dev->data->dev_private; 3324 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3325 3326 if (!ptp) 3327 return 0; 3328 3329 ptp->rx_filter = 0; 3330 ptp->tx_tstamp_en = 0; 3331 ptp->rxctl = 0; 3332 3333 bnxt_hwrm_ptp_cfg(bp); 3334 3335 if (!BNXT_CHIP_P5(bp)) 3336 bnxt_unmap_ptp_regs(bp); 3337 3338 return 0; 3339 } 3340 3341 static int 3342 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3343 struct timespec *timestamp, 3344 uint32_t flags __rte_unused) 3345 { 3346 struct bnxt *bp = dev->data->dev_private; 3347 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3348 uint64_t rx_tstamp_cycles = 0; 3349 uint64_t ns; 3350 3351 if (!ptp) 3352 return 0; 3353 3354 if (BNXT_CHIP_P5(bp)) 3355 rx_tstamp_cycles = ptp->rx_timestamp; 3356 else 3357 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3358 3359 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3360 *timestamp = rte_ns_to_timespec(ns); 3361 return 0; 3362 } 3363 3364 static int 3365 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3366 struct timespec *timestamp) 3367 { 3368 struct bnxt *bp = dev->data->dev_private; 3369 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3370 uint64_t tx_tstamp_cycles = 0; 3371 uint64_t ns; 3372 int rc = 0; 3373 3374 if (!ptp) 3375 return 0; 3376 3377 if (BNXT_CHIP_P5(bp)) 3378 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3379 &tx_tstamp_cycles); 3380 else 3381 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3382 3383 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3384 *timestamp = rte_ns_to_timespec(ns); 3385 3386 return rc; 3387 } 3388 3389 static int 3390 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3391 { 3392 struct bnxt *bp = dev->data->dev_private; 3393 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3394 3395 if (!ptp) 3396 return 0; 3397 3398 ptp->tc.nsec += delta; 3399 3400 return 0; 3401 } 3402 3403 static int 3404 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3405 { 3406 struct bnxt *bp = dev->data->dev_private; 3407 int rc; 3408 uint32_t dir_entries; 3409 uint32_t entry_length; 3410 3411 rc = is_bnxt_in_error(bp); 3412 if (rc) 3413 return rc; 3414 3415 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3416 bp->pdev->addr.domain, bp->pdev->addr.bus, 3417 bp->pdev->addr.devid, bp->pdev->addr.function); 3418 3419 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3420 if (rc != 0) 3421 return rc; 3422 3423 return dir_entries * entry_length; 3424 } 3425 3426 static int 3427 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3428 struct rte_dev_eeprom_info *in_eeprom) 3429 { 3430 struct bnxt *bp = dev->data->dev_private; 3431 uint32_t index; 3432 uint32_t offset; 3433 int rc; 3434 3435 rc = is_bnxt_in_error(bp); 3436 if (rc) 3437 return rc; 3438 3439 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3440 bp->pdev->addr.domain, bp->pdev->addr.bus, 3441 bp->pdev->addr.devid, bp->pdev->addr.function, 3442 in_eeprom->offset, in_eeprom->length); 3443 3444 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3445 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3446 in_eeprom->data); 3447 3448 index = in_eeprom->offset >> 24; 3449 offset = in_eeprom->offset & 0xffffff; 3450 3451 if (index != 0) 3452 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3453 in_eeprom->length, in_eeprom->data); 3454 3455 return 0; 3456 } 3457 3458 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3459 { 3460 switch (dir_type) { 3461 case BNX_DIR_TYPE_CHIMP_PATCH: 3462 case BNX_DIR_TYPE_BOOTCODE: 3463 case BNX_DIR_TYPE_BOOTCODE_2: 3464 case BNX_DIR_TYPE_APE_FW: 3465 case BNX_DIR_TYPE_APE_PATCH: 3466 case BNX_DIR_TYPE_KONG_FW: 3467 case BNX_DIR_TYPE_KONG_PATCH: 3468 case BNX_DIR_TYPE_BONO_FW: 3469 case BNX_DIR_TYPE_BONO_PATCH: 3470 /* FALLTHROUGH */ 3471 return true; 3472 } 3473 3474 return false; 3475 } 3476 3477 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3478 { 3479 switch (dir_type) { 3480 case BNX_DIR_TYPE_AVS: 3481 case BNX_DIR_TYPE_EXP_ROM_MBA: 3482 case BNX_DIR_TYPE_PCIE: 3483 case BNX_DIR_TYPE_TSCF_UCODE: 3484 case BNX_DIR_TYPE_EXT_PHY: 3485 case BNX_DIR_TYPE_CCM: 3486 case BNX_DIR_TYPE_ISCSI_BOOT: 3487 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3488 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3489 /* FALLTHROUGH */ 3490 return true; 3491 } 3492 3493 return false; 3494 } 3495 3496 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3497 { 3498 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3499 bnxt_dir_type_is_other_exec_format(dir_type); 3500 } 3501 3502 static int 3503 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3504 struct rte_dev_eeprom_info *in_eeprom) 3505 { 3506 struct bnxt *bp = dev->data->dev_private; 3507 uint8_t index, dir_op; 3508 uint16_t type, ext, ordinal, attr; 3509 int rc; 3510 3511 rc = is_bnxt_in_error(bp); 3512 if (rc) 3513 return rc; 3514 3515 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3516 bp->pdev->addr.domain, bp->pdev->addr.bus, 3517 bp->pdev->addr.devid, bp->pdev->addr.function, 3518 in_eeprom->offset, in_eeprom->length); 3519 3520 if (!BNXT_PF(bp)) { 3521 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3522 return -EINVAL; 3523 } 3524 3525 type = in_eeprom->magic >> 16; 3526 3527 if (type == 0xffff) { /* special value for directory operations */ 3528 index = in_eeprom->magic & 0xff; 3529 dir_op = in_eeprom->magic >> 8; 3530 if (index == 0) 3531 return -EINVAL; 3532 switch (dir_op) { 3533 case 0x0e: /* erase */ 3534 if (in_eeprom->offset != ~in_eeprom->magic) 3535 return -EINVAL; 3536 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3537 default: 3538 return -EINVAL; 3539 } 3540 } 3541 3542 /* Create or re-write an NVM item: */ 3543 if (bnxt_dir_type_is_executable(type) == true) 3544 return -EOPNOTSUPP; 3545 ext = in_eeprom->magic & 0xffff; 3546 ordinal = in_eeprom->offset >> 16; 3547 attr = in_eeprom->offset & 0xffff; 3548 3549 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3550 in_eeprom->data, in_eeprom->length); 3551 } 3552 3553 /* 3554 * Initialization 3555 */ 3556 3557 static const struct eth_dev_ops bnxt_dev_ops = { 3558 .dev_infos_get = bnxt_dev_info_get_op, 3559 .dev_close = bnxt_dev_close_op, 3560 .dev_configure = bnxt_dev_configure_op, 3561 .dev_start = bnxt_dev_start_op, 3562 .dev_stop = bnxt_dev_stop_op, 3563 .dev_set_link_up = bnxt_dev_set_link_up_op, 3564 .dev_set_link_down = bnxt_dev_set_link_down_op, 3565 .stats_get = bnxt_stats_get_op, 3566 .stats_reset = bnxt_stats_reset_op, 3567 .rx_queue_setup = bnxt_rx_queue_setup_op, 3568 .rx_queue_release = bnxt_rx_queue_release_op, 3569 .tx_queue_setup = bnxt_tx_queue_setup_op, 3570 .tx_queue_release = bnxt_tx_queue_release_op, 3571 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3572 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3573 .reta_update = bnxt_reta_update_op, 3574 .reta_query = bnxt_reta_query_op, 3575 .rss_hash_update = bnxt_rss_hash_update_op, 3576 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3577 .link_update = bnxt_link_update_op, 3578 .promiscuous_enable = bnxt_promiscuous_enable_op, 3579 .promiscuous_disable = bnxt_promiscuous_disable_op, 3580 .allmulticast_enable = bnxt_allmulticast_enable_op, 3581 .allmulticast_disable = bnxt_allmulticast_disable_op, 3582 .mac_addr_add = bnxt_mac_addr_add_op, 3583 .mac_addr_remove = bnxt_mac_addr_remove_op, 3584 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3585 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3586 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3587 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3588 .vlan_filter_set = bnxt_vlan_filter_set_op, 3589 .vlan_offload_set = bnxt_vlan_offload_set_op, 3590 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3591 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3592 .mtu_set = bnxt_mtu_set_op, 3593 .mac_addr_set = bnxt_set_default_mac_addr_op, 3594 .xstats_get = bnxt_dev_xstats_get_op, 3595 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3596 .xstats_reset = bnxt_dev_xstats_reset_op, 3597 .fw_version_get = bnxt_fw_version_get, 3598 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3599 .rxq_info_get = bnxt_rxq_info_get_op, 3600 .txq_info_get = bnxt_txq_info_get_op, 3601 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 3602 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 3603 .dev_led_on = bnxt_dev_led_on_op, 3604 .dev_led_off = bnxt_dev_led_off_op, 3605 .rx_queue_start = bnxt_rx_queue_start, 3606 .rx_queue_stop = bnxt_rx_queue_stop, 3607 .tx_queue_start = bnxt_tx_queue_start, 3608 .tx_queue_stop = bnxt_tx_queue_stop, 3609 .filter_ctrl = bnxt_filter_ctrl_op, 3610 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3611 .get_eeprom_length = bnxt_get_eeprom_length_op, 3612 .get_eeprom = bnxt_get_eeprom_op, 3613 .set_eeprom = bnxt_set_eeprom_op, 3614 .timesync_enable = bnxt_timesync_enable, 3615 .timesync_disable = bnxt_timesync_disable, 3616 .timesync_read_time = bnxt_timesync_read_time, 3617 .timesync_write_time = bnxt_timesync_write_time, 3618 .timesync_adjust_time = bnxt_timesync_adjust_time, 3619 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3620 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3621 }; 3622 3623 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3624 { 3625 uint32_t offset; 3626 3627 /* Only pre-map the reset GRC registers using window 3 */ 3628 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3629 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3630 3631 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3632 3633 return offset; 3634 } 3635 3636 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3637 { 3638 struct bnxt_error_recovery_info *info = bp->recovery_info; 3639 uint32_t reg_base = 0xffffffff; 3640 int i; 3641 3642 /* Only pre-map the monitoring GRC registers using window 2 */ 3643 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3644 uint32_t reg = info->status_regs[i]; 3645 3646 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3647 continue; 3648 3649 if (reg_base == 0xffffffff) 3650 reg_base = reg & 0xfffff000; 3651 if ((reg & 0xfffff000) != reg_base) 3652 return -ERANGE; 3653 3654 /* Use mask 0xffc as the Lower 2 bits indicates 3655 * address space location 3656 */ 3657 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3658 (reg & 0xffc); 3659 } 3660 3661 if (reg_base == 0xffffffff) 3662 return 0; 3663 3664 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3665 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3666 3667 return 0; 3668 } 3669 3670 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3671 { 3672 struct bnxt_error_recovery_info *info = bp->recovery_info; 3673 uint32_t delay = info->delay_after_reset[index]; 3674 uint32_t val = info->reset_reg_val[index]; 3675 uint32_t reg = info->reset_reg[index]; 3676 uint32_t type, offset; 3677 3678 type = BNXT_FW_STATUS_REG_TYPE(reg); 3679 offset = BNXT_FW_STATUS_REG_OFF(reg); 3680 3681 switch (type) { 3682 case BNXT_FW_STATUS_REG_TYPE_CFG: 3683 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3684 break; 3685 case BNXT_FW_STATUS_REG_TYPE_GRC: 3686 offset = bnxt_map_reset_regs(bp, offset); 3687 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3688 break; 3689 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3690 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3691 break; 3692 } 3693 /* wait on a specific interval of time until core reset is complete */ 3694 if (delay) 3695 rte_delay_ms(delay); 3696 } 3697 3698 static void bnxt_dev_cleanup(struct bnxt *bp) 3699 { 3700 bp->eth_dev->data->dev_link.link_status = 0; 3701 bp->link_info->link_up = 0; 3702 if (bp->eth_dev->data->dev_started) 3703 bnxt_dev_stop(bp->eth_dev); 3704 3705 bnxt_uninit_resources(bp, true); 3706 } 3707 3708 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3709 { 3710 struct rte_eth_dev *dev = bp->eth_dev; 3711 struct rte_vlan_filter_conf *vfc; 3712 int vidx, vbit, rc; 3713 uint16_t vlan_id; 3714 3715 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3716 vfc = &dev->data->vlan_filter_conf; 3717 vidx = vlan_id / 64; 3718 vbit = vlan_id % 64; 3719 3720 /* Each bit corresponds to a VLAN id */ 3721 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3722 rc = bnxt_add_vlan_filter(bp, vlan_id); 3723 if (rc) 3724 return rc; 3725 } 3726 } 3727 3728 return 0; 3729 } 3730 3731 static int bnxt_restore_mac_filters(struct bnxt *bp) 3732 { 3733 struct rte_eth_dev *dev = bp->eth_dev; 3734 struct rte_eth_dev_info dev_info; 3735 struct rte_ether_addr *addr; 3736 uint64_t pool_mask; 3737 uint32_t pool = 0; 3738 uint16_t i; 3739 int rc; 3740 3741 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 3742 return 0; 3743 3744 rc = bnxt_dev_info_get_op(dev, &dev_info); 3745 if (rc) 3746 return rc; 3747 3748 /* replay MAC address configuration */ 3749 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3750 addr = &dev->data->mac_addrs[i]; 3751 3752 /* skip zero address */ 3753 if (rte_is_zero_ether_addr(addr)) 3754 continue; 3755 3756 pool = 0; 3757 pool_mask = dev->data->mac_pool_sel[i]; 3758 3759 do { 3760 if (pool_mask & 1ULL) { 3761 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3762 if (rc) 3763 return rc; 3764 } 3765 pool_mask >>= 1; 3766 pool++; 3767 } while (pool_mask); 3768 } 3769 3770 return 0; 3771 } 3772 3773 static int bnxt_restore_filters(struct bnxt *bp) 3774 { 3775 struct rte_eth_dev *dev = bp->eth_dev; 3776 int ret = 0; 3777 3778 if (dev->data->all_multicast) { 3779 ret = bnxt_allmulticast_enable_op(dev); 3780 if (ret) 3781 return ret; 3782 } 3783 if (dev->data->promiscuous) { 3784 ret = bnxt_promiscuous_enable_op(dev); 3785 if (ret) 3786 return ret; 3787 } 3788 3789 ret = bnxt_restore_mac_filters(bp); 3790 if (ret) 3791 return ret; 3792 3793 ret = bnxt_restore_vlan_filters(bp); 3794 /* TODO restore other filters as well */ 3795 return ret; 3796 } 3797 3798 static void bnxt_dev_recover(void *arg) 3799 { 3800 struct bnxt *bp = arg; 3801 int timeout = bp->fw_reset_max_msecs; 3802 int rc = 0; 3803 3804 pthread_mutex_lock(&bp->err_recovery_lock); 3805 /* Clear Error flag so that device re-init should happen */ 3806 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 3807 3808 do { 3809 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); 3810 if (rc == 0) 3811 break; 3812 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 3813 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 3814 } while (rc && timeout); 3815 3816 if (rc) { 3817 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 3818 goto err; 3819 } 3820 3821 rc = bnxt_init_resources(bp, true); 3822 if (rc) { 3823 PMD_DRV_LOG(ERR, 3824 "Failed to initialize resources after reset\n"); 3825 goto err; 3826 } 3827 /* clear reset flag as the device is initialized now */ 3828 bp->flags &= ~BNXT_FLAG_FW_RESET; 3829 3830 rc = bnxt_dev_start_op(bp->eth_dev); 3831 if (rc) { 3832 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 3833 goto err_start; 3834 } 3835 3836 rc = bnxt_restore_filters(bp); 3837 if (rc) 3838 goto err_start; 3839 3840 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 3841 pthread_mutex_unlock(&bp->err_recovery_lock); 3842 3843 return; 3844 err_start: 3845 bnxt_dev_stop(bp->eth_dev); 3846 err: 3847 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3848 bnxt_uninit_resources(bp, false); 3849 pthread_mutex_unlock(&bp->err_recovery_lock); 3850 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 3851 } 3852 3853 void bnxt_dev_reset_and_resume(void *arg) 3854 { 3855 struct bnxt *bp = arg; 3856 int rc; 3857 3858 bnxt_dev_cleanup(bp); 3859 3860 bnxt_wait_for_device_shutdown(bp); 3861 3862 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 3863 bnxt_dev_recover, (void *)bp); 3864 if (rc) 3865 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 3866 } 3867 3868 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 3869 { 3870 struct bnxt_error_recovery_info *info = bp->recovery_info; 3871 uint32_t reg = info->status_regs[index]; 3872 uint32_t type, offset, val = 0; 3873 3874 type = BNXT_FW_STATUS_REG_TYPE(reg); 3875 offset = BNXT_FW_STATUS_REG_OFF(reg); 3876 3877 switch (type) { 3878 case BNXT_FW_STATUS_REG_TYPE_CFG: 3879 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 3880 break; 3881 case BNXT_FW_STATUS_REG_TYPE_GRC: 3882 offset = info->mapped_status_regs[index]; 3883 /* FALLTHROUGH */ 3884 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3885 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3886 offset)); 3887 break; 3888 } 3889 3890 return val; 3891 } 3892 3893 static int bnxt_fw_reset_all(struct bnxt *bp) 3894 { 3895 struct bnxt_error_recovery_info *info = bp->recovery_info; 3896 uint32_t i; 3897 int rc = 0; 3898 3899 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3900 /* Reset through master function driver */ 3901 for (i = 0; i < info->reg_array_cnt; i++) 3902 bnxt_write_fw_reset_reg(bp, i); 3903 /* Wait for time specified by FW after triggering reset */ 3904 rte_delay_ms(info->master_func_wait_period_after_reset); 3905 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 3906 /* Reset with the help of Kong processor */ 3907 rc = bnxt_hwrm_fw_reset(bp); 3908 if (rc) 3909 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 3910 } 3911 3912 return rc; 3913 } 3914 3915 static void bnxt_fw_reset_cb(void *arg) 3916 { 3917 struct bnxt *bp = arg; 3918 struct bnxt_error_recovery_info *info = bp->recovery_info; 3919 int rc = 0; 3920 3921 /* Only Master function can do FW reset */ 3922 if (bnxt_is_master_func(bp) && 3923 bnxt_is_recovery_enabled(bp)) { 3924 rc = bnxt_fw_reset_all(bp); 3925 if (rc) { 3926 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 3927 return; 3928 } 3929 } 3930 3931 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 3932 * EXCEPTION_FATAL_ASYNC event to all the functions 3933 * (including MASTER FUNC). After receiving this Async, all the active 3934 * drivers should treat this case as FW initiated recovery 3935 */ 3936 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3937 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 3938 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 3939 3940 /* To recover from error */ 3941 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 3942 (void *)bp); 3943 } 3944 } 3945 3946 /* Driver should poll FW heartbeat, reset_counter with the frequency 3947 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 3948 * When the driver detects heartbeat stop or change in reset_counter, 3949 * it has to trigger a reset to recover from the error condition. 3950 * A “master PF” is the function who will have the privilege to 3951 * initiate the chimp reset. The master PF will be elected by the 3952 * firmware and will be notified through async message. 3953 */ 3954 static void bnxt_check_fw_health(void *arg) 3955 { 3956 struct bnxt *bp = arg; 3957 struct bnxt_error_recovery_info *info = bp->recovery_info; 3958 uint32_t val = 0, wait_msec; 3959 3960 if (!info || !bnxt_is_recovery_enabled(bp) || 3961 is_bnxt_in_error(bp)) 3962 return; 3963 3964 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 3965 if (val == info->last_heart_beat) 3966 goto reset; 3967 3968 info->last_heart_beat = val; 3969 3970 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 3971 if (val != info->last_reset_counter) 3972 goto reset; 3973 3974 info->last_reset_counter = val; 3975 3976 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 3977 bnxt_check_fw_health, (void *)bp); 3978 3979 return; 3980 reset: 3981 /* Stop DMA to/from device */ 3982 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3983 bp->flags |= BNXT_FLAG_FW_RESET; 3984 3985 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 3986 3987 if (bnxt_is_master_func(bp)) 3988 wait_msec = info->master_func_wait_period; 3989 else 3990 wait_msec = info->normal_func_wait_period; 3991 3992 rte_eal_alarm_set(US_PER_MS * wait_msec, 3993 bnxt_fw_reset_cb, (void *)bp); 3994 } 3995 3996 void bnxt_schedule_fw_health_check(struct bnxt *bp) 3997 { 3998 uint32_t polling_freq; 3999 4000 pthread_mutex_lock(&bp->health_check_lock); 4001 4002 if (!bnxt_is_recovery_enabled(bp)) 4003 goto done; 4004 4005 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4006 goto done; 4007 4008 polling_freq = bp->recovery_info->driver_polling_freq; 4009 4010 rte_eal_alarm_set(US_PER_MS * polling_freq, 4011 bnxt_check_fw_health, (void *)bp); 4012 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4013 4014 done: 4015 pthread_mutex_unlock(&bp->health_check_lock); 4016 } 4017 4018 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4019 { 4020 if (!bnxt_is_recovery_enabled(bp)) 4021 return; 4022 4023 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4024 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4025 } 4026 4027 static bool bnxt_vf_pciid(uint16_t device_id) 4028 { 4029 switch (device_id) { 4030 case BROADCOM_DEV_ID_57304_VF: 4031 case BROADCOM_DEV_ID_57406_VF: 4032 case BROADCOM_DEV_ID_5731X_VF: 4033 case BROADCOM_DEV_ID_5741X_VF: 4034 case BROADCOM_DEV_ID_57414_VF: 4035 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4036 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4037 case BROADCOM_DEV_ID_58802_VF: 4038 case BROADCOM_DEV_ID_57500_VF1: 4039 case BROADCOM_DEV_ID_57500_VF2: 4040 case BROADCOM_DEV_ID_58818_VF: 4041 /* FALLTHROUGH */ 4042 return true; 4043 default: 4044 return false; 4045 } 4046 } 4047 4048 /* Phase 5 device */ 4049 static bool bnxt_p5_device(uint16_t device_id) 4050 { 4051 switch (device_id) { 4052 case BROADCOM_DEV_ID_57508: 4053 case BROADCOM_DEV_ID_57504: 4054 case BROADCOM_DEV_ID_57502: 4055 case BROADCOM_DEV_ID_57508_MF1: 4056 case BROADCOM_DEV_ID_57504_MF1: 4057 case BROADCOM_DEV_ID_57502_MF1: 4058 case BROADCOM_DEV_ID_57508_MF2: 4059 case BROADCOM_DEV_ID_57504_MF2: 4060 case BROADCOM_DEV_ID_57502_MF2: 4061 case BROADCOM_DEV_ID_57500_VF1: 4062 case BROADCOM_DEV_ID_57500_VF2: 4063 case BROADCOM_DEV_ID_58812: 4064 case BROADCOM_DEV_ID_58814: 4065 case BROADCOM_DEV_ID_58818: 4066 case BROADCOM_DEV_ID_58818_VF: 4067 /* FALLTHROUGH */ 4068 return true; 4069 default: 4070 return false; 4071 } 4072 } 4073 4074 bool bnxt_stratus_device(struct bnxt *bp) 4075 { 4076 uint16_t device_id = bp->pdev->id.device_id; 4077 4078 switch (device_id) { 4079 case BROADCOM_DEV_ID_STRATUS_NIC: 4080 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4081 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4082 /* FALLTHROUGH */ 4083 return true; 4084 default: 4085 return false; 4086 } 4087 } 4088 4089 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4090 { 4091 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4092 struct bnxt *bp = eth_dev->data->dev_private; 4093 4094 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4095 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4096 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4097 if (!bp->bar0 || !bp->doorbell_base) { 4098 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4099 return -ENODEV; 4100 } 4101 4102 bp->eth_dev = eth_dev; 4103 bp->pdev = pci_dev; 4104 4105 return 0; 4106 } 4107 4108 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4109 struct bnxt_ctx_pg_info *ctx_pg, 4110 uint32_t mem_size, 4111 const char *suffix, 4112 uint16_t idx) 4113 { 4114 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4115 const struct rte_memzone *mz = NULL; 4116 char mz_name[RTE_MEMZONE_NAMESIZE]; 4117 rte_iova_t mz_phys_addr; 4118 uint64_t valid_bits = 0; 4119 uint32_t sz; 4120 int i; 4121 4122 if (!mem_size) 4123 return 0; 4124 4125 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4126 BNXT_PAGE_SIZE; 4127 rmem->page_size = BNXT_PAGE_SIZE; 4128 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4129 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4130 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4131 4132 valid_bits = PTU_PTE_VALID; 4133 4134 if (rmem->nr_pages > 1) { 4135 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4136 "bnxt_ctx_pg_tbl%s_%x_%d", 4137 suffix, idx, bp->eth_dev->data->port_id); 4138 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4139 mz = rte_memzone_lookup(mz_name); 4140 if (!mz) { 4141 mz = rte_memzone_reserve_aligned(mz_name, 4142 rmem->nr_pages * 8, 4143 SOCKET_ID_ANY, 4144 RTE_MEMZONE_2MB | 4145 RTE_MEMZONE_SIZE_HINT_ONLY | 4146 RTE_MEMZONE_IOVA_CONTIG, 4147 BNXT_PAGE_SIZE); 4148 if (mz == NULL) 4149 return -ENOMEM; 4150 } 4151 4152 memset(mz->addr, 0, mz->len); 4153 mz_phys_addr = mz->iova; 4154 4155 rmem->pg_tbl = mz->addr; 4156 rmem->pg_tbl_map = mz_phys_addr; 4157 rmem->pg_tbl_mz = mz; 4158 } 4159 4160 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4161 suffix, idx, bp->eth_dev->data->port_id); 4162 mz = rte_memzone_lookup(mz_name); 4163 if (!mz) { 4164 mz = rte_memzone_reserve_aligned(mz_name, 4165 mem_size, 4166 SOCKET_ID_ANY, 4167 RTE_MEMZONE_1GB | 4168 RTE_MEMZONE_SIZE_HINT_ONLY | 4169 RTE_MEMZONE_IOVA_CONTIG, 4170 BNXT_PAGE_SIZE); 4171 if (mz == NULL) 4172 return -ENOMEM; 4173 } 4174 4175 memset(mz->addr, 0, mz->len); 4176 mz_phys_addr = mz->iova; 4177 4178 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4179 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4180 rmem->dma_arr[i] = mz_phys_addr + sz; 4181 4182 if (rmem->nr_pages > 1) { 4183 if (i == rmem->nr_pages - 2 && 4184 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4185 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4186 else if (i == rmem->nr_pages - 1 && 4187 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4188 valid_bits |= PTU_PTE_LAST; 4189 4190 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4191 valid_bits); 4192 } 4193 } 4194 4195 rmem->mz = mz; 4196 if (rmem->vmem_size) 4197 rmem->vmem = (void **)mz->addr; 4198 rmem->dma_arr[0] = mz_phys_addr; 4199 return 0; 4200 } 4201 4202 static void bnxt_free_ctx_mem(struct bnxt *bp) 4203 { 4204 int i; 4205 4206 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4207 return; 4208 4209 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4210 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4211 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4212 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4213 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4214 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4215 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4216 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4217 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4218 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4219 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4220 4221 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4222 if (bp->ctx->tqm_mem[i]) 4223 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4224 } 4225 4226 rte_free(bp->ctx); 4227 bp->ctx = NULL; 4228 } 4229 4230 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4231 4232 #define min_t(type, x, y) ({ \ 4233 type __min1 = (x); \ 4234 type __min2 = (y); \ 4235 __min1 < __min2 ? __min1 : __min2; }) 4236 4237 #define max_t(type, x, y) ({ \ 4238 type __max1 = (x); \ 4239 type __max2 = (y); \ 4240 __max1 > __max2 ? __max1 : __max2; }) 4241 4242 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4243 4244 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4245 { 4246 struct bnxt_ctx_pg_info *ctx_pg; 4247 struct bnxt_ctx_mem_info *ctx; 4248 uint32_t mem_size, ena, entries; 4249 uint32_t entries_sp, min; 4250 int i, rc; 4251 4252 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4253 if (rc) { 4254 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4255 return rc; 4256 } 4257 ctx = bp->ctx; 4258 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4259 return 0; 4260 4261 ctx_pg = &ctx->qp_mem; 4262 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4263 if (ctx->qp_entry_size) { 4264 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4265 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4266 if (rc) 4267 return rc; 4268 } 4269 4270 ctx_pg = &ctx->srq_mem; 4271 ctx_pg->entries = ctx->srq_max_l2_entries; 4272 if (ctx->srq_entry_size) { 4273 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4274 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4275 if (rc) 4276 return rc; 4277 } 4278 4279 ctx_pg = &ctx->cq_mem; 4280 ctx_pg->entries = ctx->cq_max_l2_entries; 4281 if (ctx->cq_entry_size) { 4282 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4283 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4284 if (rc) 4285 return rc; 4286 } 4287 4288 ctx_pg = &ctx->vnic_mem; 4289 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4290 ctx->vnic_max_ring_table_entries; 4291 if (ctx->vnic_entry_size) { 4292 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4293 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4294 if (rc) 4295 return rc; 4296 } 4297 4298 ctx_pg = &ctx->stat_mem; 4299 ctx_pg->entries = ctx->stat_max_entries; 4300 if (ctx->stat_entry_size) { 4301 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4302 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4303 if (rc) 4304 return rc; 4305 } 4306 4307 min = ctx->tqm_min_entries_per_ring; 4308 4309 entries_sp = ctx->qp_max_l2_entries + 4310 ctx->vnic_max_vnic_entries + 4311 2 * ctx->qp_min_qp1_entries + min; 4312 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4313 4314 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4315 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4316 entries = clamp_t(uint32_t, entries, min, 4317 ctx->tqm_max_entries_per_ring); 4318 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4319 ctx_pg = ctx->tqm_mem[i]; 4320 ctx_pg->entries = i ? entries : entries_sp; 4321 if (ctx->tqm_entry_size) { 4322 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4323 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4324 if (rc) 4325 return rc; 4326 } 4327 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4328 } 4329 4330 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4331 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4332 if (rc) 4333 PMD_DRV_LOG(ERR, 4334 "Failed to configure context mem: rc = %d\n", rc); 4335 else 4336 ctx->flags |= BNXT_CTX_FLAG_INITED; 4337 4338 return rc; 4339 } 4340 4341 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4342 { 4343 struct rte_pci_device *pci_dev = bp->pdev; 4344 char mz_name[RTE_MEMZONE_NAMESIZE]; 4345 const struct rte_memzone *mz = NULL; 4346 uint32_t total_alloc_len; 4347 rte_iova_t mz_phys_addr; 4348 4349 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4350 return 0; 4351 4352 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4353 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4354 pci_dev->addr.bus, pci_dev->addr.devid, 4355 pci_dev->addr.function, "rx_port_stats"); 4356 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4357 mz = rte_memzone_lookup(mz_name); 4358 total_alloc_len = 4359 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4360 sizeof(struct rx_port_stats_ext) + 512); 4361 if (!mz) { 4362 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4363 SOCKET_ID_ANY, 4364 RTE_MEMZONE_2MB | 4365 RTE_MEMZONE_SIZE_HINT_ONLY | 4366 RTE_MEMZONE_IOVA_CONTIG); 4367 if (mz == NULL) 4368 return -ENOMEM; 4369 } 4370 memset(mz->addr, 0, mz->len); 4371 mz_phys_addr = mz->iova; 4372 4373 bp->rx_mem_zone = (const void *)mz; 4374 bp->hw_rx_port_stats = mz->addr; 4375 bp->hw_rx_port_stats_map = mz_phys_addr; 4376 4377 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4378 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4379 pci_dev->addr.bus, pci_dev->addr.devid, 4380 pci_dev->addr.function, "tx_port_stats"); 4381 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4382 mz = rte_memzone_lookup(mz_name); 4383 total_alloc_len = 4384 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4385 sizeof(struct tx_port_stats_ext) + 512); 4386 if (!mz) { 4387 mz = rte_memzone_reserve(mz_name, 4388 total_alloc_len, 4389 SOCKET_ID_ANY, 4390 RTE_MEMZONE_2MB | 4391 RTE_MEMZONE_SIZE_HINT_ONLY | 4392 RTE_MEMZONE_IOVA_CONTIG); 4393 if (mz == NULL) 4394 return -ENOMEM; 4395 } 4396 memset(mz->addr, 0, mz->len); 4397 mz_phys_addr = mz->iova; 4398 4399 bp->tx_mem_zone = (const void *)mz; 4400 bp->hw_tx_port_stats = mz->addr; 4401 bp->hw_tx_port_stats_map = mz_phys_addr; 4402 bp->flags |= BNXT_FLAG_PORT_STATS; 4403 4404 /* Display extended statistics if FW supports it */ 4405 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4406 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4407 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4408 return 0; 4409 4410 bp->hw_rx_port_stats_ext = (void *) 4411 ((uint8_t *)bp->hw_rx_port_stats + 4412 sizeof(struct rx_port_stats)); 4413 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4414 sizeof(struct rx_port_stats); 4415 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4416 4417 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4418 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4419 bp->hw_tx_port_stats_ext = (void *) 4420 ((uint8_t *)bp->hw_tx_port_stats + 4421 sizeof(struct tx_port_stats)); 4422 bp->hw_tx_port_stats_ext_map = 4423 bp->hw_tx_port_stats_map + 4424 sizeof(struct tx_port_stats); 4425 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4426 } 4427 4428 return 0; 4429 } 4430 4431 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4432 { 4433 struct bnxt *bp = eth_dev->data->dev_private; 4434 int rc = 0; 4435 4436 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4437 RTE_ETHER_ADDR_LEN * 4438 bp->max_l2_ctx, 4439 0); 4440 if (eth_dev->data->mac_addrs == NULL) { 4441 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4442 return -ENOMEM; 4443 } 4444 4445 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4446 if (BNXT_PF(bp)) 4447 return -EINVAL; 4448 4449 /* Generate a random MAC address, if none was assigned by PF */ 4450 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4451 bnxt_eth_hw_addr_random(bp->mac_addr); 4452 PMD_DRV_LOG(INFO, 4453 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4454 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4455 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4456 4457 rc = bnxt_hwrm_set_mac(bp); 4458 if (rc) 4459 return rc; 4460 } 4461 4462 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4463 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4464 4465 return rc; 4466 } 4467 4468 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4469 { 4470 int rc = 0; 4471 4472 /* MAC is already configured in FW */ 4473 if (BNXT_HAS_DFLT_MAC_SET(bp)) 4474 return 0; 4475 4476 /* Restore the old MAC configured */ 4477 rc = bnxt_hwrm_set_mac(bp); 4478 if (rc) 4479 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4480 4481 return rc; 4482 } 4483 4484 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4485 { 4486 if (!BNXT_PF(bp)) 4487 return; 4488 4489 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 4490 4491 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 4492 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 4493 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 4494 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 4495 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 4496 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 4497 } 4498 4499 uint16_t 4500 bnxt_get_svif(uint16_t port_id, bool func_svif, 4501 enum bnxt_ulp_intf_type type) 4502 { 4503 struct rte_eth_dev *eth_dev; 4504 struct bnxt *bp; 4505 4506 eth_dev = &rte_eth_devices[port_id]; 4507 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4508 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4509 if (!vfr) 4510 return 0; 4511 4512 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4513 return vfr->svif; 4514 4515 eth_dev = vfr->parent_dev; 4516 } 4517 4518 bp = eth_dev->data->dev_private; 4519 4520 return func_svif ? bp->func_svif : bp->port_svif; 4521 } 4522 4523 uint16_t 4524 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 4525 { 4526 struct rte_eth_dev *eth_dev; 4527 struct bnxt_vnic_info *vnic; 4528 struct bnxt *bp; 4529 4530 eth_dev = &rte_eth_devices[port]; 4531 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4532 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4533 if (!vfr) 4534 return 0; 4535 4536 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4537 return vfr->dflt_vnic_id; 4538 4539 eth_dev = vfr->parent_dev; 4540 } 4541 4542 bp = eth_dev->data->dev_private; 4543 4544 vnic = BNXT_GET_DEFAULT_VNIC(bp); 4545 4546 return vnic->fw_vnic_id; 4547 } 4548 4549 uint16_t 4550 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 4551 { 4552 struct rte_eth_dev *eth_dev; 4553 struct bnxt *bp; 4554 4555 eth_dev = &rte_eth_devices[port]; 4556 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4557 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4558 if (!vfr) 4559 return 0; 4560 4561 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4562 return vfr->fw_fid; 4563 4564 eth_dev = vfr->parent_dev; 4565 } 4566 4567 bp = eth_dev->data->dev_private; 4568 4569 return bp->fw_fid; 4570 } 4571 4572 enum bnxt_ulp_intf_type 4573 bnxt_get_interface_type(uint16_t port) 4574 { 4575 struct rte_eth_dev *eth_dev; 4576 struct bnxt *bp; 4577 4578 eth_dev = &rte_eth_devices[port]; 4579 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 4580 return BNXT_ULP_INTF_TYPE_VF_REP; 4581 4582 bp = eth_dev->data->dev_private; 4583 if (BNXT_PF(bp)) 4584 return BNXT_ULP_INTF_TYPE_PF; 4585 else if (BNXT_VF_IS_TRUSTED(bp)) 4586 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 4587 else if (BNXT_VF(bp)) 4588 return BNXT_ULP_INTF_TYPE_VF; 4589 4590 return BNXT_ULP_INTF_TYPE_INVALID; 4591 } 4592 4593 uint16_t 4594 bnxt_get_phy_port_id(uint16_t port_id) 4595 { 4596 struct bnxt_representor *vfr; 4597 struct rte_eth_dev *eth_dev; 4598 struct bnxt *bp; 4599 4600 eth_dev = &rte_eth_devices[port_id]; 4601 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4602 vfr = eth_dev->data->dev_private; 4603 if (!vfr) 4604 return 0; 4605 4606 eth_dev = vfr->parent_dev; 4607 } 4608 4609 bp = eth_dev->data->dev_private; 4610 4611 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 4612 } 4613 4614 uint16_t 4615 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 4616 { 4617 struct rte_eth_dev *eth_dev; 4618 struct bnxt *bp; 4619 4620 eth_dev = &rte_eth_devices[port_id]; 4621 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4622 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4623 if (!vfr) 4624 return 0; 4625 4626 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4627 return vfr->fw_fid - 1; 4628 4629 eth_dev = vfr->parent_dev; 4630 } 4631 4632 bp = eth_dev->data->dev_private; 4633 4634 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 4635 } 4636 4637 uint16_t 4638 bnxt_get_vport(uint16_t port_id) 4639 { 4640 return (1 << bnxt_get_phy_port_id(port_id)); 4641 } 4642 4643 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 4644 { 4645 struct bnxt_error_recovery_info *info = bp->recovery_info; 4646 4647 if (info) { 4648 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 4649 memset(info, 0, sizeof(*info)); 4650 return; 4651 } 4652 4653 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4654 return; 4655 4656 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4657 sizeof(*info), 0); 4658 if (!info) 4659 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4660 4661 bp->recovery_info = info; 4662 } 4663 4664 static void bnxt_check_fw_status(struct bnxt *bp) 4665 { 4666 uint32_t fw_status; 4667 4668 if (!(bp->recovery_info && 4669 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 4670 return; 4671 4672 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 4673 if (fw_status != BNXT_FW_STATUS_HEALTHY) 4674 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 4675 fw_status); 4676 } 4677 4678 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 4679 { 4680 struct bnxt_error_recovery_info *info = bp->recovery_info; 4681 uint32_t status_loc; 4682 uint32_t sig_ver; 4683 4684 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 4685 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4686 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4687 BNXT_GRCP_WINDOW_2_BASE + 4688 offsetof(struct hcomm_status, 4689 sig_ver))); 4690 /* If the signature is absent, then FW does not support this feature */ 4691 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 4692 HCOMM_STATUS_SIGNATURE_VAL) 4693 return 0; 4694 4695 if (!info) { 4696 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4697 sizeof(*info), 0); 4698 if (!info) 4699 return -ENOMEM; 4700 bp->recovery_info = info; 4701 } else { 4702 memset(info, 0, sizeof(*info)); 4703 } 4704 4705 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4706 BNXT_GRCP_WINDOW_2_BASE + 4707 offsetof(struct hcomm_status, 4708 fw_status_loc))); 4709 4710 /* Only pre-map the FW health status GRC register */ 4711 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 4712 return 0; 4713 4714 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 4715 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 4716 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 4717 4718 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 4719 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4720 4721 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 4722 4723 return 0; 4724 } 4725 4726 static int bnxt_init_fw(struct bnxt *bp) 4727 { 4728 uint16_t mtu; 4729 int rc = 0; 4730 4731 bp->fw_cap = 0; 4732 4733 rc = bnxt_map_hcomm_fw_status_reg(bp); 4734 if (rc) 4735 return rc; 4736 4737 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 4738 if (rc) { 4739 bnxt_check_fw_status(bp); 4740 return rc; 4741 } 4742 4743 rc = bnxt_hwrm_func_reset(bp); 4744 if (rc) 4745 return -EIO; 4746 4747 rc = bnxt_hwrm_vnic_qcaps(bp); 4748 if (rc) 4749 return rc; 4750 4751 rc = bnxt_hwrm_queue_qportcfg(bp); 4752 if (rc) 4753 return rc; 4754 4755 /* Get the MAX capabilities for this function. 4756 * This function also allocates context memory for TQM rings and 4757 * informs the firmware about this allocated backing store memory. 4758 */ 4759 rc = bnxt_hwrm_func_qcaps(bp); 4760 if (rc) 4761 return rc; 4762 4763 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 4764 if (rc) 4765 return rc; 4766 4767 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 4768 if (rc) 4769 return rc; 4770 4771 bnxt_hwrm_port_mac_qcfg(bp); 4772 4773 bnxt_hwrm_parent_pf_qcfg(bp); 4774 4775 bnxt_hwrm_port_phy_qcaps(bp); 4776 4777 bnxt_alloc_error_recovery_info(bp); 4778 /* Get the adapter error recovery support info */ 4779 rc = bnxt_hwrm_error_recovery_qcfg(bp); 4780 if (rc) 4781 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4782 4783 bnxt_hwrm_port_led_qcaps(bp); 4784 4785 return 0; 4786 } 4787 4788 static int 4789 bnxt_init_locks(struct bnxt *bp) 4790 { 4791 int err; 4792 4793 err = pthread_mutex_init(&bp->flow_lock, NULL); 4794 if (err) { 4795 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 4796 return err; 4797 } 4798 4799 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 4800 if (err) { 4801 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 4802 return err; 4803 } 4804 4805 err = pthread_mutex_init(&bp->health_check_lock, NULL); 4806 if (err) { 4807 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 4808 return err; 4809 } 4810 4811 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 4812 if (err) 4813 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 4814 4815 return err; 4816 } 4817 4818 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 4819 { 4820 int rc = 0; 4821 4822 rc = bnxt_init_fw(bp); 4823 if (rc) 4824 return rc; 4825 4826 if (!reconfig_dev) { 4827 rc = bnxt_setup_mac_addr(bp->eth_dev); 4828 if (rc) 4829 return rc; 4830 } else { 4831 rc = bnxt_restore_dflt_mac(bp); 4832 if (rc) 4833 return rc; 4834 } 4835 4836 bnxt_config_vf_req_fwd(bp); 4837 4838 rc = bnxt_hwrm_func_driver_register(bp); 4839 if (rc) { 4840 PMD_DRV_LOG(ERR, "Failed to register driver"); 4841 return -EBUSY; 4842 } 4843 4844 if (BNXT_PF(bp)) { 4845 if (bp->pdev->max_vfs) { 4846 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 4847 if (rc) { 4848 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 4849 return rc; 4850 } 4851 } else { 4852 rc = bnxt_hwrm_allocate_pf_only(bp); 4853 if (rc) { 4854 PMD_DRV_LOG(ERR, 4855 "Failed to allocate PF resources"); 4856 return rc; 4857 } 4858 } 4859 } 4860 4861 rc = bnxt_alloc_mem(bp, reconfig_dev); 4862 if (rc) 4863 return rc; 4864 4865 rc = bnxt_setup_int(bp); 4866 if (rc) 4867 return rc; 4868 4869 rc = bnxt_request_int(bp); 4870 if (rc) 4871 return rc; 4872 4873 rc = bnxt_init_ctx_mem(bp); 4874 if (rc) { 4875 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 4876 return rc; 4877 } 4878 4879 return 0; 4880 } 4881 4882 static int 4883 bnxt_parse_devarg_truflow(__rte_unused const char *key, 4884 const char *value, void *opaque_arg) 4885 { 4886 struct bnxt *bp = opaque_arg; 4887 unsigned long truflow; 4888 char *end = NULL; 4889 4890 if (!value || !opaque_arg) { 4891 PMD_DRV_LOG(ERR, 4892 "Invalid parameter passed to truflow devargs.\n"); 4893 return -EINVAL; 4894 } 4895 4896 truflow = strtoul(value, &end, 10); 4897 if (end == NULL || *end != '\0' || 4898 (truflow == ULONG_MAX && errno == ERANGE)) { 4899 PMD_DRV_LOG(ERR, 4900 "Invalid parameter passed to truflow devargs.\n"); 4901 return -EINVAL; 4902 } 4903 4904 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 4905 PMD_DRV_LOG(ERR, 4906 "Invalid value passed to truflow devargs.\n"); 4907 return -EINVAL; 4908 } 4909 4910 if (truflow) { 4911 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 4912 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 4913 } else { 4914 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; 4915 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); 4916 } 4917 4918 return 0; 4919 } 4920 4921 static int 4922 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 4923 const char *value, void *opaque_arg) 4924 { 4925 struct bnxt *bp = opaque_arg; 4926 unsigned long flow_xstat; 4927 char *end = NULL; 4928 4929 if (!value || !opaque_arg) { 4930 PMD_DRV_LOG(ERR, 4931 "Invalid parameter passed to flow_xstat devarg.\n"); 4932 return -EINVAL; 4933 } 4934 4935 flow_xstat = strtoul(value, &end, 10); 4936 if (end == NULL || *end != '\0' || 4937 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 4938 PMD_DRV_LOG(ERR, 4939 "Invalid parameter passed to flow_xstat devarg.\n"); 4940 return -EINVAL; 4941 } 4942 4943 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 4944 PMD_DRV_LOG(ERR, 4945 "Invalid value passed to flow_xstat devarg.\n"); 4946 return -EINVAL; 4947 } 4948 4949 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 4950 if (BNXT_FLOW_XSTATS_EN(bp)) 4951 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 4952 4953 return 0; 4954 } 4955 4956 static int 4957 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 4958 const char *value, void *opaque_arg) 4959 { 4960 struct bnxt *bp = opaque_arg; 4961 unsigned long max_num_kflows; 4962 char *end = NULL; 4963 4964 if (!value || !opaque_arg) { 4965 PMD_DRV_LOG(ERR, 4966 "Invalid parameter passed to max_num_kflows devarg.\n"); 4967 return -EINVAL; 4968 } 4969 4970 max_num_kflows = strtoul(value, &end, 10); 4971 if (end == NULL || *end != '\0' || 4972 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 4973 PMD_DRV_LOG(ERR, 4974 "Invalid parameter passed to max_num_kflows devarg.\n"); 4975 return -EINVAL; 4976 } 4977 4978 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 4979 PMD_DRV_LOG(ERR, 4980 "Invalid value passed to max_num_kflows devarg.\n"); 4981 return -EINVAL; 4982 } 4983 4984 bp->max_num_kflows = max_num_kflows; 4985 if (bp->max_num_kflows) 4986 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 4987 max_num_kflows); 4988 4989 return 0; 4990 } 4991 4992 static int 4993 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 4994 const char *value, void *opaque_arg) 4995 { 4996 struct bnxt_representor *vfr_bp = opaque_arg; 4997 unsigned long rep_is_pf; 4998 char *end = NULL; 4999 5000 if (!value || !opaque_arg) { 5001 PMD_DRV_LOG(ERR, 5002 "Invalid parameter passed to rep_is_pf devargs.\n"); 5003 return -EINVAL; 5004 } 5005 5006 rep_is_pf = strtoul(value, &end, 10); 5007 if (end == NULL || *end != '\0' || 5008 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5009 PMD_DRV_LOG(ERR, 5010 "Invalid parameter passed to rep_is_pf devargs.\n"); 5011 return -EINVAL; 5012 } 5013 5014 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5015 PMD_DRV_LOG(ERR, 5016 "Invalid value passed to rep_is_pf devargs.\n"); 5017 return -EINVAL; 5018 } 5019 5020 vfr_bp->flags |= rep_is_pf; 5021 if (BNXT_REP_PF(vfr_bp)) 5022 PMD_DRV_LOG(INFO, "PF representor\n"); 5023 else 5024 PMD_DRV_LOG(INFO, "VF representor\n"); 5025 5026 return 0; 5027 } 5028 5029 static int 5030 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5031 const char *value, void *opaque_arg) 5032 { 5033 struct bnxt_representor *vfr_bp = opaque_arg; 5034 unsigned long rep_based_pf; 5035 char *end = NULL; 5036 5037 if (!value || !opaque_arg) { 5038 PMD_DRV_LOG(ERR, 5039 "Invalid parameter passed to rep_based_pf " 5040 "devargs.\n"); 5041 return -EINVAL; 5042 } 5043 5044 rep_based_pf = strtoul(value, &end, 10); 5045 if (end == NULL || *end != '\0' || 5046 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5047 PMD_DRV_LOG(ERR, 5048 "Invalid parameter passed to rep_based_pf " 5049 "devargs.\n"); 5050 return -EINVAL; 5051 } 5052 5053 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5054 PMD_DRV_LOG(ERR, 5055 "Invalid value passed to rep_based_pf devargs.\n"); 5056 return -EINVAL; 5057 } 5058 5059 vfr_bp->rep_based_pf = rep_based_pf; 5060 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5061 5062 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5063 5064 return 0; 5065 } 5066 5067 static int 5068 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5069 const char *value, void *opaque_arg) 5070 { 5071 struct bnxt_representor *vfr_bp = opaque_arg; 5072 unsigned long rep_q_r2f; 5073 char *end = NULL; 5074 5075 if (!value || !opaque_arg) { 5076 PMD_DRV_LOG(ERR, 5077 "Invalid parameter passed to rep_q_r2f " 5078 "devargs.\n"); 5079 return -EINVAL; 5080 } 5081 5082 rep_q_r2f = strtoul(value, &end, 10); 5083 if (end == NULL || *end != '\0' || 5084 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5085 PMD_DRV_LOG(ERR, 5086 "Invalid parameter passed to rep_q_r2f " 5087 "devargs.\n"); 5088 return -EINVAL; 5089 } 5090 5091 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5092 PMD_DRV_LOG(ERR, 5093 "Invalid value passed to rep_q_r2f devargs.\n"); 5094 return -EINVAL; 5095 } 5096 5097 vfr_bp->rep_q_r2f = rep_q_r2f; 5098 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5099 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5100 5101 return 0; 5102 } 5103 5104 static int 5105 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5106 const char *value, void *opaque_arg) 5107 { 5108 struct bnxt_representor *vfr_bp = opaque_arg; 5109 unsigned long rep_q_f2r; 5110 char *end = NULL; 5111 5112 if (!value || !opaque_arg) { 5113 PMD_DRV_LOG(ERR, 5114 "Invalid parameter passed to rep_q_f2r " 5115 "devargs.\n"); 5116 return -EINVAL; 5117 } 5118 5119 rep_q_f2r = strtoul(value, &end, 10); 5120 if (end == NULL || *end != '\0' || 5121 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5122 PMD_DRV_LOG(ERR, 5123 "Invalid parameter passed to rep_q_f2r " 5124 "devargs.\n"); 5125 return -EINVAL; 5126 } 5127 5128 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5129 PMD_DRV_LOG(ERR, 5130 "Invalid value passed to rep_q_f2r devargs.\n"); 5131 return -EINVAL; 5132 } 5133 5134 vfr_bp->rep_q_f2r = rep_q_f2r; 5135 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5136 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5137 5138 return 0; 5139 } 5140 5141 static int 5142 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5143 const char *value, void *opaque_arg) 5144 { 5145 struct bnxt_representor *vfr_bp = opaque_arg; 5146 unsigned long rep_fc_r2f; 5147 char *end = NULL; 5148 5149 if (!value || !opaque_arg) { 5150 PMD_DRV_LOG(ERR, 5151 "Invalid parameter passed to rep_fc_r2f " 5152 "devargs.\n"); 5153 return -EINVAL; 5154 } 5155 5156 rep_fc_r2f = strtoul(value, &end, 10); 5157 if (end == NULL || *end != '\0' || 5158 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5159 PMD_DRV_LOG(ERR, 5160 "Invalid parameter passed to rep_fc_r2f " 5161 "devargs.\n"); 5162 return -EINVAL; 5163 } 5164 5165 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5166 PMD_DRV_LOG(ERR, 5167 "Invalid value passed to rep_fc_r2f devargs.\n"); 5168 return -EINVAL; 5169 } 5170 5171 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5172 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5173 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5174 5175 return 0; 5176 } 5177 5178 static int 5179 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5180 const char *value, void *opaque_arg) 5181 { 5182 struct bnxt_representor *vfr_bp = opaque_arg; 5183 unsigned long rep_fc_f2r; 5184 char *end = NULL; 5185 5186 if (!value || !opaque_arg) { 5187 PMD_DRV_LOG(ERR, 5188 "Invalid parameter passed to rep_fc_f2r " 5189 "devargs.\n"); 5190 return -EINVAL; 5191 } 5192 5193 rep_fc_f2r = strtoul(value, &end, 10); 5194 if (end == NULL || *end != '\0' || 5195 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5196 PMD_DRV_LOG(ERR, 5197 "Invalid parameter passed to rep_fc_f2r " 5198 "devargs.\n"); 5199 return -EINVAL; 5200 } 5201 5202 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5203 PMD_DRV_LOG(ERR, 5204 "Invalid value passed to rep_fc_f2r devargs.\n"); 5205 return -EINVAL; 5206 } 5207 5208 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5209 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5210 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5211 5212 return 0; 5213 } 5214 5215 static void 5216 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5217 { 5218 struct rte_kvargs *kvlist; 5219 5220 if (devargs == NULL) 5221 return; 5222 5223 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5224 if (kvlist == NULL) 5225 return; 5226 5227 /* 5228 * Handler for "truflow" devarg. 5229 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" 5230 */ 5231 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5232 bnxt_parse_devarg_truflow, bp); 5233 5234 /* 5235 * Handler for "flow_xstat" devarg. 5236 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5237 */ 5238 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5239 bnxt_parse_devarg_flow_xstat, bp); 5240 5241 /* 5242 * Handler for "max_num_kflows" devarg. 5243 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5244 */ 5245 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5246 bnxt_parse_devarg_max_num_kflows, bp); 5247 5248 rte_kvargs_free(kvlist); 5249 } 5250 5251 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5252 { 5253 int rc = 0; 5254 5255 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5256 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5257 if (rc) 5258 PMD_DRV_LOG(ERR, 5259 "Failed to alloc switch domain: %d\n", rc); 5260 else 5261 PMD_DRV_LOG(INFO, 5262 "Switch domain allocated %d\n", 5263 bp->switch_domain_id); 5264 } 5265 5266 return rc; 5267 } 5268 5269 static int 5270 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5271 { 5272 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5273 static int version_printed; 5274 struct bnxt *bp; 5275 int rc; 5276 5277 if (version_printed++ == 0) 5278 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5279 5280 eth_dev->dev_ops = &bnxt_dev_ops; 5281 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 5282 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 5283 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 5284 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5285 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5286 5287 /* 5288 * For secondary processes, we don't initialise any further 5289 * as primary has already done this work. 5290 */ 5291 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5292 return 0; 5293 5294 rte_eth_copy_pci_info(eth_dev, pci_dev); 5295 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 5296 5297 bp = eth_dev->data->dev_private; 5298 5299 /* Parse dev arguments passed on when starting the DPDK application. */ 5300 bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5301 5302 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5303 5304 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5305 bp->flags |= BNXT_FLAG_VF; 5306 5307 if (bnxt_p5_device(pci_dev->id.device_id)) 5308 bp->flags |= BNXT_FLAG_CHIP_P5; 5309 5310 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5311 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5312 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5313 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5314 bp->flags |= BNXT_FLAG_STINGRAY; 5315 5316 if (BNXT_TRUFLOW_EN(bp)) { 5317 /* extra mbuf field is required to store CFA code from mark */ 5318 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5319 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5320 .size = sizeof(bnxt_cfa_code_dynfield_t), 5321 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5322 }; 5323 bnxt_cfa_code_dynfield_offset = 5324 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5325 if (bnxt_cfa_code_dynfield_offset < 0) { 5326 PMD_DRV_LOG(ERR, 5327 "Failed to register mbuf field for TruFlow mark\n"); 5328 return -rte_errno; 5329 } 5330 } 5331 5332 rc = bnxt_init_board(eth_dev); 5333 if (rc) { 5334 PMD_DRV_LOG(ERR, 5335 "Failed to initialize board rc: %x\n", rc); 5336 return rc; 5337 } 5338 5339 rc = bnxt_alloc_pf_info(bp); 5340 if (rc) 5341 goto error_free; 5342 5343 rc = bnxt_alloc_link_info(bp); 5344 if (rc) 5345 goto error_free; 5346 5347 rc = bnxt_alloc_parent_info(bp); 5348 if (rc) 5349 goto error_free; 5350 5351 rc = bnxt_alloc_hwrm_resources(bp); 5352 if (rc) { 5353 PMD_DRV_LOG(ERR, 5354 "Failed to allocate hwrm resource rc: %x\n", rc); 5355 goto error_free; 5356 } 5357 rc = bnxt_alloc_leds_info(bp); 5358 if (rc) 5359 goto error_free; 5360 5361 rc = bnxt_alloc_cos_queues(bp); 5362 if (rc) 5363 goto error_free; 5364 5365 rc = bnxt_init_locks(bp); 5366 if (rc) 5367 goto error_free; 5368 5369 rc = bnxt_init_resources(bp, false); 5370 if (rc) 5371 goto error_free; 5372 5373 rc = bnxt_alloc_stats_mem(bp); 5374 if (rc) 5375 goto error_free; 5376 5377 bnxt_alloc_switch_domain(bp); 5378 5379 PMD_DRV_LOG(INFO, 5380 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5381 pci_dev->mem_resource[0].phys_addr, 5382 pci_dev->mem_resource[0].addr); 5383 5384 return 0; 5385 5386 error_free: 5387 bnxt_dev_uninit(eth_dev); 5388 return rc; 5389 } 5390 5391 5392 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5393 { 5394 if (!ctx) 5395 return; 5396 5397 if (ctx->va) 5398 rte_free(ctx->va); 5399 5400 ctx->va = NULL; 5401 ctx->dma = RTE_BAD_IOVA; 5402 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5403 } 5404 5405 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5406 { 5407 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5408 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5409 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5410 bp->flow_stat->max_fc, 5411 false); 5412 5413 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5414 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5415 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5416 bp->flow_stat->max_fc, 5417 false); 5418 5419 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5420 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5421 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5422 5423 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5424 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5425 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5426 5427 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5428 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5429 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5430 5431 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5432 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5433 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5434 } 5435 5436 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5437 { 5438 bnxt_unregister_fc_ctx_mem(bp); 5439 5440 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5441 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5442 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5443 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5444 } 5445 5446 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5447 { 5448 if (BNXT_FLOW_XSTATS_EN(bp)) 5449 bnxt_uninit_fc_ctx_mem(bp); 5450 } 5451 5452 static void 5453 bnxt_free_error_recovery_info(struct bnxt *bp) 5454 { 5455 rte_free(bp->recovery_info); 5456 bp->recovery_info = NULL; 5457 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5458 } 5459 5460 static int 5461 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5462 { 5463 int rc; 5464 5465 bnxt_free_int(bp); 5466 bnxt_free_mem(bp, reconfig_dev); 5467 5468 bnxt_hwrm_func_buf_unrgtr(bp); 5469 rte_free(bp->pf->vf_req_buf); 5470 5471 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5472 bp->flags &= ~BNXT_FLAG_REGISTERED; 5473 bnxt_free_ctx_mem(bp); 5474 if (!reconfig_dev) { 5475 bnxt_free_hwrm_resources(bp); 5476 bnxt_free_error_recovery_info(bp); 5477 } 5478 5479 bnxt_uninit_ctx_mem(bp); 5480 5481 bnxt_free_flow_stats_info(bp); 5482 bnxt_free_rep_info(bp); 5483 rte_free(bp->ptp_cfg); 5484 bp->ptp_cfg = NULL; 5485 return rc; 5486 } 5487 5488 static int 5489 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5490 { 5491 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5492 return -EPERM; 5493 5494 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5495 5496 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5497 bnxt_dev_close_op(eth_dev); 5498 5499 return 0; 5500 } 5501 5502 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5503 { 5504 struct bnxt *bp = eth_dev->data->dev_private; 5505 struct rte_eth_dev *vf_rep_eth_dev; 5506 int ret = 0, i; 5507 5508 if (!bp) 5509 return -EINVAL; 5510 5511 for (i = 0; i < bp->num_reps; i++) { 5512 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5513 if (!vf_rep_eth_dev) 5514 continue; 5515 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 5516 vf_rep_eth_dev->data->port_id); 5517 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 5518 } 5519 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 5520 eth_dev->data->port_id); 5521 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5522 5523 return ret; 5524 } 5525 5526 static void bnxt_free_rep_info(struct bnxt *bp) 5527 { 5528 rte_free(bp->rep_info); 5529 bp->rep_info = NULL; 5530 rte_free(bp->cfa_code_map); 5531 bp->cfa_code_map = NULL; 5532 } 5533 5534 static int bnxt_init_rep_info(struct bnxt *bp) 5535 { 5536 int i = 0, rc; 5537 5538 if (bp->rep_info) 5539 return 0; 5540 5541 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5542 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5543 0); 5544 if (!bp->rep_info) { 5545 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5546 return -ENOMEM; 5547 } 5548 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5549 sizeof(*bp->cfa_code_map) * 5550 BNXT_MAX_CFA_CODE, 0); 5551 if (!bp->cfa_code_map) { 5552 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5553 bnxt_free_rep_info(bp); 5554 return -ENOMEM; 5555 } 5556 5557 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5558 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5559 5560 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 5561 if (rc) { 5562 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 5563 bnxt_free_rep_info(bp); 5564 return rc; 5565 } 5566 5567 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 5568 if (rc) { 5569 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 5570 bnxt_free_rep_info(bp); 5571 return rc; 5572 } 5573 5574 return rc; 5575 } 5576 5577 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 5578 struct rte_eth_devargs *eth_da, 5579 struct rte_eth_dev *backing_eth_dev, 5580 const char *dev_args) 5581 { 5582 struct rte_eth_dev *vf_rep_eth_dev; 5583 char name[RTE_ETH_NAME_MAX_LEN]; 5584 struct bnxt *backing_bp; 5585 uint16_t num_rep; 5586 int i, ret = 0; 5587 struct rte_kvargs *kvlist = NULL; 5588 5589 num_rep = eth_da->nb_representor_ports; 5590 if (num_rep > BNXT_MAX_VF_REPS) { 5591 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 5592 num_rep, BNXT_MAX_VF_REPS); 5593 return -EINVAL; 5594 } 5595 5596 if (num_rep >= RTE_MAX_ETHPORTS) { 5597 PMD_DRV_LOG(ERR, 5598 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 5599 num_rep, RTE_MAX_ETHPORTS); 5600 return -EINVAL; 5601 } 5602 5603 backing_bp = backing_eth_dev->data->dev_private; 5604 5605 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 5606 PMD_DRV_LOG(ERR, 5607 "Not a PF or trusted VF. No Representor support\n"); 5608 /* Returning an error is not an option. 5609 * Applications are not handling this correctly 5610 */ 5611 return 0; 5612 } 5613 5614 if (bnxt_init_rep_info(backing_bp)) 5615 return 0; 5616 5617 for (i = 0; i < num_rep; i++) { 5618 struct bnxt_representor representor = { 5619 .vf_id = eth_da->representor_ports[i], 5620 .switch_domain_id = backing_bp->switch_domain_id, 5621 .parent_dev = backing_eth_dev 5622 }; 5623 5624 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 5625 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 5626 representor.vf_id, BNXT_MAX_VF_REPS); 5627 continue; 5628 } 5629 5630 /* representor port net_bdf_port */ 5631 snprintf(name, sizeof(name), "net_%s_representor_%d", 5632 pci_dev->device.name, eth_da->representor_ports[i]); 5633 5634 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 5635 if (kvlist) { 5636 /* 5637 * Handler for "rep_is_pf" devarg. 5638 * Invoked as for ex: "-a 000:00:0d.0, 5639 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5640 */ 5641 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 5642 bnxt_parse_devarg_rep_is_pf, 5643 (void *)&representor); 5644 if (ret) { 5645 ret = -EINVAL; 5646 goto err; 5647 } 5648 /* 5649 * Handler for "rep_based_pf" devarg. 5650 * Invoked as for ex: "-a 000:00:0d.0, 5651 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5652 */ 5653 ret = rte_kvargs_process(kvlist, 5654 BNXT_DEVARG_REP_BASED_PF, 5655 bnxt_parse_devarg_rep_based_pf, 5656 (void *)&representor); 5657 if (ret) { 5658 ret = -EINVAL; 5659 goto err; 5660 } 5661 /* 5662 * Handler for "rep_based_pf" devarg. 5663 * Invoked as for ex: "-a 000:00:0d.0, 5664 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5665 */ 5666 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 5667 bnxt_parse_devarg_rep_q_r2f, 5668 (void *)&representor); 5669 if (ret) { 5670 ret = -EINVAL; 5671 goto err; 5672 } 5673 /* 5674 * Handler for "rep_based_pf" devarg. 5675 * Invoked as for ex: "-a 000:00:0d.0, 5676 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5677 */ 5678 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 5679 bnxt_parse_devarg_rep_q_f2r, 5680 (void *)&representor); 5681 if (ret) { 5682 ret = -EINVAL; 5683 goto err; 5684 } 5685 /* 5686 * Handler for "rep_based_pf" devarg. 5687 * Invoked as for ex: "-a 000:00:0d.0, 5688 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5689 */ 5690 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 5691 bnxt_parse_devarg_rep_fc_r2f, 5692 (void *)&representor); 5693 if (ret) { 5694 ret = -EINVAL; 5695 goto err; 5696 } 5697 /* 5698 * Handler for "rep_based_pf" devarg. 5699 * Invoked as for ex: "-a 000:00:0d.0, 5700 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5701 */ 5702 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 5703 bnxt_parse_devarg_rep_fc_f2r, 5704 (void *)&representor); 5705 if (ret) { 5706 ret = -EINVAL; 5707 goto err; 5708 } 5709 } 5710 5711 ret = rte_eth_dev_create(&pci_dev->device, name, 5712 sizeof(struct bnxt_representor), 5713 NULL, NULL, 5714 bnxt_representor_init, 5715 &representor); 5716 if (ret) { 5717 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 5718 "representor %s.", name); 5719 goto err; 5720 } 5721 5722 vf_rep_eth_dev = rte_eth_dev_allocated(name); 5723 if (!vf_rep_eth_dev) { 5724 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 5725 " for VF-Rep: %s.", name); 5726 ret = -ENODEV; 5727 goto err; 5728 } 5729 5730 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 5731 backing_eth_dev->data->port_id); 5732 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 5733 vf_rep_eth_dev; 5734 backing_bp->num_reps++; 5735 5736 } 5737 5738 rte_kvargs_free(kvlist); 5739 return 0; 5740 5741 err: 5742 /* If num_rep > 1, then rollback already created 5743 * ports, since we'll be failing the probe anyway 5744 */ 5745 if (num_rep > 1) 5746 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 5747 rte_errno = -ret; 5748 rte_kvargs_free(kvlist); 5749 5750 return ret; 5751 } 5752 5753 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5754 struct rte_pci_device *pci_dev) 5755 { 5756 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 5757 struct rte_eth_dev *backing_eth_dev; 5758 uint16_t num_rep; 5759 int ret = 0; 5760 5761 if (pci_dev->device.devargs) { 5762 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 5763 ð_da); 5764 if (ret) 5765 return ret; 5766 } 5767 5768 num_rep = eth_da.nb_representor_ports; 5769 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 5770 num_rep); 5771 5772 /* We could come here after first level of probe is already invoked 5773 * as part of an application bringup(OVS-DPDK vswitchd), so first check 5774 * for already allocated eth_dev for the backing device (PF/Trusted VF) 5775 */ 5776 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 5777 if (backing_eth_dev == NULL) { 5778 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 5779 sizeof(struct bnxt), 5780 eth_dev_pci_specific_init, pci_dev, 5781 bnxt_dev_init, NULL); 5782 5783 if (ret || !num_rep) 5784 return ret; 5785 5786 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 5787 } 5788 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 5789 backing_eth_dev->data->port_id); 5790 5791 if (!num_rep) 5792 return ret; 5793 5794 /* probe representor ports now */ 5795 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 5796 pci_dev->device.devargs->args); 5797 5798 return ret; 5799 } 5800 5801 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 5802 { 5803 struct rte_eth_dev *eth_dev; 5804 5805 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 5806 if (!eth_dev) 5807 return 0; /* Invoked typically only by OVS-DPDK, by the 5808 * time it comes here the eth_dev is already 5809 * deleted by rte_eth_dev_close(), so returning 5810 * +ve value will at least help in proper cleanup 5811 */ 5812 5813 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 5814 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 5815 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 5816 return rte_eth_dev_destroy(eth_dev, 5817 bnxt_representor_uninit); 5818 else 5819 return rte_eth_dev_destroy(eth_dev, 5820 bnxt_dev_uninit); 5821 } else { 5822 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 5823 } 5824 } 5825 5826 static struct rte_pci_driver bnxt_rte_pmd = { 5827 .id_table = bnxt_pci_id_map, 5828 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 5829 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 5830 * and OVS-DPDK 5831 */ 5832 .probe = bnxt_pci_probe, 5833 .remove = bnxt_pci_remove, 5834 }; 5835 5836 static bool 5837 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 5838 { 5839 if (strcmp(dev->device->driver->name, drv->driver.name)) 5840 return false; 5841 5842 return true; 5843 } 5844 5845 bool is_bnxt_supported(struct rte_eth_dev *dev) 5846 { 5847 return is_device_supported(dev, &bnxt_rte_pmd); 5848 } 5849 5850 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 5851 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 5852 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 5853 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 5854