1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <rte_ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57304_VF 0x16cb 37 #define BROADCOM_DEV_ID_57417_MF 0x16cc 38 #define BROADCOM_DEV_ID_NS2 0x16cd 39 #define BROADCOM_DEV_ID_57406_VF 0x16d3 40 #define BROADCOM_DEV_ID_57412 0x16d6 41 #define BROADCOM_DEV_ID_57414 0x16d7 42 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 43 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 44 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 45 #define BROADCOM_DEV_ID_57412_MF 0x16de 46 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 47 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 48 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 49 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 50 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 51 #define BROADCOM_DEV_ID_57407_MF 0x16ea 52 #define BROADCOM_DEV_ID_57414_MF 0x16ec 53 #define BROADCOM_DEV_ID_57416_MF 0x16ee 54 #define BROADCOM_DEV_ID_57508 0x1750 55 #define BROADCOM_DEV_ID_57504 0x1751 56 #define BROADCOM_DEV_ID_57502 0x1752 57 #define BROADCOM_DEV_ID_57508_MF1 0x1800 58 #define BROADCOM_DEV_ID_57504_MF1 0x1801 59 #define BROADCOM_DEV_ID_57502_MF1 0x1802 60 #define BROADCOM_DEV_ID_57508_MF2 0x1803 61 #define BROADCOM_DEV_ID_57504_MF2 0x1804 62 #define BROADCOM_DEV_ID_57502_MF2 0x1805 63 #define BROADCOM_DEV_ID_57500_VF1 0x1806 64 #define BROADCOM_DEV_ID_57500_VF2 0x1807 65 #define BROADCOM_DEV_ID_58802 0xd802 66 #define BROADCOM_DEV_ID_58804 0xd804 67 #define BROADCOM_DEV_ID_58808 0x16f0 68 #define BROADCOM_DEV_ID_58802_VF 0xd800 69 70 #define BROADCOM_DEV_957508_N2100 0x5208 71 #define IS_BNXT_DEV_957508_N2100(bp) \ 72 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) 73 74 #define BNXT_MAX_MTU 9574 75 #define VLAN_TAG_SIZE 4 76 #define BNXT_NUM_VLANS 2 77 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 78 RTE_ETHER_CRC_LEN +\ 79 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 80 /* FW adds extra 4 bytes for FCS */ 81 #define BNXT_VNIC_MRU(mtu)\ 82 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 83 #define BNXT_VF_RSV_NUM_RSS_CTX 1 84 #define BNXT_VF_RSV_NUM_L2_CTX 4 85 /* TODO: For now, do not support VMDq/RFS on VFs. */ 86 #define BNXT_VF_RSV_NUM_VNIC 1 87 #define BNXT_MAX_LED 4 88 #define BNXT_MIN_RING_DESC 16 89 #define BNXT_MAX_TX_RING_DESC 4096 90 #define BNXT_MAX_RX_RING_DESC 8192 91 #define BNXT_DB_SIZE 0x80 92 93 #define TPA_MAX_AGGS 64 94 #define TPA_MAX_AGGS_TH 1024 95 96 #define TPA_MAX_NUM_SEGS 32 97 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 98 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 99 100 #define BNXT_TPA_MAX_AGGS(bp) \ 101 (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \ 102 TPA_MAX_AGGS) 103 104 #define BNXT_TPA_MAX_SEGS(bp) \ 105 (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \ 106 TPA_MAX_SEGS) 107 108 /* 109 * Define the number of async completion rings to be used. Set to zero for 110 * configurations in which the maximum number of packet completion rings 111 * for packet completions is desired or when async completion handling 112 * cannot be interrupt-driven. 113 */ 114 #ifdef RTE_EXEC_ENV_FREEBSD 115 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 116 #define BNXT_NUM_ASYNC_CPR(bp) 0U 117 #else 118 #define BNXT_NUM_ASYNC_CPR(bp) 1U 119 #endif 120 121 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 122 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 123 124 /* Chimp Communication Channel */ 125 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 126 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 127 /* Kong Communication Channel */ 128 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 129 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 130 131 #define BNXT_INT_LAT_TMR_MIN 75 132 #define BNXT_INT_LAT_TMR_MAX 150 133 #define BNXT_NUM_CMPL_AGGR_INT 36 134 #define BNXT_CMPL_AGGR_DMA_TMR 37 135 #define BNXT_NUM_CMPL_DMA_AGGR 36 136 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 137 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 138 139 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 140 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 141 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 142 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 143 #define BNXT_DEFAULT_VNIC_ALLOC \ 144 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 145 #define BNXT_DEFAULT_VNIC_FREE \ 146 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 147 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 148 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 149 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 150 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 151 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 152 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 153 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 154 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 155 156 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ 157 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) 158 159 struct bnxt_led_info { 160 uint8_t num_leds; 161 uint8_t led_id; 162 uint8_t led_type; 163 uint8_t led_group_id; 164 uint8_t unused; 165 uint16_t led_state_caps; 166 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 167 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 168 169 uint16_t led_color_caps; 170 }; 171 172 struct bnxt_led_cfg { 173 uint8_t led_id; 174 uint8_t led_state; 175 uint8_t led_color; 176 uint8_t unused; 177 uint16_t led_blink_on; 178 uint16_t led_blink_off; 179 uint8_t led_group_id; 180 uint8_t rsvd; 181 }; 182 183 #define BNXT_LED_DFLT_ENA \ 184 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 185 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 186 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 187 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 188 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 189 190 #define BNXT_LED_DFLT_ENA_SHIFT 6 191 192 #define BNXT_LED_DFLT_ENABLES(x) \ 193 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 194 195 struct bnxt_vlan_table_entry { 196 uint16_t tpid; 197 uint16_t vid; 198 } __rte_packed; 199 200 struct bnxt_vlan_antispoof_table_entry { 201 uint16_t tpid; 202 uint16_t vid; 203 uint16_t mask; 204 } __rte_packed; 205 206 struct bnxt_child_vf_info { 207 void *req_buf; 208 struct bnxt_vlan_table_entry *vlan_table; 209 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 210 STAILQ_HEAD(, bnxt_filter_info) filter; 211 uint32_t func_cfg_flags; 212 uint32_t l2_rx_mask; 213 uint16_t fid; 214 uint16_t max_tx_rate; 215 uint16_t dflt_vlan; 216 uint16_t vlan_count; 217 uint8_t mac_spoof_en; 218 uint8_t vlan_spoof_en; 219 bool random_mac; 220 bool persist_stats; 221 }; 222 223 struct bnxt_parent_info { 224 #define BNXT_PF_FID_INVALID 0xFFFF 225 uint16_t fid; 226 uint16_t vnic; 227 uint16_t port_id; 228 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 229 }; 230 231 struct bnxt_pf_info { 232 #define BNXT_FIRST_PF_FID 1 233 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 234 #define BNXT_MAX_VF_REPS 64 235 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 236 #define BNXT_FIRST_VF_FID 128 237 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 238 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 239 BNXT_PF_RINGS_USED(bp)) 240 uint16_t port_id; 241 uint16_t first_vf_id; 242 uint16_t active_vfs; 243 uint16_t max_vfs; 244 uint16_t total_vfs; /* Total VFs possible. 245 * Not necessarily enabled. 246 */ 247 uint32_t func_cfg_flags; 248 void *vf_req_buf; 249 rte_iova_t vf_req_buf_dma_addr; 250 uint32_t vf_req_fwd[8]; 251 uint16_t total_vnics; 252 struct bnxt_child_vf_info *vf_info; 253 #define BNXT_EVB_MODE_NONE 0 254 #define BNXT_EVB_MODE_VEB 1 255 #define BNXT_EVB_MODE_VEPA 2 256 uint8_t evb_mode; 257 }; 258 259 /* Max wait time for link up is 10s and link down is 500ms */ 260 #define BNXT_MAX_LINK_WAIT_CNT 200 261 #define BNXT_MIN_LINK_WAIT_CNT 10 262 #define BNXT_LINK_WAIT_INTERVAL 50 263 struct bnxt_link_info { 264 uint32_t phy_flags; 265 uint8_t mac_type; 266 uint8_t phy_link_status; 267 uint8_t loop_back; 268 uint8_t link_up; 269 uint8_t duplex; 270 uint8_t pause; 271 uint8_t force_pause; 272 uint8_t auto_pause; 273 uint8_t auto_mode; 274 #define PHY_VER_LEN 3 275 uint8_t phy_ver[PHY_VER_LEN]; 276 uint16_t link_speed; 277 uint16_t support_speeds; 278 uint16_t auto_link_speed; 279 uint16_t force_link_speed; 280 uint16_t auto_link_speed_mask; 281 uint32_t preemphasis; 282 uint8_t phy_type; 283 uint8_t media_type; 284 uint16_t support_auto_speeds; 285 uint8_t link_signal_mode; 286 uint16_t force_pam4_link_speed; 287 uint16_t support_pam4_speeds; 288 uint16_t auto_pam4_link_speeds; 289 uint16_t support_pam4_auto_speeds; 290 uint8_t req_signal_mode; 291 }; 292 293 #define BNXT_COS_QUEUE_COUNT 8 294 struct bnxt_cos_queue_info { 295 uint8_t id; 296 uint8_t profile; 297 }; 298 299 struct rte_flow { 300 STAILQ_ENTRY(rte_flow) next; 301 struct bnxt_filter_info *filter; 302 struct bnxt_vnic_info *vnic; 303 }; 304 305 #define BNXT_PTP_FLAGS_PATH_TX 0x0 306 #define BNXT_PTP_FLAGS_PATH_RX 0x1 307 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 308 309 struct bnxt_ptp_cfg { 310 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 311 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 312 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 313 struct rte_timecounter tc; 314 struct rte_timecounter tx_tstamp_tc; 315 struct rte_timecounter rx_tstamp_tc; 316 struct bnxt *bp; 317 #define BNXT_MAX_TX_TS 1 318 uint16_t rxctl; 319 #define BNXT_PTP_MSG_SYNC BIT(0) 320 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 321 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 322 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 323 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 324 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 325 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 326 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 327 #define BNXT_PTP_MSG_SIGNALING BIT(12) 328 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 329 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 330 BNXT_PTP_MSG_DELAY_REQ | \ 331 BNXT_PTP_MSG_PDELAY_REQ | \ 332 BNXT_PTP_MSG_PDELAY_RESP) 333 uint8_t tx_tstamp_en:1; 334 int rx_filter; 335 336 #define BNXT_PTP_RX_TS_L 0 337 #define BNXT_PTP_RX_TS_H 1 338 #define BNXT_PTP_RX_SEQ 2 339 #define BNXT_PTP_RX_FIFO 3 340 #define BNXT_PTP_RX_FIFO_PENDING 0x1 341 #define BNXT_PTP_RX_FIFO_ADV 4 342 #define BNXT_PTP_RX_REGS 5 343 344 #define BNXT_PTP_TX_TS_L 0 345 #define BNXT_PTP_TX_TS_H 1 346 #define BNXT_PTP_TX_SEQ 2 347 #define BNXT_PTP_TX_FIFO 3 348 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 349 #define BNXT_PTP_TX_REGS 4 350 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 351 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 352 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 353 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 354 355 /* On Thor, the Rx timestamp is present in the Rx completion record */ 356 uint64_t rx_timestamp; 357 }; 358 359 struct bnxt_coal { 360 uint16_t num_cmpl_aggr_int; 361 uint16_t num_cmpl_dma_aggr; 362 uint16_t num_cmpl_dma_aggr_during_int; 363 uint16_t int_lat_tmr_max; 364 uint16_t int_lat_tmr_min; 365 uint16_t cmpl_aggr_dma_tmr; 366 uint16_t cmpl_aggr_dma_tmr_during_int; 367 }; 368 369 /* 64-bit doorbell */ 370 #define DBR_XID_SFT 32 371 #define DBR_PATH_L2 (0x1ULL << 56) 372 #define DBR_TYPE_SQ (0x0ULL << 60) 373 #define DBR_TYPE_SRQ (0x2ULL << 60) 374 #define DBR_TYPE_CQ (0x4ULL << 60) 375 #define DBR_TYPE_NQ (0xaULL << 60) 376 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 377 378 #define BNXT_RSS_TBL_SIZE_P5 512U 379 #define BNXT_RSS_ENTRIES_PER_CTX_P5 64 380 #define BNXT_MAX_RSS_CTXTS_P5 \ 381 (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5) 382 383 #define BNXT_MAX_TC 8 384 #define BNXT_MAX_QUEUE 8 385 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) 386 #define BNXT_PAGE_SHFT 12 387 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 388 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 389 390 #define PTU_PTE_VALID 0x1UL 391 #define PTU_PTE_LAST 0x2UL 392 #define PTU_PTE_NEXT_TO_LAST 0x4UL 393 394 struct bnxt_ring_mem_info { 395 int nr_pages; 396 int page_size; 397 uint32_t flags; 398 #define BNXT_RMEM_VALID_PTE_FLAG 1 399 #define BNXT_RMEM_RING_PTE_FLAG 2 400 401 void **pg_arr; 402 rte_iova_t *dma_arr; 403 const struct rte_memzone *mz; 404 405 uint64_t *pg_tbl; 406 rte_iova_t pg_tbl_map; 407 const struct rte_memzone *pg_tbl_mz; 408 409 int vmem_size; 410 void **vmem; 411 }; 412 413 struct bnxt_ctx_pg_info { 414 uint32_t entries; 415 void *ctx_pg_arr[MAX_CTX_PAGES]; 416 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 417 struct bnxt_ring_mem_info ring_mem; 418 }; 419 420 struct bnxt_ctx_mem_info { 421 uint32_t qp_max_entries; 422 uint16_t qp_min_qp1_entries; 423 uint16_t qp_max_l2_entries; 424 uint16_t qp_entry_size; 425 uint16_t srq_max_l2_entries; 426 uint32_t srq_max_entries; 427 uint16_t srq_entry_size; 428 uint16_t cq_max_l2_entries; 429 uint32_t cq_max_entries; 430 uint16_t cq_entry_size; 431 uint16_t vnic_max_vnic_entries; 432 uint16_t vnic_max_ring_table_entries; 433 uint16_t vnic_entry_size; 434 uint32_t stat_max_entries; 435 uint16_t stat_entry_size; 436 uint16_t tqm_entry_size; 437 uint32_t tqm_min_entries_per_ring; 438 uint32_t tqm_max_entries_per_ring; 439 uint32_t mrav_max_entries; 440 uint16_t mrav_entry_size; 441 uint16_t tim_entry_size; 442 uint32_t tim_max_entries; 443 uint8_t tqm_entries_multiple; 444 uint8_t tqm_fp_rings_count; 445 446 uint32_t flags; 447 #define BNXT_CTX_FLAG_INITED 0x01 448 449 struct bnxt_ctx_pg_info qp_mem; 450 struct bnxt_ctx_pg_info srq_mem; 451 struct bnxt_ctx_pg_info cq_mem; 452 struct bnxt_ctx_pg_info vnic_mem; 453 struct bnxt_ctx_pg_info stat_mem; 454 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; 455 }; 456 457 struct bnxt_ctx_mem_buf_info { 458 void *va; 459 rte_iova_t dma; 460 uint16_t ctx_id; 461 size_t size; 462 }; 463 464 /* Maximum Firmware Reset bail out value in milliseconds */ 465 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 466 /* Minimum time required for the firmware readiness in milliseconds */ 467 #define BNXT_MIN_FW_READY_TIMEOUT 2000 468 /* Frequency for the firmware readiness check in milliseconds */ 469 #define BNXT_FW_READY_WAIT_INTERVAL 100 470 471 #define US_PER_MS 1000 472 #define NS_PER_US 1000 473 474 struct bnxt_error_recovery_info { 475 /* All units in milliseconds */ 476 uint32_t driver_polling_freq; 477 uint32_t master_func_wait_period; 478 uint32_t normal_func_wait_period; 479 uint32_t master_func_wait_period_after_reset; 480 uint32_t max_bailout_time_after_reset; 481 #define BNXT_FW_STATUS_REG 0 482 #define BNXT_FW_HEARTBEAT_CNT_REG 1 483 #define BNXT_FW_RECOVERY_CNT_REG 2 484 #define BNXT_FW_RESET_INPROG_REG 3 485 #define BNXT_FW_STATUS_REG_CNT 4 486 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 487 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 488 uint32_t reset_inprogress_reg_mask; 489 #define BNXT_NUM_RESET_REG 16 490 uint8_t reg_array_cnt; 491 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 492 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 493 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 494 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 495 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 496 #define BNXT_FLAG_MASTER_FUNC BIT(2) 497 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 498 uint32_t flags; 499 500 uint32_t last_heart_beat; 501 uint32_t last_reset_counter; 502 }; 503 504 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 505 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 506 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 507 #define BNXT_IF_CHANGE_RETRY_COUNT 40 508 509 struct bnxt_mark_info { 510 uint32_t mark_id; 511 bool valid; 512 }; 513 514 struct bnxt_rep_info { 515 struct rte_eth_dev *vfr_eth_dev; 516 pthread_mutex_t vfr_lock; 517 pthread_mutex_t vfr_start_lock; 518 bool conduit_valid; 519 }; 520 521 /* address space location of register */ 522 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 523 /* register is located in PCIe config space */ 524 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 525 /* register is located in GRC address space */ 526 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 527 /* register is located in BAR0 */ 528 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 529 /* register is located in BAR1 */ 530 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 531 532 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 533 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 534 535 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 536 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 537 538 #define BNXT_GRCP_BASE_MASK 0xfffff000 539 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 540 541 #define BNXT_FW_STATUS_HEALTHY 0x8000 542 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 543 544 #define BNXT_ETH_RSS_SUPPORT ( \ 545 ETH_RSS_IPV4 | \ 546 ETH_RSS_NONFRAG_IPV4_TCP | \ 547 ETH_RSS_NONFRAG_IPV4_UDP | \ 548 ETH_RSS_IPV6 | \ 549 ETH_RSS_NONFRAG_IPV6_TCP | \ 550 ETH_RSS_NONFRAG_IPV6_UDP | \ 551 ETH_RSS_LEVEL_MASK) 552 553 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 554 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 555 DEV_TX_OFFLOAD_TCP_CKSUM | \ 556 DEV_TX_OFFLOAD_UDP_CKSUM | \ 557 DEV_TX_OFFLOAD_TCP_TSO | \ 558 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 559 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 560 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 561 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 562 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 563 DEV_TX_OFFLOAD_QINQ_INSERT | \ 564 DEV_TX_OFFLOAD_MULTI_SEGS) 565 566 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 567 DEV_RX_OFFLOAD_VLAN_STRIP | \ 568 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 569 DEV_RX_OFFLOAD_UDP_CKSUM | \ 570 DEV_RX_OFFLOAD_TCP_CKSUM | \ 571 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 572 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \ 573 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 574 DEV_RX_OFFLOAD_KEEP_CRC | \ 575 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 576 DEV_RX_OFFLOAD_TCP_LRO | \ 577 DEV_RX_OFFLOAD_SCATTER | \ 578 DEV_RX_OFFLOAD_RSS_HASH) 579 580 #define MAX_TABLE_SUPPORT 4 581 #define MAX_DIR_SUPPORT 2 582 struct bnxt_dmabuf_info { 583 uint32_t entry_num; 584 int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT]; 585 }; 586 587 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 588 589 struct bnxt_flow_stat_info { 590 uint16_t max_fc; 591 uint16_t flow_count; 592 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 593 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 594 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 595 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 596 }; 597 598 struct bnxt { 599 void *bar0; 600 601 struct rte_eth_dev *eth_dev; 602 struct rte_pci_device *pdev; 603 void *doorbell_base; 604 605 uint32_t flags; 606 #define BNXT_FLAG_REGISTERED BIT(0) 607 #define BNXT_FLAG_VF BIT(1) 608 #define BNXT_FLAG_PORT_STATS BIT(2) 609 #define BNXT_FLAG_JUMBO BIT(3) 610 #define BNXT_FLAG_SHORT_CMD BIT(4) 611 #define BNXT_FLAG_UPDATE_HASH BIT(5) 612 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 613 #define BNXT_FLAG_MULTI_HOST BIT(7) 614 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 615 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 616 #define BNXT_FLAG_KONG_MB_EN BIT(10) 617 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 618 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 619 #define BNXT_FLAG_CHIP_P5 BIT(13) 620 #define BNXT_FLAG_STINGRAY BIT(14) 621 #define BNXT_FLAG_FW_RESET BIT(15) 622 #define BNXT_FLAG_FATAL_ERROR BIT(16) 623 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 624 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 625 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 626 #define BNXT_FLAG_NEW_RM BIT(20) 627 #define BNXT_FLAG_NPAR_PF BIT(21) 628 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 629 #define BNXT_FLAG_FC_THREAD BIT(23) 630 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 631 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 632 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 633 #define BNXT_FLAG_TRUFLOW_EN BIT(27) 634 #define BNXT_FLAG_GFID_ENABLE BIT(28) 635 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 636 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 637 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 638 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 639 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 640 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 641 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 642 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 643 #define BNXT_CHIP_P5(bp) ((bp)->flags & BNXT_FLAG_CHIP_P5) 644 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 645 #define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp) 646 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp)) 647 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 648 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 649 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) 650 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 651 652 uint32_t fw_cap; 653 #define BNXT_FW_CAP_HOT_RESET BIT(0) 654 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 655 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 656 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 657 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) 658 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 659 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 660 #define BNXT_FW_CAP_LINK_ADMIN BIT(7) 661 662 pthread_mutex_t flow_lock; 663 664 uint32_t vnic_cap_flags; 665 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 666 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) 667 unsigned int rx_nr_rings; 668 unsigned int rx_cp_nr_rings; 669 unsigned int rx_num_qs_per_vnic; 670 struct bnxt_rx_queue **rx_queues; 671 const void *rx_mem_zone; 672 struct rx_port_stats *hw_rx_port_stats; 673 rte_iova_t hw_rx_port_stats_map; 674 struct rx_port_stats_ext *hw_rx_port_stats_ext; 675 rte_iova_t hw_rx_port_stats_ext_map; 676 uint16_t fw_rx_port_stats_ext_size; 677 678 unsigned int tx_nr_rings; 679 unsigned int tx_cp_nr_rings; 680 struct bnxt_tx_queue **tx_queues; 681 const void *tx_mem_zone; 682 struct tx_port_stats *hw_tx_port_stats; 683 rte_iova_t hw_tx_port_stats_map; 684 struct tx_port_stats_ext *hw_tx_port_stats_ext; 685 rte_iova_t hw_tx_port_stats_ext_map; 686 uint16_t fw_tx_port_stats_ext_size; 687 688 /* Default completion ring */ 689 struct bnxt_cp_ring_info *async_cp_ring; 690 struct bnxt_cp_ring_info *rxtx_nq_ring; 691 uint32_t max_ring_grps; 692 struct bnxt_ring_grp_info *grp_info; 693 694 unsigned int nr_vnics; 695 696 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 697 struct bnxt_vnic_info *vnic_info; 698 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 699 700 struct bnxt_filter_info *filter_info; 701 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 702 703 struct bnxt_irq *irq_tbl; 704 705 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 706 707 uint16_t chimp_cmd_seq; 708 uint16_t kong_cmd_seq; 709 void *hwrm_cmd_resp_addr; 710 rte_iova_t hwrm_cmd_resp_dma_addr; 711 void *hwrm_short_cmd_req_addr; 712 rte_iova_t hwrm_short_cmd_req_dma_addr; 713 rte_spinlock_t hwrm_lock; 714 /* synchronize between dev_configure_op and int handler */ 715 pthread_mutex_t def_cp_lock; 716 /* synchronize between dev_start_op and async evt handler 717 * Locking sequence in async evt handler will be 718 * def_cp_lock 719 * health_check_lock 720 */ 721 pthread_mutex_t health_check_lock; 722 uint16_t max_req_len; 723 uint16_t max_resp_len; 724 uint16_t hwrm_max_ext_req_len; 725 726 /* default command timeout value of 500ms */ 727 #define DFLT_HWRM_CMD_TIMEOUT 500000 728 /* short command timeout value of 50ms */ 729 #define SHORT_HWRM_CMD_TIMEOUT 50000 730 /* default HWRM request timeout value */ 731 uint32_t hwrm_cmd_timeout; 732 733 struct bnxt_link_info *link_info; 734 struct bnxt_cos_queue_info *rx_cos_queue; 735 struct bnxt_cos_queue_info *tx_cos_queue; 736 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 737 uint8_t rx_cosq_cnt; 738 uint8_t max_tc; 739 uint8_t max_lltc; 740 uint8_t max_q; 741 742 uint16_t fw_fid; 743 uint16_t max_rsscos_ctx; 744 uint16_t max_cp_rings; 745 uint16_t max_tx_rings; 746 uint16_t max_rx_rings; 747 #define MAX_STINGRAY_RINGS 236U 748 #define BNXT_MAX_VF_REP_RINGS 8 749 750 uint16_t max_nq_rings; 751 uint16_t max_l2_ctx; 752 uint16_t max_rx_em_flows; 753 uint16_t max_vnics; 754 uint16_t max_stat_ctx; 755 uint16_t max_tpa_v2; 756 uint16_t first_vf_id; 757 uint16_t vlan; 758 #define BNXT_OUTER_TPID_MASK 0x0000ffff 759 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 760 #define BNXT_OUTER_TPID_BD_SHFT 16 761 uint32_t outer_tpid_bd; 762 struct bnxt_pf_info *pf; 763 struct bnxt_parent_info *parent; 764 uint8_t port_cnt; 765 uint8_t vxlan_port_cnt; 766 uint8_t geneve_port_cnt; 767 uint16_t vxlan_port; 768 uint16_t geneve_port; 769 uint16_t vxlan_fw_dst_port_id; 770 uint16_t geneve_fw_dst_port_id; 771 uint32_t fw_ver; 772 uint32_t hwrm_spec_code; 773 774 struct bnxt_led_info *leds; 775 struct bnxt_ptp_cfg *ptp_cfg; 776 uint16_t vf_resv_strategy; 777 struct bnxt_ctx_mem_info *ctx; 778 779 uint16_t fw_reset_min_msecs; 780 uint16_t fw_reset_max_msecs; 781 uint16_t switch_domain_id; 782 uint16_t num_reps; 783 struct bnxt_rep_info *rep_info; 784 uint16_t *cfa_code_map; 785 /* Struct to hold adapter error recovery related info */ 786 struct bnxt_error_recovery_info *recovery_info; 787 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 788 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 789 #define BNXT_FLOW_ID_MASK 0x0000ffff 790 struct bnxt_mark_info *mark_table; 791 792 #define BNXT_SVIF_INVALID 0xFFFF 793 uint16_t func_svif; 794 uint16_t port_svif; 795 796 struct tf tfp; 797 struct bnxt_dmabuf_info dmabuf; 798 struct bnxt_ulp_context *ulp_ctx; 799 struct bnxt_flow_stat_info *flow_stat; 800 uint16_t max_num_kflows; 801 uint16_t tx_cfa_action; 802 }; 803 804 static 805 inline uint16_t bnxt_max_rings(struct bnxt *bp) 806 { 807 uint16_t max_tx_rings = bp->max_tx_rings; 808 uint16_t max_rx_rings = bp->max_rx_rings; 809 uint16_t max_cp_rings = bp->max_cp_rings; 810 uint16_t max_rings; 811 812 /* For the sake of symmetry: 813 * max Tx rings == max Rx rings, one stat ctx for each. 814 */ 815 if (BNXT_STINGRAY(bp)) { 816 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U, 817 MAX_STINGRAY_RINGS), 818 bp->max_stat_ctx / 2U); 819 } else { 820 max_rx_rings = RTE_MIN(max_rx_rings / 2U, 821 bp->max_stat_ctx / 2U); 822 } 823 824 max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); 825 if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp)) 826 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp); 827 max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings); 828 829 return max_rings; 830 } 831 832 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 833 834 /** 835 * Structure to store private data for each VF representor instance 836 */ 837 struct bnxt_representor { 838 uint16_t switch_domain_id; 839 uint16_t vf_id; 840 #define BNXT_REP_IS_PF BIT(0) 841 #define BNXT_REP_Q_R2F_VALID BIT(1) 842 #define BNXT_REP_Q_F2R_VALID BIT(2) 843 #define BNXT_REP_FC_R2F_VALID BIT(3) 844 #define BNXT_REP_FC_F2R_VALID BIT(4) 845 #define BNXT_REP_BASED_PF_VALID BIT(5) 846 uint32_t flags; 847 uint16_t fw_fid; 848 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 849 uint16_t dflt_vnic_id; 850 uint16_t svif; 851 uint16_t vfr_tx_cfa_action; 852 uint8_t parent_pf_idx; /* Logical PF index */ 853 uint32_t dpdk_port_id; 854 uint32_t rep_based_pf; 855 uint8_t rep_q_r2f; 856 uint8_t rep_q_f2r; 857 uint8_t rep_fc_r2f; 858 uint8_t rep_fc_f2r; 859 /* Private data store of associated PF/Trusted VF */ 860 struct rte_eth_dev *parent_dev; 861 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 862 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 863 struct bnxt_rx_queue **rx_queues; 864 unsigned int rx_nr_rings; 865 unsigned int tx_nr_rings; 866 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 867 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 868 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 869 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 870 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 871 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 872 }; 873 874 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) 875 #define BNXT_REP_BASED_PF(vfr_bp) \ 876 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID) 877 878 struct bnxt_vf_rep_tx_queue { 879 struct bnxt_tx_queue *txq; 880 struct bnxt_representor *bp; 881 }; 882 883 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 884 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 885 bool exp_link_status); 886 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 887 int is_bnxt_in_error(struct bnxt *bp); 888 889 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 890 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 891 void bnxt_schedule_fw_health_check(struct bnxt *bp); 892 893 bool is_bnxt_supported(struct rte_eth_dev *dev); 894 bool bnxt_stratus_device(struct bnxt *bp); 895 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 896 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 897 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 898 int wait_to_complete); 899 uint16_t bnxt_dummy_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 900 uint16_t nb_pkts); 901 uint16_t bnxt_dummy_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 902 uint16_t nb_pkts); 903 904 extern const struct rte_flow_ops bnxt_flow_ops; 905 906 #define bnxt_acquire_flow_lock(bp) \ 907 pthread_mutex_lock(&(bp)->flow_lock) 908 909 #define bnxt_release_flow_lock(bp) \ 910 pthread_mutex_unlock(&(bp)->flow_lock) 911 912 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 913 if ((vnic_id) >= (bp)->max_vnics) { \ 914 rte_flow_error_set(error, \ 915 EINVAL, \ 916 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 917 NULL, \ 918 "Group id is invalid!"); \ 919 rc = -rte_errno; \ 920 goto ret; \ 921 } \ 922 } while (0) 923 924 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 925 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 926 927 extern int bnxt_logtype_driver; 928 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 929 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 930 __func__, ## args) 931 932 #define PMD_DRV_LOG(level, fmt, args...) \ 933 PMD_DRV_LOG_RAW(level, fmt, ## args) 934 935 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 936 int32_t bnxt_ulp_port_init(struct bnxt *bp); 937 void bnxt_ulp_port_deinit(struct bnxt *bp); 938 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 939 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 940 int32_t 941 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 942 int32_t 943 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); 944 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); 945 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, 946 enum bnxt_ulp_intf_type type); 947 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); 948 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); 949 uint16_t bnxt_get_phy_port_id(uint16_t port); 950 uint16_t bnxt_get_vport(uint16_t port); 951 enum bnxt_ulp_intf_type 952 bnxt_get_interface_type(uint16_t port); 953 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); 954 955 void bnxt_cancel_fc_thread(struct bnxt *bp); 956 void bnxt_flow_cnt_alarm_cb(void *arg); 957 int bnxt_flow_stats_req(struct bnxt *bp); 958 int bnxt_flow_stats_cnt(struct bnxt *bp); 959 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 960 961 int 962 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 963 enum rte_filter_type filter_type, 964 enum rte_filter_op filter_op, void *arg); 965 #endif 966