1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57304_VF 0x16cb 37 #define BROADCOM_DEV_ID_57417_MF 0x16cc 38 #define BROADCOM_DEV_ID_NS2 0x16cd 39 #define BROADCOM_DEV_ID_57406_VF 0x16d3 40 #define BROADCOM_DEV_ID_57412 0x16d6 41 #define BROADCOM_DEV_ID_57414 0x16d7 42 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 43 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 44 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 45 #define BROADCOM_DEV_ID_57412_MF 0x16de 46 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 47 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 48 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 49 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 50 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 51 #define BROADCOM_DEV_ID_57407_MF 0x16ea 52 #define BROADCOM_DEV_ID_57414_MF 0x16ec 53 #define BROADCOM_DEV_ID_57416_MF 0x16ee 54 #define BROADCOM_DEV_ID_57508 0x1750 55 #define BROADCOM_DEV_ID_57504 0x1751 56 #define BROADCOM_DEV_ID_57502 0x1752 57 #define BROADCOM_DEV_ID_57508_MF1 0x1800 58 #define BROADCOM_DEV_ID_57504_MF1 0x1801 59 #define BROADCOM_DEV_ID_57502_MF1 0x1802 60 #define BROADCOM_DEV_ID_57508_MF2 0x1803 61 #define BROADCOM_DEV_ID_57504_MF2 0x1804 62 #define BROADCOM_DEV_ID_57502_MF2 0x1805 63 #define BROADCOM_DEV_ID_57500_VF1 0x1806 64 #define BROADCOM_DEV_ID_57500_VF2 0x1807 65 #define BROADCOM_DEV_ID_58802 0xd802 66 #define BROADCOM_DEV_ID_58804 0xd804 67 #define BROADCOM_DEV_ID_58808 0x16f0 68 #define BROADCOM_DEV_ID_58802_VF 0xd800 69 #define BROADCOM_DEV_ID_58812 0xd812 70 #define BROADCOM_DEV_ID_58814 0xd814 71 #define BROADCOM_DEV_ID_58818 0xd818 72 #define BROADCOM_DEV_ID_58818_VF 0xd82e 73 74 #define BROADCOM_DEV_957508_N2100 0x5208 75 #define IS_BNXT_DEV_957508_N2100(bp) \ 76 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) 77 78 #define BNXT_MAX_MTU 9574 79 #define VLAN_TAG_SIZE 4 80 #define BNXT_NUM_VLANS 2 81 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 82 RTE_ETHER_CRC_LEN +\ 83 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 84 /* FW adds extra 4 bytes for FCS */ 85 #define BNXT_VNIC_MRU(mtu)\ 86 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 87 #define BNXT_VF_RSV_NUM_RSS_CTX 1 88 #define BNXT_VF_RSV_NUM_L2_CTX 4 89 /* TODO: For now, do not support VMDq/RFS on VFs. */ 90 #define BNXT_VF_RSV_NUM_VNIC 1 91 #define BNXT_MAX_LED 4 92 #define BNXT_MIN_RING_DESC 16 93 #define BNXT_MAX_TX_RING_DESC 4096 94 #define BNXT_MAX_RX_RING_DESC 8192 95 #define BNXT_DB_SIZE 0x80 96 97 #define TPA_MAX_AGGS 64 98 #define TPA_MAX_AGGS_TH 1024 99 100 #define TPA_MAX_NUM_SEGS 32 101 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 102 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 103 104 #define BNXT_TPA_MAX_AGGS(bp) \ 105 (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \ 106 TPA_MAX_AGGS) 107 108 #define BNXT_TPA_MAX_SEGS(bp) \ 109 (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \ 110 TPA_MAX_SEGS) 111 112 /* 113 * Define the number of async completion rings to be used. Set to zero for 114 * configurations in which the maximum number of packet completion rings 115 * for packet completions is desired or when async completion handling 116 * cannot be interrupt-driven. 117 */ 118 #ifdef RTE_EXEC_ENV_FREEBSD 119 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 120 #define BNXT_NUM_ASYNC_CPR(bp) 0U 121 #else 122 #define BNXT_NUM_ASYNC_CPR(bp) 1U 123 #endif 124 125 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 126 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 127 128 /* Chimp Communication Channel */ 129 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 130 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 131 /* Kong Communication Channel */ 132 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 133 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 134 135 #define BNXT_INT_LAT_TMR_MIN 75 136 #define BNXT_INT_LAT_TMR_MAX 150 137 #define BNXT_NUM_CMPL_AGGR_INT 36 138 #define BNXT_CMPL_AGGR_DMA_TMR 37 139 #define BNXT_NUM_CMPL_DMA_AGGR 36 140 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 141 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 142 143 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 144 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 145 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 146 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 147 #define BNXT_DEFAULT_VNIC_ALLOC \ 148 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 149 #define BNXT_DEFAULT_VNIC_FREE \ 150 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 151 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 152 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 153 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 154 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 155 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 156 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 157 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 158 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 159 160 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 161 (((data1) & \ 162 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\ 163 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 164 165 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ 166 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) 167 168 struct bnxt_led_info { 169 uint8_t num_leds; 170 uint8_t led_id; 171 uint8_t led_type; 172 uint8_t led_group_id; 173 uint8_t unused; 174 uint16_t led_state_caps; 175 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 176 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 177 178 uint16_t led_color_caps; 179 }; 180 181 struct bnxt_led_cfg { 182 uint8_t led_id; 183 uint8_t led_state; 184 uint8_t led_color; 185 uint8_t unused; 186 uint16_t led_blink_on; 187 uint16_t led_blink_off; 188 uint8_t led_group_id; 189 uint8_t rsvd; 190 }; 191 192 #define BNXT_LED_DFLT_ENA \ 193 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 194 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 195 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 196 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 197 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 198 199 #define BNXT_LED_DFLT_ENA_SHIFT 6 200 201 #define BNXT_LED_DFLT_ENABLES(x) \ 202 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 203 204 struct bnxt_vlan_table_entry { 205 uint16_t tpid; 206 uint16_t vid; 207 } __rte_packed; 208 209 struct bnxt_vlan_antispoof_table_entry { 210 uint16_t tpid; 211 uint16_t vid; 212 uint16_t mask; 213 } __rte_packed; 214 215 struct bnxt_child_vf_info { 216 void *req_buf; 217 struct bnxt_vlan_table_entry *vlan_table; 218 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 219 STAILQ_HEAD(, bnxt_filter_info) filter; 220 uint32_t func_cfg_flags; 221 uint32_t l2_rx_mask; 222 uint16_t fid; 223 uint16_t max_tx_rate; 224 uint16_t dflt_vlan; 225 uint16_t vlan_count; 226 uint8_t mac_spoof_en; 227 uint8_t vlan_spoof_en; 228 bool random_mac; 229 bool persist_stats; 230 }; 231 232 struct bnxt_parent_info { 233 #define BNXT_PF_FID_INVALID 0xFFFF 234 uint16_t fid; 235 uint16_t vnic; 236 uint16_t port_id; 237 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 238 }; 239 240 struct bnxt_pf_info { 241 #define BNXT_FIRST_PF_FID 1 242 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 243 #define BNXT_MAX_VF_REPS 64 244 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 245 #define BNXT_FIRST_VF_FID 128 246 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 247 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 248 BNXT_PF_RINGS_USED(bp)) 249 uint16_t port_id; 250 uint16_t first_vf_id; 251 uint16_t active_vfs; 252 uint16_t max_vfs; 253 uint16_t total_vfs; /* Total VFs possible. 254 * Not necessarily enabled. 255 */ 256 uint32_t func_cfg_flags; 257 void *vf_req_buf; 258 rte_iova_t vf_req_buf_dma_addr; 259 uint32_t vf_req_fwd[8]; 260 uint16_t total_vnics; 261 struct bnxt_child_vf_info *vf_info; 262 #define BNXT_EVB_MODE_NONE 0 263 #define BNXT_EVB_MODE_VEB 1 264 #define BNXT_EVB_MODE_VEPA 2 265 uint8_t evb_mode; 266 }; 267 268 /* Max wait time for link up is 10s and link down is 500ms */ 269 #define BNXT_MAX_LINK_WAIT_CNT 200 270 #define BNXT_MIN_LINK_WAIT_CNT 10 271 #define BNXT_LINK_WAIT_INTERVAL 50 272 struct bnxt_link_info { 273 uint32_t phy_flags; 274 uint8_t mac_type; 275 uint8_t phy_link_status; 276 uint8_t loop_back; 277 uint8_t link_up; 278 uint8_t duplex; 279 uint8_t pause; 280 uint8_t force_pause; 281 uint8_t auto_pause; 282 uint8_t auto_mode; 283 #define PHY_VER_LEN 3 284 uint8_t phy_ver[PHY_VER_LEN]; 285 uint16_t link_speed; 286 uint16_t support_speeds; 287 uint16_t auto_link_speed; 288 uint16_t force_link_speed; 289 uint16_t auto_link_speed_mask; 290 uint32_t preemphasis; 291 uint8_t phy_type; 292 uint8_t media_type; 293 uint16_t support_auto_speeds; 294 uint8_t link_signal_mode; 295 uint16_t force_pam4_link_speed; 296 uint16_t support_pam4_speeds; 297 uint16_t auto_pam4_link_speeds; 298 uint16_t support_pam4_auto_speeds; 299 uint8_t req_signal_mode; 300 uint8_t module_status; 301 }; 302 303 #define BNXT_COS_QUEUE_COUNT 8 304 struct bnxt_cos_queue_info { 305 uint8_t id; 306 uint8_t profile; 307 }; 308 309 struct rte_flow { 310 STAILQ_ENTRY(rte_flow) next; 311 struct bnxt_filter_info *filter; 312 struct bnxt_vnic_info *vnic; 313 }; 314 315 #define BNXT_PTP_RX_PND_CNT 10 316 #define BNXT_PTP_FLAGS_PATH_TX 0x0 317 #define BNXT_PTP_FLAGS_PATH_RX 0x1 318 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 319 #define BNXT_PTP_CURRENT_TIME_MASK 0xFFFF00000000ULL 320 321 struct bnxt_ptp_cfg { 322 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 323 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 324 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 325 struct rte_timecounter tc; 326 struct rte_timecounter tx_tstamp_tc; 327 struct rte_timecounter rx_tstamp_tc; 328 struct bnxt *bp; 329 #define BNXT_MAX_TX_TS 1 330 uint16_t rxctl; 331 #define BNXT_PTP_MSG_SYNC BIT(0) 332 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 333 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 334 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 335 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 336 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 337 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 338 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 339 #define BNXT_PTP_MSG_SIGNALING BIT(12) 340 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 341 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 342 BNXT_PTP_MSG_DELAY_REQ | \ 343 BNXT_PTP_MSG_PDELAY_REQ | \ 344 BNXT_PTP_MSG_PDELAY_RESP) 345 uint8_t tx_tstamp_en:1; 346 int rx_filter; 347 348 #define BNXT_PTP_RX_TS_L 0 349 #define BNXT_PTP_RX_TS_H 1 350 #define BNXT_PTP_RX_SEQ 2 351 #define BNXT_PTP_RX_FIFO 3 352 #define BNXT_PTP_RX_FIFO_PENDING 0x1 353 #define BNXT_PTP_RX_FIFO_ADV 4 354 #define BNXT_PTP_RX_REGS 5 355 356 #define BNXT_PTP_TX_TS_L 0 357 #define BNXT_PTP_TX_TS_H 1 358 #define BNXT_PTP_TX_SEQ 2 359 #define BNXT_PTP_TX_FIFO 3 360 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 361 #define BNXT_PTP_TX_REGS 4 362 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 363 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 364 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 365 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 366 367 /* On Thor, the Rx timestamp is present in the Rx completion record */ 368 uint64_t rx_timestamp; 369 uint64_t current_time; 370 }; 371 372 struct bnxt_coal { 373 uint16_t num_cmpl_aggr_int; 374 uint16_t num_cmpl_dma_aggr; 375 uint16_t num_cmpl_dma_aggr_during_int; 376 uint16_t int_lat_tmr_max; 377 uint16_t int_lat_tmr_min; 378 uint16_t cmpl_aggr_dma_tmr; 379 uint16_t cmpl_aggr_dma_tmr_during_int; 380 }; 381 382 /* 64-bit doorbell */ 383 #define DBR_EPOCH_MASK 0x01000000UL 384 #define DBR_EPOCH_SFT 24 385 #define DBR_XID_SFT 32 386 #define DBR_PATH_L2 (0x1ULL << 56) 387 #define DBR_VALID (0x1ULL << 58) 388 #define DBR_TYPE_SQ (0x0ULL << 60) 389 #define DBR_TYPE_SRQ (0x2ULL << 60) 390 #define DBR_TYPE_CQ (0x4ULL << 60) 391 #define DBR_TYPE_NQ (0xaULL << 60) 392 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 393 394 #define DB_PF_OFFSET 0x10000 395 #define DB_VF_OFFSET 0x4000 396 397 #define BNXT_RSS_TBL_SIZE_P5 512U 398 #define BNXT_RSS_ENTRIES_PER_CTX_P5 64 399 #define BNXT_MAX_RSS_CTXTS_P5 \ 400 (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5) 401 402 #define BNXT_MAX_QUEUE 8 403 #define BNXT_MAX_TQM_SP_RINGS 1 404 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 405 #define BNXT_MAX_TQM_FP_RINGS 9 406 #define BNXT_MAX_TQM_LEGACY_RINGS \ 407 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 408 #define BNXT_MAX_TQM_RINGS \ 409 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 410 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 411 #define BNXT_BACKING_STORE_CFG_LEN \ 412 sizeof(struct hwrm_func_backing_store_cfg_input) 413 #define BNXT_PAGE_SHFT 12 414 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 415 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 416 417 #define PTU_PTE_VALID 0x1UL 418 #define PTU_PTE_LAST 0x2UL 419 #define PTU_PTE_NEXT_TO_LAST 0x4UL 420 421 struct bnxt_ring_mem_info { 422 int nr_pages; 423 int page_size; 424 uint32_t flags; 425 #define BNXT_RMEM_VALID_PTE_FLAG 1 426 #define BNXT_RMEM_RING_PTE_FLAG 2 427 428 void **pg_arr; 429 rte_iova_t *dma_arr; 430 const struct rte_memzone *mz; 431 432 uint64_t *pg_tbl; 433 rte_iova_t pg_tbl_map; 434 const struct rte_memzone *pg_tbl_mz; 435 436 int vmem_size; 437 void **vmem; 438 }; 439 440 struct bnxt_ctx_pg_info { 441 uint32_t entries; 442 void *ctx_pg_arr[MAX_CTX_PAGES]; 443 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 444 struct bnxt_ring_mem_info ring_mem; 445 }; 446 447 struct bnxt_ctx_mem_info { 448 uint32_t qp_max_entries; 449 uint16_t qp_min_qp1_entries; 450 uint16_t qp_max_l2_entries; 451 uint16_t qp_entry_size; 452 uint16_t srq_max_l2_entries; 453 uint32_t srq_max_entries; 454 uint16_t srq_entry_size; 455 uint16_t cq_max_l2_entries; 456 uint32_t cq_max_entries; 457 uint16_t cq_entry_size; 458 uint16_t vnic_max_vnic_entries; 459 uint16_t vnic_max_ring_table_entries; 460 uint16_t vnic_entry_size; 461 uint32_t stat_max_entries; 462 uint16_t stat_entry_size; 463 uint16_t tqm_entry_size; 464 uint32_t tqm_min_entries_per_ring; 465 uint32_t tqm_max_entries_per_ring; 466 uint32_t mrav_max_entries; 467 uint16_t mrav_entry_size; 468 uint16_t tim_entry_size; 469 uint32_t tim_max_entries; 470 uint8_t tqm_entries_multiple; 471 uint8_t tqm_fp_rings_count; 472 473 uint32_t flags; 474 #define BNXT_CTX_FLAG_INITED 0x01 475 476 struct bnxt_ctx_pg_info qp_mem; 477 struct bnxt_ctx_pg_info srq_mem; 478 struct bnxt_ctx_pg_info cq_mem; 479 struct bnxt_ctx_pg_info vnic_mem; 480 struct bnxt_ctx_pg_info stat_mem; 481 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; 482 }; 483 484 struct bnxt_ctx_mem_buf_info { 485 void *va; 486 rte_iova_t dma; 487 uint16_t ctx_id; 488 size_t size; 489 }; 490 491 /* Maximum Firmware Reset bail out value in milliseconds */ 492 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 493 /* Minimum time required for the firmware readiness in milliseconds */ 494 #define BNXT_MIN_FW_READY_TIMEOUT 2000 495 /* Frequency for the firmware readiness check in milliseconds */ 496 #define BNXT_FW_READY_WAIT_INTERVAL 100 497 498 #define US_PER_MS 1000 499 #define NS_PER_US 1000 500 501 struct bnxt_error_recovery_info { 502 /* All units in milliseconds */ 503 uint32_t driver_polling_freq; 504 uint32_t master_func_wait_period; 505 uint32_t normal_func_wait_period; 506 uint32_t master_func_wait_period_after_reset; 507 uint32_t max_bailout_time_after_reset; 508 #define BNXT_FW_STATUS_REG 0 509 #define BNXT_FW_HEARTBEAT_CNT_REG 1 510 #define BNXT_FW_RECOVERY_CNT_REG 2 511 #define BNXT_FW_RESET_INPROG_REG 3 512 #define BNXT_FW_STATUS_REG_CNT 4 513 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 514 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 515 uint32_t reset_inprogress_reg_mask; 516 #define BNXT_NUM_RESET_REG 16 517 uint8_t reg_array_cnt; 518 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 519 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 520 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 521 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 522 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 523 #define BNXT_FLAG_MASTER_FUNC BIT(2) 524 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 525 uint32_t flags; 526 527 uint32_t last_heart_beat; 528 uint32_t last_reset_counter; 529 }; 530 531 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 532 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 533 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 534 #define BNXT_IF_CHANGE_RETRY_COUNT 40 535 536 struct bnxt_mark_info { 537 uint32_t mark_id; 538 bool valid; 539 }; 540 541 struct bnxt_rep_info { 542 struct rte_eth_dev *vfr_eth_dev; 543 pthread_mutex_t vfr_lock; 544 pthread_mutex_t vfr_start_lock; 545 bool conduit_valid; 546 }; 547 548 /* address space location of register */ 549 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 550 /* register is located in PCIe config space */ 551 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 552 /* register is located in GRC address space */ 553 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 554 /* register is located in BAR0 */ 555 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 556 /* register is located in BAR1 */ 557 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 558 559 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 560 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 561 562 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 563 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 564 565 #define BNXT_GRCP_BASE_MASK 0xfffff000 566 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 567 568 #define BNXT_FW_STATUS_HEALTHY 0x8000 569 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 570 571 #define BNXT_ETH_RSS_SUPPORT ( \ 572 ETH_RSS_IPV4 | \ 573 ETH_RSS_NONFRAG_IPV4_TCP | \ 574 ETH_RSS_NONFRAG_IPV4_UDP | \ 575 ETH_RSS_IPV6 | \ 576 ETH_RSS_NONFRAG_IPV6_TCP | \ 577 ETH_RSS_NONFRAG_IPV6_UDP | \ 578 ETH_RSS_LEVEL_MASK) 579 580 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 581 DEV_TX_OFFLOAD_TCP_CKSUM | \ 582 DEV_TX_OFFLOAD_UDP_CKSUM | \ 583 DEV_TX_OFFLOAD_TCP_TSO | \ 584 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 585 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 586 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 587 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 588 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 589 DEV_TX_OFFLOAD_QINQ_INSERT | \ 590 DEV_TX_OFFLOAD_MULTI_SEGS) 591 592 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 593 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 594 DEV_RX_OFFLOAD_UDP_CKSUM | \ 595 DEV_RX_OFFLOAD_TCP_CKSUM | \ 596 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 597 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \ 598 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 599 DEV_RX_OFFLOAD_KEEP_CRC | \ 600 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 601 DEV_RX_OFFLOAD_TCP_LRO | \ 602 DEV_RX_OFFLOAD_SCATTER | \ 603 DEV_RX_OFFLOAD_RSS_HASH) 604 605 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 606 607 struct bnxt_flow_stat_info { 608 uint16_t max_fc; 609 uint16_t flow_count; 610 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 611 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 612 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 613 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 614 }; 615 616 struct bnxt_ring_stats { 617 /* Number of transmitted unicast packets */ 618 uint64_t tx_ucast_pkts; 619 /* Number of transmitted multicast packets */ 620 uint64_t tx_mcast_pkts; 621 /* Number of transmitted broadcast packets */ 622 uint64_t tx_bcast_pkts; 623 /* Number of packets discarded in transmit path */ 624 uint64_t tx_discard_pkts; 625 /* Number of packets in transmit path with error */ 626 uint64_t tx_error_pkts; 627 /* Number of transmitted bytes for unicast traffic */ 628 uint64_t tx_ucast_bytes; 629 /* Number of transmitted bytes for multicast traffic */ 630 uint64_t tx_mcast_bytes; 631 /* Number of transmitted bytes for broadcast traffic */ 632 uint64_t tx_bcast_bytes; 633 /* Number of received unicast packets */ 634 uint64_t rx_ucast_pkts; 635 /* Number of received multicast packets */ 636 uint64_t rx_mcast_pkts; 637 /* Number of received broadcast packets */ 638 uint64_t rx_bcast_pkts; 639 /* Number of packets discarded in receive path */ 640 uint64_t rx_discard_pkts; 641 /* Number of packets in receive path with errors */ 642 uint64_t rx_error_pkts; 643 /* Number of received bytes for unicast traffic */ 644 uint64_t rx_ucast_bytes; 645 /* Number of received bytes for multicast traffic */ 646 uint64_t rx_mcast_bytes; 647 /* Number of received bytes for broadcast traffic */ 648 uint64_t rx_bcast_bytes; 649 /* Number of aggregated unicast packets */ 650 uint64_t rx_agg_pkts; 651 /* Number of aggregated unicast bytes */ 652 uint64_t rx_agg_bytes; 653 /* Number of aggregation events */ 654 uint64_t rx_agg_events; 655 /* Number of aborted aggregations */ 656 uint64_t rx_agg_aborts; 657 }; 658 659 struct bnxt { 660 void *bar0; 661 662 struct rte_eth_dev *eth_dev; 663 struct rte_pci_device *pdev; 664 void *doorbell_base; 665 int legacy_db_size; 666 667 uint32_t flags; 668 #define BNXT_FLAG_REGISTERED BIT(0) 669 #define BNXT_FLAG_VF BIT(1) 670 #define BNXT_FLAG_PORT_STATS BIT(2) 671 #define BNXT_FLAG_JUMBO BIT(3) 672 #define BNXT_FLAG_SHORT_CMD BIT(4) 673 #define BNXT_FLAG_UPDATE_HASH BIT(5) 674 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 675 #define BNXT_FLAG_MULTI_HOST BIT(7) 676 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 677 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 678 #define BNXT_FLAG_KONG_MB_EN BIT(10) 679 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 680 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 681 #define BNXT_FLAG_CHIP_P5 BIT(13) 682 #define BNXT_FLAG_STINGRAY BIT(14) 683 #define BNXT_FLAG_FW_RESET BIT(15) 684 #define BNXT_FLAG_FATAL_ERROR BIT(16) 685 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 686 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 687 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 688 #define BNXT_FLAG_NEW_RM BIT(20) 689 #define BNXT_FLAG_NPAR_PF BIT(21) 690 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 691 #define BNXT_FLAG_FC_THREAD BIT(23) 692 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 693 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 694 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 695 #define BNXT_FLAG_GFID_ENABLE BIT(27) 696 #define BNXT_FLAG_RFS_NEEDS_VNIC BIT(28) 697 #define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(29) 698 #define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) 699 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 700 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 701 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 702 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 703 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 704 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 705 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 706 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 707 #define BNXT_CHIP_P5(bp) ((bp)->flags & BNXT_FLAG_CHIP_P5) 708 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 709 #define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp) 710 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp)) 711 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 712 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 713 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 714 715 uint32_t flags2; 716 #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) 717 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) 718 #define BNXT_FLAGS2_ACCUM_STATS_EN BIT(2) 719 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ 720 ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) 721 #define BNXT_ACCUM_STATS_EN(bp) \ 722 ((bp)->flags2 & BNXT_FLAGS2_ACCUM_STATS_EN) 723 724 uint16_t chip_num; 725 #define CHIP_NUM_58818 0xd818 726 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) 727 728 uint32_t fw_cap; 729 #define BNXT_FW_CAP_HOT_RESET BIT(0) 730 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 731 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 732 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 733 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) 734 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 735 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 736 #define BNXT_FW_CAP_LINK_ADMIN BIT(7) 737 #define BNXT_FW_CAP_TRUFLOW_EN BIT(8) 738 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9) 739 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 740 741 pthread_mutex_t flow_lock; 742 743 uint32_t vnic_cap_flags; 744 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 745 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) 746 #define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) 747 #define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3) 748 #define BNXT_RX_VLAN_STRIP_EN(bp) ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 749 unsigned int rx_nr_rings; 750 unsigned int rx_cp_nr_rings; 751 unsigned int rx_num_qs_per_vnic; 752 struct bnxt_rx_queue **rx_queues; 753 const void *rx_mem_zone; 754 struct rx_port_stats *hw_rx_port_stats; 755 rte_iova_t hw_rx_port_stats_map; 756 struct rx_port_stats_ext *hw_rx_port_stats_ext; 757 rte_iova_t hw_rx_port_stats_ext_map; 758 uint16_t fw_rx_port_stats_ext_size; 759 760 unsigned int tx_nr_rings; 761 unsigned int tx_cp_nr_rings; 762 struct bnxt_tx_queue **tx_queues; 763 const void *tx_mem_zone; 764 struct tx_port_stats *hw_tx_port_stats; 765 rte_iova_t hw_tx_port_stats_map; 766 struct tx_port_stats_ext *hw_tx_port_stats_ext; 767 rte_iova_t hw_tx_port_stats_ext_map; 768 uint16_t fw_tx_port_stats_ext_size; 769 770 /* Default completion ring */ 771 struct bnxt_cp_ring_info *async_cp_ring; 772 struct bnxt_cp_ring_info *rxtx_nq_ring; 773 uint32_t max_ring_grps; 774 struct bnxt_ring_grp_info *grp_info; 775 776 uint16_t nr_vnics; 777 778 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 779 struct bnxt_vnic_info *vnic_info; 780 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 781 782 struct bnxt_filter_info *filter_info; 783 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 784 785 struct bnxt_irq *irq_tbl; 786 787 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 788 789 uint16_t chimp_cmd_seq; 790 uint16_t kong_cmd_seq; 791 void *hwrm_cmd_resp_addr; 792 rte_iova_t hwrm_cmd_resp_dma_addr; 793 void *hwrm_short_cmd_req_addr; 794 rte_iova_t hwrm_short_cmd_req_dma_addr; 795 rte_spinlock_t hwrm_lock; 796 /* synchronize between dev_configure_op and int handler */ 797 pthread_mutex_t def_cp_lock; 798 /* synchronize between dev_start_op and async evt handler 799 * Locking sequence in async evt handler will be 800 * def_cp_lock 801 * health_check_lock 802 */ 803 pthread_mutex_t health_check_lock; 804 /* synchronize between dev_stop/dev_close_op and 805 * error recovery thread triggered as part of 806 * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 807 */ 808 pthread_mutex_t err_recovery_lock; 809 uint16_t max_req_len; 810 uint16_t max_resp_len; 811 uint16_t hwrm_max_ext_req_len; 812 813 /* default command timeout value of 500ms */ 814 #define DFLT_HWRM_CMD_TIMEOUT 500000 815 /* short command timeout value of 50ms */ 816 #define SHORT_HWRM_CMD_TIMEOUT 50000 817 /* default HWRM request timeout value */ 818 uint32_t hwrm_cmd_timeout; 819 820 struct bnxt_link_info *link_info; 821 struct bnxt_cos_queue_info *rx_cos_queue; 822 struct bnxt_cos_queue_info *tx_cos_queue; 823 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 824 uint8_t rx_cosq_cnt; 825 uint8_t max_tc; 826 uint8_t max_lltc; 827 uint8_t max_q; 828 829 uint16_t fw_fid; 830 uint16_t max_rsscos_ctx; 831 uint16_t max_cp_rings; 832 uint16_t max_tx_rings; 833 uint16_t max_rx_rings; 834 #define MAX_STINGRAY_RINGS 236U 835 #define BNXT_MAX_VF_REP_RINGS 8 836 837 uint16_t max_nq_rings; 838 uint16_t max_l2_ctx; 839 uint16_t max_rx_em_flows; 840 uint16_t max_vnics; 841 uint16_t max_stat_ctx; 842 uint16_t max_tpa_v2; 843 uint16_t first_vf_id; 844 uint16_t vlan; 845 #define BNXT_OUTER_TPID_MASK 0x0000ffff 846 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 847 #define BNXT_OUTER_TPID_BD_SHFT 16 848 uint32_t outer_tpid_bd; 849 struct bnxt_pf_info *pf; 850 struct bnxt_parent_info *parent; 851 uint8_t port_cnt; 852 uint8_t vxlan_port_cnt; 853 uint8_t geneve_port_cnt; 854 uint16_t vxlan_port; 855 uint16_t geneve_port; 856 uint16_t vxlan_fw_dst_port_id; 857 uint16_t geneve_fw_dst_port_id; 858 uint32_t fw_ver; 859 uint32_t hwrm_spec_code; 860 861 struct bnxt_led_info *leds; 862 struct bnxt_ptp_cfg *ptp_cfg; 863 uint16_t vf_resv_strategy; 864 struct bnxt_ctx_mem_info *ctx; 865 866 uint16_t fw_reset_min_msecs; 867 uint16_t fw_reset_max_msecs; 868 uint16_t switch_domain_id; 869 uint16_t num_reps; 870 struct bnxt_rep_info *rep_info; 871 uint16_t *cfa_code_map; 872 /* Struct to hold adapter error recovery related info */ 873 struct bnxt_error_recovery_info *recovery_info; 874 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 875 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 876 #define BNXT_FLOW_ID_MASK 0x0000ffff 877 struct bnxt_mark_info *mark_table; 878 879 #define BNXT_SVIF_INVALID 0xFFFF 880 uint16_t func_svif; 881 uint16_t port_svif; 882 883 struct tf tfp; 884 struct tf tfp_shared; 885 struct bnxt_ulp_context *ulp_ctx; 886 struct bnxt_flow_stat_info *flow_stat; 887 uint16_t max_num_kflows; 888 uint8_t app_id; 889 uint16_t tx_cfa_action; 890 struct bnxt_ring_stats *prev_rx_ring_stats; 891 struct bnxt_ring_stats *prev_tx_ring_stats; 892 }; 893 894 static 895 inline uint16_t bnxt_max_rings(struct bnxt *bp) 896 { 897 uint16_t max_tx_rings = bp->max_tx_rings; 898 uint16_t max_rx_rings = bp->max_rx_rings; 899 uint16_t max_cp_rings = bp->max_cp_rings; 900 uint16_t max_rings; 901 902 /* For the sake of symmetry: 903 * max Tx rings == max Rx rings, one stat ctx for each. 904 */ 905 if (BNXT_STINGRAY(bp)) { 906 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U, 907 MAX_STINGRAY_RINGS), 908 bp->max_stat_ctx / 2U); 909 } else { 910 max_rx_rings = RTE_MIN(max_rx_rings / 2U, 911 bp->max_stat_ctx / 2U); 912 } 913 914 /* 915 * RSS table size in Thor is 512. 916 * Cap max Rx rings to the same value for RSS. 917 */ 918 if (BNXT_CHIP_P5(bp)) 919 max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5); 920 921 max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); 922 if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp)) 923 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp); 924 max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings); 925 926 return max_rings; 927 } 928 929 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 930 931 /** 932 * Structure to store private data for each VF representor instance 933 */ 934 struct bnxt_representor { 935 uint16_t switch_domain_id; 936 uint16_t vf_id; 937 #define BNXT_REP_IS_PF BIT(0) 938 #define BNXT_REP_Q_R2F_VALID BIT(1) 939 #define BNXT_REP_Q_F2R_VALID BIT(2) 940 #define BNXT_REP_FC_R2F_VALID BIT(3) 941 #define BNXT_REP_FC_F2R_VALID BIT(4) 942 #define BNXT_REP_BASED_PF_VALID BIT(5) 943 uint32_t flags; 944 uint16_t fw_fid; 945 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 946 uint16_t dflt_vnic_id; 947 uint16_t svif; 948 uint16_t vfr_tx_cfa_action; 949 uint8_t parent_pf_idx; /* Logical PF index */ 950 uint32_t dpdk_port_id; 951 uint32_t rep_based_pf; 952 uint8_t rep_q_r2f; 953 uint8_t rep_q_f2r; 954 uint8_t rep_fc_r2f; 955 uint8_t rep_fc_f2r; 956 /* Private data store of associated PF/Trusted VF */ 957 struct rte_eth_dev *parent_dev; 958 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 959 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 960 struct bnxt_rx_queue **rx_queues; 961 unsigned int rx_nr_rings; 962 unsigned int tx_nr_rings; 963 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 964 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 965 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 966 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 967 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 968 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 969 }; 970 971 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) 972 #define BNXT_REP_BASED_PF(vfr_bp) \ 973 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID) 974 975 struct bnxt_vf_rep_tx_queue { 976 struct bnxt_tx_queue *txq; 977 struct bnxt_representor *bp; 978 }; 979 980 #define I2C_DEV_ADDR_A0 0xa0 981 #define I2C_DEV_ADDR_A2 0xa2 982 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 983 #define SFF_MODULE_ID_SFP 0x3 984 #define SFF_MODULE_ID_QSFP 0xc 985 #define SFF_MODULE_ID_QSFP_PLUS 0xd 986 #define SFF_MODULE_ID_QSFP28 0x11 987 #define SFF8636_FLATMEM_OFFSET 0x2 988 #define SFF8636_FLATMEM_MASK 0x4 989 #define SFF8636_OPT_PAGES_OFFSET 0xc3 990 #define SFF8636_PAGE1_MASK 0x40 991 #define SFF8636_PAGE2_MASK 0x80 992 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 993 994 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 995 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 996 bool exp_link_status); 997 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 998 int is_bnxt_in_error(struct bnxt *bp); 999 1000 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 1001 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 1002 void bnxt_schedule_fw_health_check(struct bnxt *bp); 1003 1004 bool is_bnxt_supported(struct rte_eth_dev *dev); 1005 bool bnxt_stratus_device(struct bnxt *bp); 1006 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 1007 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 1008 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1009 int wait_to_complete); 1010 uint16_t bnxt_dummy_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1011 uint16_t nb_pkts); 1012 uint16_t bnxt_dummy_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 1013 uint16_t nb_pkts); 1014 1015 extern const struct rte_flow_ops bnxt_flow_ops; 1016 1017 #define bnxt_acquire_flow_lock(bp) \ 1018 pthread_mutex_lock(&(bp)->flow_lock) 1019 1020 #define bnxt_release_flow_lock(bp) \ 1021 pthread_mutex_unlock(&(bp)->flow_lock) 1022 1023 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 1024 if ((vnic_id) >= (bp)->max_vnics) { \ 1025 rte_flow_error_set(error, \ 1026 EINVAL, \ 1027 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 1028 NULL, \ 1029 "Group id is invalid!"); \ 1030 rc = -rte_errno; \ 1031 goto ret; \ 1032 } \ 1033 } while (0) 1034 1035 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 1036 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1037 1038 extern int bnxt_logtype_driver; 1039 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 1040 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 1041 __func__, ## args) 1042 1043 #define PMD_DRV_LOG(level, fmt, args...) \ 1044 PMD_DRV_LOG_RAW(level, fmt, ## args) 1045 1046 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 1047 int32_t bnxt_ulp_port_init(struct bnxt *bp); 1048 void bnxt_ulp_port_deinit(struct bnxt *bp); 1049 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 1050 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 1051 int32_t 1052 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 1053 int32_t 1054 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); 1055 void bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, 1056 uint8_t *mac, uint8_t *parent_mac); 1057 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); 1058 uint16_t bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); 1059 struct bnxt *bnxt_get_bp(uint16_t port); 1060 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, 1061 enum bnxt_ulp_intf_type type); 1062 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); 1063 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); 1064 uint16_t bnxt_get_phy_port_id(uint16_t port); 1065 uint16_t bnxt_get_vport(uint16_t port); 1066 enum bnxt_ulp_intf_type 1067 bnxt_get_interface_type(uint16_t port); 1068 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); 1069 1070 void bnxt_cancel_fc_thread(struct bnxt *bp); 1071 void bnxt_flow_cnt_alarm_cb(void *arg); 1072 int bnxt_flow_stats_req(struct bnxt *bp); 1073 int bnxt_flow_stats_cnt(struct bnxt *bp); 1074 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 1075 int bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 1076 const struct rte_flow_ops **ops); 1077 1078 #endif 1079