1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <rte_ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 27 /* Vendor ID */ 28 #define PCI_VENDOR_ID_BROADCOM 0x14E4 29 30 /* Device IDs */ 31 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 33 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 34 #define BROADCOM_DEV_ID_57414_VF 0x16c1 35 #define BROADCOM_DEV_ID_57301 0x16c8 36 #define BROADCOM_DEV_ID_57302 0x16c9 37 #define BROADCOM_DEV_ID_57304_PF 0x16ca 38 #define BROADCOM_DEV_ID_57304_VF 0x16cb 39 #define BROADCOM_DEV_ID_57417_MF 0x16cc 40 #define BROADCOM_DEV_ID_NS2 0x16cd 41 #define BROADCOM_DEV_ID_57311 0x16ce 42 #define BROADCOM_DEV_ID_57312 0x16cf 43 #define BROADCOM_DEV_ID_57402 0x16d0 44 #define BROADCOM_DEV_ID_57404 0x16d1 45 #define BROADCOM_DEV_ID_57406_PF 0x16d2 46 #define BROADCOM_DEV_ID_57406_VF 0x16d3 47 #define BROADCOM_DEV_ID_57402_MF 0x16d4 48 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 49 #define BROADCOM_DEV_ID_57412 0x16d6 50 #define BROADCOM_DEV_ID_57414 0x16d7 51 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 52 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 53 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 54 #define BROADCOM_DEV_ID_57412_MF 0x16de 55 #define BROADCOM_DEV_ID_57314 0x16df 56 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 57 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 58 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 59 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 60 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 61 #define BROADCOM_DEV_ID_57404_MF 0x16e7 62 #define BROADCOM_DEV_ID_57406_MF 0x16e8 63 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 64 #define BROADCOM_DEV_ID_57407_MF 0x16ea 65 #define BROADCOM_DEV_ID_57414_MF 0x16ec 66 #define BROADCOM_DEV_ID_57416_MF 0x16ee 67 #define BROADCOM_DEV_ID_57508 0x1750 68 #define BROADCOM_DEV_ID_57504 0x1751 69 #define BROADCOM_DEV_ID_57502 0x1752 70 #define BROADCOM_DEV_ID_57508_MF1 0x1800 71 #define BROADCOM_DEV_ID_57504_MF1 0x1801 72 #define BROADCOM_DEV_ID_57502_MF1 0x1802 73 #define BROADCOM_DEV_ID_57508_MF2 0x1803 74 #define BROADCOM_DEV_ID_57504_MF2 0x1804 75 #define BROADCOM_DEV_ID_57502_MF2 0x1805 76 #define BROADCOM_DEV_ID_57500_VF1 0x1806 77 #define BROADCOM_DEV_ID_57500_VF2 0x1807 78 #define BROADCOM_DEV_ID_58802 0xd802 79 #define BROADCOM_DEV_ID_58804 0xd804 80 #define BROADCOM_DEV_ID_58808 0x16f0 81 #define BROADCOM_DEV_ID_58802_VF 0xd800 82 83 #define BNXT_MAX_MTU 9574 84 #define VLAN_TAG_SIZE 4 85 #define BNXT_NUM_VLANS 2 86 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 87 RTE_ETHER_CRC_LEN +\ 88 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 89 /* FW adds extra 4 bytes for FCS */ 90 #define BNXT_VNIC_MRU(mtu)\ 91 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 92 #define BNXT_VF_RSV_NUM_RSS_CTX 1 93 #define BNXT_VF_RSV_NUM_L2_CTX 4 94 /* TODO: For now, do not support VMDq/RFS on VFs. */ 95 #define BNXT_VF_RSV_NUM_VNIC 1 96 #define BNXT_MAX_LED 4 97 #define BNXT_MIN_RING_DESC 16 98 #define BNXT_MAX_TX_RING_DESC 4096 99 #define BNXT_MAX_RX_RING_DESC 8192 100 #define BNXT_DB_SIZE 0x80 101 102 #define TPA_MAX_AGGS 64 103 #define TPA_MAX_AGGS_TH 1024 104 105 #define TPA_MAX_NUM_SEGS 32 106 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 107 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 108 109 #define BNXT_TPA_MAX_AGGS(bp) \ 110 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \ 111 TPA_MAX_AGGS) 112 113 #define BNXT_TPA_MAX_SEGS(bp) \ 114 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \ 115 TPA_MAX_SEGS) 116 117 #ifdef RTE_ARCH_ARM64 118 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1) 119 #else 120 #define BNXT_NUM_ASYNC_CPR(bp) 1 121 #endif 122 123 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 124 #ifdef RTE_EXEC_ENV_FREEBSD 125 #ifdef BNXT_NUM_ASYNC_CPR 126 #undef BNXT_NUM_ASYNC_CPR 127 #endif 128 #define BNXT_NUM_ASYNC_CPR(bp) 0 129 #endif 130 131 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 132 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 133 134 /* Chimp Communication Channel */ 135 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 136 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 137 /* Kong Communication Channel */ 138 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 139 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 140 141 #define BNXT_INT_LAT_TMR_MIN 75 142 #define BNXT_INT_LAT_TMR_MAX 150 143 #define BNXT_NUM_CMPL_AGGR_INT 36 144 #define BNXT_CMPL_AGGR_DMA_TMR 37 145 #define BNXT_NUM_CMPL_DMA_AGGR 36 146 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 147 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 148 149 struct bnxt_led_info { 150 uint8_t num_leds; 151 uint8_t led_id; 152 uint8_t led_type; 153 uint8_t led_group_id; 154 uint8_t unused; 155 uint16_t led_state_caps; 156 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 157 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 158 159 uint16_t led_color_caps; 160 }; 161 162 struct bnxt_led_cfg { 163 uint8_t led_id; 164 uint8_t led_state; 165 uint8_t led_color; 166 uint8_t unused; 167 uint16_t led_blink_on; 168 uint16_t led_blink_off; 169 uint8_t led_group_id; 170 uint8_t rsvd; 171 }; 172 173 #define BNXT_LED_DFLT_ENA \ 174 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 175 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 176 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 177 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 178 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 179 180 #define BNXT_LED_DFLT_ENA_SHIFT 6 181 182 #define BNXT_LED_DFLT_ENABLES(x) \ 183 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 184 185 enum bnxt_hw_context { 186 HW_CONTEXT_NONE = 0, 187 HW_CONTEXT_IS_RSS = 1, 188 HW_CONTEXT_IS_COS = 2, 189 HW_CONTEXT_IS_LB = 3, 190 }; 191 192 struct bnxt_vlan_table_entry { 193 uint16_t tpid; 194 uint16_t vid; 195 } __rte_packed; 196 197 struct bnxt_vlan_antispoof_table_entry { 198 uint16_t tpid; 199 uint16_t vid; 200 uint16_t mask; 201 } __rte_packed; 202 203 struct bnxt_child_vf_info { 204 void *req_buf; 205 struct bnxt_vlan_table_entry *vlan_table; 206 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 207 STAILQ_HEAD(, bnxt_filter_info) filter; 208 uint32_t func_cfg_flags; 209 uint32_t l2_rx_mask; 210 uint16_t fid; 211 uint16_t max_tx_rate; 212 uint16_t dflt_vlan; 213 uint16_t vlan_count; 214 uint8_t mac_spoof_en; 215 uint8_t vlan_spoof_en; 216 bool random_mac; 217 bool persist_stats; 218 }; 219 220 struct bnxt_pf_info { 221 #define BNXT_FIRST_PF_FID 1 222 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 223 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 224 #define BNXT_FIRST_VF_FID 128 225 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 226 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 227 BNXT_PF_RINGS_USED(bp)) 228 uint16_t port_id; 229 uint16_t first_vf_id; 230 uint16_t active_vfs; 231 uint16_t max_vfs; 232 uint16_t total_vfs; /* Total VFs possible. 233 * Not necessarily enabled. 234 */ 235 uint32_t func_cfg_flags; 236 void *vf_req_buf; 237 rte_iova_t vf_req_buf_dma_addr; 238 uint32_t vf_req_fwd[8]; 239 uint16_t total_vnics; 240 struct bnxt_child_vf_info *vf_info; 241 #define BNXT_EVB_MODE_NONE 0 242 #define BNXT_EVB_MODE_VEB 1 243 #define BNXT_EVB_MODE_VEPA 2 244 uint8_t evb_mode; 245 }; 246 247 /* Max wait time for link up is 10s and link down is 500ms */ 248 #define BNXT_LINK_UP_WAIT_CNT 200 249 #define BNXT_LINK_DOWN_WAIT_CNT 10 250 #define BNXT_LINK_WAIT_INTERVAL 50 251 struct bnxt_link_info { 252 uint32_t phy_flags; 253 uint8_t mac_type; 254 uint8_t phy_link_status; 255 uint8_t loop_back; 256 uint8_t link_up; 257 uint8_t duplex; 258 uint8_t pause; 259 uint8_t force_pause; 260 uint8_t auto_pause; 261 uint8_t auto_mode; 262 #define PHY_VER_LEN 3 263 uint8_t phy_ver[PHY_VER_LEN]; 264 uint16_t link_speed; 265 uint16_t support_speeds; 266 uint16_t auto_link_speed; 267 uint16_t force_link_speed; 268 uint16_t auto_link_speed_mask; 269 uint32_t preemphasis; 270 uint8_t phy_type; 271 uint8_t media_type; 272 }; 273 274 #define BNXT_COS_QUEUE_COUNT 8 275 struct bnxt_cos_queue_info { 276 uint8_t id; 277 uint8_t profile; 278 }; 279 280 struct rte_flow { 281 STAILQ_ENTRY(rte_flow) next; 282 struct bnxt_filter_info *filter; 283 struct bnxt_vnic_info *vnic; 284 }; 285 286 #define BNXT_PTP_FLAGS_PATH_TX 0x0 287 #define BNXT_PTP_FLAGS_PATH_RX 0x1 288 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 289 290 struct bnxt_ptp_cfg { 291 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 292 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 293 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 294 struct rte_timecounter tc; 295 struct rte_timecounter tx_tstamp_tc; 296 struct rte_timecounter rx_tstamp_tc; 297 struct bnxt *bp; 298 #define BNXT_MAX_TX_TS 1 299 uint16_t rxctl; 300 #define BNXT_PTP_MSG_SYNC BIT(0) 301 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 302 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 303 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 304 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 305 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 306 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 307 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 308 #define BNXT_PTP_MSG_SIGNALING BIT(12) 309 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 310 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 311 BNXT_PTP_MSG_DELAY_REQ | \ 312 BNXT_PTP_MSG_PDELAY_REQ | \ 313 BNXT_PTP_MSG_PDELAY_RESP) 314 uint8_t tx_tstamp_en:1; 315 int rx_filter; 316 317 #define BNXT_PTP_RX_TS_L 0 318 #define BNXT_PTP_RX_TS_H 1 319 #define BNXT_PTP_RX_SEQ 2 320 #define BNXT_PTP_RX_FIFO 3 321 #define BNXT_PTP_RX_FIFO_PENDING 0x1 322 #define BNXT_PTP_RX_FIFO_ADV 4 323 #define BNXT_PTP_RX_REGS 5 324 325 #define BNXT_PTP_TX_TS_L 0 326 #define BNXT_PTP_TX_TS_H 1 327 #define BNXT_PTP_TX_SEQ 2 328 #define BNXT_PTP_TX_FIFO 3 329 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 330 #define BNXT_PTP_TX_REGS 4 331 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 332 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 333 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 334 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 335 336 /* On Thor, the Rx timestamp is present in the Rx completion record */ 337 uint64_t rx_timestamp; 338 }; 339 340 struct bnxt_coal { 341 uint16_t num_cmpl_aggr_int; 342 uint16_t num_cmpl_dma_aggr; 343 uint16_t num_cmpl_dma_aggr_during_int; 344 uint16_t int_lat_tmr_max; 345 uint16_t int_lat_tmr_min; 346 uint16_t cmpl_aggr_dma_tmr; 347 uint16_t cmpl_aggr_dma_tmr_during_int; 348 }; 349 350 /* 64-bit doorbell */ 351 #define DBR_XID_SFT 32 352 #define DBR_PATH_L2 (0x1ULL << 56) 353 #define DBR_TYPE_SQ (0x0ULL << 60) 354 #define DBR_TYPE_SRQ (0x2ULL << 60) 355 #define DBR_TYPE_CQ (0x4ULL << 60) 356 #define DBR_TYPE_NQ (0xaULL << 60) 357 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 358 359 #define BNXT_RSS_TBL_SIZE_THOR 512 360 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64 361 #define BNXT_MAX_RSS_CTXTS_THOR \ 362 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR) 363 364 #define BNXT_MAX_TC 8 365 #define BNXT_MAX_QUEUE 8 366 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) 367 #define BNXT_PAGE_SHFT 12 368 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 369 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 370 371 #define PTU_PTE_VALID 0x1UL 372 #define PTU_PTE_LAST 0x2UL 373 #define PTU_PTE_NEXT_TO_LAST 0x4UL 374 375 struct bnxt_ring_mem_info { 376 int nr_pages; 377 int page_size; 378 uint32_t flags; 379 #define BNXT_RMEM_VALID_PTE_FLAG 1 380 #define BNXT_RMEM_RING_PTE_FLAG 2 381 382 void **pg_arr; 383 rte_iova_t *dma_arr; 384 const struct rte_memzone *mz; 385 386 uint64_t *pg_tbl; 387 rte_iova_t pg_tbl_map; 388 const struct rte_memzone *pg_tbl_mz; 389 390 int vmem_size; 391 void **vmem; 392 }; 393 394 struct bnxt_ctx_pg_info { 395 uint32_t entries; 396 void *ctx_pg_arr[MAX_CTX_PAGES]; 397 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 398 struct bnxt_ring_mem_info ring_mem; 399 }; 400 401 struct bnxt_ctx_mem_info { 402 uint32_t qp_max_entries; 403 uint16_t qp_min_qp1_entries; 404 uint16_t qp_max_l2_entries; 405 uint16_t qp_entry_size; 406 uint16_t srq_max_l2_entries; 407 uint32_t srq_max_entries; 408 uint16_t srq_entry_size; 409 uint16_t cq_max_l2_entries; 410 uint32_t cq_max_entries; 411 uint16_t cq_entry_size; 412 uint16_t vnic_max_vnic_entries; 413 uint16_t vnic_max_ring_table_entries; 414 uint16_t vnic_entry_size; 415 uint32_t stat_max_entries; 416 uint16_t stat_entry_size; 417 uint16_t tqm_entry_size; 418 uint32_t tqm_min_entries_per_ring; 419 uint32_t tqm_max_entries_per_ring; 420 uint32_t mrav_max_entries; 421 uint16_t mrav_entry_size; 422 uint16_t tim_entry_size; 423 uint32_t tim_max_entries; 424 uint8_t tqm_entries_multiple; 425 uint8_t tqm_fp_rings_count; 426 427 uint32_t flags; 428 #define BNXT_CTX_FLAG_INITED 0x01 429 430 struct bnxt_ctx_pg_info qp_mem; 431 struct bnxt_ctx_pg_info srq_mem; 432 struct bnxt_ctx_pg_info cq_mem; 433 struct bnxt_ctx_pg_info vnic_mem; 434 struct bnxt_ctx_pg_info stat_mem; 435 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; 436 }; 437 438 struct bnxt_ctx_mem_buf_info { 439 void *va; 440 rte_iova_t dma; 441 uint16_t ctx_id; 442 size_t size; 443 }; 444 445 /* Maximum Firmware Reset bail out value in milliseconds */ 446 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 447 /* Minimum time required for the firmware readiness in milliseconds */ 448 #define BNXT_MIN_FW_READY_TIMEOUT 2000 449 /* Frequency for the firmware readiness check in milliseconds */ 450 #define BNXT_FW_READY_WAIT_INTERVAL 100 451 452 #define US_PER_MS 1000 453 #define NS_PER_US 1000 454 455 struct bnxt_error_recovery_info { 456 /* All units in milliseconds */ 457 uint32_t driver_polling_freq; 458 uint32_t master_func_wait_period; 459 uint32_t normal_func_wait_period; 460 uint32_t master_func_wait_period_after_reset; 461 uint32_t max_bailout_time_after_reset; 462 #define BNXT_FW_STATUS_REG 0 463 #define BNXT_FW_HEARTBEAT_CNT_REG 1 464 #define BNXT_FW_RECOVERY_CNT_REG 2 465 #define BNXT_FW_RESET_INPROG_REG 3 466 #define BNXT_FW_STATUS_REG_CNT 4 467 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 468 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 469 uint32_t reset_inprogress_reg_mask; 470 #define BNXT_NUM_RESET_REG 16 471 uint8_t reg_array_cnt; 472 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 473 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 474 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 475 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 476 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 477 #define BNXT_FLAG_MASTER_FUNC BIT(2) 478 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 479 uint32_t flags; 480 481 uint32_t last_heart_beat; 482 uint32_t last_reset_counter; 483 }; 484 485 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 486 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 487 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 488 #define BNXT_IF_CHANGE_RETRY_COUNT 40 489 490 struct bnxt_mark_info { 491 uint32_t mark_id; 492 bool valid; 493 }; 494 495 /* address space location of register */ 496 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 497 /* register is located in PCIe config space */ 498 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 499 /* register is located in GRC address space */ 500 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 501 /* register is located in BAR0 */ 502 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 503 /* register is located in BAR1 */ 504 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 505 506 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 507 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 508 509 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 510 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 511 512 #define BNXT_GRCP_BASE_MASK 0xfffff000 513 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 514 515 #define BNXT_FW_STATUS_HEALTHY 0x8000 516 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 517 518 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 519 520 struct bnxt_flow_stat_info { 521 uint16_t max_fc; 522 uint16_t flow_count; 523 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 524 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 525 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 526 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 527 }; 528 529 struct bnxt { 530 void *bar0; 531 532 struct rte_eth_dev *eth_dev; 533 struct rte_pci_device *pdev; 534 void *doorbell_base; 535 536 uint32_t flags; 537 #define BNXT_FLAG_REGISTERED BIT(0) 538 #define BNXT_FLAG_VF BIT(1) 539 #define BNXT_FLAG_PORT_STATS BIT(2) 540 #define BNXT_FLAG_JUMBO BIT(3) 541 #define BNXT_FLAG_SHORT_CMD BIT(4) 542 #define BNXT_FLAG_UPDATE_HASH BIT(5) 543 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 544 #define BNXT_FLAG_MULTI_HOST BIT(7) 545 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 546 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 547 #define BNXT_FLAG_KONG_MB_EN BIT(10) 548 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 549 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 550 #define BNXT_FLAG_THOR_CHIP BIT(13) 551 #define BNXT_FLAG_STINGRAY BIT(14) 552 #define BNXT_FLAG_FW_RESET BIT(15) 553 #define BNXT_FLAG_FATAL_ERROR BIT(16) 554 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 555 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 556 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 557 #define BNXT_FLAG_NEW_RM BIT(20) 558 #define BNXT_FLAG_NPAR_PF BIT(21) 559 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 560 #define BNXT_FLAG_FC_THREAD BIT(23) 561 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 562 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 563 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 564 #define BNXT_FLAG_TRUFLOW_EN BIT(27) 565 #define BNXT_FLAG_GFID_ENABLE BIT(28) 566 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 567 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 568 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 569 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 570 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 571 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 572 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 573 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 574 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP) 575 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 576 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) 577 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) 578 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 579 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 580 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) 581 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 582 583 uint32_t fw_cap; 584 #define BNXT_FW_CAP_HOT_RESET BIT(0) 585 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 586 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 587 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 588 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 589 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 590 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(7) 591 592 uint32_t flow_flags; 593 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0) 594 pthread_mutex_t flow_lock; 595 596 uint32_t vnic_cap_flags; 597 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 598 unsigned int rx_nr_rings; 599 unsigned int rx_cp_nr_rings; 600 unsigned int rx_num_qs_per_vnic; 601 struct bnxt_rx_queue **rx_queues; 602 const void *rx_mem_zone; 603 struct rx_port_stats *hw_rx_port_stats; 604 rte_iova_t hw_rx_port_stats_map; 605 struct rx_port_stats_ext *hw_rx_port_stats_ext; 606 rte_iova_t hw_rx_port_stats_ext_map; 607 uint16_t fw_rx_port_stats_ext_size; 608 609 unsigned int tx_nr_rings; 610 unsigned int tx_cp_nr_rings; 611 struct bnxt_tx_queue **tx_queues; 612 const void *tx_mem_zone; 613 struct tx_port_stats *hw_tx_port_stats; 614 rte_iova_t hw_tx_port_stats_map; 615 struct tx_port_stats_ext *hw_tx_port_stats_ext; 616 rte_iova_t hw_tx_port_stats_ext_map; 617 uint16_t fw_tx_port_stats_ext_size; 618 619 /* Default completion ring */ 620 struct bnxt_cp_ring_info *async_cp_ring; 621 struct bnxt_cp_ring_info *rxtx_nq_ring; 622 uint32_t max_ring_grps; 623 struct bnxt_ring_grp_info *grp_info; 624 625 unsigned int nr_vnics; 626 627 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 628 struct bnxt_vnic_info *vnic_info; 629 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 630 631 struct bnxt_filter_info *filter_info; 632 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 633 634 struct bnxt_irq *irq_tbl; 635 636 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 637 638 uint16_t chimp_cmd_seq; 639 uint16_t kong_cmd_seq; 640 void *hwrm_cmd_resp_addr; 641 rte_iova_t hwrm_cmd_resp_dma_addr; 642 void *hwrm_short_cmd_req_addr; 643 rte_iova_t hwrm_short_cmd_req_dma_addr; 644 rte_spinlock_t hwrm_lock; 645 pthread_mutex_t def_cp_lock; 646 uint16_t max_req_len; 647 uint16_t max_resp_len; 648 uint16_t hwrm_max_ext_req_len; 649 650 /* default command timeout value of 500ms */ 651 #define DFLT_HWRM_CMD_TIMEOUT 500000 652 /* short command timeout value of 50ms */ 653 #define SHORT_HWRM_CMD_TIMEOUT 50000 654 /* default HWRM request timeout value */ 655 uint32_t hwrm_cmd_timeout; 656 657 struct bnxt_link_info *link_info; 658 struct bnxt_cos_queue_info *rx_cos_queue; 659 struct bnxt_cos_queue_info *tx_cos_queue; 660 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 661 uint8_t rx_cosq_cnt; 662 uint8_t max_tc; 663 uint8_t max_lltc; 664 uint8_t max_q; 665 666 uint16_t fw_fid; 667 uint16_t max_rsscos_ctx; 668 uint16_t max_cp_rings; 669 uint16_t max_tx_rings; 670 uint16_t max_rx_rings; 671 #define MAX_STINGRAY_RINGS 128U 672 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */ 673 #define BNXT_MAX_RX_RINGS(bp) \ 674 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \ 675 MAX_STINGRAY_RINGS), \ 676 bp->max_stat_ctx / 2U) : \ 677 RTE_MIN(bp->max_rx_rings / 2U, \ 678 bp->max_stat_ctx / 2U)) 679 #define BNXT_MAX_TX_RINGS(bp) \ 680 (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp))) 681 682 #define BNXT_MAX_RINGS(bp) \ 683 (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \ 684 BNXT_MAX_TX_RINGS(bp))) 685 uint16_t max_nq_rings; 686 uint16_t max_l2_ctx; 687 uint16_t max_rx_em_flows; 688 uint16_t max_vnics; 689 uint16_t max_stat_ctx; 690 uint16_t max_tpa_v2; 691 uint16_t first_vf_id; 692 uint16_t vlan; 693 #define BNXT_OUTER_TPID_MASK 0x0000ffff 694 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 695 #define BNXT_OUTER_TPID_BD_SHFT 16 696 uint32_t outer_tpid_bd; 697 struct bnxt_pf_info *pf; 698 uint8_t vxlan_port_cnt; 699 uint8_t geneve_port_cnt; 700 uint16_t vxlan_port; 701 uint16_t geneve_port; 702 uint16_t vxlan_fw_dst_port_id; 703 uint16_t geneve_fw_dst_port_id; 704 uint32_t fw_ver; 705 uint32_t hwrm_spec_code; 706 707 struct bnxt_led_info *leds; 708 struct bnxt_ptp_cfg *ptp_cfg; 709 uint16_t vf_resv_strategy; 710 struct bnxt_ctx_mem_info *ctx; 711 712 uint16_t fw_reset_min_msecs; 713 uint16_t fw_reset_max_msecs; 714 715 /* Struct to hold adapter error recovery related info */ 716 struct bnxt_error_recovery_info *recovery_info; 717 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 718 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 719 #define BNXT_FLOW_ID_MASK 0x0000ffff 720 struct bnxt_mark_info *mark_table; 721 722 #define BNXT_SVIF_INVALID 0xFFFF 723 uint16_t func_svif; 724 uint16_t port_svif; 725 726 struct tf tfp; 727 struct bnxt_ulp_context *ulp_ctx; 728 struct bnxt_flow_stat_info *flow_stat; 729 uint8_t flow_xstat; 730 uint16_t max_num_kflows; 731 }; 732 733 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 734 735 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 736 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 737 bool exp_link_status); 738 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 739 int is_bnxt_in_error(struct bnxt *bp); 740 741 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 742 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 743 void bnxt_schedule_fw_health_check(struct bnxt *bp); 744 745 bool is_bnxt_supported(struct rte_eth_dev *dev); 746 bool bnxt_stratus_device(struct bnxt *bp); 747 extern const struct rte_flow_ops bnxt_flow_ops; 748 #define bnxt_acquire_flow_lock(bp) \ 749 pthread_mutex_lock(&(bp)->flow_lock) 750 751 #define bnxt_release_flow_lock(bp) \ 752 pthread_mutex_unlock(&(bp)->flow_lock) 753 754 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 755 if ((vnic_id) >= (bp)->max_vnics) { \ 756 rte_flow_error_set(error, \ 757 EINVAL, \ 758 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 759 NULL, \ 760 "Group id is invalid!"); \ 761 rc = -rte_errno; \ 762 goto ret; \ 763 } \ 764 } while (0) 765 766 extern int bnxt_logtype_driver; 767 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 768 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 769 __func__, ## args) 770 771 #define PMD_DRV_LOG(level, fmt, args...) \ 772 PMD_DRV_LOG_RAW(level, fmt, ## args) 773 774 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 775 int32_t bnxt_ulp_init(struct bnxt *bp); 776 void bnxt_ulp_deinit(struct bnxt *bp); 777 778 uint16_t bnxt_get_vnic_id(uint16_t port); 779 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif); 780 uint16_t bnxt_get_fw_func_id(uint16_t port); 781 782 void bnxt_cancel_fc_thread(struct bnxt *bp); 783 void bnxt_flow_cnt_alarm_cb(void *arg); 784 int bnxt_flow_stats_req(struct bnxt *bp); 785 int bnxt_flow_stats_cnt(struct bnxt *bp); 786 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 787 #endif 788