1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57304_VF 0x16cb 37 #define BROADCOM_DEV_ID_57417_MF 0x16cc 38 #define BROADCOM_DEV_ID_NS2 0x16cd 39 #define BROADCOM_DEV_ID_57406_VF 0x16d3 40 #define BROADCOM_DEV_ID_57412 0x16d6 41 #define BROADCOM_DEV_ID_57414 0x16d7 42 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 43 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 44 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 45 #define BROADCOM_DEV_ID_57412_MF 0x16de 46 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 47 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 48 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 49 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 50 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 51 #define BROADCOM_DEV_ID_57407_MF 0x16ea 52 #define BROADCOM_DEV_ID_57414_MF 0x16ec 53 #define BROADCOM_DEV_ID_57416_MF 0x16ee 54 #define BROADCOM_DEV_ID_57508 0x1750 55 #define BROADCOM_DEV_ID_57504 0x1751 56 #define BROADCOM_DEV_ID_57502 0x1752 57 #define BROADCOM_DEV_ID_57508_MF1 0x1800 58 #define BROADCOM_DEV_ID_57504_MF1 0x1801 59 #define BROADCOM_DEV_ID_57502_MF1 0x1802 60 #define BROADCOM_DEV_ID_57508_MF2 0x1803 61 #define BROADCOM_DEV_ID_57504_MF2 0x1804 62 #define BROADCOM_DEV_ID_57502_MF2 0x1805 63 #define BROADCOM_DEV_ID_57500_VF1 0x1806 64 #define BROADCOM_DEV_ID_57500_VF2 0x1807 65 #define BROADCOM_DEV_ID_58802 0xd802 66 #define BROADCOM_DEV_ID_58804 0xd804 67 #define BROADCOM_DEV_ID_58808 0x16f0 68 #define BROADCOM_DEV_ID_58802_VF 0xd800 69 #define BROADCOM_DEV_ID_58812 0xd812 70 #define BROADCOM_DEV_ID_58814 0xd814 71 #define BROADCOM_DEV_ID_58818 0xd818 72 #define BROADCOM_DEV_ID_58818_VF 0xd82e 73 74 #define BROADCOM_DEV_957508_N2100 0x5208 75 #define IS_BNXT_DEV_957508_N2100(bp) \ 76 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) 77 78 #define BNXT_MAX_MTU 9574 79 #define VLAN_TAG_SIZE 4 80 #define BNXT_NUM_VLANS 2 81 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 82 RTE_ETHER_CRC_LEN +\ 83 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 84 /* FW adds extra 4 bytes for FCS */ 85 #define BNXT_VNIC_MRU(mtu)\ 86 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 87 #define BNXT_VF_RSV_NUM_RSS_CTX 1 88 #define BNXT_VF_RSV_NUM_L2_CTX 4 89 /* TODO: For now, do not support VMDq/RFS on VFs. */ 90 #define BNXT_VF_RSV_NUM_VNIC 1 91 #define BNXT_MAX_LED 4 92 #define BNXT_MIN_RING_DESC 16 93 #define BNXT_MAX_TX_RING_DESC 4096 94 #define BNXT_MAX_RX_RING_DESC 8192 95 #define BNXT_DB_SIZE 0x80 96 97 #define TPA_MAX_AGGS 64 98 #define TPA_MAX_AGGS_TH 1024 99 100 #define TPA_MAX_NUM_SEGS 32 101 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 102 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 103 104 #define BNXT_TPA_MAX_AGGS(bp) \ 105 (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \ 106 TPA_MAX_AGGS) 107 108 #define BNXT_TPA_MAX_SEGS(bp) \ 109 (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \ 110 TPA_MAX_SEGS) 111 112 /* 113 * Define the number of async completion rings to be used. Set to zero for 114 * configurations in which the maximum number of packet completion rings 115 * for packet completions is desired or when async completion handling 116 * cannot be interrupt-driven. 117 */ 118 #ifdef RTE_EXEC_ENV_FREEBSD 119 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 120 #define BNXT_NUM_ASYNC_CPR(bp) 0U 121 #else 122 #define BNXT_NUM_ASYNC_CPR(bp) 1U 123 #endif 124 125 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 126 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 127 128 /* Chimp Communication Channel */ 129 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 130 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 131 /* Kong Communication Channel */ 132 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 133 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 134 135 #define BNXT_INT_LAT_TMR_MIN 75 136 #define BNXT_INT_LAT_TMR_MAX 150 137 #define BNXT_NUM_CMPL_AGGR_INT 36 138 #define BNXT_CMPL_AGGR_DMA_TMR 37 139 #define BNXT_NUM_CMPL_DMA_AGGR 36 140 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 141 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 142 143 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 144 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 145 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 146 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 147 #define BNXT_DEFAULT_VNIC_ALLOC \ 148 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 149 #define BNXT_DEFAULT_VNIC_FREE \ 150 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 151 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 152 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 153 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 154 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 155 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 156 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 157 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 158 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 159 160 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ 161 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) 162 163 struct bnxt_led_info { 164 uint8_t num_leds; 165 uint8_t led_id; 166 uint8_t led_type; 167 uint8_t led_group_id; 168 uint8_t unused; 169 uint16_t led_state_caps; 170 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 171 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 172 173 uint16_t led_color_caps; 174 }; 175 176 struct bnxt_led_cfg { 177 uint8_t led_id; 178 uint8_t led_state; 179 uint8_t led_color; 180 uint8_t unused; 181 uint16_t led_blink_on; 182 uint16_t led_blink_off; 183 uint8_t led_group_id; 184 uint8_t rsvd; 185 }; 186 187 #define BNXT_LED_DFLT_ENA \ 188 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 189 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 190 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 191 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 192 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 193 194 #define BNXT_LED_DFLT_ENA_SHIFT 6 195 196 #define BNXT_LED_DFLT_ENABLES(x) \ 197 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 198 199 struct bnxt_vlan_table_entry { 200 uint16_t tpid; 201 uint16_t vid; 202 } __rte_packed; 203 204 struct bnxt_vlan_antispoof_table_entry { 205 uint16_t tpid; 206 uint16_t vid; 207 uint16_t mask; 208 } __rte_packed; 209 210 struct bnxt_child_vf_info { 211 void *req_buf; 212 struct bnxt_vlan_table_entry *vlan_table; 213 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 214 STAILQ_HEAD(, bnxt_filter_info) filter; 215 uint32_t func_cfg_flags; 216 uint32_t l2_rx_mask; 217 uint16_t fid; 218 uint16_t max_tx_rate; 219 uint16_t dflt_vlan; 220 uint16_t vlan_count; 221 uint8_t mac_spoof_en; 222 uint8_t vlan_spoof_en; 223 bool random_mac; 224 bool persist_stats; 225 }; 226 227 struct bnxt_parent_info { 228 #define BNXT_PF_FID_INVALID 0xFFFF 229 uint16_t fid; 230 uint16_t vnic; 231 uint16_t port_id; 232 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 233 }; 234 235 struct bnxt_pf_info { 236 #define BNXT_FIRST_PF_FID 1 237 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 238 #define BNXT_MAX_VF_REPS 64 239 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 240 #define BNXT_FIRST_VF_FID 128 241 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 242 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 243 BNXT_PF_RINGS_USED(bp)) 244 uint16_t port_id; 245 uint16_t first_vf_id; 246 uint16_t active_vfs; 247 uint16_t max_vfs; 248 uint16_t total_vfs; /* Total VFs possible. 249 * Not necessarily enabled. 250 */ 251 uint32_t func_cfg_flags; 252 void *vf_req_buf; 253 rte_iova_t vf_req_buf_dma_addr; 254 uint32_t vf_req_fwd[8]; 255 uint16_t total_vnics; 256 struct bnxt_child_vf_info *vf_info; 257 #define BNXT_EVB_MODE_NONE 0 258 #define BNXT_EVB_MODE_VEB 1 259 #define BNXT_EVB_MODE_VEPA 2 260 uint8_t evb_mode; 261 }; 262 263 /* Max wait time for link up is 10s and link down is 500ms */ 264 #define BNXT_MAX_LINK_WAIT_CNT 200 265 #define BNXT_MIN_LINK_WAIT_CNT 10 266 #define BNXT_LINK_WAIT_INTERVAL 50 267 struct bnxt_link_info { 268 uint32_t phy_flags; 269 uint8_t mac_type; 270 uint8_t phy_link_status; 271 uint8_t loop_back; 272 uint8_t link_up; 273 uint8_t duplex; 274 uint8_t pause; 275 uint8_t force_pause; 276 uint8_t auto_pause; 277 uint8_t auto_mode; 278 #define PHY_VER_LEN 3 279 uint8_t phy_ver[PHY_VER_LEN]; 280 uint16_t link_speed; 281 uint16_t support_speeds; 282 uint16_t auto_link_speed; 283 uint16_t force_link_speed; 284 uint16_t auto_link_speed_mask; 285 uint32_t preemphasis; 286 uint8_t phy_type; 287 uint8_t media_type; 288 uint16_t support_auto_speeds; 289 uint8_t link_signal_mode; 290 uint16_t force_pam4_link_speed; 291 uint16_t support_pam4_speeds; 292 uint16_t auto_pam4_link_speeds; 293 uint16_t support_pam4_auto_speeds; 294 uint8_t req_signal_mode; 295 }; 296 297 #define BNXT_COS_QUEUE_COUNT 8 298 struct bnxt_cos_queue_info { 299 uint8_t id; 300 uint8_t profile; 301 }; 302 303 struct rte_flow { 304 STAILQ_ENTRY(rte_flow) next; 305 struct bnxt_filter_info *filter; 306 struct bnxt_vnic_info *vnic; 307 }; 308 309 #define BNXT_PTP_FLAGS_PATH_TX 0x0 310 #define BNXT_PTP_FLAGS_PATH_RX 0x1 311 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 312 313 struct bnxt_ptp_cfg { 314 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 315 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 316 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 317 struct rte_timecounter tc; 318 struct rte_timecounter tx_tstamp_tc; 319 struct rte_timecounter rx_tstamp_tc; 320 struct bnxt *bp; 321 #define BNXT_MAX_TX_TS 1 322 uint16_t rxctl; 323 #define BNXT_PTP_MSG_SYNC BIT(0) 324 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 325 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 326 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 327 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 328 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 329 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 330 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 331 #define BNXT_PTP_MSG_SIGNALING BIT(12) 332 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 333 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 334 BNXT_PTP_MSG_DELAY_REQ | \ 335 BNXT_PTP_MSG_PDELAY_REQ | \ 336 BNXT_PTP_MSG_PDELAY_RESP) 337 uint8_t tx_tstamp_en:1; 338 int rx_filter; 339 340 #define BNXT_PTP_RX_TS_L 0 341 #define BNXT_PTP_RX_TS_H 1 342 #define BNXT_PTP_RX_SEQ 2 343 #define BNXT_PTP_RX_FIFO 3 344 #define BNXT_PTP_RX_FIFO_PENDING 0x1 345 #define BNXT_PTP_RX_FIFO_ADV 4 346 #define BNXT_PTP_RX_REGS 5 347 348 #define BNXT_PTP_TX_TS_L 0 349 #define BNXT_PTP_TX_TS_H 1 350 #define BNXT_PTP_TX_SEQ 2 351 #define BNXT_PTP_TX_FIFO 3 352 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 353 #define BNXT_PTP_TX_REGS 4 354 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 355 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 356 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 357 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 358 359 /* On Thor, the Rx timestamp is present in the Rx completion record */ 360 uint64_t rx_timestamp; 361 }; 362 363 struct bnxt_coal { 364 uint16_t num_cmpl_aggr_int; 365 uint16_t num_cmpl_dma_aggr; 366 uint16_t num_cmpl_dma_aggr_during_int; 367 uint16_t int_lat_tmr_max; 368 uint16_t int_lat_tmr_min; 369 uint16_t cmpl_aggr_dma_tmr; 370 uint16_t cmpl_aggr_dma_tmr_during_int; 371 }; 372 373 /* 64-bit doorbell */ 374 #define DBR_EPOCH_MASK 0x01000000UL 375 #define DBR_EPOCH_SFT 24 376 #define DBR_XID_SFT 32 377 #define DBR_PATH_L2 (0x1ULL << 56) 378 #define DBR_VALID (0x1ULL << 58) 379 #define DBR_TYPE_SQ (0x0ULL << 60) 380 #define DBR_TYPE_SRQ (0x2ULL << 60) 381 #define DBR_TYPE_CQ (0x4ULL << 60) 382 #define DBR_TYPE_NQ (0xaULL << 60) 383 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 384 385 #define DB_PF_OFFSET 0x10000 386 #define DB_VF_OFFSET 0x4000 387 388 #define BNXT_RSS_TBL_SIZE_P5 512U 389 #define BNXT_RSS_ENTRIES_PER_CTX_P5 64 390 #define BNXT_MAX_RSS_CTXTS_P5 \ 391 (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5) 392 393 #define BNXT_MAX_TC 8 394 #define BNXT_MAX_QUEUE 8 395 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) 396 #define BNXT_PAGE_SHFT 12 397 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 398 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 399 400 #define PTU_PTE_VALID 0x1UL 401 #define PTU_PTE_LAST 0x2UL 402 #define PTU_PTE_NEXT_TO_LAST 0x4UL 403 404 struct bnxt_ring_mem_info { 405 int nr_pages; 406 int page_size; 407 uint32_t flags; 408 #define BNXT_RMEM_VALID_PTE_FLAG 1 409 #define BNXT_RMEM_RING_PTE_FLAG 2 410 411 void **pg_arr; 412 rte_iova_t *dma_arr; 413 const struct rte_memzone *mz; 414 415 uint64_t *pg_tbl; 416 rte_iova_t pg_tbl_map; 417 const struct rte_memzone *pg_tbl_mz; 418 419 int vmem_size; 420 void **vmem; 421 }; 422 423 struct bnxt_ctx_pg_info { 424 uint32_t entries; 425 void *ctx_pg_arr[MAX_CTX_PAGES]; 426 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 427 struct bnxt_ring_mem_info ring_mem; 428 }; 429 430 struct bnxt_ctx_mem_info { 431 uint32_t qp_max_entries; 432 uint16_t qp_min_qp1_entries; 433 uint16_t qp_max_l2_entries; 434 uint16_t qp_entry_size; 435 uint16_t srq_max_l2_entries; 436 uint32_t srq_max_entries; 437 uint16_t srq_entry_size; 438 uint16_t cq_max_l2_entries; 439 uint32_t cq_max_entries; 440 uint16_t cq_entry_size; 441 uint16_t vnic_max_vnic_entries; 442 uint16_t vnic_max_ring_table_entries; 443 uint16_t vnic_entry_size; 444 uint32_t stat_max_entries; 445 uint16_t stat_entry_size; 446 uint16_t tqm_entry_size; 447 uint32_t tqm_min_entries_per_ring; 448 uint32_t tqm_max_entries_per_ring; 449 uint32_t mrav_max_entries; 450 uint16_t mrav_entry_size; 451 uint16_t tim_entry_size; 452 uint32_t tim_max_entries; 453 uint8_t tqm_entries_multiple; 454 uint8_t tqm_fp_rings_count; 455 456 uint32_t flags; 457 #define BNXT_CTX_FLAG_INITED 0x01 458 459 struct bnxt_ctx_pg_info qp_mem; 460 struct bnxt_ctx_pg_info srq_mem; 461 struct bnxt_ctx_pg_info cq_mem; 462 struct bnxt_ctx_pg_info vnic_mem; 463 struct bnxt_ctx_pg_info stat_mem; 464 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; 465 }; 466 467 struct bnxt_ctx_mem_buf_info { 468 void *va; 469 rte_iova_t dma; 470 uint16_t ctx_id; 471 size_t size; 472 }; 473 474 /* Maximum Firmware Reset bail out value in milliseconds */ 475 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 476 /* Minimum time required for the firmware readiness in milliseconds */ 477 #define BNXT_MIN_FW_READY_TIMEOUT 2000 478 /* Frequency for the firmware readiness check in milliseconds */ 479 #define BNXT_FW_READY_WAIT_INTERVAL 100 480 481 #define US_PER_MS 1000 482 #define NS_PER_US 1000 483 484 struct bnxt_error_recovery_info { 485 /* All units in milliseconds */ 486 uint32_t driver_polling_freq; 487 uint32_t master_func_wait_period; 488 uint32_t normal_func_wait_period; 489 uint32_t master_func_wait_period_after_reset; 490 uint32_t max_bailout_time_after_reset; 491 #define BNXT_FW_STATUS_REG 0 492 #define BNXT_FW_HEARTBEAT_CNT_REG 1 493 #define BNXT_FW_RECOVERY_CNT_REG 2 494 #define BNXT_FW_RESET_INPROG_REG 3 495 #define BNXT_FW_STATUS_REG_CNT 4 496 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 497 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 498 uint32_t reset_inprogress_reg_mask; 499 #define BNXT_NUM_RESET_REG 16 500 uint8_t reg_array_cnt; 501 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 502 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 503 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 504 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 505 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 506 #define BNXT_FLAG_MASTER_FUNC BIT(2) 507 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 508 uint32_t flags; 509 510 uint32_t last_heart_beat; 511 uint32_t last_reset_counter; 512 }; 513 514 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 515 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 516 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 517 #define BNXT_IF_CHANGE_RETRY_COUNT 40 518 519 struct bnxt_mark_info { 520 uint32_t mark_id; 521 bool valid; 522 }; 523 524 struct bnxt_rep_info { 525 struct rte_eth_dev *vfr_eth_dev; 526 pthread_mutex_t vfr_lock; 527 pthread_mutex_t vfr_start_lock; 528 bool conduit_valid; 529 }; 530 531 /* address space location of register */ 532 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 533 /* register is located in PCIe config space */ 534 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 535 /* register is located in GRC address space */ 536 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 537 /* register is located in BAR0 */ 538 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 539 /* register is located in BAR1 */ 540 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 541 542 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 543 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 544 545 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 546 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 547 548 #define BNXT_GRCP_BASE_MASK 0xfffff000 549 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 550 551 #define BNXT_FW_STATUS_HEALTHY 0x8000 552 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 553 554 #define BNXT_ETH_RSS_SUPPORT ( \ 555 ETH_RSS_IPV4 | \ 556 ETH_RSS_NONFRAG_IPV4_TCP | \ 557 ETH_RSS_NONFRAG_IPV4_UDP | \ 558 ETH_RSS_IPV6 | \ 559 ETH_RSS_NONFRAG_IPV6_TCP | \ 560 ETH_RSS_NONFRAG_IPV6_UDP | \ 561 ETH_RSS_LEVEL_MASK) 562 563 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 564 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 565 DEV_TX_OFFLOAD_TCP_CKSUM | \ 566 DEV_TX_OFFLOAD_UDP_CKSUM | \ 567 DEV_TX_OFFLOAD_TCP_TSO | \ 568 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 569 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 570 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 571 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 572 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 573 DEV_TX_OFFLOAD_QINQ_INSERT | \ 574 DEV_TX_OFFLOAD_MULTI_SEGS) 575 576 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 577 DEV_RX_OFFLOAD_VLAN_STRIP | \ 578 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 579 DEV_RX_OFFLOAD_UDP_CKSUM | \ 580 DEV_RX_OFFLOAD_TCP_CKSUM | \ 581 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 582 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \ 583 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 584 DEV_RX_OFFLOAD_KEEP_CRC | \ 585 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 586 DEV_RX_OFFLOAD_TCP_LRO | \ 587 DEV_RX_OFFLOAD_SCATTER | \ 588 DEV_RX_OFFLOAD_RSS_HASH) 589 590 #define MAX_TABLE_SUPPORT 4 591 #define MAX_DIR_SUPPORT 2 592 struct bnxt_dmabuf_info { 593 uint32_t entry_num; 594 int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT]; 595 }; 596 597 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 598 599 struct bnxt_flow_stat_info { 600 uint16_t max_fc; 601 uint16_t flow_count; 602 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 603 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 604 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 605 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 606 }; 607 608 struct bnxt { 609 void *bar0; 610 611 struct rte_eth_dev *eth_dev; 612 struct rte_pci_device *pdev; 613 void *doorbell_base; 614 int legacy_db_size; 615 616 uint32_t flags; 617 #define BNXT_FLAG_REGISTERED BIT(0) 618 #define BNXT_FLAG_VF BIT(1) 619 #define BNXT_FLAG_PORT_STATS BIT(2) 620 #define BNXT_FLAG_JUMBO BIT(3) 621 #define BNXT_FLAG_SHORT_CMD BIT(4) 622 #define BNXT_FLAG_UPDATE_HASH BIT(5) 623 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 624 #define BNXT_FLAG_MULTI_HOST BIT(7) 625 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 626 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 627 #define BNXT_FLAG_KONG_MB_EN BIT(10) 628 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 629 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 630 #define BNXT_FLAG_CHIP_P5 BIT(13) 631 #define BNXT_FLAG_STINGRAY BIT(14) 632 #define BNXT_FLAG_FW_RESET BIT(15) 633 #define BNXT_FLAG_FATAL_ERROR BIT(16) 634 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 635 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 636 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 637 #define BNXT_FLAG_NEW_RM BIT(20) 638 #define BNXT_FLAG_NPAR_PF BIT(21) 639 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 640 #define BNXT_FLAG_FC_THREAD BIT(23) 641 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 642 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 643 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 644 #define BNXT_FLAG_TRUFLOW_EN BIT(27) 645 #define BNXT_FLAG_GFID_ENABLE BIT(28) 646 #define BNXT_FLAG_RFS_NEEDS_VNIC BIT(29) 647 #define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(30) 648 #define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) 649 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 650 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 651 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 652 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 653 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 654 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 655 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 656 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 657 #define BNXT_CHIP_P5(bp) ((bp)->flags & BNXT_FLAG_CHIP_P5) 658 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 659 #define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp) 660 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp)) 661 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 662 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 663 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) 664 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 665 666 uint16_t chip_num; 667 #define CHIP_NUM_58818 0xd818 668 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) 669 670 uint32_t fw_cap; 671 #define BNXT_FW_CAP_HOT_RESET BIT(0) 672 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 673 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 674 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 675 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) 676 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 677 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 678 #define BNXT_FW_CAP_LINK_ADMIN BIT(7) 679 680 pthread_mutex_t flow_lock; 681 682 uint32_t vnic_cap_flags; 683 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 684 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) 685 #define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) 686 unsigned int rx_nr_rings; 687 unsigned int rx_cp_nr_rings; 688 unsigned int rx_num_qs_per_vnic; 689 struct bnxt_rx_queue **rx_queues; 690 const void *rx_mem_zone; 691 struct rx_port_stats *hw_rx_port_stats; 692 rte_iova_t hw_rx_port_stats_map; 693 struct rx_port_stats_ext *hw_rx_port_stats_ext; 694 rte_iova_t hw_rx_port_stats_ext_map; 695 uint16_t fw_rx_port_stats_ext_size; 696 697 unsigned int tx_nr_rings; 698 unsigned int tx_cp_nr_rings; 699 struct bnxt_tx_queue **tx_queues; 700 const void *tx_mem_zone; 701 struct tx_port_stats *hw_tx_port_stats; 702 rte_iova_t hw_tx_port_stats_map; 703 struct tx_port_stats_ext *hw_tx_port_stats_ext; 704 rte_iova_t hw_tx_port_stats_ext_map; 705 uint16_t fw_tx_port_stats_ext_size; 706 707 /* Default completion ring */ 708 struct bnxt_cp_ring_info *async_cp_ring; 709 struct bnxt_cp_ring_info *rxtx_nq_ring; 710 uint32_t max_ring_grps; 711 struct bnxt_ring_grp_info *grp_info; 712 713 unsigned int nr_vnics; 714 715 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 716 struct bnxt_vnic_info *vnic_info; 717 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 718 719 struct bnxt_filter_info *filter_info; 720 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 721 722 struct bnxt_irq *irq_tbl; 723 724 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 725 726 uint16_t chimp_cmd_seq; 727 uint16_t kong_cmd_seq; 728 void *hwrm_cmd_resp_addr; 729 rte_iova_t hwrm_cmd_resp_dma_addr; 730 void *hwrm_short_cmd_req_addr; 731 rte_iova_t hwrm_short_cmd_req_dma_addr; 732 rte_spinlock_t hwrm_lock; 733 /* synchronize between dev_configure_op and int handler */ 734 pthread_mutex_t def_cp_lock; 735 /* synchronize between dev_start_op and async evt handler 736 * Locking sequence in async evt handler will be 737 * def_cp_lock 738 * health_check_lock 739 */ 740 pthread_mutex_t health_check_lock; 741 /* synchronize between dev_stop/dev_close_op and 742 * error recovery thread triggered as part of 743 * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 744 */ 745 pthread_mutex_t err_recovery_lock; 746 uint16_t max_req_len; 747 uint16_t max_resp_len; 748 uint16_t hwrm_max_ext_req_len; 749 750 /* default command timeout value of 500ms */ 751 #define DFLT_HWRM_CMD_TIMEOUT 500000 752 /* short command timeout value of 50ms */ 753 #define SHORT_HWRM_CMD_TIMEOUT 50000 754 /* default HWRM request timeout value */ 755 uint32_t hwrm_cmd_timeout; 756 757 struct bnxt_link_info *link_info; 758 struct bnxt_cos_queue_info *rx_cos_queue; 759 struct bnxt_cos_queue_info *tx_cos_queue; 760 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 761 uint8_t rx_cosq_cnt; 762 uint8_t max_tc; 763 uint8_t max_lltc; 764 uint8_t max_q; 765 766 uint16_t fw_fid; 767 uint16_t max_rsscos_ctx; 768 uint16_t max_cp_rings; 769 uint16_t max_tx_rings; 770 uint16_t max_rx_rings; 771 #define MAX_STINGRAY_RINGS 236U 772 #define BNXT_MAX_VF_REP_RINGS 8 773 774 uint16_t max_nq_rings; 775 uint16_t max_l2_ctx; 776 uint16_t max_rx_em_flows; 777 uint16_t max_vnics; 778 uint16_t max_stat_ctx; 779 uint16_t max_tpa_v2; 780 uint16_t first_vf_id; 781 uint16_t vlan; 782 #define BNXT_OUTER_TPID_MASK 0x0000ffff 783 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 784 #define BNXT_OUTER_TPID_BD_SHFT 16 785 uint32_t outer_tpid_bd; 786 struct bnxt_pf_info *pf; 787 struct bnxt_parent_info *parent; 788 uint8_t port_cnt; 789 uint8_t vxlan_port_cnt; 790 uint8_t geneve_port_cnt; 791 uint16_t vxlan_port; 792 uint16_t geneve_port; 793 uint16_t vxlan_fw_dst_port_id; 794 uint16_t geneve_fw_dst_port_id; 795 uint32_t fw_ver; 796 uint32_t hwrm_spec_code; 797 798 struct bnxt_led_info *leds; 799 struct bnxt_ptp_cfg *ptp_cfg; 800 uint16_t vf_resv_strategy; 801 struct bnxt_ctx_mem_info *ctx; 802 803 uint16_t fw_reset_min_msecs; 804 uint16_t fw_reset_max_msecs; 805 uint16_t switch_domain_id; 806 uint16_t num_reps; 807 struct bnxt_rep_info *rep_info; 808 uint16_t *cfa_code_map; 809 /* Struct to hold adapter error recovery related info */ 810 struct bnxt_error_recovery_info *recovery_info; 811 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 812 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 813 #define BNXT_FLOW_ID_MASK 0x0000ffff 814 struct bnxt_mark_info *mark_table; 815 816 #define BNXT_SVIF_INVALID 0xFFFF 817 uint16_t func_svif; 818 uint16_t port_svif; 819 820 struct tf tfp; 821 struct bnxt_dmabuf_info dmabuf; 822 struct bnxt_ulp_context *ulp_ctx; 823 struct bnxt_flow_stat_info *flow_stat; 824 uint16_t max_num_kflows; 825 uint16_t tx_cfa_action; 826 }; 827 828 static 829 inline uint16_t bnxt_max_rings(struct bnxt *bp) 830 { 831 uint16_t max_tx_rings = bp->max_tx_rings; 832 uint16_t max_rx_rings = bp->max_rx_rings; 833 uint16_t max_cp_rings = bp->max_cp_rings; 834 uint16_t max_rings; 835 836 /* For the sake of symmetry: 837 * max Tx rings == max Rx rings, one stat ctx for each. 838 */ 839 if (BNXT_STINGRAY(bp)) { 840 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U, 841 MAX_STINGRAY_RINGS), 842 bp->max_stat_ctx / 2U); 843 } else { 844 max_rx_rings = RTE_MIN(max_rx_rings / 2U, 845 bp->max_stat_ctx / 2U); 846 } 847 848 max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); 849 if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp)) 850 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp); 851 max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings); 852 853 return max_rings; 854 } 855 856 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 857 858 /** 859 * Structure to store private data for each VF representor instance 860 */ 861 struct bnxt_representor { 862 uint16_t switch_domain_id; 863 uint16_t vf_id; 864 #define BNXT_REP_IS_PF BIT(0) 865 #define BNXT_REP_Q_R2F_VALID BIT(1) 866 #define BNXT_REP_Q_F2R_VALID BIT(2) 867 #define BNXT_REP_FC_R2F_VALID BIT(3) 868 #define BNXT_REP_FC_F2R_VALID BIT(4) 869 #define BNXT_REP_BASED_PF_VALID BIT(5) 870 uint32_t flags; 871 uint16_t fw_fid; 872 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 873 uint16_t dflt_vnic_id; 874 uint16_t svif; 875 uint16_t vfr_tx_cfa_action; 876 uint8_t parent_pf_idx; /* Logical PF index */ 877 uint32_t dpdk_port_id; 878 uint32_t rep_based_pf; 879 uint8_t rep_q_r2f; 880 uint8_t rep_q_f2r; 881 uint8_t rep_fc_r2f; 882 uint8_t rep_fc_f2r; 883 /* Private data store of associated PF/Trusted VF */ 884 struct rte_eth_dev *parent_dev; 885 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 886 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 887 struct bnxt_rx_queue **rx_queues; 888 unsigned int rx_nr_rings; 889 unsigned int tx_nr_rings; 890 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 891 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 892 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 893 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 894 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 895 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 896 }; 897 898 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) 899 #define BNXT_REP_BASED_PF(vfr_bp) \ 900 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID) 901 902 struct bnxt_vf_rep_tx_queue { 903 struct bnxt_tx_queue *txq; 904 struct bnxt_representor *bp; 905 }; 906 907 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 908 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 909 bool exp_link_status); 910 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 911 int is_bnxt_in_error(struct bnxt *bp); 912 913 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 914 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 915 void bnxt_schedule_fw_health_check(struct bnxt *bp); 916 917 bool is_bnxt_supported(struct rte_eth_dev *dev); 918 bool bnxt_stratus_device(struct bnxt *bp); 919 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 920 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 921 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 922 int wait_to_complete); 923 uint16_t bnxt_dummy_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 924 uint16_t nb_pkts); 925 uint16_t bnxt_dummy_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 926 uint16_t nb_pkts); 927 928 extern const struct rte_flow_ops bnxt_flow_ops; 929 930 #define bnxt_acquire_flow_lock(bp) \ 931 pthread_mutex_lock(&(bp)->flow_lock) 932 933 #define bnxt_release_flow_lock(bp) \ 934 pthread_mutex_unlock(&(bp)->flow_lock) 935 936 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 937 if ((vnic_id) >= (bp)->max_vnics) { \ 938 rte_flow_error_set(error, \ 939 EINVAL, \ 940 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 941 NULL, \ 942 "Group id is invalid!"); \ 943 rc = -rte_errno; \ 944 goto ret; \ 945 } \ 946 } while (0) 947 948 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 949 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 950 951 extern int bnxt_logtype_driver; 952 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 953 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 954 __func__, ## args) 955 956 #define PMD_DRV_LOG(level, fmt, args...) \ 957 PMD_DRV_LOG_RAW(level, fmt, ## args) 958 959 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 960 int32_t bnxt_ulp_port_init(struct bnxt *bp); 961 void bnxt_ulp_port_deinit(struct bnxt *bp); 962 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 963 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 964 int32_t 965 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 966 int32_t 967 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); 968 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); 969 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, 970 enum bnxt_ulp_intf_type type); 971 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); 972 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); 973 uint16_t bnxt_get_phy_port_id(uint16_t port); 974 uint16_t bnxt_get_vport(uint16_t port); 975 enum bnxt_ulp_intf_type 976 bnxt_get_interface_type(uint16_t port); 977 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); 978 979 void bnxt_cancel_fc_thread(struct bnxt *bp); 980 void bnxt_flow_cnt_alarm_cb(void *arg); 981 int bnxt_flow_stats_req(struct bnxt *bp); 982 int bnxt_flow_stats_cnt(struct bnxt *bp); 983 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 984 985 int 986 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 987 enum rte_filter_type filter_type, 988 enum rte_filter_op filter_op, void *arg); 989 #endif 990