1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <rte_ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57301 0x16c8 37 #define BROADCOM_DEV_ID_57302 0x16c9 38 #define BROADCOM_DEV_ID_57304_PF 0x16ca 39 #define BROADCOM_DEV_ID_57304_VF 0x16cb 40 #define BROADCOM_DEV_ID_57417_MF 0x16cc 41 #define BROADCOM_DEV_ID_NS2 0x16cd 42 #define BROADCOM_DEV_ID_57311 0x16ce 43 #define BROADCOM_DEV_ID_57312 0x16cf 44 #define BROADCOM_DEV_ID_57402 0x16d0 45 #define BROADCOM_DEV_ID_57404 0x16d1 46 #define BROADCOM_DEV_ID_57406_PF 0x16d2 47 #define BROADCOM_DEV_ID_57406_VF 0x16d3 48 #define BROADCOM_DEV_ID_57402_MF 0x16d4 49 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 50 #define BROADCOM_DEV_ID_57412 0x16d6 51 #define BROADCOM_DEV_ID_57414 0x16d7 52 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 53 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 54 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 55 #define BROADCOM_DEV_ID_57412_MF 0x16de 56 #define BROADCOM_DEV_ID_57314 0x16df 57 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 58 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 59 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 60 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 61 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 62 #define BROADCOM_DEV_ID_57404_MF 0x16e7 63 #define BROADCOM_DEV_ID_57406_MF 0x16e8 64 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 65 #define BROADCOM_DEV_ID_57407_MF 0x16ea 66 #define BROADCOM_DEV_ID_57414_MF 0x16ec 67 #define BROADCOM_DEV_ID_57416_MF 0x16ee 68 #define BROADCOM_DEV_ID_57508 0x1750 69 #define BROADCOM_DEV_ID_57504 0x1751 70 #define BROADCOM_DEV_ID_57502 0x1752 71 #define BROADCOM_DEV_ID_57508_MF1 0x1800 72 #define BROADCOM_DEV_ID_57504_MF1 0x1801 73 #define BROADCOM_DEV_ID_57502_MF1 0x1802 74 #define BROADCOM_DEV_ID_57508_MF2 0x1803 75 #define BROADCOM_DEV_ID_57504_MF2 0x1804 76 #define BROADCOM_DEV_ID_57502_MF2 0x1805 77 #define BROADCOM_DEV_ID_57500_VF1 0x1806 78 #define BROADCOM_DEV_ID_57500_VF2 0x1807 79 #define BROADCOM_DEV_ID_58802 0xd802 80 #define BROADCOM_DEV_ID_58804 0xd804 81 #define BROADCOM_DEV_ID_58808 0x16f0 82 #define BROADCOM_DEV_ID_58802_VF 0xd800 83 84 #define BNXT_MAX_MTU 9574 85 #define VLAN_TAG_SIZE 4 86 #define BNXT_NUM_VLANS 2 87 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 88 RTE_ETHER_CRC_LEN +\ 89 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 90 /* FW adds extra 4 bytes for FCS */ 91 #define BNXT_VNIC_MRU(mtu)\ 92 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 93 #define BNXT_VF_RSV_NUM_RSS_CTX 1 94 #define BNXT_VF_RSV_NUM_L2_CTX 4 95 /* TODO: For now, do not support VMDq/RFS on VFs. */ 96 #define BNXT_VF_RSV_NUM_VNIC 1 97 #define BNXT_MAX_LED 4 98 #define BNXT_MIN_RING_DESC 16 99 #define BNXT_MAX_TX_RING_DESC 4096 100 #define BNXT_MAX_RX_RING_DESC 8192 101 #define BNXT_DB_SIZE 0x80 102 103 #define TPA_MAX_AGGS 64 104 #define TPA_MAX_AGGS_TH 1024 105 106 #define TPA_MAX_NUM_SEGS 32 107 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 108 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 109 110 #define BNXT_TPA_MAX_AGGS(bp) \ 111 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \ 112 TPA_MAX_AGGS) 113 114 #define BNXT_TPA_MAX_SEGS(bp) \ 115 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \ 116 TPA_MAX_SEGS) 117 118 #ifdef RTE_ARCH_ARM64 119 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1) 120 #else 121 #define BNXT_NUM_ASYNC_CPR(bp) 1 122 #endif 123 124 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 125 #ifdef RTE_EXEC_ENV_FREEBSD 126 #ifdef BNXT_NUM_ASYNC_CPR 127 #undef BNXT_NUM_ASYNC_CPR 128 #endif 129 #define BNXT_NUM_ASYNC_CPR(bp) 0 130 #endif 131 132 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 133 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 134 135 /* Chimp Communication Channel */ 136 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 137 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 138 /* Kong Communication Channel */ 139 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 140 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 141 142 #define BNXT_INT_LAT_TMR_MIN 75 143 #define BNXT_INT_LAT_TMR_MAX 150 144 #define BNXT_NUM_CMPL_AGGR_INT 36 145 #define BNXT_CMPL_AGGR_DMA_TMR 37 146 #define BNXT_NUM_CMPL_DMA_AGGR 36 147 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 148 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 149 150 struct bnxt_led_info { 151 uint8_t num_leds; 152 uint8_t led_id; 153 uint8_t led_type; 154 uint8_t led_group_id; 155 uint8_t unused; 156 uint16_t led_state_caps; 157 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 158 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 159 160 uint16_t led_color_caps; 161 }; 162 163 struct bnxt_led_cfg { 164 uint8_t led_id; 165 uint8_t led_state; 166 uint8_t led_color; 167 uint8_t unused; 168 uint16_t led_blink_on; 169 uint16_t led_blink_off; 170 uint8_t led_group_id; 171 uint8_t rsvd; 172 }; 173 174 #define BNXT_LED_DFLT_ENA \ 175 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 176 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 177 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 178 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 179 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 180 181 #define BNXT_LED_DFLT_ENA_SHIFT 6 182 183 #define BNXT_LED_DFLT_ENABLES(x) \ 184 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 185 186 struct bnxt_vlan_table_entry { 187 uint16_t tpid; 188 uint16_t vid; 189 } __rte_packed; 190 191 struct bnxt_vlan_antispoof_table_entry { 192 uint16_t tpid; 193 uint16_t vid; 194 uint16_t mask; 195 } __rte_packed; 196 197 struct bnxt_child_vf_info { 198 void *req_buf; 199 struct bnxt_vlan_table_entry *vlan_table; 200 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 201 STAILQ_HEAD(, bnxt_filter_info) filter; 202 uint32_t func_cfg_flags; 203 uint32_t l2_rx_mask; 204 uint16_t fid; 205 uint16_t max_tx_rate; 206 uint16_t dflt_vlan; 207 uint16_t vlan_count; 208 uint8_t mac_spoof_en; 209 uint8_t vlan_spoof_en; 210 bool random_mac; 211 bool persist_stats; 212 }; 213 214 struct bnxt_parent_info { 215 #define BNXT_PF_FID_INVALID 0xFFFF 216 uint16_t fid; 217 uint16_t vnic; 218 uint16_t port_id; 219 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 220 }; 221 222 struct bnxt_pf_info { 223 #define BNXT_FIRST_PF_FID 1 224 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 225 #define BNXT_MAX_VF_REPS 64 226 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 227 #define BNXT_FIRST_VF_FID 128 228 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 229 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 230 BNXT_PF_RINGS_USED(bp)) 231 uint16_t port_id; 232 uint16_t first_vf_id; 233 uint16_t active_vfs; 234 uint16_t max_vfs; 235 uint16_t total_vfs; /* Total VFs possible. 236 * Not necessarily enabled. 237 */ 238 uint32_t func_cfg_flags; 239 void *vf_req_buf; 240 rte_iova_t vf_req_buf_dma_addr; 241 uint32_t vf_req_fwd[8]; 242 uint16_t total_vnics; 243 struct bnxt_child_vf_info *vf_info; 244 #define BNXT_EVB_MODE_NONE 0 245 #define BNXT_EVB_MODE_VEB 1 246 #define BNXT_EVB_MODE_VEPA 2 247 uint8_t evb_mode; 248 }; 249 250 /* Max wait time for link up is 10s and link down is 500ms */ 251 #define BNXT_LINK_UP_WAIT_CNT 200 252 #define BNXT_LINK_DOWN_WAIT_CNT 10 253 #define BNXT_LINK_WAIT_INTERVAL 50 254 struct bnxt_link_info { 255 uint32_t phy_flags; 256 uint8_t mac_type; 257 uint8_t phy_link_status; 258 uint8_t loop_back; 259 uint8_t link_up; 260 uint8_t duplex; 261 uint8_t pause; 262 uint8_t force_pause; 263 uint8_t auto_pause; 264 uint8_t auto_mode; 265 #define PHY_VER_LEN 3 266 uint8_t phy_ver[PHY_VER_LEN]; 267 uint16_t link_speed; 268 uint16_t support_speeds; 269 uint16_t auto_link_speed; 270 uint16_t force_link_speed; 271 uint16_t auto_link_speed_mask; 272 uint32_t preemphasis; 273 uint8_t phy_type; 274 uint8_t media_type; 275 }; 276 277 #define BNXT_COS_QUEUE_COUNT 8 278 struct bnxt_cos_queue_info { 279 uint8_t id; 280 uint8_t profile; 281 }; 282 283 struct rte_flow { 284 STAILQ_ENTRY(rte_flow) next; 285 struct bnxt_filter_info *filter; 286 struct bnxt_vnic_info *vnic; 287 }; 288 289 #define BNXT_PTP_FLAGS_PATH_TX 0x0 290 #define BNXT_PTP_FLAGS_PATH_RX 0x1 291 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 292 293 struct bnxt_ptp_cfg { 294 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 295 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 296 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 297 struct rte_timecounter tc; 298 struct rte_timecounter tx_tstamp_tc; 299 struct rte_timecounter rx_tstamp_tc; 300 struct bnxt *bp; 301 #define BNXT_MAX_TX_TS 1 302 uint16_t rxctl; 303 #define BNXT_PTP_MSG_SYNC BIT(0) 304 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 305 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 306 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 307 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 308 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 309 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 310 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 311 #define BNXT_PTP_MSG_SIGNALING BIT(12) 312 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 313 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 314 BNXT_PTP_MSG_DELAY_REQ | \ 315 BNXT_PTP_MSG_PDELAY_REQ | \ 316 BNXT_PTP_MSG_PDELAY_RESP) 317 uint8_t tx_tstamp_en:1; 318 int rx_filter; 319 320 #define BNXT_PTP_RX_TS_L 0 321 #define BNXT_PTP_RX_TS_H 1 322 #define BNXT_PTP_RX_SEQ 2 323 #define BNXT_PTP_RX_FIFO 3 324 #define BNXT_PTP_RX_FIFO_PENDING 0x1 325 #define BNXT_PTP_RX_FIFO_ADV 4 326 #define BNXT_PTP_RX_REGS 5 327 328 #define BNXT_PTP_TX_TS_L 0 329 #define BNXT_PTP_TX_TS_H 1 330 #define BNXT_PTP_TX_SEQ 2 331 #define BNXT_PTP_TX_FIFO 3 332 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 333 #define BNXT_PTP_TX_REGS 4 334 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 335 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 336 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 337 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 338 339 /* On Thor, the Rx timestamp is present in the Rx completion record */ 340 uint64_t rx_timestamp; 341 }; 342 343 struct bnxt_coal { 344 uint16_t num_cmpl_aggr_int; 345 uint16_t num_cmpl_dma_aggr; 346 uint16_t num_cmpl_dma_aggr_during_int; 347 uint16_t int_lat_tmr_max; 348 uint16_t int_lat_tmr_min; 349 uint16_t cmpl_aggr_dma_tmr; 350 uint16_t cmpl_aggr_dma_tmr_during_int; 351 }; 352 353 /* 64-bit doorbell */ 354 #define DBR_XID_SFT 32 355 #define DBR_PATH_L2 (0x1ULL << 56) 356 #define DBR_TYPE_SQ (0x0ULL << 60) 357 #define DBR_TYPE_SRQ (0x2ULL << 60) 358 #define DBR_TYPE_CQ (0x4ULL << 60) 359 #define DBR_TYPE_NQ (0xaULL << 60) 360 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 361 362 #define BNXT_RSS_TBL_SIZE_THOR 512 363 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64 364 #define BNXT_MAX_RSS_CTXTS_THOR \ 365 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR) 366 367 #define BNXT_MAX_TC 8 368 #define BNXT_MAX_QUEUE 8 369 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) 370 #define BNXT_PAGE_SHFT 12 371 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 372 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 373 374 #define PTU_PTE_VALID 0x1UL 375 #define PTU_PTE_LAST 0x2UL 376 #define PTU_PTE_NEXT_TO_LAST 0x4UL 377 378 struct bnxt_ring_mem_info { 379 int nr_pages; 380 int page_size; 381 uint32_t flags; 382 #define BNXT_RMEM_VALID_PTE_FLAG 1 383 #define BNXT_RMEM_RING_PTE_FLAG 2 384 385 void **pg_arr; 386 rte_iova_t *dma_arr; 387 const struct rte_memzone *mz; 388 389 uint64_t *pg_tbl; 390 rte_iova_t pg_tbl_map; 391 const struct rte_memzone *pg_tbl_mz; 392 393 int vmem_size; 394 void **vmem; 395 }; 396 397 struct bnxt_ctx_pg_info { 398 uint32_t entries; 399 void *ctx_pg_arr[MAX_CTX_PAGES]; 400 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 401 struct bnxt_ring_mem_info ring_mem; 402 }; 403 404 struct bnxt_ctx_mem_info { 405 uint32_t qp_max_entries; 406 uint16_t qp_min_qp1_entries; 407 uint16_t qp_max_l2_entries; 408 uint16_t qp_entry_size; 409 uint16_t srq_max_l2_entries; 410 uint32_t srq_max_entries; 411 uint16_t srq_entry_size; 412 uint16_t cq_max_l2_entries; 413 uint32_t cq_max_entries; 414 uint16_t cq_entry_size; 415 uint16_t vnic_max_vnic_entries; 416 uint16_t vnic_max_ring_table_entries; 417 uint16_t vnic_entry_size; 418 uint32_t stat_max_entries; 419 uint16_t stat_entry_size; 420 uint16_t tqm_entry_size; 421 uint32_t tqm_min_entries_per_ring; 422 uint32_t tqm_max_entries_per_ring; 423 uint32_t mrav_max_entries; 424 uint16_t mrav_entry_size; 425 uint16_t tim_entry_size; 426 uint32_t tim_max_entries; 427 uint8_t tqm_entries_multiple; 428 uint8_t tqm_fp_rings_count; 429 430 uint32_t flags; 431 #define BNXT_CTX_FLAG_INITED 0x01 432 433 struct bnxt_ctx_pg_info qp_mem; 434 struct bnxt_ctx_pg_info srq_mem; 435 struct bnxt_ctx_pg_info cq_mem; 436 struct bnxt_ctx_pg_info vnic_mem; 437 struct bnxt_ctx_pg_info stat_mem; 438 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; 439 }; 440 441 struct bnxt_ctx_mem_buf_info { 442 void *va; 443 rte_iova_t dma; 444 uint16_t ctx_id; 445 size_t size; 446 }; 447 448 /* Maximum Firmware Reset bail out value in milliseconds */ 449 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 450 /* Minimum time required for the firmware readiness in milliseconds */ 451 #define BNXT_MIN_FW_READY_TIMEOUT 2000 452 /* Frequency for the firmware readiness check in milliseconds */ 453 #define BNXT_FW_READY_WAIT_INTERVAL 100 454 455 #define US_PER_MS 1000 456 #define NS_PER_US 1000 457 458 struct bnxt_error_recovery_info { 459 /* All units in milliseconds */ 460 uint32_t driver_polling_freq; 461 uint32_t master_func_wait_period; 462 uint32_t normal_func_wait_period; 463 uint32_t master_func_wait_period_after_reset; 464 uint32_t max_bailout_time_after_reset; 465 #define BNXT_FW_STATUS_REG 0 466 #define BNXT_FW_HEARTBEAT_CNT_REG 1 467 #define BNXT_FW_RECOVERY_CNT_REG 2 468 #define BNXT_FW_RESET_INPROG_REG 3 469 #define BNXT_FW_STATUS_REG_CNT 4 470 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 471 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 472 uint32_t reset_inprogress_reg_mask; 473 #define BNXT_NUM_RESET_REG 16 474 uint8_t reg_array_cnt; 475 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 476 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 477 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 478 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 479 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 480 #define BNXT_FLAG_MASTER_FUNC BIT(2) 481 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 482 uint32_t flags; 483 484 uint32_t last_heart_beat; 485 uint32_t last_reset_counter; 486 }; 487 488 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 489 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 490 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 491 #define BNXT_IF_CHANGE_RETRY_COUNT 40 492 493 struct bnxt_mark_info { 494 uint32_t mark_id; 495 bool valid; 496 }; 497 498 struct bnxt_rep_info { 499 struct rte_eth_dev *vfr_eth_dev; 500 pthread_mutex_t vfr_lock; 501 }; 502 503 /* address space location of register */ 504 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 505 /* register is located in PCIe config space */ 506 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 507 /* register is located in GRC address space */ 508 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 509 /* register is located in BAR0 */ 510 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 511 /* register is located in BAR1 */ 512 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 513 514 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 515 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 516 517 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 518 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 519 520 #define BNXT_GRCP_BASE_MASK 0xfffff000 521 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 522 523 #define BNXT_FW_STATUS_HEALTHY 0x8000 524 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 525 526 #define BNXT_ETH_RSS_SUPPORT ( \ 527 ETH_RSS_IPV4 | \ 528 ETH_RSS_NONFRAG_IPV4_TCP | \ 529 ETH_RSS_NONFRAG_IPV4_UDP | \ 530 ETH_RSS_IPV6 | \ 531 ETH_RSS_NONFRAG_IPV6_TCP | \ 532 ETH_RSS_NONFRAG_IPV6_UDP) 533 534 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 535 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 536 DEV_TX_OFFLOAD_TCP_CKSUM | \ 537 DEV_TX_OFFLOAD_UDP_CKSUM | \ 538 DEV_TX_OFFLOAD_TCP_TSO | \ 539 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 540 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 541 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 542 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 543 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 544 DEV_TX_OFFLOAD_QINQ_INSERT | \ 545 DEV_TX_OFFLOAD_MULTI_SEGS) 546 547 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 548 DEV_RX_OFFLOAD_VLAN_STRIP | \ 549 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 550 DEV_RX_OFFLOAD_UDP_CKSUM | \ 551 DEV_RX_OFFLOAD_TCP_CKSUM | \ 552 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 553 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 554 DEV_RX_OFFLOAD_KEEP_CRC | \ 555 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 556 DEV_RX_OFFLOAD_TCP_LRO | \ 557 DEV_RX_OFFLOAD_SCATTER | \ 558 DEV_RX_OFFLOAD_RSS_HASH) 559 560 #define MAX_TABLE_SUPPORT 4 561 #define MAX_DIR_SUPPORT 2 562 struct bnxt_dmabuf_info { 563 uint32_t entry_num; 564 int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT]; 565 }; 566 567 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 568 569 struct bnxt_flow_stat_info { 570 uint16_t max_fc; 571 uint16_t flow_count; 572 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 573 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 574 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 575 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 576 }; 577 578 struct bnxt { 579 void *bar0; 580 581 struct rte_eth_dev *eth_dev; 582 struct rte_pci_device *pdev; 583 void *doorbell_base; 584 585 uint32_t flags; 586 #define BNXT_FLAG_REGISTERED BIT(0) 587 #define BNXT_FLAG_VF BIT(1) 588 #define BNXT_FLAG_PORT_STATS BIT(2) 589 #define BNXT_FLAG_JUMBO BIT(3) 590 #define BNXT_FLAG_SHORT_CMD BIT(4) 591 #define BNXT_FLAG_UPDATE_HASH BIT(5) 592 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 593 #define BNXT_FLAG_MULTI_HOST BIT(7) 594 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 595 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 596 #define BNXT_FLAG_KONG_MB_EN BIT(10) 597 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 598 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 599 #define BNXT_FLAG_THOR_CHIP BIT(13) 600 #define BNXT_FLAG_STINGRAY BIT(14) 601 #define BNXT_FLAG_FW_RESET BIT(15) 602 #define BNXT_FLAG_FATAL_ERROR BIT(16) 603 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 604 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 605 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 606 #define BNXT_FLAG_NEW_RM BIT(20) 607 #define BNXT_FLAG_NPAR_PF BIT(21) 608 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 609 #define BNXT_FLAG_FC_THREAD BIT(23) 610 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 611 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 612 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 613 #define BNXT_FLAG_TRUFLOW_EN BIT(27) 614 #define BNXT_FLAG_GFID_ENABLE BIT(28) 615 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 616 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 617 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 618 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 619 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 620 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 621 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 622 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 623 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP) 624 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 625 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) 626 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) 627 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 628 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 629 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) 630 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 631 632 uint32_t fw_cap; 633 #define BNXT_FW_CAP_HOT_RESET BIT(0) 634 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 635 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 636 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 637 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 638 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 639 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(7) 640 641 pthread_mutex_t flow_lock; 642 643 uint32_t vnic_cap_flags; 644 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 645 unsigned int rx_nr_rings; 646 unsigned int rx_cp_nr_rings; 647 unsigned int rx_num_qs_per_vnic; 648 struct bnxt_rx_queue **rx_queues; 649 const void *rx_mem_zone; 650 struct rx_port_stats *hw_rx_port_stats; 651 rte_iova_t hw_rx_port_stats_map; 652 struct rx_port_stats_ext *hw_rx_port_stats_ext; 653 rte_iova_t hw_rx_port_stats_ext_map; 654 uint16_t fw_rx_port_stats_ext_size; 655 656 unsigned int tx_nr_rings; 657 unsigned int tx_cp_nr_rings; 658 struct bnxt_tx_queue **tx_queues; 659 const void *tx_mem_zone; 660 struct tx_port_stats *hw_tx_port_stats; 661 rte_iova_t hw_tx_port_stats_map; 662 struct tx_port_stats_ext *hw_tx_port_stats_ext; 663 rte_iova_t hw_tx_port_stats_ext_map; 664 uint16_t fw_tx_port_stats_ext_size; 665 666 /* Default completion ring */ 667 struct bnxt_cp_ring_info *async_cp_ring; 668 struct bnxt_cp_ring_info *rxtx_nq_ring; 669 uint32_t max_ring_grps; 670 struct bnxt_ring_grp_info *grp_info; 671 672 unsigned int nr_vnics; 673 674 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 675 struct bnxt_vnic_info *vnic_info; 676 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 677 678 struct bnxt_filter_info *filter_info; 679 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 680 681 struct bnxt_irq *irq_tbl; 682 683 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 684 685 uint16_t chimp_cmd_seq; 686 uint16_t kong_cmd_seq; 687 void *hwrm_cmd_resp_addr; 688 rte_iova_t hwrm_cmd_resp_dma_addr; 689 void *hwrm_short_cmd_req_addr; 690 rte_iova_t hwrm_short_cmd_req_dma_addr; 691 rte_spinlock_t hwrm_lock; 692 pthread_mutex_t def_cp_lock; 693 uint16_t max_req_len; 694 uint16_t max_resp_len; 695 uint16_t hwrm_max_ext_req_len; 696 697 /* default command timeout value of 500ms */ 698 #define DFLT_HWRM_CMD_TIMEOUT 500000 699 /* short command timeout value of 50ms */ 700 #define SHORT_HWRM_CMD_TIMEOUT 50000 701 /* default HWRM request timeout value */ 702 uint32_t hwrm_cmd_timeout; 703 704 struct bnxt_link_info *link_info; 705 struct bnxt_cos_queue_info *rx_cos_queue; 706 struct bnxt_cos_queue_info *tx_cos_queue; 707 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 708 uint8_t rx_cosq_cnt; 709 uint8_t max_tc; 710 uint8_t max_lltc; 711 uint8_t max_q; 712 713 uint16_t fw_fid; 714 uint16_t max_rsscos_ctx; 715 uint16_t max_cp_rings; 716 uint16_t max_tx_rings; 717 uint16_t max_rx_rings; 718 #define MAX_STINGRAY_RINGS 128U 719 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */ 720 #define BNXT_MAX_RX_RINGS(bp) \ 721 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \ 722 MAX_STINGRAY_RINGS), \ 723 bp->max_stat_ctx / 2U) : \ 724 RTE_MIN(bp->max_rx_rings / 2U, \ 725 bp->max_stat_ctx / 2U)) 726 #define BNXT_MAX_TX_RINGS(bp) \ 727 (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp))) 728 729 #define BNXT_MAX_RINGS(bp) \ 730 (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \ 731 BNXT_MAX_TX_RINGS(bp))) 732 733 #define BNXT_MAX_VF_REP_RINGS 8 734 735 uint16_t max_nq_rings; 736 uint16_t max_l2_ctx; 737 uint16_t max_rx_em_flows; 738 uint16_t max_vnics; 739 uint16_t max_stat_ctx; 740 uint16_t max_tpa_v2; 741 uint16_t first_vf_id; 742 uint16_t vlan; 743 #define BNXT_OUTER_TPID_MASK 0x0000ffff 744 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 745 #define BNXT_OUTER_TPID_BD_SHFT 16 746 uint32_t outer_tpid_bd; 747 struct bnxt_pf_info *pf; 748 struct bnxt_parent_info *parent; 749 uint8_t port_cnt; 750 uint8_t vxlan_port_cnt; 751 uint8_t geneve_port_cnt; 752 uint16_t vxlan_port; 753 uint16_t geneve_port; 754 uint16_t vxlan_fw_dst_port_id; 755 uint16_t geneve_fw_dst_port_id; 756 uint32_t fw_ver; 757 uint32_t hwrm_spec_code; 758 759 struct bnxt_led_info *leds; 760 struct bnxt_ptp_cfg *ptp_cfg; 761 uint16_t vf_resv_strategy; 762 struct bnxt_ctx_mem_info *ctx; 763 764 uint16_t fw_reset_min_msecs; 765 uint16_t fw_reset_max_msecs; 766 uint16_t switch_domain_id; 767 uint16_t num_reps; 768 struct bnxt_rep_info *rep_info; 769 uint16_t *cfa_code_map; 770 /* Struct to hold adapter error recovery related info */ 771 struct bnxt_error_recovery_info *recovery_info; 772 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 773 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 774 #define BNXT_FLOW_ID_MASK 0x0000ffff 775 struct bnxt_mark_info *mark_table; 776 777 #define BNXT_SVIF_INVALID 0xFFFF 778 uint16_t func_svif; 779 uint16_t port_svif; 780 781 struct tf tfp; 782 struct bnxt_dmabuf_info dmabuf; 783 struct bnxt_ulp_context *ulp_ctx; 784 struct bnxt_flow_stat_info *flow_stat; 785 uint8_t flow_xstat; 786 uint16_t max_num_kflows; 787 uint16_t tx_cfa_action; 788 }; 789 790 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 791 792 /** 793 * Structure to store private data for each VF representor instance 794 */ 795 struct bnxt_vf_representor { 796 uint16_t switch_domain_id; 797 uint16_t vf_id; 798 uint16_t fw_fid; 799 uint16_t dflt_vnic_id; 800 uint16_t svif; 801 uint16_t vfr_tx_cfa_action; 802 uint32_t rep2vf_flow_id; 803 uint32_t vf2rep_flow_id; 804 /* Private data store of associated PF/Trusted VF */ 805 struct rte_eth_dev *parent_dev; 806 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 807 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 808 struct bnxt_rx_queue **rx_queues; 809 unsigned int rx_nr_rings; 810 unsigned int tx_nr_rings; 811 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 812 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 813 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 814 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 815 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 816 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 817 }; 818 819 struct bnxt_vf_rep_tx_queue { 820 struct bnxt_tx_queue *txq; 821 struct bnxt_vf_representor *bp; 822 }; 823 824 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 825 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 826 bool exp_link_status); 827 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 828 int is_bnxt_in_error(struct bnxt *bp); 829 830 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 831 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 832 void bnxt_schedule_fw_health_check(struct bnxt *bp); 833 834 bool is_bnxt_supported(struct rte_eth_dev *dev); 835 bool bnxt_stratus_device(struct bnxt *bp); 836 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 837 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 838 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 839 int wait_to_complete); 840 841 extern const struct rte_flow_ops bnxt_flow_ops; 842 843 #define bnxt_acquire_flow_lock(bp) \ 844 pthread_mutex_lock(&(bp)->flow_lock) 845 846 #define bnxt_release_flow_lock(bp) \ 847 pthread_mutex_unlock(&(bp)->flow_lock) 848 849 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 850 if ((vnic_id) >= (bp)->max_vnics) { \ 851 rte_flow_error_set(error, \ 852 EINVAL, \ 853 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 854 NULL, \ 855 "Group id is invalid!"); \ 856 rc = -rte_errno; \ 857 goto ret; \ 858 } \ 859 } while (0) 860 861 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 862 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 863 864 extern int bnxt_logtype_driver; 865 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 866 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 867 __func__, ## args) 868 869 #define PMD_DRV_LOG(level, fmt, args...) \ 870 PMD_DRV_LOG_RAW(level, fmt, ## args) 871 872 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 873 int32_t bnxt_ulp_init(struct bnxt *bp); 874 void bnxt_ulp_deinit(struct bnxt *bp); 875 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 876 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 877 878 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); 879 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, 880 enum bnxt_ulp_intf_type type); 881 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); 882 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); 883 uint16_t bnxt_get_phy_port_id(uint16_t port); 884 uint16_t bnxt_get_vport(uint16_t port); 885 enum bnxt_ulp_intf_type 886 bnxt_get_interface_type(uint16_t port); 887 888 void bnxt_cancel_fc_thread(struct bnxt *bp); 889 void bnxt_flow_cnt_alarm_cb(void *arg); 890 int bnxt_flow_stats_req(struct bnxt *bp); 891 int bnxt_flow_stats_cnt(struct bnxt *bp); 892 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 893 894 int 895 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 896 enum rte_filter_type filter_type, 897 enum rte_filter_op filter_op, void *arg); 898 #endif 899