1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <rte_ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57301 0x16c8 37 #define BROADCOM_DEV_ID_57302 0x16c9 38 #define BROADCOM_DEV_ID_57304_PF 0x16ca 39 #define BROADCOM_DEV_ID_57304_VF 0x16cb 40 #define BROADCOM_DEV_ID_57417_MF 0x16cc 41 #define BROADCOM_DEV_ID_NS2 0x16cd 42 #define BROADCOM_DEV_ID_57311 0x16ce 43 #define BROADCOM_DEV_ID_57312 0x16cf 44 #define BROADCOM_DEV_ID_57402 0x16d0 45 #define BROADCOM_DEV_ID_57404 0x16d1 46 #define BROADCOM_DEV_ID_57406_PF 0x16d2 47 #define BROADCOM_DEV_ID_57406_VF 0x16d3 48 #define BROADCOM_DEV_ID_57402_MF 0x16d4 49 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 50 #define BROADCOM_DEV_ID_57412 0x16d6 51 #define BROADCOM_DEV_ID_57414 0x16d7 52 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 53 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 54 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 55 #define BROADCOM_DEV_ID_57412_MF 0x16de 56 #define BROADCOM_DEV_ID_57314 0x16df 57 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 58 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 59 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 60 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 61 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 62 #define BROADCOM_DEV_ID_57404_MF 0x16e7 63 #define BROADCOM_DEV_ID_57406_MF 0x16e8 64 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 65 #define BROADCOM_DEV_ID_57407_MF 0x16ea 66 #define BROADCOM_DEV_ID_57414_MF 0x16ec 67 #define BROADCOM_DEV_ID_57416_MF 0x16ee 68 #define BROADCOM_DEV_ID_57508 0x1750 69 #define BROADCOM_DEV_ID_57504 0x1751 70 #define BROADCOM_DEV_ID_57502 0x1752 71 #define BROADCOM_DEV_ID_57508_MF1 0x1800 72 #define BROADCOM_DEV_ID_57504_MF1 0x1801 73 #define BROADCOM_DEV_ID_57502_MF1 0x1802 74 #define BROADCOM_DEV_ID_57508_MF2 0x1803 75 #define BROADCOM_DEV_ID_57504_MF2 0x1804 76 #define BROADCOM_DEV_ID_57502_MF2 0x1805 77 #define BROADCOM_DEV_ID_57500_VF1 0x1806 78 #define BROADCOM_DEV_ID_57500_VF2 0x1807 79 #define BROADCOM_DEV_ID_58802 0xd802 80 #define BROADCOM_DEV_ID_58804 0xd804 81 #define BROADCOM_DEV_ID_58808 0x16f0 82 #define BROADCOM_DEV_ID_58802_VF 0xd800 83 84 #define BROADCOM_DEV_957508_N2100 0x5208 85 #define IS_BNXT_DEV_957508_N2100(bp) \ 86 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) 87 88 #define BNXT_MAX_MTU 9574 89 #define VLAN_TAG_SIZE 4 90 #define BNXT_NUM_VLANS 2 91 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 92 RTE_ETHER_CRC_LEN +\ 93 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 94 /* FW adds extra 4 bytes for FCS */ 95 #define BNXT_VNIC_MRU(mtu)\ 96 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 97 #define BNXT_VF_RSV_NUM_RSS_CTX 1 98 #define BNXT_VF_RSV_NUM_L2_CTX 4 99 /* TODO: For now, do not support VMDq/RFS on VFs. */ 100 #define BNXT_VF_RSV_NUM_VNIC 1 101 #define BNXT_MAX_LED 4 102 #define BNXT_MIN_RING_DESC 16 103 #define BNXT_MAX_TX_RING_DESC 4096 104 #define BNXT_MAX_RX_RING_DESC 8192 105 #define BNXT_DB_SIZE 0x80 106 107 #define TPA_MAX_AGGS 64 108 #define TPA_MAX_AGGS_TH 1024 109 110 #define TPA_MAX_NUM_SEGS 32 111 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 112 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 113 114 #define BNXT_TPA_MAX_AGGS(bp) \ 115 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \ 116 TPA_MAX_AGGS) 117 118 #define BNXT_TPA_MAX_SEGS(bp) \ 119 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \ 120 TPA_MAX_SEGS) 121 122 /* 123 * Define the number of async completion rings to be used. Set to zero for 124 * configurations in which the maximum number of packet completion rings 125 * for packet completions is desired or when async completion handling 126 * cannot be interrupt-driven. 127 */ 128 #ifdef RTE_EXEC_ENV_FREEBSD 129 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 130 #define BNXT_NUM_ASYNC_CPR(bp) 0 131 #else 132 #define BNXT_NUM_ASYNC_CPR(bp) 1 133 #endif 134 135 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 136 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 137 138 /* Chimp Communication Channel */ 139 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 140 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 141 /* Kong Communication Channel */ 142 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 143 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 144 145 #define BNXT_INT_LAT_TMR_MIN 75 146 #define BNXT_INT_LAT_TMR_MAX 150 147 #define BNXT_NUM_CMPL_AGGR_INT 36 148 #define BNXT_CMPL_AGGR_DMA_TMR 37 149 #define BNXT_NUM_CMPL_DMA_AGGR 36 150 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 151 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 152 153 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 154 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 155 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 156 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 157 #define BNXT_DEFAULT_VNIC_ALLOC \ 158 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 159 #define BNXT_DEFAULT_VNIC_FREE \ 160 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 161 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 162 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 163 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 164 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 165 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 166 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 167 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 168 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 169 170 struct bnxt_led_info { 171 uint8_t num_leds; 172 uint8_t led_id; 173 uint8_t led_type; 174 uint8_t led_group_id; 175 uint8_t unused; 176 uint16_t led_state_caps; 177 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 178 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 179 180 uint16_t led_color_caps; 181 }; 182 183 struct bnxt_led_cfg { 184 uint8_t led_id; 185 uint8_t led_state; 186 uint8_t led_color; 187 uint8_t unused; 188 uint16_t led_blink_on; 189 uint16_t led_blink_off; 190 uint8_t led_group_id; 191 uint8_t rsvd; 192 }; 193 194 #define BNXT_LED_DFLT_ENA \ 195 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 196 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 197 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 198 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 199 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 200 201 #define BNXT_LED_DFLT_ENA_SHIFT 6 202 203 #define BNXT_LED_DFLT_ENABLES(x) \ 204 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 205 206 struct bnxt_vlan_table_entry { 207 uint16_t tpid; 208 uint16_t vid; 209 } __rte_packed; 210 211 struct bnxt_vlan_antispoof_table_entry { 212 uint16_t tpid; 213 uint16_t vid; 214 uint16_t mask; 215 } __rte_packed; 216 217 struct bnxt_child_vf_info { 218 void *req_buf; 219 struct bnxt_vlan_table_entry *vlan_table; 220 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 221 STAILQ_HEAD(, bnxt_filter_info) filter; 222 uint32_t func_cfg_flags; 223 uint32_t l2_rx_mask; 224 uint16_t fid; 225 uint16_t max_tx_rate; 226 uint16_t dflt_vlan; 227 uint16_t vlan_count; 228 uint8_t mac_spoof_en; 229 uint8_t vlan_spoof_en; 230 bool random_mac; 231 bool persist_stats; 232 }; 233 234 struct bnxt_parent_info { 235 #define BNXT_PF_FID_INVALID 0xFFFF 236 uint16_t fid; 237 uint16_t vnic; 238 uint16_t port_id; 239 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 240 }; 241 242 struct bnxt_pf_info { 243 #define BNXT_FIRST_PF_FID 1 244 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 245 #define BNXT_MAX_VF_REPS 64 246 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 247 #define BNXT_FIRST_VF_FID 128 248 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 249 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 250 BNXT_PF_RINGS_USED(bp)) 251 uint16_t port_id; 252 uint16_t first_vf_id; 253 uint16_t active_vfs; 254 uint16_t max_vfs; 255 uint16_t total_vfs; /* Total VFs possible. 256 * Not necessarily enabled. 257 */ 258 uint32_t func_cfg_flags; 259 void *vf_req_buf; 260 rte_iova_t vf_req_buf_dma_addr; 261 uint32_t vf_req_fwd[8]; 262 uint16_t total_vnics; 263 struct bnxt_child_vf_info *vf_info; 264 #define BNXT_EVB_MODE_NONE 0 265 #define BNXT_EVB_MODE_VEB 1 266 #define BNXT_EVB_MODE_VEPA 2 267 uint8_t evb_mode; 268 }; 269 270 /* Max wait time for link up is 10s and link down is 500ms */ 271 #define BNXT_LINK_UP_WAIT_CNT 200 272 #define BNXT_LINK_DOWN_WAIT_CNT 10 273 #define BNXT_LINK_WAIT_INTERVAL 50 274 struct bnxt_link_info { 275 uint32_t phy_flags; 276 uint8_t mac_type; 277 uint8_t phy_link_status; 278 uint8_t loop_back; 279 uint8_t link_up; 280 uint8_t duplex; 281 uint8_t pause; 282 uint8_t force_pause; 283 uint8_t auto_pause; 284 uint8_t auto_mode; 285 #define PHY_VER_LEN 3 286 uint8_t phy_ver[PHY_VER_LEN]; 287 uint16_t link_speed; 288 uint16_t support_speeds; 289 uint16_t auto_link_speed; 290 uint16_t force_link_speed; 291 uint16_t auto_link_speed_mask; 292 uint32_t preemphasis; 293 uint8_t phy_type; 294 uint8_t media_type; 295 }; 296 297 #define BNXT_COS_QUEUE_COUNT 8 298 struct bnxt_cos_queue_info { 299 uint8_t id; 300 uint8_t profile; 301 }; 302 303 struct rte_flow { 304 STAILQ_ENTRY(rte_flow) next; 305 struct bnxt_filter_info *filter; 306 struct bnxt_vnic_info *vnic; 307 }; 308 309 #define BNXT_PTP_FLAGS_PATH_TX 0x0 310 #define BNXT_PTP_FLAGS_PATH_RX 0x1 311 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 312 313 struct bnxt_ptp_cfg { 314 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 315 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 316 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 317 struct rte_timecounter tc; 318 struct rte_timecounter tx_tstamp_tc; 319 struct rte_timecounter rx_tstamp_tc; 320 struct bnxt *bp; 321 #define BNXT_MAX_TX_TS 1 322 uint16_t rxctl; 323 #define BNXT_PTP_MSG_SYNC BIT(0) 324 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 325 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 326 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 327 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 328 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 329 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 330 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 331 #define BNXT_PTP_MSG_SIGNALING BIT(12) 332 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 333 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 334 BNXT_PTP_MSG_DELAY_REQ | \ 335 BNXT_PTP_MSG_PDELAY_REQ | \ 336 BNXT_PTP_MSG_PDELAY_RESP) 337 uint8_t tx_tstamp_en:1; 338 int rx_filter; 339 340 #define BNXT_PTP_RX_TS_L 0 341 #define BNXT_PTP_RX_TS_H 1 342 #define BNXT_PTP_RX_SEQ 2 343 #define BNXT_PTP_RX_FIFO 3 344 #define BNXT_PTP_RX_FIFO_PENDING 0x1 345 #define BNXT_PTP_RX_FIFO_ADV 4 346 #define BNXT_PTP_RX_REGS 5 347 348 #define BNXT_PTP_TX_TS_L 0 349 #define BNXT_PTP_TX_TS_H 1 350 #define BNXT_PTP_TX_SEQ 2 351 #define BNXT_PTP_TX_FIFO 3 352 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 353 #define BNXT_PTP_TX_REGS 4 354 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 355 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 356 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 357 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 358 359 /* On Thor, the Rx timestamp is present in the Rx completion record */ 360 uint64_t rx_timestamp; 361 }; 362 363 struct bnxt_coal { 364 uint16_t num_cmpl_aggr_int; 365 uint16_t num_cmpl_dma_aggr; 366 uint16_t num_cmpl_dma_aggr_during_int; 367 uint16_t int_lat_tmr_max; 368 uint16_t int_lat_tmr_min; 369 uint16_t cmpl_aggr_dma_tmr; 370 uint16_t cmpl_aggr_dma_tmr_during_int; 371 }; 372 373 /* 64-bit doorbell */ 374 #define DBR_XID_SFT 32 375 #define DBR_PATH_L2 (0x1ULL << 56) 376 #define DBR_TYPE_SQ (0x0ULL << 60) 377 #define DBR_TYPE_SRQ (0x2ULL << 60) 378 #define DBR_TYPE_CQ (0x4ULL << 60) 379 #define DBR_TYPE_NQ (0xaULL << 60) 380 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 381 382 #define BNXT_RSS_TBL_SIZE_THOR 512 383 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64 384 #define BNXT_MAX_RSS_CTXTS_THOR \ 385 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR) 386 387 #define BNXT_MAX_TC 8 388 #define BNXT_MAX_QUEUE 8 389 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) 390 #define BNXT_PAGE_SHFT 12 391 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 392 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 393 394 #define PTU_PTE_VALID 0x1UL 395 #define PTU_PTE_LAST 0x2UL 396 #define PTU_PTE_NEXT_TO_LAST 0x4UL 397 398 struct bnxt_ring_mem_info { 399 int nr_pages; 400 int page_size; 401 uint32_t flags; 402 #define BNXT_RMEM_VALID_PTE_FLAG 1 403 #define BNXT_RMEM_RING_PTE_FLAG 2 404 405 void **pg_arr; 406 rte_iova_t *dma_arr; 407 const struct rte_memzone *mz; 408 409 uint64_t *pg_tbl; 410 rte_iova_t pg_tbl_map; 411 const struct rte_memzone *pg_tbl_mz; 412 413 int vmem_size; 414 void **vmem; 415 }; 416 417 struct bnxt_ctx_pg_info { 418 uint32_t entries; 419 void *ctx_pg_arr[MAX_CTX_PAGES]; 420 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 421 struct bnxt_ring_mem_info ring_mem; 422 }; 423 424 struct bnxt_ctx_mem_info { 425 uint32_t qp_max_entries; 426 uint16_t qp_min_qp1_entries; 427 uint16_t qp_max_l2_entries; 428 uint16_t qp_entry_size; 429 uint16_t srq_max_l2_entries; 430 uint32_t srq_max_entries; 431 uint16_t srq_entry_size; 432 uint16_t cq_max_l2_entries; 433 uint32_t cq_max_entries; 434 uint16_t cq_entry_size; 435 uint16_t vnic_max_vnic_entries; 436 uint16_t vnic_max_ring_table_entries; 437 uint16_t vnic_entry_size; 438 uint32_t stat_max_entries; 439 uint16_t stat_entry_size; 440 uint16_t tqm_entry_size; 441 uint32_t tqm_min_entries_per_ring; 442 uint32_t tqm_max_entries_per_ring; 443 uint32_t mrav_max_entries; 444 uint16_t mrav_entry_size; 445 uint16_t tim_entry_size; 446 uint32_t tim_max_entries; 447 uint8_t tqm_entries_multiple; 448 uint8_t tqm_fp_rings_count; 449 450 uint32_t flags; 451 #define BNXT_CTX_FLAG_INITED 0x01 452 453 struct bnxt_ctx_pg_info qp_mem; 454 struct bnxt_ctx_pg_info srq_mem; 455 struct bnxt_ctx_pg_info cq_mem; 456 struct bnxt_ctx_pg_info vnic_mem; 457 struct bnxt_ctx_pg_info stat_mem; 458 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; 459 }; 460 461 struct bnxt_ctx_mem_buf_info { 462 void *va; 463 rte_iova_t dma; 464 uint16_t ctx_id; 465 size_t size; 466 }; 467 468 /* Maximum Firmware Reset bail out value in milliseconds */ 469 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 470 /* Minimum time required for the firmware readiness in milliseconds */ 471 #define BNXT_MIN_FW_READY_TIMEOUT 2000 472 /* Frequency for the firmware readiness check in milliseconds */ 473 #define BNXT_FW_READY_WAIT_INTERVAL 100 474 475 #define US_PER_MS 1000 476 #define NS_PER_US 1000 477 478 struct bnxt_error_recovery_info { 479 /* All units in milliseconds */ 480 uint32_t driver_polling_freq; 481 uint32_t master_func_wait_period; 482 uint32_t normal_func_wait_period; 483 uint32_t master_func_wait_period_after_reset; 484 uint32_t max_bailout_time_after_reset; 485 #define BNXT_FW_STATUS_REG 0 486 #define BNXT_FW_HEARTBEAT_CNT_REG 1 487 #define BNXT_FW_RECOVERY_CNT_REG 2 488 #define BNXT_FW_RESET_INPROG_REG 3 489 #define BNXT_FW_STATUS_REG_CNT 4 490 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 491 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 492 uint32_t reset_inprogress_reg_mask; 493 #define BNXT_NUM_RESET_REG 16 494 uint8_t reg_array_cnt; 495 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 496 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 497 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 498 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 499 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 500 #define BNXT_FLAG_MASTER_FUNC BIT(2) 501 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 502 uint32_t flags; 503 504 uint32_t last_heart_beat; 505 uint32_t last_reset_counter; 506 }; 507 508 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 509 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 510 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 511 #define BNXT_IF_CHANGE_RETRY_COUNT 40 512 513 struct bnxt_mark_info { 514 uint32_t mark_id; 515 bool valid; 516 }; 517 518 struct bnxt_rep_info { 519 struct rte_eth_dev *vfr_eth_dev; 520 pthread_mutex_t vfr_lock; 521 pthread_mutex_t vfr_start_lock; 522 bool conduit_valid; 523 }; 524 525 /* address space location of register */ 526 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 527 /* register is located in PCIe config space */ 528 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 529 /* register is located in GRC address space */ 530 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 531 /* register is located in BAR0 */ 532 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 533 /* register is located in BAR1 */ 534 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 535 536 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 537 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 538 539 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 540 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 541 542 #define BNXT_GRCP_BASE_MASK 0xfffff000 543 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 544 545 #define BNXT_FW_STATUS_HEALTHY 0x8000 546 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 547 548 #define BNXT_ETH_RSS_SUPPORT ( \ 549 ETH_RSS_IPV4 | \ 550 ETH_RSS_NONFRAG_IPV4_TCP | \ 551 ETH_RSS_NONFRAG_IPV4_UDP | \ 552 ETH_RSS_IPV6 | \ 553 ETH_RSS_NONFRAG_IPV6_TCP | \ 554 ETH_RSS_NONFRAG_IPV6_UDP) 555 556 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 557 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 558 DEV_TX_OFFLOAD_TCP_CKSUM | \ 559 DEV_TX_OFFLOAD_UDP_CKSUM | \ 560 DEV_TX_OFFLOAD_TCP_TSO | \ 561 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 562 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 563 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 564 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 565 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 566 DEV_TX_OFFLOAD_QINQ_INSERT | \ 567 DEV_TX_OFFLOAD_MULTI_SEGS) 568 569 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 570 DEV_RX_OFFLOAD_VLAN_STRIP | \ 571 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 572 DEV_RX_OFFLOAD_UDP_CKSUM | \ 573 DEV_RX_OFFLOAD_TCP_CKSUM | \ 574 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 575 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 576 DEV_RX_OFFLOAD_KEEP_CRC | \ 577 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 578 DEV_RX_OFFLOAD_TCP_LRO | \ 579 DEV_RX_OFFLOAD_SCATTER | \ 580 DEV_RX_OFFLOAD_RSS_HASH) 581 582 #define MAX_TABLE_SUPPORT 4 583 #define MAX_DIR_SUPPORT 2 584 struct bnxt_dmabuf_info { 585 uint32_t entry_num; 586 int fd[MAX_DIR_SUPPORT][MAX_TABLE_SUPPORT]; 587 }; 588 589 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 590 591 struct bnxt_flow_stat_info { 592 uint16_t max_fc; 593 uint16_t flow_count; 594 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 595 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 596 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 597 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 598 }; 599 600 struct bnxt { 601 void *bar0; 602 603 struct rte_eth_dev *eth_dev; 604 struct rte_pci_device *pdev; 605 void *doorbell_base; 606 607 uint32_t flags; 608 #define BNXT_FLAG_REGISTERED BIT(0) 609 #define BNXT_FLAG_VF BIT(1) 610 #define BNXT_FLAG_PORT_STATS BIT(2) 611 #define BNXT_FLAG_JUMBO BIT(3) 612 #define BNXT_FLAG_SHORT_CMD BIT(4) 613 #define BNXT_FLAG_UPDATE_HASH BIT(5) 614 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 615 #define BNXT_FLAG_MULTI_HOST BIT(7) 616 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 617 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 618 #define BNXT_FLAG_KONG_MB_EN BIT(10) 619 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 620 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 621 #define BNXT_FLAG_THOR_CHIP BIT(13) 622 #define BNXT_FLAG_STINGRAY BIT(14) 623 #define BNXT_FLAG_FW_RESET BIT(15) 624 #define BNXT_FLAG_FATAL_ERROR BIT(16) 625 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 626 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 627 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 628 #define BNXT_FLAG_NEW_RM BIT(20) 629 #define BNXT_FLAG_NPAR_PF BIT(21) 630 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 631 #define BNXT_FLAG_FC_THREAD BIT(23) 632 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 633 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 634 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 635 #define BNXT_FLAG_TRUFLOW_EN BIT(27) 636 #define BNXT_FLAG_GFID_ENABLE BIT(28) 637 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 638 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 639 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 640 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 641 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 642 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 643 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 644 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 645 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP) 646 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 647 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) 648 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) 649 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 650 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 651 #define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) 652 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 653 654 uint32_t fw_cap; 655 #define BNXT_FW_CAP_HOT_RESET BIT(0) 656 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 657 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 658 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 659 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 660 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 661 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(7) 662 663 pthread_mutex_t flow_lock; 664 665 uint32_t vnic_cap_flags; 666 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 667 unsigned int rx_nr_rings; 668 unsigned int rx_cp_nr_rings; 669 unsigned int rx_num_qs_per_vnic; 670 struct bnxt_rx_queue **rx_queues; 671 const void *rx_mem_zone; 672 struct rx_port_stats *hw_rx_port_stats; 673 rte_iova_t hw_rx_port_stats_map; 674 struct rx_port_stats_ext *hw_rx_port_stats_ext; 675 rte_iova_t hw_rx_port_stats_ext_map; 676 uint16_t fw_rx_port_stats_ext_size; 677 678 unsigned int tx_nr_rings; 679 unsigned int tx_cp_nr_rings; 680 struct bnxt_tx_queue **tx_queues; 681 const void *tx_mem_zone; 682 struct tx_port_stats *hw_tx_port_stats; 683 rte_iova_t hw_tx_port_stats_map; 684 struct tx_port_stats_ext *hw_tx_port_stats_ext; 685 rte_iova_t hw_tx_port_stats_ext_map; 686 uint16_t fw_tx_port_stats_ext_size; 687 688 /* Default completion ring */ 689 struct bnxt_cp_ring_info *async_cp_ring; 690 struct bnxt_cp_ring_info *rxtx_nq_ring; 691 uint32_t max_ring_grps; 692 struct bnxt_ring_grp_info *grp_info; 693 694 unsigned int nr_vnics; 695 696 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 697 struct bnxt_vnic_info *vnic_info; 698 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 699 700 struct bnxt_filter_info *filter_info; 701 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 702 703 struct bnxt_irq *irq_tbl; 704 705 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 706 707 uint16_t chimp_cmd_seq; 708 uint16_t kong_cmd_seq; 709 void *hwrm_cmd_resp_addr; 710 rte_iova_t hwrm_cmd_resp_dma_addr; 711 void *hwrm_short_cmd_req_addr; 712 rte_iova_t hwrm_short_cmd_req_dma_addr; 713 rte_spinlock_t hwrm_lock; 714 pthread_mutex_t def_cp_lock; 715 pthread_mutex_t health_check_lock; 716 uint16_t max_req_len; 717 uint16_t max_resp_len; 718 uint16_t hwrm_max_ext_req_len; 719 720 /* default command timeout value of 500ms */ 721 #define DFLT_HWRM_CMD_TIMEOUT 500000 722 /* short command timeout value of 50ms */ 723 #define SHORT_HWRM_CMD_TIMEOUT 50000 724 /* default HWRM request timeout value */ 725 uint32_t hwrm_cmd_timeout; 726 727 struct bnxt_link_info *link_info; 728 struct bnxt_cos_queue_info *rx_cos_queue; 729 struct bnxt_cos_queue_info *tx_cos_queue; 730 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 731 uint8_t rx_cosq_cnt; 732 uint8_t max_tc; 733 uint8_t max_lltc; 734 uint8_t max_q; 735 736 uint16_t fw_fid; 737 uint16_t max_rsscos_ctx; 738 uint16_t max_cp_rings; 739 uint16_t max_tx_rings; 740 uint16_t max_rx_rings; 741 #define MAX_STINGRAY_RINGS 128U 742 /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */ 743 #define BNXT_MAX_RX_RINGS(bp) \ 744 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \ 745 MAX_STINGRAY_RINGS), \ 746 bp->max_stat_ctx / 2U) : \ 747 RTE_MIN(bp->max_rx_rings / 2U, \ 748 bp->max_stat_ctx / 2U)) 749 #define BNXT_MAX_TX_RINGS(bp) \ 750 (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp))) 751 752 #define BNXT_MAX_RINGS(bp) \ 753 (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \ 754 BNXT_MAX_TX_RINGS(bp))) 755 756 #define BNXT_MAX_VF_REP_RINGS 8 757 758 uint16_t max_nq_rings; 759 uint16_t max_l2_ctx; 760 uint16_t max_rx_em_flows; 761 uint16_t max_vnics; 762 uint16_t max_stat_ctx; 763 uint16_t max_tpa_v2; 764 uint16_t first_vf_id; 765 uint16_t vlan; 766 #define BNXT_OUTER_TPID_MASK 0x0000ffff 767 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 768 #define BNXT_OUTER_TPID_BD_SHFT 16 769 uint32_t outer_tpid_bd; 770 struct bnxt_pf_info *pf; 771 struct bnxt_parent_info *parent; 772 uint8_t port_cnt; 773 uint8_t vxlan_port_cnt; 774 uint8_t geneve_port_cnt; 775 uint16_t vxlan_port; 776 uint16_t geneve_port; 777 uint16_t vxlan_fw_dst_port_id; 778 uint16_t geneve_fw_dst_port_id; 779 uint32_t fw_ver; 780 uint32_t hwrm_spec_code; 781 782 struct bnxt_led_info *leds; 783 struct bnxt_ptp_cfg *ptp_cfg; 784 uint16_t vf_resv_strategy; 785 struct bnxt_ctx_mem_info *ctx; 786 787 uint16_t fw_reset_min_msecs; 788 uint16_t fw_reset_max_msecs; 789 uint16_t switch_domain_id; 790 uint16_t num_reps; 791 struct bnxt_rep_info *rep_info; 792 uint16_t *cfa_code_map; 793 /* Struct to hold adapter error recovery related info */ 794 struct bnxt_error_recovery_info *recovery_info; 795 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 796 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 797 #define BNXT_FLOW_ID_MASK 0x0000ffff 798 struct bnxt_mark_info *mark_table; 799 800 #define BNXT_SVIF_INVALID 0xFFFF 801 uint16_t func_svif; 802 uint16_t port_svif; 803 804 struct tf tfp; 805 struct bnxt_dmabuf_info dmabuf; 806 struct bnxt_ulp_context *ulp_ctx; 807 struct bnxt_flow_stat_info *flow_stat; 808 uint8_t flow_xstat; 809 uint16_t max_num_kflows; 810 uint16_t tx_cfa_action; 811 }; 812 813 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 814 815 /** 816 * Structure to store private data for each VF representor instance 817 */ 818 struct bnxt_vf_representor { 819 uint16_t switch_domain_id; 820 uint16_t vf_id; 821 uint16_t fw_fid; 822 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 823 uint16_t dflt_vnic_id; 824 uint16_t svif; 825 uint16_t vfr_tx_cfa_action; 826 uint32_t dpdk_port_id; 827 /* Private data store of associated PF/Trusted VF */ 828 struct rte_eth_dev *parent_dev; 829 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 830 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 831 struct bnxt_rx_queue **rx_queues; 832 unsigned int rx_nr_rings; 833 unsigned int tx_nr_rings; 834 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 835 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 836 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 837 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 838 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 839 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 840 }; 841 842 struct bnxt_vf_rep_tx_queue { 843 struct bnxt_tx_queue *txq; 844 struct bnxt_vf_representor *bp; 845 }; 846 847 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 848 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 849 bool exp_link_status); 850 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 851 int is_bnxt_in_error(struct bnxt *bp); 852 853 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 854 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 855 void bnxt_schedule_fw_health_check(struct bnxt *bp); 856 857 bool is_bnxt_supported(struct rte_eth_dev *dev); 858 bool bnxt_stratus_device(struct bnxt *bp); 859 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 860 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 861 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 862 int wait_to_complete); 863 864 extern const struct rte_flow_ops bnxt_flow_ops; 865 866 #define bnxt_acquire_flow_lock(bp) \ 867 pthread_mutex_lock(&(bp)->flow_lock) 868 869 #define bnxt_release_flow_lock(bp) \ 870 pthread_mutex_unlock(&(bp)->flow_lock) 871 872 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 873 if ((vnic_id) >= (bp)->max_vnics) { \ 874 rte_flow_error_set(error, \ 875 EINVAL, \ 876 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 877 NULL, \ 878 "Group id is invalid!"); \ 879 rc = -rte_errno; \ 880 goto ret; \ 881 } \ 882 } while (0) 883 884 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 885 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 886 887 extern int bnxt_logtype_driver; 888 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 889 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 890 __func__, ## args) 891 892 #define PMD_DRV_LOG(level, fmt, args...) \ 893 PMD_DRV_LOG_RAW(level, fmt, ## args) 894 895 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 896 int32_t bnxt_ulp_port_init(struct bnxt *bp); 897 void bnxt_ulp_port_deinit(struct bnxt *bp); 898 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 899 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 900 int32_t 901 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 902 int32_t 903 bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr); 904 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type); 905 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif, 906 enum bnxt_ulp_intf_type type); 907 uint16_t bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type); 908 uint16_t bnxt_get_parif(uint16_t port, enum bnxt_ulp_intf_type type); 909 uint16_t bnxt_get_phy_port_id(uint16_t port); 910 uint16_t bnxt_get_vport(uint16_t port); 911 enum bnxt_ulp_intf_type 912 bnxt_get_interface_type(uint16_t port); 913 int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev); 914 915 void bnxt_cancel_fc_thread(struct bnxt *bp); 916 void bnxt_flow_cnt_alarm_cb(void *arg); 917 int bnxt_flow_stats_req(struct bnxt *bp); 918 int bnxt_flow_stats_cnt(struct bnxt *bp); 919 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 920 921 int 922 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 923 enum rte_filter_type filter_type, 924 enum rte_filter_op filter_op, void *arg); 925 #endif 926