1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57304_VF 0x16cb 37 #define BROADCOM_DEV_ID_57417_MF 0x16cc 38 #define BROADCOM_DEV_ID_NS2 0x16cd 39 #define BROADCOM_DEV_ID_57406_VF 0x16d3 40 #define BROADCOM_DEV_ID_57412 0x16d6 41 #define BROADCOM_DEV_ID_57414 0x16d7 42 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 43 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 44 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 45 #define BROADCOM_DEV_ID_57412_MF 0x16de 46 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 47 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 48 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 49 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 50 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 51 #define BROADCOM_DEV_ID_57407_MF 0x16ea 52 #define BROADCOM_DEV_ID_57414_MF 0x16ec 53 #define BROADCOM_DEV_ID_57416_MF 0x16ee 54 #define BROADCOM_DEV_ID_57508 0x1750 55 #define BROADCOM_DEV_ID_57504 0x1751 56 #define BROADCOM_DEV_ID_57502 0x1752 57 #define BROADCOM_DEV_ID_57508_MF1 0x1800 58 #define BROADCOM_DEV_ID_57504_MF1 0x1801 59 #define BROADCOM_DEV_ID_57502_MF1 0x1802 60 #define BROADCOM_DEV_ID_57508_MF2 0x1803 61 #define BROADCOM_DEV_ID_57504_MF2 0x1804 62 #define BROADCOM_DEV_ID_57502_MF2 0x1805 63 #define BROADCOM_DEV_ID_57500_VF1 0x1806 64 #define BROADCOM_DEV_ID_57500_VF2 0x1807 65 #define BROADCOM_DEV_ID_58802 0xd802 66 #define BROADCOM_DEV_ID_58804 0xd804 67 #define BROADCOM_DEV_ID_58808 0x16f0 68 #define BROADCOM_DEV_ID_58802_VF 0xd800 69 #define BROADCOM_DEV_ID_58812 0xd812 70 #define BROADCOM_DEV_ID_58814 0xd814 71 #define BROADCOM_DEV_ID_58818 0xd818 72 #define BROADCOM_DEV_ID_58818_VF 0xd82e 73 74 #define BROADCOM_DEV_957508_N2100 0x5208 75 #define IS_BNXT_DEV_957508_N2100(bp) \ 76 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) 77 78 #define BNXT_MAX_MTU 9574 79 #define BNXT_NUM_VLANS 2 80 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 81 RTE_ETHER_CRC_LEN +\ 82 (BNXT_NUM_VLANS * RTE_VLAN_HLEN)) 83 /* FW adds extra 4 bytes for FCS */ 84 #define BNXT_VNIC_MRU(mtu)\ 85 ((mtu) + RTE_ETHER_HDR_LEN + RTE_VLAN_HLEN * BNXT_NUM_VLANS) 86 #define BNXT_VF_RSV_NUM_RSS_CTX 1 87 #define BNXT_VF_RSV_NUM_L2_CTX 4 88 /* TODO: For now, do not support VMDq/RFS on VFs. */ 89 #define BNXT_VF_RSV_NUM_VNIC 1 90 #define BNXT_MAX_LED 4 91 #define BNXT_MIN_RING_DESC 16 92 #define BNXT_MAX_TX_RING_DESC 4096 93 #define BNXT_MAX_RX_RING_DESC 8192 94 #define BNXT_DB_SIZE 0x80 95 96 #define TPA_MAX_AGGS 64 97 #define TPA_MAX_AGGS_TH 1024 98 99 #define TPA_MAX_NUM_SEGS 32 100 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 101 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 102 103 #define BNXT_TPA_MAX_AGGS(bp) \ 104 (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \ 105 TPA_MAX_AGGS) 106 107 #define BNXT_TPA_MAX_SEGS(bp) \ 108 (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \ 109 TPA_MAX_SEGS) 110 111 /* 112 * Define the number of async completion rings to be used. Set to zero for 113 * configurations in which the maximum number of packet completion rings 114 * for packet completions is desired or when async completion handling 115 * cannot be interrupt-driven. 116 */ 117 #ifdef RTE_EXEC_ENV_FREEBSD 118 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 119 #define BNXT_NUM_ASYNC_CPR(bp) 0U 120 #else 121 #define BNXT_NUM_ASYNC_CPR(bp) 1U 122 #endif 123 124 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 125 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 126 127 /* Chimp Communication Channel */ 128 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 129 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 130 /* Kong Communication Channel */ 131 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 132 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 133 134 #define BNXT_INT_LAT_TMR_MIN 75 135 #define BNXT_INT_LAT_TMR_MAX 150 136 #define BNXT_NUM_CMPL_AGGR_INT 36 137 #define BNXT_CMPL_AGGR_DMA_TMR 37 138 #define BNXT_NUM_CMPL_DMA_AGGR 36 139 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 140 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 141 142 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 143 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 144 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 145 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 146 #define BNXT_DEFAULT_VNIC_ALLOC \ 147 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 148 #define BNXT_DEFAULT_VNIC_FREE \ 149 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 150 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 151 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 152 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 153 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 154 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 155 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 156 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 157 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 158 159 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 160 (((data1) & \ 161 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\ 162 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 163 164 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ 165 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) 166 167 struct bnxt_led_info { 168 uint8_t num_leds; 169 uint8_t led_id; 170 uint8_t led_type; 171 uint8_t led_group_id; 172 uint8_t unused; 173 uint16_t led_state_caps; 174 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 175 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 176 177 uint16_t led_color_caps; 178 }; 179 180 struct bnxt_led_cfg { 181 uint8_t led_id; 182 uint8_t led_state; 183 uint8_t led_color; 184 uint8_t unused; 185 uint16_t led_blink_on; 186 uint16_t led_blink_off; 187 uint8_t led_group_id; 188 uint8_t rsvd; 189 }; 190 191 #define BNXT_LED_DFLT_ENA \ 192 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 193 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 194 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 195 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 196 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 197 198 #define BNXT_LED_DFLT_ENA_SHIFT 6 199 200 #define BNXT_LED_DFLT_ENABLES(x) \ 201 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 202 203 struct bnxt_vlan_table_entry { 204 uint16_t tpid; 205 uint16_t vid; 206 } __rte_packed; 207 208 struct bnxt_vlan_antispoof_table_entry { 209 uint16_t tpid; 210 uint16_t vid; 211 uint16_t mask; 212 } __rte_packed; 213 214 struct bnxt_child_vf_info { 215 void *req_buf; 216 struct bnxt_vlan_table_entry *vlan_table; 217 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 218 STAILQ_HEAD(, bnxt_filter_info) filter; 219 uint32_t func_cfg_flags; 220 uint32_t l2_rx_mask; 221 uint16_t fid; 222 uint16_t max_tx_rate; 223 uint16_t dflt_vlan; 224 uint16_t vlan_count; 225 uint8_t mac_spoof_en; 226 uint8_t vlan_spoof_en; 227 bool random_mac; 228 bool persist_stats; 229 }; 230 231 struct bnxt_parent_info { 232 #define BNXT_PF_FID_INVALID 0xFFFF 233 uint16_t fid; 234 uint16_t vnic; 235 uint16_t port_id; 236 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 237 }; 238 239 struct bnxt_pf_info { 240 #define BNXT_FIRST_PF_FID 1 241 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 242 #define BNXT_MAX_VF_REPS_WH 64 243 #define BNXT_MAX_VF_REPS_TH 256 244 #define BNXT_MAX_VF_REPS(bp) \ 245 (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ 246 BNXT_MAX_VF_REPS_WH) 247 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 248 #define BNXT_FIRST_VF_FID 128 249 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 250 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 251 BNXT_PF_RINGS_USED(bp)) 252 uint16_t port_id; 253 uint16_t first_vf_id; 254 uint16_t active_vfs; 255 uint16_t max_vfs; 256 uint16_t total_vfs; /* Total VFs possible. 257 * Not necessarily enabled. 258 */ 259 uint32_t func_cfg_flags; 260 void *vf_req_buf; 261 rte_iova_t vf_req_buf_dma_addr; 262 uint32_t vf_req_fwd[8]; 263 uint16_t total_vnics; 264 struct bnxt_child_vf_info *vf_info; 265 #define BNXT_EVB_MODE_NONE 0 266 #define BNXT_EVB_MODE_VEB 1 267 #define BNXT_EVB_MODE_VEPA 2 268 uint8_t evb_mode; 269 }; 270 271 /* Max wait time for link up is 10s and link down is 500ms */ 272 #define BNXT_MAX_LINK_WAIT_CNT 200 273 #define BNXT_MIN_LINK_WAIT_CNT 10 274 #define BNXT_LINK_WAIT_INTERVAL 50 275 struct bnxt_link_info { 276 uint32_t phy_flags; 277 uint8_t mac_type; 278 uint8_t phy_link_status; 279 uint8_t loop_back; 280 uint8_t link_up; 281 uint8_t duplex; 282 uint8_t pause; 283 uint8_t force_pause; 284 uint8_t auto_pause; 285 uint8_t auto_mode; 286 #define PHY_VER_LEN 3 287 uint8_t phy_ver[PHY_VER_LEN]; 288 uint16_t link_speed; 289 uint16_t support_speeds; 290 uint16_t auto_link_speed; 291 uint16_t force_link_speed; 292 uint16_t auto_link_speed_mask; 293 uint32_t preemphasis; 294 uint8_t phy_type; 295 uint8_t media_type; 296 uint16_t support_auto_speeds; 297 uint8_t link_signal_mode; 298 uint16_t force_pam4_link_speed; 299 uint16_t support_pam4_speeds; 300 uint16_t auto_pam4_link_speed_mask; 301 uint16_t support_pam4_auto_speeds; 302 uint8_t req_signal_mode; 303 uint8_t module_status; 304 }; 305 306 #define BNXT_COS_QUEUE_COUNT 8 307 struct bnxt_cos_queue_info { 308 uint8_t id; 309 uint8_t profile; 310 }; 311 312 struct rte_flow { 313 STAILQ_ENTRY(rte_flow) next; 314 struct bnxt_filter_info *filter; 315 struct bnxt_vnic_info *vnic; 316 }; 317 318 #define BNXT_PTP_RX_PND_CNT 10 319 #define BNXT_PTP_FLAGS_PATH_TX 0x0 320 #define BNXT_PTP_FLAGS_PATH_RX 0x1 321 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 322 #define BNXT_PTP_CURRENT_TIME_MASK 0xFFFF00000000ULL 323 324 struct bnxt_ptp_cfg { 325 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 326 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 327 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 328 struct rte_timecounter tc; 329 struct rte_timecounter tx_tstamp_tc; 330 struct rte_timecounter rx_tstamp_tc; 331 struct bnxt *bp; 332 #define BNXT_MAX_TX_TS 1 333 uint16_t rxctl; 334 #define BNXT_PTP_MSG_SYNC BIT(0) 335 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 336 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 337 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 338 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 339 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 340 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 341 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 342 #define BNXT_PTP_MSG_SIGNALING BIT(12) 343 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 344 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 345 BNXT_PTP_MSG_DELAY_REQ | \ 346 BNXT_PTP_MSG_PDELAY_REQ | \ 347 BNXT_PTP_MSG_PDELAY_RESP) 348 uint8_t tx_tstamp_en:1; 349 int rx_filter; 350 351 #define BNXT_PTP_RX_TS_L 0 352 #define BNXT_PTP_RX_TS_H 1 353 #define BNXT_PTP_RX_SEQ 2 354 #define BNXT_PTP_RX_FIFO 3 355 #define BNXT_PTP_RX_FIFO_PENDING 0x1 356 #define BNXT_PTP_RX_FIFO_ADV 4 357 #define BNXT_PTP_RX_REGS 5 358 359 #define BNXT_PTP_TX_TS_L 0 360 #define BNXT_PTP_TX_TS_H 1 361 #define BNXT_PTP_TX_SEQ 2 362 #define BNXT_PTP_TX_FIFO 3 363 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 364 #define BNXT_PTP_TX_REGS 4 365 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 366 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 367 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 368 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 369 370 /* On Thor, the Rx timestamp is present in the Rx completion record */ 371 uint64_t rx_timestamp; 372 uint64_t current_time; 373 }; 374 375 struct bnxt_coal { 376 uint16_t num_cmpl_aggr_int; 377 uint16_t num_cmpl_dma_aggr; 378 uint16_t num_cmpl_dma_aggr_during_int; 379 uint16_t int_lat_tmr_max; 380 uint16_t int_lat_tmr_min; 381 uint16_t cmpl_aggr_dma_tmr; 382 uint16_t cmpl_aggr_dma_tmr_during_int; 383 }; 384 385 /* 64-bit doorbell */ 386 #define DBR_EPOCH_MASK 0x01000000UL 387 #define DBR_EPOCH_SFT 24 388 #define DBR_XID_SFT 32 389 #define DBR_PATH_L2 (0x1ULL << 56) 390 #define DBR_VALID (0x1ULL << 58) 391 #define DBR_TYPE_SQ (0x0ULL << 60) 392 #define DBR_TYPE_SRQ (0x2ULL << 60) 393 #define DBR_TYPE_CQ (0x4ULL << 60) 394 #define DBR_TYPE_NQ (0xaULL << 60) 395 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 396 397 #define DB_PF_OFFSET 0x10000 398 #define DB_VF_OFFSET 0x4000 399 400 #define BNXT_RSS_TBL_SIZE_P5 512U 401 #define BNXT_RSS_ENTRIES_PER_CTX_P5 64 402 #define BNXT_MAX_RSS_CTXTS_P5 \ 403 (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5) 404 405 #define BNXT_MAX_QUEUE 8 406 #define BNXT_MAX_TQM_SP_RINGS 1 407 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 408 #define BNXT_MAX_TQM_FP_RINGS 9 409 #define BNXT_MAX_TQM_LEGACY_RINGS \ 410 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 411 #define BNXT_MAX_TQM_RINGS \ 412 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 413 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 414 #define BNXT_BACKING_STORE_CFG_LEN \ 415 sizeof(struct hwrm_func_backing_store_cfg_input) 416 #define BNXT_PAGE_SHFT 12 417 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 418 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 419 420 #define PTU_PTE_VALID 0x1UL 421 #define PTU_PTE_LAST 0x2UL 422 #define PTU_PTE_NEXT_TO_LAST 0x4UL 423 424 struct bnxt_ring_mem_info { 425 int nr_pages; 426 int page_size; 427 uint32_t flags; 428 #define BNXT_RMEM_VALID_PTE_FLAG 1 429 #define BNXT_RMEM_RING_PTE_FLAG 2 430 431 void **pg_arr; 432 rte_iova_t *dma_arr; 433 const struct rte_memzone *mz; 434 435 uint64_t *pg_tbl; 436 rte_iova_t pg_tbl_map; 437 const struct rte_memzone *pg_tbl_mz; 438 439 int vmem_size; 440 void **vmem; 441 }; 442 443 struct bnxt_ctx_pg_info { 444 uint32_t entries; 445 void *ctx_pg_arr[MAX_CTX_PAGES]; 446 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 447 struct bnxt_ring_mem_info ring_mem; 448 }; 449 450 struct bnxt_ctx_mem_info { 451 uint32_t qp_max_entries; 452 uint16_t qp_min_qp1_entries; 453 uint16_t qp_max_l2_entries; 454 uint16_t qp_entry_size; 455 uint16_t srq_max_l2_entries; 456 uint32_t srq_max_entries; 457 uint16_t srq_entry_size; 458 uint16_t cq_max_l2_entries; 459 uint32_t cq_max_entries; 460 uint16_t cq_entry_size; 461 uint16_t vnic_max_vnic_entries; 462 uint16_t vnic_max_ring_table_entries; 463 uint16_t vnic_entry_size; 464 uint32_t stat_max_entries; 465 uint16_t stat_entry_size; 466 uint16_t tqm_entry_size; 467 uint32_t tqm_min_entries_per_ring; 468 uint32_t tqm_max_entries_per_ring; 469 uint32_t mrav_max_entries; 470 uint16_t mrav_entry_size; 471 uint16_t tim_entry_size; 472 uint32_t tim_max_entries; 473 uint8_t tqm_entries_multiple; 474 uint8_t tqm_fp_rings_count; 475 476 uint32_t flags; 477 #define BNXT_CTX_FLAG_INITED 0x01 478 479 struct bnxt_ctx_pg_info qp_mem; 480 struct bnxt_ctx_pg_info srq_mem; 481 struct bnxt_ctx_pg_info cq_mem; 482 struct bnxt_ctx_pg_info vnic_mem; 483 struct bnxt_ctx_pg_info stat_mem; 484 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; 485 }; 486 487 struct bnxt_ctx_mem_buf_info { 488 void *va; 489 rte_iova_t dma; 490 uint16_t ctx_id; 491 size_t size; 492 }; 493 494 /* Maximum Firmware Reset bail out value in milliseconds */ 495 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 496 /* Minimum time required for the firmware readiness in milliseconds */ 497 #define BNXT_MIN_FW_READY_TIMEOUT 2000 498 /* Frequency for the firmware readiness check in milliseconds */ 499 #define BNXT_FW_READY_WAIT_INTERVAL 100 500 501 #define US_PER_MS 1000 502 #define NS_PER_US 1000 503 504 struct bnxt_error_recovery_info { 505 /* All units in milliseconds */ 506 uint32_t driver_polling_freq; 507 uint32_t primary_func_wait_period; 508 uint32_t normal_func_wait_period; 509 uint32_t primary_func_wait_period_after_reset; 510 uint32_t max_bailout_time_after_reset; 511 #define BNXT_FW_STATUS_REG 0 512 #define BNXT_FW_HEARTBEAT_CNT_REG 1 513 #define BNXT_FW_RECOVERY_CNT_REG 2 514 #define BNXT_FW_RESET_INPROG_REG 3 515 #define BNXT_FW_STATUS_REG_CNT 4 516 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 517 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 518 uint32_t reset_inprogress_reg_mask; 519 #define BNXT_NUM_RESET_REG 16 520 uint8_t reg_array_cnt; 521 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 522 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 523 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 524 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 525 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 526 #define BNXT_FLAG_PRIMARY_FUNC BIT(2) 527 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 528 uint32_t flags; 529 530 uint32_t last_heart_beat; 531 uint32_t last_reset_counter; 532 }; 533 534 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 535 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 536 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 537 #define BNXT_IF_CHANGE_RETRY_COUNT 40 538 539 struct bnxt_mark_info { 540 uint32_t mark_id; 541 bool valid; 542 }; 543 544 struct bnxt_rep_info { 545 struct rte_eth_dev *vfr_eth_dev; 546 pthread_mutex_t vfr_lock; 547 pthread_mutex_t vfr_start_lock; 548 bool conduit_valid; 549 }; 550 551 /* address space location of register */ 552 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 553 /* register is located in PCIe config space */ 554 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 555 /* register is located in GRC address space */ 556 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 557 /* register is located in BAR0 */ 558 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 559 /* register is located in BAR1 */ 560 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 561 562 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 563 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 564 565 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 566 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 567 568 #define BNXT_GRCP_BASE_MASK 0xfffff000 569 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 570 571 #define BNXT_FW_STATUS_HEALTHY 0x8000 572 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 573 574 #define BNXT_ETH_RSS_SUPPORT ( \ 575 RTE_ETH_RSS_IPV4 | \ 576 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 577 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 578 RTE_ETH_RSS_IPV6 | \ 579 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 580 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ 581 RTE_ETH_RSS_LEVEL_MASK) 582 583 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \ 584 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \ 585 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \ 586 RTE_ETH_TX_OFFLOAD_TCP_TSO | \ 587 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 588 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \ 589 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | \ 590 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO | \ 591 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \ 592 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \ 593 RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 594 595 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \ 596 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \ 597 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \ 598 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | \ 599 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 600 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | \ 601 RTE_ETH_RX_OFFLOAD_KEEP_CRC | \ 602 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | \ 603 RTE_ETH_RX_OFFLOAD_TCP_LRO | \ 604 RTE_ETH_RX_OFFLOAD_SCATTER | \ 605 RTE_ETH_RX_OFFLOAD_RSS_HASH) 606 607 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 608 609 struct bnxt_flow_stat_info { 610 uint16_t max_fc; 611 uint16_t flow_count; 612 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 613 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 614 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 615 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 616 }; 617 618 struct bnxt_ring_stats { 619 /* Number of transmitted unicast packets */ 620 uint64_t tx_ucast_pkts; 621 /* Number of transmitted multicast packets */ 622 uint64_t tx_mcast_pkts; 623 /* Number of transmitted broadcast packets */ 624 uint64_t tx_bcast_pkts; 625 /* Number of packets discarded in transmit path */ 626 uint64_t tx_discard_pkts; 627 /* Number of packets in transmit path with error */ 628 uint64_t tx_error_pkts; 629 /* Number of transmitted bytes for unicast traffic */ 630 uint64_t tx_ucast_bytes; 631 /* Number of transmitted bytes for multicast traffic */ 632 uint64_t tx_mcast_bytes; 633 /* Number of transmitted bytes for broadcast traffic */ 634 uint64_t tx_bcast_bytes; 635 /* Number of received unicast packets */ 636 uint64_t rx_ucast_pkts; 637 /* Number of received multicast packets */ 638 uint64_t rx_mcast_pkts; 639 /* Number of received broadcast packets */ 640 uint64_t rx_bcast_pkts; 641 /* Number of packets discarded in receive path */ 642 uint64_t rx_discard_pkts; 643 /* Number of packets in receive path with errors */ 644 uint64_t rx_error_pkts; 645 /* Number of received bytes for unicast traffic */ 646 uint64_t rx_ucast_bytes; 647 /* Number of received bytes for multicast traffic */ 648 uint64_t rx_mcast_bytes; 649 /* Number of received bytes for broadcast traffic */ 650 uint64_t rx_bcast_bytes; 651 /* Number of aggregated unicast packets */ 652 uint64_t rx_agg_pkts; 653 /* Number of aggregated unicast bytes */ 654 uint64_t rx_agg_bytes; 655 /* Number of aggregation events */ 656 uint64_t rx_agg_events; 657 /* Number of aborted aggregations */ 658 uint64_t rx_agg_aborts; 659 }; 660 661 struct bnxt { 662 void *bar0; 663 664 struct rte_eth_dev *eth_dev; 665 struct rte_pci_device *pdev; 666 void *doorbell_base; 667 int legacy_db_size; 668 669 uint32_t flags; 670 #define BNXT_FLAG_REGISTERED BIT(0) 671 #define BNXT_FLAG_VF BIT(1) 672 #define BNXT_FLAG_PORT_STATS BIT(2) 673 #define BNXT_FLAG_JUMBO BIT(3) 674 #define BNXT_FLAG_SHORT_CMD BIT(4) 675 #define BNXT_FLAG_UPDATE_HASH BIT(5) 676 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 677 #define BNXT_FLAG_MULTI_HOST BIT(7) 678 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 679 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 680 #define BNXT_FLAG_KONG_MB_EN BIT(10) 681 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 682 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 683 #define BNXT_FLAG_CHIP_P5 BIT(13) 684 #define BNXT_FLAG_STINGRAY BIT(14) 685 #define BNXT_FLAG_FW_RESET BIT(15) 686 #define BNXT_FLAG_FATAL_ERROR BIT(16) 687 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 688 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 689 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 690 #define BNXT_FLAG_NEW_RM BIT(20) 691 #define BNXT_FLAG_NPAR_PF BIT(21) 692 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 693 #define BNXT_FLAG_FC_THREAD BIT(23) 694 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 695 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 696 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 697 #define BNXT_FLAG_GFID_ENABLE BIT(27) 698 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 699 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 700 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 701 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 702 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 703 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 704 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 705 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 706 #define BNXT_CHIP_P5(bp) ((bp)->flags & BNXT_FLAG_CHIP_P5) 707 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 708 #define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp) 709 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp)) 710 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 711 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 712 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 713 714 uint32_t flags2; 715 #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) 716 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) 717 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ 718 ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) 719 720 uint16_t chip_num; 721 #define CHIP_NUM_58818 0xd818 722 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) 723 #define BNXT_FLAGS2_MULTIROOT_EN BIT(4) 724 #define BNXT_MULTIROOT_EN(bp) \ 725 ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) 726 727 uint32_t fw_cap; 728 #define BNXT_FW_CAP_HOT_RESET BIT(0) 729 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 730 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 731 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 732 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) 733 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 734 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 735 #define BNXT_FW_CAP_LINK_ADMIN BIT(7) 736 #define BNXT_FW_CAP_TRUFLOW_EN BIT(8) 737 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9) 738 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 739 740 pthread_mutex_t flow_lock; 741 742 uint32_t vnic_cap_flags; 743 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 744 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) 745 #define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) 746 #define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3) 747 #define BNXT_RX_VLAN_STRIP_EN(bp) ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 748 unsigned int rx_nr_rings; 749 unsigned int rx_cp_nr_rings; 750 unsigned int rx_num_qs_per_vnic; 751 struct bnxt_rx_queue **rx_queues; 752 const void *rx_mem_zone; 753 struct rx_port_stats *hw_rx_port_stats; 754 rte_iova_t hw_rx_port_stats_map; 755 struct rx_port_stats_ext *hw_rx_port_stats_ext; 756 rte_iova_t hw_rx_port_stats_ext_map; 757 uint16_t fw_rx_port_stats_ext_size; 758 759 unsigned int tx_nr_rings; 760 unsigned int tx_cp_nr_rings; 761 struct bnxt_tx_queue **tx_queues; 762 const void *tx_mem_zone; 763 struct tx_port_stats *hw_tx_port_stats; 764 rte_iova_t hw_tx_port_stats_map; 765 struct tx_port_stats_ext *hw_tx_port_stats_ext; 766 rte_iova_t hw_tx_port_stats_ext_map; 767 uint16_t fw_tx_port_stats_ext_size; 768 769 /* Default completion ring */ 770 struct bnxt_cp_ring_info *async_cp_ring; 771 struct bnxt_cp_ring_info *rxtx_nq_ring; 772 uint32_t max_ring_grps; 773 struct bnxt_ring_grp_info *grp_info; 774 775 uint16_t nr_vnics; 776 777 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 778 struct bnxt_vnic_info *vnic_info; 779 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 780 781 struct bnxt_filter_info *filter_info; 782 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 783 784 struct bnxt_irq *irq_tbl; 785 786 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 787 788 uint16_t chimp_cmd_seq; 789 uint16_t kong_cmd_seq; 790 void *hwrm_cmd_resp_addr; 791 rte_iova_t hwrm_cmd_resp_dma_addr; 792 void *hwrm_short_cmd_req_addr; 793 rte_iova_t hwrm_short_cmd_req_dma_addr; 794 rte_spinlock_t hwrm_lock; 795 /* synchronize between dev_configure_op and int handler */ 796 pthread_mutex_t def_cp_lock; 797 /* synchronize between dev_start_op and async evt handler 798 * Locking sequence in async evt handler will be 799 * def_cp_lock 800 * health_check_lock 801 */ 802 pthread_mutex_t health_check_lock; 803 /* synchronize between dev_stop/dev_close_op and 804 * error recovery thread triggered as part of 805 * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 806 */ 807 pthread_mutex_t err_recovery_lock; 808 uint16_t max_req_len; 809 uint16_t max_resp_len; 810 uint16_t hwrm_max_ext_req_len; 811 812 /* default command timeout value of 500ms */ 813 #define DFLT_HWRM_CMD_TIMEOUT 500000 814 /* short command timeout value of 50ms */ 815 #define SHORT_HWRM_CMD_TIMEOUT 50000 816 /* default HWRM request timeout value */ 817 uint32_t hwrm_cmd_timeout; 818 819 struct bnxt_link_info *link_info; 820 struct bnxt_cos_queue_info *rx_cos_queue; 821 struct bnxt_cos_queue_info *tx_cos_queue; 822 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 823 uint8_t rx_cosq_cnt; 824 uint8_t max_tc; 825 uint8_t max_lltc; 826 uint8_t max_q; 827 828 uint16_t fw_fid; 829 uint16_t max_rsscos_ctx; 830 uint16_t max_cp_rings; 831 uint16_t max_tx_rings; 832 uint16_t max_rx_rings; 833 #define MAX_STINGRAY_RINGS 236U 834 #define BNXT_MAX_VF_REP_RINGS 8U 835 836 uint16_t max_nq_rings; 837 uint16_t max_l2_ctx; 838 uint16_t max_rx_em_flows; 839 uint16_t max_vnics; 840 uint16_t max_stat_ctx; 841 uint16_t max_tpa_v2; 842 uint16_t first_vf_id; 843 uint16_t vlan; 844 #define BNXT_OUTER_TPID_MASK 0x0000ffff 845 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 846 #define BNXT_OUTER_TPID_BD_SHFT 16 847 uint32_t outer_tpid_bd; 848 struct bnxt_pf_info *pf; 849 struct bnxt_parent_info *parent; 850 uint8_t port_cnt; 851 uint8_t vxlan_port_cnt; 852 uint8_t geneve_port_cnt; 853 uint16_t vxlan_port; 854 uint16_t geneve_port; 855 uint16_t vxlan_fw_dst_port_id; 856 uint16_t geneve_fw_dst_port_id; 857 uint32_t fw_ver; 858 uint32_t hwrm_spec_code; 859 860 struct bnxt_led_info *leds; 861 struct bnxt_ptp_cfg *ptp_cfg; 862 uint16_t vf_resv_strategy; 863 struct bnxt_ctx_mem_info *ctx; 864 865 uint16_t fw_reset_min_msecs; 866 uint16_t fw_reset_max_msecs; 867 uint16_t switch_domain_id; 868 uint16_t num_reps; 869 struct bnxt_rep_info *rep_info; 870 uint16_t *cfa_code_map; 871 /* Struct to hold adapter error recovery related info */ 872 struct bnxt_error_recovery_info *recovery_info; 873 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 874 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 875 #define BNXT_FLOW_ID_MASK 0x0000ffff 876 struct bnxt_mark_info *mark_table; 877 878 #define BNXT_SVIF_INVALID 0xFFFF 879 uint16_t func_svif; 880 uint16_t port_svif; 881 882 struct tf tfp; 883 struct tf tfp_shared; 884 struct bnxt_ulp_context *ulp_ctx; 885 struct bnxt_flow_stat_info *flow_stat; 886 uint16_t max_num_kflows; 887 uint8_t app_id; 888 uint16_t tx_cfa_action; 889 struct bnxt_ring_stats *prev_rx_ring_stats; 890 struct bnxt_ring_stats *prev_tx_ring_stats; 891 892 #define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr) 893 struct rte_ether_addr *mcast_addr_list; 894 rte_iova_t mc_list_dma_addr; 895 uint32_t nb_mc_addr; 896 uint32_t max_mcast_addr; /* maximum number of mcast filters supported */ 897 898 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 899 }; 900 901 static 902 inline uint16_t bnxt_max_rings(struct bnxt *bp) 903 { 904 uint16_t max_tx_rings = bp->max_tx_rings; 905 uint16_t max_rx_rings = bp->max_rx_rings; 906 uint16_t max_cp_rings = bp->max_cp_rings; 907 uint16_t max_rings; 908 909 /* For the sake of symmetry: 910 * max Tx rings == max Rx rings, one stat ctx for each. 911 */ 912 if (BNXT_STINGRAY(bp)) { 913 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U, 914 MAX_STINGRAY_RINGS), 915 bp->max_stat_ctx / 2U); 916 } else { 917 max_rx_rings = RTE_MIN(max_rx_rings / 2U, 918 bp->max_stat_ctx / 2U); 919 } 920 921 /* 922 * RSS table size in Thor is 512. 923 * Cap max Rx rings to the same value for RSS. 924 */ 925 if (BNXT_CHIP_P5(bp)) 926 max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5); 927 928 max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); 929 if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp)) 930 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp); 931 max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings); 932 933 return max_rings; 934 } 935 936 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 937 938 /** 939 * Structure to store private data for each VF representor instance 940 */ 941 struct bnxt_representor { 942 uint16_t switch_domain_id; 943 uint16_t vf_id; 944 #define BNXT_REP_IS_PF BIT(0) 945 #define BNXT_REP_Q_R2F_VALID BIT(1) 946 #define BNXT_REP_Q_F2R_VALID BIT(2) 947 #define BNXT_REP_FC_R2F_VALID BIT(3) 948 #define BNXT_REP_FC_F2R_VALID BIT(4) 949 #define BNXT_REP_BASED_PF_VALID BIT(5) 950 uint32_t flags; 951 uint16_t fw_fid; 952 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 953 uint16_t dflt_vnic_id; 954 uint16_t svif; 955 uint16_t vfr_tx_cfa_action; 956 uint8_t parent_pf_idx; /* Logical PF index */ 957 uint32_t dpdk_port_id; 958 uint32_t rep_based_pf; 959 uint8_t rep_q_r2f; 960 uint8_t rep_q_f2r; 961 uint8_t rep_fc_r2f; 962 uint8_t rep_fc_f2r; 963 /* Private data store of associated PF/Trusted VF */ 964 struct rte_eth_dev *parent_dev; 965 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 966 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 967 struct bnxt_rx_queue **rx_queues; 968 unsigned int rx_nr_rings; 969 unsigned int tx_nr_rings; 970 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 971 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 972 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 973 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 974 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 975 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 976 }; 977 978 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) 979 #define BNXT_REP_BASED_PF(vfr_bp) \ 980 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID) 981 982 struct bnxt_vf_rep_tx_queue { 983 struct bnxt_tx_queue *txq; 984 struct bnxt_representor *bp; 985 }; 986 987 #define I2C_DEV_ADDR_A0 0xa0 988 #define I2C_DEV_ADDR_A2 0xa2 989 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 990 #define SFF_MODULE_ID_SFP 0x3 991 #define SFF_MODULE_ID_QSFP 0xc 992 #define SFF_MODULE_ID_QSFP_PLUS 0xd 993 #define SFF_MODULE_ID_QSFP28 0x11 994 #define SFF8636_FLATMEM_OFFSET 0x2 995 #define SFF8636_FLATMEM_MASK 0x4 996 #define SFF8636_OPT_PAGES_OFFSET 0xc3 997 #define SFF8636_PAGE1_MASK 0x40 998 #define SFF8636_PAGE2_MASK 0x80 999 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1000 1001 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 1002 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1003 bool exp_link_status); 1004 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 1005 int is_bnxt_in_error(struct bnxt *bp); 1006 1007 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 1008 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 1009 void bnxt_schedule_fw_health_check(struct bnxt *bp); 1010 1011 bool is_bnxt_supported(struct rte_eth_dev *dev); 1012 bool bnxt_stratus_device(struct bnxt *bp); 1013 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 1014 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 1015 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1016 int wait_to_complete); 1017 1018 extern const struct rte_flow_ops bnxt_flow_ops; 1019 1020 #define bnxt_acquire_flow_lock(bp) \ 1021 pthread_mutex_lock(&(bp)->flow_lock) 1022 1023 #define bnxt_release_flow_lock(bp) \ 1024 pthread_mutex_unlock(&(bp)->flow_lock) 1025 1026 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 1027 if ((vnic_id) >= (bp)->max_vnics) { \ 1028 rte_flow_error_set(error, \ 1029 EINVAL, \ 1030 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 1031 NULL, \ 1032 "Group id is invalid!"); \ 1033 rc = -rte_errno; \ 1034 goto ret; \ 1035 } \ 1036 } while (0) 1037 1038 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 1039 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1040 1041 extern int bnxt_logtype_driver; 1042 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 1043 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 1044 __func__, ## args) 1045 1046 #define PMD_DRV_LOG(level, fmt, args...) \ 1047 PMD_DRV_LOG_RAW(level, fmt, ## args) 1048 1049 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 1050 int32_t bnxt_ulp_port_init(struct bnxt *bp); 1051 void bnxt_ulp_port_deinit(struct bnxt *bp); 1052 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 1053 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 1054 int32_t 1055 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 1056 int32_t 1057 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); 1058 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); 1059 1060 void bnxt_cancel_fc_thread(struct bnxt *bp); 1061 void bnxt_flow_cnt_alarm_cb(void *arg); 1062 int bnxt_flow_stats_req(struct bnxt *bp); 1063 int bnxt_flow_stats_cnt(struct bnxt *bp); 1064 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 1065 int bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 1066 const struct rte_flow_ops **ops); 1067 int bnxt_dev_start_op(struct rte_eth_dev *eth_dev); 1068 int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev); 1069 void bnxt_handle_vf_cfg_change(void *arg); 1070 1071 #endif 1072