1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _BNXT_H_ 7 #define _BNXT_H_ 8 9 #include <inttypes.h> 10 #include <stdbool.h> 11 #include <sys/queue.h> 12 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <ethdev_driver.h> 16 #include <rte_memory.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_time.h> 20 21 #include "bnxt_cpr.h" 22 #include "bnxt_util.h" 23 24 #include "tf_core.h" 25 #include "bnxt_ulp.h" 26 #include "bnxt_tf_common.h" 27 28 /* Vendor ID */ 29 #define PCI_VENDOR_ID_BROADCOM 0x14E4 30 31 /* Device IDs */ 32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 34 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 35 #define BROADCOM_DEV_ID_57414_VF 0x16c1 36 #define BROADCOM_DEV_ID_57304_VF 0x16cb 37 #define BROADCOM_DEV_ID_57417_MF 0x16cc 38 #define BROADCOM_DEV_ID_NS2 0x16cd 39 #define BROADCOM_DEV_ID_57406_VF 0x16d3 40 #define BROADCOM_DEV_ID_57412 0x16d6 41 #define BROADCOM_DEV_ID_57414 0x16d7 42 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 43 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 44 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 45 #define BROADCOM_DEV_ID_57412_MF 0x16de 46 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 47 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 48 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 49 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 50 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 51 #define BROADCOM_DEV_ID_57407_MF 0x16ea 52 #define BROADCOM_DEV_ID_57414_MF 0x16ec 53 #define BROADCOM_DEV_ID_57416_MF 0x16ee 54 #define BROADCOM_DEV_ID_57508 0x1750 55 #define BROADCOM_DEV_ID_57504 0x1751 56 #define BROADCOM_DEV_ID_57502 0x1752 57 #define BROADCOM_DEV_ID_57508_MF1 0x1800 58 #define BROADCOM_DEV_ID_57504_MF1 0x1801 59 #define BROADCOM_DEV_ID_57502_MF1 0x1802 60 #define BROADCOM_DEV_ID_57508_MF2 0x1803 61 #define BROADCOM_DEV_ID_57504_MF2 0x1804 62 #define BROADCOM_DEV_ID_57502_MF2 0x1805 63 #define BROADCOM_DEV_ID_57500_VF1 0x1806 64 #define BROADCOM_DEV_ID_57500_VF2 0x1807 65 #define BROADCOM_DEV_ID_58802 0xd802 66 #define BROADCOM_DEV_ID_58804 0xd804 67 #define BROADCOM_DEV_ID_58808 0x16f0 68 #define BROADCOM_DEV_ID_58802_VF 0xd800 69 #define BROADCOM_DEV_ID_58812 0xd812 70 #define BROADCOM_DEV_ID_58814 0xd814 71 #define BROADCOM_DEV_ID_58818 0xd818 72 #define BROADCOM_DEV_ID_58818_VF 0xd82e 73 74 #define BROADCOM_DEV_957508_N2100 0x5208 75 #define IS_BNXT_DEV_957508_N2100(bp) \ 76 ((bp)->pdev->id.subsystem_device_id == BROADCOM_DEV_957508_N2100) 77 78 #define BNXT_MAX_MTU 9574 79 #define VLAN_TAG_SIZE 4 80 #define BNXT_NUM_VLANS 2 81 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ 82 RTE_ETHER_CRC_LEN +\ 83 (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) 84 /* FW adds extra 4 bytes for FCS */ 85 #define BNXT_VNIC_MRU(mtu)\ 86 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS) 87 #define BNXT_VF_RSV_NUM_RSS_CTX 1 88 #define BNXT_VF_RSV_NUM_L2_CTX 4 89 /* TODO: For now, do not support VMDq/RFS on VFs. */ 90 #define BNXT_VF_RSV_NUM_VNIC 1 91 #define BNXT_MAX_LED 4 92 #define BNXT_MIN_RING_DESC 16 93 #define BNXT_MAX_TX_RING_DESC 4096 94 #define BNXT_MAX_RX_RING_DESC 8192 95 #define BNXT_DB_SIZE 0x80 96 97 #define TPA_MAX_AGGS 64 98 #define TPA_MAX_AGGS_TH 1024 99 100 #define TPA_MAX_NUM_SEGS 32 101 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */ 102 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ 103 104 #define BNXT_TPA_MAX_AGGS(bp) \ 105 (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \ 106 TPA_MAX_AGGS) 107 108 #define BNXT_TPA_MAX_SEGS(bp) \ 109 (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \ 110 TPA_MAX_SEGS) 111 112 /* 113 * Define the number of async completion rings to be used. Set to zero for 114 * configurations in which the maximum number of packet completion rings 115 * for packet completions is desired or when async completion handling 116 * cannot be interrupt-driven. 117 */ 118 #ifdef RTE_EXEC_ENV_FREEBSD 119 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 120 #define BNXT_NUM_ASYNC_CPR(bp) 0U 121 #else 122 #define BNXT_NUM_ASYNC_CPR(bp) 1U 123 #endif 124 125 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 126 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 127 128 /* Chimp Communication Channel */ 129 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 130 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 131 /* Kong Communication Channel */ 132 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 133 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 134 135 #define BNXT_INT_LAT_TMR_MIN 75 136 #define BNXT_INT_LAT_TMR_MAX 150 137 #define BNXT_NUM_CMPL_AGGR_INT 36 138 #define BNXT_CMPL_AGGR_DMA_TMR 37 139 #define BNXT_NUM_CMPL_DMA_AGGR 36 140 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50 141 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 142 143 #define BNXT_DEFAULT_VNIC_STATE_MASK \ 144 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 145 #define BNXT_DEFAULT_VNIC_STATE_SFT \ 146 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 147 #define BNXT_DEFAULT_VNIC_ALLOC \ 148 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 149 #define BNXT_DEFAULT_VNIC_FREE \ 150 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 151 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK \ 152 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 153 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT \ 154 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 155 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK \ 156 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 157 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT \ 158 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 159 160 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 161 (((data1) & \ 162 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\ 163 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 164 165 #define BNXT_HWRM_CMD_TO_FORWARD(cmd) \ 166 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32))) 167 168 struct bnxt_led_info { 169 uint8_t num_leds; 170 uint8_t led_id; 171 uint8_t led_type; 172 uint8_t led_group_id; 173 uint8_t unused; 174 uint16_t led_state_caps; 175 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 176 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT)) 177 178 uint16_t led_color_caps; 179 }; 180 181 struct bnxt_led_cfg { 182 uint8_t led_id; 183 uint8_t led_state; 184 uint8_t led_color; 185 uint8_t unused; 186 uint16_t led_blink_on; 187 uint16_t led_blink_off; 188 uint8_t led_group_id; 189 uint8_t rsvd; 190 }; 191 192 #define BNXT_LED_DFLT_ENA \ 193 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \ 194 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \ 195 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \ 196 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \ 197 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID) 198 199 #define BNXT_LED_DFLT_ENA_SHIFT 6 200 201 #define BNXT_LED_DFLT_ENABLES(x) \ 202 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 203 204 struct bnxt_vlan_table_entry { 205 uint16_t tpid; 206 uint16_t vid; 207 } __rte_packed; 208 209 struct bnxt_vlan_antispoof_table_entry { 210 uint16_t tpid; 211 uint16_t vid; 212 uint16_t mask; 213 } __rte_packed; 214 215 struct bnxt_child_vf_info { 216 void *req_buf; 217 struct bnxt_vlan_table_entry *vlan_table; 218 struct bnxt_vlan_antispoof_table_entry *vlan_as_table; 219 STAILQ_HEAD(, bnxt_filter_info) filter; 220 uint32_t func_cfg_flags; 221 uint32_t l2_rx_mask; 222 uint16_t fid; 223 uint16_t max_tx_rate; 224 uint16_t dflt_vlan; 225 uint16_t vlan_count; 226 uint8_t mac_spoof_en; 227 uint8_t vlan_spoof_en; 228 bool random_mac; 229 bool persist_stats; 230 }; 231 232 struct bnxt_parent_info { 233 #define BNXT_PF_FID_INVALID 0xFFFF 234 uint16_t fid; 235 uint16_t vnic; 236 uint16_t port_id; 237 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 238 }; 239 240 struct bnxt_pf_info { 241 #define BNXT_FIRST_PF_FID 1 242 #define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) 243 #define BNXT_MAX_VF_REPS_WH 64 244 #define BNXT_MAX_VF_REPS_TH 256 245 #define BNXT_MAX_VF_REPS(bp) \ 246 (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \ 247 BNXT_MAX_VF_REPS_WH) 248 #define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) 249 #define BNXT_FIRST_VF_FID 128 250 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) 251 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ 252 BNXT_PF_RINGS_USED(bp)) 253 uint16_t port_id; 254 uint16_t first_vf_id; 255 uint16_t active_vfs; 256 uint16_t max_vfs; 257 uint16_t total_vfs; /* Total VFs possible. 258 * Not necessarily enabled. 259 */ 260 uint32_t func_cfg_flags; 261 void *vf_req_buf; 262 rte_iova_t vf_req_buf_dma_addr; 263 uint32_t vf_req_fwd[8]; 264 uint16_t total_vnics; 265 struct bnxt_child_vf_info *vf_info; 266 #define BNXT_EVB_MODE_NONE 0 267 #define BNXT_EVB_MODE_VEB 1 268 #define BNXT_EVB_MODE_VEPA 2 269 uint8_t evb_mode; 270 }; 271 272 /* Max wait time for link up is 10s and link down is 500ms */ 273 #define BNXT_MAX_LINK_WAIT_CNT 200 274 #define BNXT_MIN_LINK_WAIT_CNT 10 275 #define BNXT_LINK_WAIT_INTERVAL 50 276 struct bnxt_link_info { 277 uint32_t phy_flags; 278 uint8_t mac_type; 279 uint8_t phy_link_status; 280 uint8_t loop_back; 281 uint8_t link_up; 282 uint8_t duplex; 283 uint8_t pause; 284 uint8_t force_pause; 285 uint8_t auto_pause; 286 uint8_t auto_mode; 287 #define PHY_VER_LEN 3 288 uint8_t phy_ver[PHY_VER_LEN]; 289 uint16_t link_speed; 290 uint16_t support_speeds; 291 uint16_t auto_link_speed; 292 uint16_t force_link_speed; 293 uint16_t auto_link_speed_mask; 294 uint32_t preemphasis; 295 uint8_t phy_type; 296 uint8_t media_type; 297 uint16_t support_auto_speeds; 298 uint8_t link_signal_mode; 299 uint16_t force_pam4_link_speed; 300 uint16_t support_pam4_speeds; 301 uint16_t auto_pam4_link_speeds; 302 uint16_t support_pam4_auto_speeds; 303 uint8_t req_signal_mode; 304 uint8_t module_status; 305 }; 306 307 #define BNXT_COS_QUEUE_COUNT 8 308 struct bnxt_cos_queue_info { 309 uint8_t id; 310 uint8_t profile; 311 }; 312 313 struct rte_flow { 314 STAILQ_ENTRY(rte_flow) next; 315 struct bnxt_filter_info *filter; 316 struct bnxt_vnic_info *vnic; 317 }; 318 319 #define BNXT_PTP_RX_PND_CNT 10 320 #define BNXT_PTP_FLAGS_PATH_TX 0x0 321 #define BNXT_PTP_FLAGS_PATH_RX 0x1 322 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 323 #define BNXT_PTP_CURRENT_TIME_MASK 0xFFFF00000000ULL 324 325 struct bnxt_ptp_cfg { 326 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 327 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 328 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL 329 struct rte_timecounter tc; 330 struct rte_timecounter tx_tstamp_tc; 331 struct rte_timecounter rx_tstamp_tc; 332 struct bnxt *bp; 333 #define BNXT_MAX_TX_TS 1 334 uint16_t rxctl; 335 #define BNXT_PTP_MSG_SYNC BIT(0) 336 #define BNXT_PTP_MSG_DELAY_REQ BIT(1) 337 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2) 338 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3) 339 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8) 340 #define BNXT_PTP_MSG_DELAY_RESP BIT(9) 341 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) 342 #define BNXT_PTP_MSG_ANNOUNCE BIT(11) 343 #define BNXT_PTP_MSG_SIGNALING BIT(12) 344 #define BNXT_PTP_MSG_MANAGEMENT BIT(13) 345 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ 346 BNXT_PTP_MSG_DELAY_REQ | \ 347 BNXT_PTP_MSG_PDELAY_REQ | \ 348 BNXT_PTP_MSG_PDELAY_RESP) 349 uint8_t tx_tstamp_en:1; 350 int rx_filter; 351 352 #define BNXT_PTP_RX_TS_L 0 353 #define BNXT_PTP_RX_TS_H 1 354 #define BNXT_PTP_RX_SEQ 2 355 #define BNXT_PTP_RX_FIFO 3 356 #define BNXT_PTP_RX_FIFO_PENDING 0x1 357 #define BNXT_PTP_RX_FIFO_ADV 4 358 #define BNXT_PTP_RX_REGS 5 359 360 #define BNXT_PTP_TX_TS_L 0 361 #define BNXT_PTP_TX_TS_H 1 362 #define BNXT_PTP_TX_SEQ 2 363 #define BNXT_PTP_TX_FIFO 3 364 #define BNXT_PTP_TX_FIFO_EMPTY 0x2 365 #define BNXT_PTP_TX_REGS 4 366 uint32_t rx_regs[BNXT_PTP_RX_REGS]; 367 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; 368 uint32_t tx_regs[BNXT_PTP_TX_REGS]; 369 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; 370 371 /* On Thor, the Rx timestamp is present in the Rx completion record */ 372 uint64_t rx_timestamp; 373 uint64_t current_time; 374 }; 375 376 struct bnxt_coal { 377 uint16_t num_cmpl_aggr_int; 378 uint16_t num_cmpl_dma_aggr; 379 uint16_t num_cmpl_dma_aggr_during_int; 380 uint16_t int_lat_tmr_max; 381 uint16_t int_lat_tmr_min; 382 uint16_t cmpl_aggr_dma_tmr; 383 uint16_t cmpl_aggr_dma_tmr_during_int; 384 }; 385 386 /* 64-bit doorbell */ 387 #define DBR_EPOCH_MASK 0x01000000UL 388 #define DBR_EPOCH_SFT 24 389 #define DBR_XID_SFT 32 390 #define DBR_PATH_L2 (0x1ULL << 56) 391 #define DBR_VALID (0x1ULL << 58) 392 #define DBR_TYPE_SQ (0x0ULL << 60) 393 #define DBR_TYPE_SRQ (0x2ULL << 60) 394 #define DBR_TYPE_CQ (0x4ULL << 60) 395 #define DBR_TYPE_NQ (0xaULL << 60) 396 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 397 398 #define DB_PF_OFFSET 0x10000 399 #define DB_VF_OFFSET 0x4000 400 401 #define BNXT_RSS_TBL_SIZE_P5 512U 402 #define BNXT_RSS_ENTRIES_PER_CTX_P5 64 403 #define BNXT_MAX_RSS_CTXTS_P5 \ 404 (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5) 405 406 #define BNXT_MAX_QUEUE 8 407 #define BNXT_MAX_TQM_SP_RINGS 1 408 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 409 #define BNXT_MAX_TQM_FP_RINGS 9 410 #define BNXT_MAX_TQM_LEGACY_RINGS \ 411 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 412 #define BNXT_MAX_TQM_RINGS \ 413 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 414 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 415 #define BNXT_BACKING_STORE_CFG_LEN \ 416 sizeof(struct hwrm_func_backing_store_cfg_input) 417 #define BNXT_PAGE_SHFT 12 418 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) 419 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 420 421 #define PTU_PTE_VALID 0x1UL 422 #define PTU_PTE_LAST 0x2UL 423 #define PTU_PTE_NEXT_TO_LAST 0x4UL 424 425 struct bnxt_ring_mem_info { 426 int nr_pages; 427 int page_size; 428 uint32_t flags; 429 #define BNXT_RMEM_VALID_PTE_FLAG 1 430 #define BNXT_RMEM_RING_PTE_FLAG 2 431 432 void **pg_arr; 433 rte_iova_t *dma_arr; 434 const struct rte_memzone *mz; 435 436 uint64_t *pg_tbl; 437 rte_iova_t pg_tbl_map; 438 const struct rte_memzone *pg_tbl_mz; 439 440 int vmem_size; 441 void **vmem; 442 }; 443 444 struct bnxt_ctx_pg_info { 445 uint32_t entries; 446 void *ctx_pg_arr[MAX_CTX_PAGES]; 447 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; 448 struct bnxt_ring_mem_info ring_mem; 449 }; 450 451 struct bnxt_ctx_mem_info { 452 uint32_t qp_max_entries; 453 uint16_t qp_min_qp1_entries; 454 uint16_t qp_max_l2_entries; 455 uint16_t qp_entry_size; 456 uint16_t srq_max_l2_entries; 457 uint32_t srq_max_entries; 458 uint16_t srq_entry_size; 459 uint16_t cq_max_l2_entries; 460 uint32_t cq_max_entries; 461 uint16_t cq_entry_size; 462 uint16_t vnic_max_vnic_entries; 463 uint16_t vnic_max_ring_table_entries; 464 uint16_t vnic_entry_size; 465 uint32_t stat_max_entries; 466 uint16_t stat_entry_size; 467 uint16_t tqm_entry_size; 468 uint32_t tqm_min_entries_per_ring; 469 uint32_t tqm_max_entries_per_ring; 470 uint32_t mrav_max_entries; 471 uint16_t mrav_entry_size; 472 uint16_t tim_entry_size; 473 uint32_t tim_max_entries; 474 uint8_t tqm_entries_multiple; 475 uint8_t tqm_fp_rings_count; 476 477 uint32_t flags; 478 #define BNXT_CTX_FLAG_INITED 0x01 479 480 struct bnxt_ctx_pg_info qp_mem; 481 struct bnxt_ctx_pg_info srq_mem; 482 struct bnxt_ctx_pg_info cq_mem; 483 struct bnxt_ctx_pg_info vnic_mem; 484 struct bnxt_ctx_pg_info stat_mem; 485 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; 486 }; 487 488 struct bnxt_ctx_mem_buf_info { 489 void *va; 490 rte_iova_t dma; 491 uint16_t ctx_id; 492 size_t size; 493 }; 494 495 /* Maximum Firmware Reset bail out value in milliseconds */ 496 #define BNXT_MAX_FW_RESET_TIMEOUT 6000 497 /* Minimum time required for the firmware readiness in milliseconds */ 498 #define BNXT_MIN_FW_READY_TIMEOUT 2000 499 /* Frequency for the firmware readiness check in milliseconds */ 500 #define BNXT_FW_READY_WAIT_INTERVAL 100 501 502 #define US_PER_MS 1000 503 #define NS_PER_US 1000 504 505 struct bnxt_error_recovery_info { 506 /* All units in milliseconds */ 507 uint32_t driver_polling_freq; 508 uint32_t primary_func_wait_period; 509 uint32_t normal_func_wait_period; 510 uint32_t primary_func_wait_period_after_reset; 511 uint32_t max_bailout_time_after_reset; 512 #define BNXT_FW_STATUS_REG 0 513 #define BNXT_FW_HEARTBEAT_CNT_REG 1 514 #define BNXT_FW_RECOVERY_CNT_REG 2 515 #define BNXT_FW_RESET_INPROG_REG 3 516 #define BNXT_FW_STATUS_REG_CNT 4 517 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; 518 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; 519 uint32_t reset_inprogress_reg_mask; 520 #define BNXT_NUM_RESET_REG 16 521 uint8_t reg_array_cnt; 522 uint32_t reset_reg[BNXT_NUM_RESET_REG]; 523 uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; 524 uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; 525 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) 526 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) 527 #define BNXT_FLAG_PRIMARY_FUNC BIT(2) 528 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3) 529 uint32_t flags; 530 531 uint32_t last_heart_beat; 532 uint32_t last_reset_counter; 533 }; 534 535 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ 536 #define BNXT_IF_CHANGE_RETRY_INTERVAL 50 537 /* Maximum retry count for FUNC_DRV_IF_CHANGE */ 538 #define BNXT_IF_CHANGE_RETRY_COUNT 40 539 540 struct bnxt_mark_info { 541 uint32_t mark_id; 542 bool valid; 543 }; 544 545 struct bnxt_rep_info { 546 struct rte_eth_dev *vfr_eth_dev; 547 pthread_mutex_t vfr_lock; 548 pthread_mutex_t vfr_start_lock; 549 bool conduit_valid; 550 }; 551 552 /* address space location of register */ 553 #define BNXT_FW_STATUS_REG_TYPE_MASK 3 554 /* register is located in PCIe config space */ 555 #define BNXT_FW_STATUS_REG_TYPE_CFG 0 556 /* register is located in GRC address space */ 557 #define BNXT_FW_STATUS_REG_TYPE_GRC 1 558 /* register is located in BAR0 */ 559 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2 560 /* register is located in BAR1 */ 561 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3 562 563 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) 564 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) 565 566 #define BNXT_GRCP_WINDOW_2_BASE 0x2000 567 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 568 569 #define BNXT_GRCP_BASE_MASK 0xfffff000 570 #define BNXT_GRCP_OFFSET_MASK 0x00000ffc 571 572 #define BNXT_FW_STATUS_HEALTHY 0x8000 573 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 574 575 #define BNXT_ETH_RSS_SUPPORT ( \ 576 RTE_ETH_RSS_IPV4 | \ 577 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 578 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ 579 RTE_ETH_RSS_IPV6 | \ 580 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 581 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ 582 RTE_ETH_RSS_LEVEL_MASK) 583 584 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \ 585 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \ 586 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \ 587 RTE_ETH_TX_OFFLOAD_TCP_TSO | \ 588 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 589 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \ 590 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | \ 591 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO | \ 592 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \ 593 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \ 594 RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 595 596 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \ 597 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \ 598 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \ 599 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | \ 600 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 601 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | \ 602 RTE_ETH_RX_OFFLOAD_KEEP_CRC | \ 603 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | \ 604 RTE_ETH_RX_OFFLOAD_TCP_LRO | \ 605 RTE_ETH_RX_OFFLOAD_SCATTER | \ 606 RTE_ETH_RX_OFFLOAD_RSS_HASH) 607 608 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 609 610 struct bnxt_flow_stat_info { 611 uint16_t max_fc; 612 uint16_t flow_count; 613 struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; 614 struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; 615 struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; 616 struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; 617 }; 618 619 struct bnxt_ring_stats { 620 /* Number of transmitted unicast packets */ 621 uint64_t tx_ucast_pkts; 622 /* Number of transmitted multicast packets */ 623 uint64_t tx_mcast_pkts; 624 /* Number of transmitted broadcast packets */ 625 uint64_t tx_bcast_pkts; 626 /* Number of packets discarded in transmit path */ 627 uint64_t tx_discard_pkts; 628 /* Number of packets in transmit path with error */ 629 uint64_t tx_error_pkts; 630 /* Number of transmitted bytes for unicast traffic */ 631 uint64_t tx_ucast_bytes; 632 /* Number of transmitted bytes for multicast traffic */ 633 uint64_t tx_mcast_bytes; 634 /* Number of transmitted bytes for broadcast traffic */ 635 uint64_t tx_bcast_bytes; 636 /* Number of received unicast packets */ 637 uint64_t rx_ucast_pkts; 638 /* Number of received multicast packets */ 639 uint64_t rx_mcast_pkts; 640 /* Number of received broadcast packets */ 641 uint64_t rx_bcast_pkts; 642 /* Number of packets discarded in receive path */ 643 uint64_t rx_discard_pkts; 644 /* Number of packets in receive path with errors */ 645 uint64_t rx_error_pkts; 646 /* Number of received bytes for unicast traffic */ 647 uint64_t rx_ucast_bytes; 648 /* Number of received bytes for multicast traffic */ 649 uint64_t rx_mcast_bytes; 650 /* Number of received bytes for broadcast traffic */ 651 uint64_t rx_bcast_bytes; 652 /* Number of aggregated unicast packets */ 653 uint64_t rx_agg_pkts; 654 /* Number of aggregated unicast bytes */ 655 uint64_t rx_agg_bytes; 656 /* Number of aggregation events */ 657 uint64_t rx_agg_events; 658 /* Number of aborted aggregations */ 659 uint64_t rx_agg_aborts; 660 }; 661 662 struct bnxt { 663 void *bar0; 664 665 struct rte_eth_dev *eth_dev; 666 struct rte_pci_device *pdev; 667 void *doorbell_base; 668 int legacy_db_size; 669 670 uint32_t flags; 671 #define BNXT_FLAG_REGISTERED BIT(0) 672 #define BNXT_FLAG_VF BIT(1) 673 #define BNXT_FLAG_PORT_STATS BIT(2) 674 #define BNXT_FLAG_JUMBO BIT(3) 675 #define BNXT_FLAG_SHORT_CMD BIT(4) 676 #define BNXT_FLAG_UPDATE_HASH BIT(5) 677 #define BNXT_FLAG_PTP_SUPPORTED BIT(6) 678 #define BNXT_FLAG_MULTI_HOST BIT(7) 679 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) 680 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) 681 #define BNXT_FLAG_KONG_MB_EN BIT(10) 682 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11) 683 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12) 684 #define BNXT_FLAG_CHIP_P5 BIT(13) 685 #define BNXT_FLAG_STINGRAY BIT(14) 686 #define BNXT_FLAG_FW_RESET BIT(15) 687 #define BNXT_FLAG_FATAL_ERROR BIT(16) 688 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(17) 689 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(18) 690 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(19) 691 #define BNXT_FLAG_NEW_RM BIT(20) 692 #define BNXT_FLAG_NPAR_PF BIT(21) 693 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) 694 #define BNXT_FLAG_FC_THREAD BIT(23) 695 #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) 696 #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) 697 #define BNXT_FLAG_DFLT_MAC_SET BIT(26) 698 #define BNXT_FLAG_GFID_ENABLE BIT(27) 699 #define BNXT_FLAG_RFS_NEEDS_VNIC BIT(28) 700 #define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(29) 701 #define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) 702 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 703 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 704 #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) 705 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 706 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 707 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. 708 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) 709 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) 710 #define BNXT_CHIP_P5(bp) ((bp)->flags & BNXT_FLAG_CHIP_P5) 711 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) 712 #define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp) 713 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp)) 714 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) 715 #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) 716 #define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) 717 718 uint32_t flags2; 719 #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED BIT(0) 720 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1) 721 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \ 722 ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED) 723 724 uint16_t chip_num; 725 #define CHIP_NUM_58818 0xd818 726 #define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) 727 #define BNXT_FLAGS2_MULTIROOT_EN BIT(4) 728 #define BNXT_MULTIROOT_EN(bp) \ 729 ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) 730 731 uint32_t fw_cap; 732 #define BNXT_FW_CAP_HOT_RESET BIT(0) 733 #define BNXT_FW_CAP_IF_CHANGE BIT(1) 734 #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) 735 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) 736 #define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(4) 737 #define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) 738 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) 739 #define BNXT_FW_CAP_LINK_ADMIN BIT(7) 740 #define BNXT_FW_CAP_TRUFLOW_EN BIT(8) 741 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9) 742 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 743 744 pthread_mutex_t flow_lock; 745 746 uint32_t vnic_cap_flags; 747 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) 748 #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) 749 #define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) 750 #define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3) 751 #define BNXT_RX_VLAN_STRIP_EN(bp) ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 752 unsigned int rx_nr_rings; 753 unsigned int rx_cp_nr_rings; 754 unsigned int rx_num_qs_per_vnic; 755 struct bnxt_rx_queue **rx_queues; 756 const void *rx_mem_zone; 757 struct rx_port_stats *hw_rx_port_stats; 758 rte_iova_t hw_rx_port_stats_map; 759 struct rx_port_stats_ext *hw_rx_port_stats_ext; 760 rte_iova_t hw_rx_port_stats_ext_map; 761 uint16_t fw_rx_port_stats_ext_size; 762 763 unsigned int tx_nr_rings; 764 unsigned int tx_cp_nr_rings; 765 struct bnxt_tx_queue **tx_queues; 766 const void *tx_mem_zone; 767 struct tx_port_stats *hw_tx_port_stats; 768 rte_iova_t hw_tx_port_stats_map; 769 struct tx_port_stats_ext *hw_tx_port_stats_ext; 770 rte_iova_t hw_tx_port_stats_ext_map; 771 uint16_t fw_tx_port_stats_ext_size; 772 773 /* Default completion ring */ 774 struct bnxt_cp_ring_info *async_cp_ring; 775 struct bnxt_cp_ring_info *rxtx_nq_ring; 776 uint32_t max_ring_grps; 777 struct bnxt_ring_grp_info *grp_info; 778 779 uint16_t nr_vnics; 780 781 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) 782 struct bnxt_vnic_info *vnic_info; 783 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; 784 785 struct bnxt_filter_info *filter_info; 786 STAILQ_HEAD(, bnxt_filter_info) free_filter_list; 787 788 struct bnxt_irq *irq_tbl; 789 790 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 791 792 uint16_t chimp_cmd_seq; 793 uint16_t kong_cmd_seq; 794 void *hwrm_cmd_resp_addr; 795 rte_iova_t hwrm_cmd_resp_dma_addr; 796 void *hwrm_short_cmd_req_addr; 797 rte_iova_t hwrm_short_cmd_req_dma_addr; 798 rte_spinlock_t hwrm_lock; 799 /* synchronize between dev_configure_op and int handler */ 800 pthread_mutex_t def_cp_lock; 801 /* synchronize between dev_start_op and async evt handler 802 * Locking sequence in async evt handler will be 803 * def_cp_lock 804 * health_check_lock 805 */ 806 pthread_mutex_t health_check_lock; 807 /* synchronize between dev_stop/dev_close_op and 808 * error recovery thread triggered as part of 809 * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 810 */ 811 pthread_mutex_t err_recovery_lock; 812 uint16_t max_req_len; 813 uint16_t max_resp_len; 814 uint16_t hwrm_max_ext_req_len; 815 816 /* default command timeout value of 500ms */ 817 #define DFLT_HWRM_CMD_TIMEOUT 500000 818 /* short command timeout value of 50ms */ 819 #define SHORT_HWRM_CMD_TIMEOUT 50000 820 /* default HWRM request timeout value */ 821 uint32_t hwrm_cmd_timeout; 822 823 struct bnxt_link_info *link_info; 824 struct bnxt_cos_queue_info *rx_cos_queue; 825 struct bnxt_cos_queue_info *tx_cos_queue; 826 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; 827 uint8_t rx_cosq_cnt; 828 uint8_t max_tc; 829 uint8_t max_lltc; 830 uint8_t max_q; 831 832 uint16_t fw_fid; 833 uint16_t max_rsscos_ctx; 834 uint16_t max_cp_rings; 835 uint16_t max_tx_rings; 836 uint16_t max_rx_rings; 837 #define MAX_STINGRAY_RINGS 236U 838 #define BNXT_MAX_VF_REP_RINGS 8 839 840 uint16_t max_nq_rings; 841 uint16_t max_l2_ctx; 842 uint16_t max_rx_em_flows; 843 uint16_t max_vnics; 844 uint16_t max_stat_ctx; 845 uint16_t max_tpa_v2; 846 uint16_t first_vf_id; 847 uint16_t vlan; 848 #define BNXT_OUTER_TPID_MASK 0x0000ffff 849 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 850 #define BNXT_OUTER_TPID_BD_SHFT 16 851 uint32_t outer_tpid_bd; 852 struct bnxt_pf_info *pf; 853 struct bnxt_parent_info *parent; 854 uint8_t port_cnt; 855 uint8_t vxlan_port_cnt; 856 uint8_t geneve_port_cnt; 857 uint16_t vxlan_port; 858 uint16_t geneve_port; 859 uint16_t vxlan_fw_dst_port_id; 860 uint16_t geneve_fw_dst_port_id; 861 uint32_t fw_ver; 862 uint32_t hwrm_spec_code; 863 864 struct bnxt_led_info *leds; 865 struct bnxt_ptp_cfg *ptp_cfg; 866 uint16_t vf_resv_strategy; 867 struct bnxt_ctx_mem_info *ctx; 868 869 uint16_t fw_reset_min_msecs; 870 uint16_t fw_reset_max_msecs; 871 uint16_t switch_domain_id; 872 uint16_t num_reps; 873 struct bnxt_rep_info *rep_info; 874 uint16_t *cfa_code_map; 875 /* Struct to hold adapter error recovery related info */ 876 struct bnxt_error_recovery_info *recovery_info; 877 #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) 878 /* TCAM and EM should be 16-bit only. Other modes not supported. */ 879 #define BNXT_FLOW_ID_MASK 0x0000ffff 880 struct bnxt_mark_info *mark_table; 881 882 #define BNXT_SVIF_INVALID 0xFFFF 883 uint16_t func_svif; 884 uint16_t port_svif; 885 886 struct tf tfp; 887 struct tf tfp_shared; 888 struct bnxt_ulp_context *ulp_ctx; 889 struct bnxt_flow_stat_info *flow_stat; 890 uint16_t max_num_kflows; 891 uint8_t app_id; 892 uint16_t tx_cfa_action; 893 struct bnxt_ring_stats *prev_rx_ring_stats; 894 struct bnxt_ring_stats *prev_tx_ring_stats; 895 }; 896 897 static 898 inline uint16_t bnxt_max_rings(struct bnxt *bp) 899 { 900 uint16_t max_tx_rings = bp->max_tx_rings; 901 uint16_t max_rx_rings = bp->max_rx_rings; 902 uint16_t max_cp_rings = bp->max_cp_rings; 903 uint16_t max_rings; 904 905 /* For the sake of symmetry: 906 * max Tx rings == max Rx rings, one stat ctx for each. 907 */ 908 if (BNXT_STINGRAY(bp)) { 909 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U, 910 MAX_STINGRAY_RINGS), 911 bp->max_stat_ctx / 2U); 912 } else { 913 max_rx_rings = RTE_MIN(max_rx_rings / 2U, 914 bp->max_stat_ctx / 2U); 915 } 916 917 /* 918 * RSS table size in Thor is 512. 919 * Cap max Rx rings to the same value for RSS. 920 */ 921 if (BNXT_CHIP_P5(bp)) 922 max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5); 923 924 max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); 925 if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp)) 926 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp); 927 max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings); 928 929 return max_rings; 930 } 931 932 #define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ 933 934 /** 935 * Structure to store private data for each VF representor instance 936 */ 937 struct bnxt_representor { 938 uint16_t switch_domain_id; 939 uint16_t vf_id; 940 #define BNXT_REP_IS_PF BIT(0) 941 #define BNXT_REP_Q_R2F_VALID BIT(1) 942 #define BNXT_REP_Q_F2R_VALID BIT(2) 943 #define BNXT_REP_FC_R2F_VALID BIT(3) 944 #define BNXT_REP_FC_F2R_VALID BIT(4) 945 #define BNXT_REP_BASED_PF_VALID BIT(5) 946 uint32_t flags; 947 uint16_t fw_fid; 948 #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF 949 uint16_t dflt_vnic_id; 950 uint16_t svif; 951 uint16_t vfr_tx_cfa_action; 952 uint8_t parent_pf_idx; /* Logical PF index */ 953 uint32_t dpdk_port_id; 954 uint32_t rep_based_pf; 955 uint8_t rep_q_r2f; 956 uint8_t rep_q_f2r; 957 uint8_t rep_fc_r2f; 958 uint8_t rep_fc_f2r; 959 /* Private data store of associated PF/Trusted VF */ 960 struct rte_eth_dev *parent_dev; 961 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 962 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; 963 struct bnxt_rx_queue **rx_queues; 964 unsigned int rx_nr_rings; 965 unsigned int tx_nr_rings; 966 uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; 967 uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; 968 uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; 969 uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; 970 uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; 971 uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; 972 }; 973 974 #define BNXT_REP_PF(vfr_bp) ((vfr_bp)->flags & BNXT_REP_IS_PF) 975 #define BNXT_REP_BASED_PF(vfr_bp) \ 976 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID) 977 978 struct bnxt_vf_rep_tx_queue { 979 struct bnxt_tx_queue *txq; 980 struct bnxt_representor *bp; 981 }; 982 983 #define I2C_DEV_ADDR_A0 0xa0 984 #define I2C_DEV_ADDR_A2 0xa2 985 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 986 #define SFF_MODULE_ID_SFP 0x3 987 #define SFF_MODULE_ID_QSFP 0xc 988 #define SFF_MODULE_ID_QSFP_PLUS 0xd 989 #define SFF_MODULE_ID_QSFP28 0x11 990 #define SFF8636_FLATMEM_OFFSET 0x2 991 #define SFF8636_FLATMEM_MASK 0x4 992 #define SFF8636_OPT_PAGES_OFFSET 0xc3 993 #define SFF8636_PAGE1_MASK 0x40 994 #define SFF8636_PAGE2_MASK 0x80 995 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 996 997 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 998 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 999 bool exp_link_status); 1000 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); 1001 int is_bnxt_in_error(struct bnxt *bp); 1002 1003 int bnxt_map_fw_health_status_regs(struct bnxt *bp); 1004 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); 1005 void bnxt_schedule_fw_health_check(struct bnxt *bp); 1006 1007 bool is_bnxt_supported(struct rte_eth_dev *dev); 1008 bool bnxt_stratus_device(struct bnxt *bp); 1009 void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 1010 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); 1011 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1012 int wait_to_complete); 1013 uint16_t bnxt_dummy_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1014 uint16_t nb_pkts); 1015 uint16_t bnxt_dummy_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 1016 uint16_t nb_pkts); 1017 1018 extern const struct rte_flow_ops bnxt_flow_ops; 1019 1020 #define bnxt_acquire_flow_lock(bp) \ 1021 pthread_mutex_lock(&(bp)->flow_lock) 1022 1023 #define bnxt_release_flow_lock(bp) \ 1024 pthread_mutex_unlock(&(bp)->flow_lock) 1025 1026 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \ 1027 if ((vnic_id) >= (bp)->max_vnics) { \ 1028 rte_flow_error_set(error, \ 1029 EINVAL, \ 1030 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \ 1031 NULL, \ 1032 "Group id is invalid!"); \ 1033 rc = -rte_errno; \ 1034 goto ret; \ 1035 } \ 1036 } while (0) 1037 1038 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ 1039 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1040 1041 extern int bnxt_logtype_driver; 1042 #define PMD_DRV_LOG_RAW(level, fmt, args...) \ 1043 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \ 1044 __func__, ## args) 1045 1046 #define PMD_DRV_LOG(level, fmt, args...) \ 1047 PMD_DRV_LOG_RAW(level, fmt, ## args) 1048 1049 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; 1050 int32_t bnxt_ulp_port_init(struct bnxt *bp); 1051 void bnxt_ulp_port_deinit(struct bnxt *bp); 1052 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp); 1053 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global); 1054 int32_t 1055 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev); 1056 int32_t 1057 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr); 1058 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev); 1059 1060 void bnxt_cancel_fc_thread(struct bnxt *bp); 1061 void bnxt_flow_cnt_alarm_cb(void *arg); 1062 int bnxt_flow_stats_req(struct bnxt *bp); 1063 int bnxt_flow_stats_cnt(struct bnxt *bp); 1064 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); 1065 int bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 1066 const struct rte_flow_ops **ops); 1067 1068 #endif 1069