1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #include "efx_regs_ef100.h" 14 #if EFSYS_OPT_MCDI 15 #include "efx_mcdi.h" 16 #endif /* EFSYS_OPT_MCDI */ 17 18 /* FIXME: Add definition for driver generated software events */ 19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 21 #endif 22 23 24 #if EFSYS_OPT_SIENA 25 #include "siena_impl.h" 26 #endif /* EFSYS_OPT_SIENA */ 27 28 #if EFSYS_OPT_HUNTINGTON 29 #include "hunt_impl.h" 30 #endif /* EFSYS_OPT_HUNTINGTON */ 31 32 #if EFSYS_OPT_MEDFORD 33 #include "medford_impl.h" 34 #endif /* EFSYS_OPT_MEDFORD */ 35 36 #if EFSYS_OPT_MEDFORD2 37 #include "medford2_impl.h" 38 #endif /* EFSYS_OPT_MEDFORD2 */ 39 40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 41 #include "ef10_impl.h" 42 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 43 44 #if EFSYS_OPT_RIVERHEAD 45 #include "rhead_impl.h" 46 #endif /* EFSYS_OPT_RIVERHEAD */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define EFX_MOD_MCDI 0x00000001 53 #define EFX_MOD_PROBE 0x00000002 54 #define EFX_MOD_NVRAM 0x00000004 55 #define EFX_MOD_VPD 0x00000008 56 #define EFX_MOD_NIC 0x00000010 57 #define EFX_MOD_INTR 0x00000020 58 #define EFX_MOD_EV 0x00000040 59 #define EFX_MOD_RX 0x00000080 60 #define EFX_MOD_TX 0x00000100 61 #define EFX_MOD_PORT 0x00000200 62 #define EFX_MOD_MON 0x00000400 63 #define EFX_MOD_FILTER 0x00001000 64 #define EFX_MOD_LIC 0x00002000 65 #define EFX_MOD_TUNNEL 0x00004000 66 #define EFX_MOD_EVB 0x00008000 67 #define EFX_MOD_PROXY 0x00010000 68 #define EFX_MOD_VIRTIO 0x00020000 69 70 #define EFX_RESET_PHY 0x00000001 71 #define EFX_RESET_RXQ_ERR 0x00000002 72 #define EFX_RESET_TXQ_ERR 0x00000004 73 #define EFX_RESET_HW_UNAVAIL 0x00000008 74 75 typedef enum efx_mac_type_e { 76 EFX_MAC_INVALID = 0, 77 EFX_MAC_SIENA, 78 EFX_MAC_HUNTINGTON, 79 EFX_MAC_MEDFORD, 80 EFX_MAC_MEDFORD2, 81 EFX_MAC_RIVERHEAD, 82 EFX_MAC_NTYPES 83 } efx_mac_type_t; 84 85 typedef struct efx_ev_ops_s { 86 efx_rc_t (*eevo_init)(efx_nic_t *); 87 void (*eevo_fini)(efx_nic_t *); 88 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 89 efsys_mem_t *, size_t, uint32_t, 90 uint32_t, uint32_t, efx_evq_t *); 91 void (*eevo_qdestroy)(efx_evq_t *); 92 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 93 void (*eevo_qpost)(efx_evq_t *, uint16_t); 94 void (*eevo_qpoll)(efx_evq_t *, unsigned int *, 95 const efx_ev_callbacks_t *, void *); 96 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 97 #if EFSYS_OPT_QSTATS 98 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 99 #endif 100 } efx_ev_ops_t; 101 102 typedef struct efx_tx_ops_s { 103 efx_rc_t (*etxo_init)(efx_nic_t *); 104 void (*etxo_fini)(efx_nic_t *); 105 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 106 unsigned int, unsigned int, 107 efsys_mem_t *, size_t, 108 uint32_t, uint16_t, 109 efx_evq_t *, efx_txq_t *, 110 unsigned int *); 111 void (*etxo_qdestroy)(efx_txq_t *); 112 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 113 unsigned int, unsigned int, 114 unsigned int *); 115 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 116 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 117 efx_rc_t (*etxo_qflush)(efx_txq_t *); 118 void (*etxo_qenable)(efx_txq_t *); 119 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 120 void (*etxo_qpio_disable)(efx_txq_t *); 121 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 122 size_t); 123 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 124 unsigned int *); 125 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 126 unsigned int, unsigned int, 127 unsigned int *); 128 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 129 size_t, boolean_t, 130 efx_desc_t *); 131 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 132 uint32_t, uint8_t, 133 efx_desc_t *); 134 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 135 uint16_t, uint32_t, uint16_t, 136 efx_desc_t *, int); 137 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 138 efx_desc_t *); 139 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 140 efx_desc_t *); 141 #if EFSYS_OPT_QSTATS 142 void (*etxo_qstats_update)(efx_txq_t *, 143 efsys_stat_t *); 144 #endif 145 } efx_tx_ops_t; 146 147 typedef union efx_rxq_type_data_u { 148 struct { 149 size_t ed_buf_size; 150 } ertd_default; 151 #if EFSYS_OPT_RX_PACKED_STREAM 152 struct { 153 uint32_t eps_buf_size; 154 } ertd_packed_stream; 155 #endif 156 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 157 struct { 158 uint32_t eessb_bufs_per_desc; 159 uint32_t eessb_max_dma_len; 160 uint32_t eessb_buf_stride; 161 uint32_t eessb_hol_block_timeout; 162 } ertd_es_super_buffer; 163 #endif 164 } efx_rxq_type_data_t; 165 166 typedef struct efx_rx_ops_s { 167 efx_rc_t (*erxo_init)(efx_nic_t *); 168 void (*erxo_fini)(efx_nic_t *); 169 #if EFSYS_OPT_RX_SCATTER 170 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 171 #endif 172 #if EFSYS_OPT_RX_SCALE 173 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 174 efx_rx_scale_context_type_t, 175 uint32_t, uint32_t *); 176 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 177 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 178 efx_rx_hash_alg_t, 179 efx_rx_hash_type_t, boolean_t); 180 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 181 uint8_t *, size_t); 182 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 183 unsigned int *, size_t); 184 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 185 uint8_t *); 186 #endif /* EFSYS_OPT_RX_SCALE */ 187 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 188 uint16_t *); 189 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 190 unsigned int, unsigned int, 191 unsigned int); 192 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 193 #if EFSYS_OPT_RX_PACKED_STREAM 194 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 195 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 196 uint32_t, uint32_t, 197 uint16_t *, uint32_t *, uint32_t *); 198 #endif 199 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 200 void (*erxo_qenable)(efx_rxq_t *); 201 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 202 unsigned int, efx_rxq_type_t, 203 const efx_rxq_type_data_t *, 204 efsys_mem_t *, size_t, uint32_t, 205 unsigned int, 206 efx_evq_t *, efx_rxq_t *); 207 void (*erxo_qdestroy)(efx_rxq_t *); 208 } efx_rx_ops_t; 209 210 typedef struct efx_mac_ops_s { 211 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 212 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 213 efx_rc_t (*emo_addr_set)(efx_nic_t *); 214 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 215 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 216 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 217 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 218 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 219 efx_rxq_t *, boolean_t); 220 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 221 #if EFSYS_OPT_LOOPBACK 222 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 223 efx_loopback_type_t); 224 #endif /* EFSYS_OPT_LOOPBACK */ 225 #if EFSYS_OPT_MAC_STATS 226 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 227 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 228 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 229 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 230 uint16_t, boolean_t); 231 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 232 efsys_stat_t *, uint32_t *); 233 #endif /* EFSYS_OPT_MAC_STATS */ 234 } efx_mac_ops_t; 235 236 typedef struct efx_phy_ops_s { 237 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 238 efx_rc_t (*epo_reset)(efx_nic_t *); 239 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 240 efx_rc_t (*epo_verify)(efx_nic_t *); 241 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 242 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 243 #if EFSYS_OPT_PHY_STATS 244 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 245 uint32_t *); 246 #endif /* EFSYS_OPT_PHY_STATS */ 247 #if EFSYS_OPT_BIST 248 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 249 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 250 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 251 efx_bist_result_t *, uint32_t *, 252 unsigned long *, size_t); 253 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 254 #endif /* EFSYS_OPT_BIST */ 255 } efx_phy_ops_t; 256 257 #if EFSYS_OPT_FILTER 258 259 /* 260 * Policy for replacing existing filter when inserting a new one. 261 * Note that all policies allow for storing the new lower priority 262 * filters as overridden by existing higher priority ones. It is needed 263 * to restore the lower priority filters on higher priority ones removal. 264 */ 265 typedef enum efx_filter_replacement_policy_e { 266 /* Cannot replace existing filter */ 267 EFX_FILTER_REPLACEMENT_NEVER, 268 /* Higher priority filters can replace lower priotiry ones */ 269 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 270 /* 271 * Higher priority filters can replace lower priority ones and 272 * equal priority filters can replace each other. 273 */ 274 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 275 } efx_filter_replacement_policy_t; 276 277 typedef struct efx_filter_ops_s { 278 efx_rc_t (*efo_init)(efx_nic_t *); 279 void (*efo_fini)(efx_nic_t *); 280 efx_rc_t (*efo_restore)(efx_nic_t *); 281 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 282 efx_filter_replacement_policy_t policy); 283 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 284 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 285 size_t, size_t *); 286 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 287 boolean_t, boolean_t, boolean_t, 288 uint8_t const *, uint32_t); 289 } efx_filter_ops_t; 290 291 LIBEFX_INTERNAL 292 extern __checkReturn efx_rc_t 293 efx_filter_reconfigure( 294 __in efx_nic_t *enp, 295 __in_ecount(6) uint8_t const *mac_addr, 296 __in boolean_t all_unicst, 297 __in boolean_t mulcst, 298 __in boolean_t all_mulcst, 299 __in boolean_t brdcst, 300 __in_ecount(6*count) uint8_t const *addrs, 301 __in uint32_t count); 302 303 #endif /* EFSYS_OPT_FILTER */ 304 305 #if EFSYS_OPT_TUNNEL 306 typedef struct efx_tunnel_ops_s { 307 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 308 void (*eto_fini)(efx_nic_t *); 309 } efx_tunnel_ops_t; 310 #endif /* EFSYS_OPT_TUNNEL */ 311 312 #if EFSYS_OPT_VIRTIO 313 typedef struct efx_virtio_ops_s { 314 efx_rc_t (*evo_virtio_qstart)(efx_virtio_vq_t *, 315 efx_virtio_vq_cfg_t *, 316 efx_virtio_vq_dyncfg_t *); 317 efx_rc_t (*evo_virtio_qstop)(efx_virtio_vq_t *, 318 efx_virtio_vq_dyncfg_t *); 319 efx_rc_t (*evo_get_doorbell_offset)(efx_virtio_vq_t *, 320 uint32_t *); 321 } efx_virtio_ops_t; 322 #endif /* EFSYS_OPT_VIRTIO */ 323 324 typedef struct efx_port_s { 325 efx_mac_type_t ep_mac_type; 326 uint32_t ep_phy_type; 327 uint8_t ep_port; 328 uint32_t ep_mac_pdu; 329 uint8_t ep_mac_addr[6]; 330 efx_link_mode_t ep_link_mode; 331 boolean_t ep_all_unicst; 332 boolean_t ep_all_unicst_inserted; 333 boolean_t ep_mulcst; 334 boolean_t ep_all_mulcst; 335 boolean_t ep_all_mulcst_inserted; 336 boolean_t ep_brdcst; 337 unsigned int ep_fcntl; 338 boolean_t ep_fcntl_autoneg; 339 efx_oword_t ep_multicst_hash[2]; 340 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 341 EFX_MAC_MULTICAST_LIST_MAX]; 342 uint32_t ep_mulcst_addr_count; 343 #if EFSYS_OPT_LOOPBACK 344 efx_loopback_type_t ep_loopback_type; 345 efx_link_mode_t ep_loopback_link_mode; 346 #endif /* EFSYS_OPT_LOOPBACK */ 347 #if EFSYS_OPT_PHY_FLAGS 348 uint32_t ep_phy_flags; 349 #endif /* EFSYS_OPT_PHY_FLAGS */ 350 #if EFSYS_OPT_PHY_LED_CONTROL 351 efx_phy_led_mode_t ep_phy_led_mode; 352 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 353 efx_phy_media_type_t ep_fixed_port_type; 354 efx_phy_media_type_t ep_module_type; 355 uint32_t ep_adv_cap_mask; 356 uint32_t ep_lp_cap_mask; 357 uint32_t ep_default_adv_cap_mask; 358 uint32_t ep_phy_cap_mask; 359 boolean_t ep_mac_drain; 360 #if EFSYS_OPT_BIST 361 efx_bist_type_t ep_current_bist; 362 #endif 363 const efx_mac_ops_t *ep_emop; 364 const efx_phy_ops_t *ep_epop; 365 } efx_port_t; 366 367 typedef struct efx_mon_ops_s { 368 #if EFSYS_OPT_MON_STATS 369 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 370 efx_mon_stat_value_t *); 371 efx_rc_t (*emo_limits_update)(efx_nic_t *, 372 efx_mon_stat_limits_t *); 373 #endif /* EFSYS_OPT_MON_STATS */ 374 } efx_mon_ops_t; 375 376 typedef struct efx_mon_s { 377 efx_mon_type_t em_type; 378 const efx_mon_ops_t *em_emop; 379 } efx_mon_t; 380 381 typedef struct efx_intr_ops_s { 382 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 383 void (*eio_enable)(efx_nic_t *); 384 void (*eio_disable)(efx_nic_t *); 385 void (*eio_disable_unlocked)(efx_nic_t *); 386 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 387 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 388 void (*eio_status_message)(efx_nic_t *, unsigned int, 389 boolean_t *); 390 void (*eio_fatal)(efx_nic_t *); 391 void (*eio_fini)(efx_nic_t *); 392 } efx_intr_ops_t; 393 394 typedef struct efx_intr_s { 395 const efx_intr_ops_t *ei_eiop; 396 efsys_mem_t *ei_esmp; 397 efx_intr_type_t ei_type; 398 unsigned int ei_level; 399 } efx_intr_t; 400 401 typedef struct efx_nic_ops_s { 402 efx_rc_t (*eno_probe)(efx_nic_t *); 403 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 404 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 405 efx_rc_t (*eno_reset)(efx_nic_t *); 406 efx_rc_t (*eno_init)(efx_nic_t *); 407 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 408 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 409 uint32_t *, size_t *); 410 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 411 void (*eno_set_hw_unavailable)(efx_nic_t *); 412 #if EFSYS_OPT_DIAG 413 efx_rc_t (*eno_register_test)(efx_nic_t *); 414 #endif /* EFSYS_OPT_DIAG */ 415 void (*eno_fini)(efx_nic_t *); 416 void (*eno_unprobe)(efx_nic_t *); 417 } efx_nic_ops_t; 418 419 #ifndef EFX_TXQ_LIMIT_TARGET 420 #define EFX_TXQ_LIMIT_TARGET 259 421 #endif 422 #ifndef EFX_RXQ_LIMIT_TARGET 423 #define EFX_RXQ_LIMIT_TARGET 512 424 #endif 425 426 427 #if EFSYS_OPT_FILTER 428 429 #if EFSYS_OPT_SIENA 430 431 typedef struct siena_filter_spec_s { 432 uint8_t sfs_type; 433 uint32_t sfs_flags; 434 uint32_t sfs_dmaq_id; 435 uint32_t sfs_dword[3]; 436 } siena_filter_spec_t; 437 438 typedef enum siena_filter_type_e { 439 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 440 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 441 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 442 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 443 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 444 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 445 446 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 447 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 448 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 449 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 450 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 451 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 452 453 EFX_SIENA_FILTER_NTYPES 454 } siena_filter_type_t; 455 456 typedef enum siena_filter_tbl_id_e { 457 EFX_SIENA_FILTER_TBL_RX_IP = 0, 458 EFX_SIENA_FILTER_TBL_RX_MAC, 459 EFX_SIENA_FILTER_TBL_TX_IP, 460 EFX_SIENA_FILTER_TBL_TX_MAC, 461 EFX_SIENA_FILTER_NTBLS 462 } siena_filter_tbl_id_t; 463 464 typedef struct siena_filter_tbl_s { 465 int sft_size; /* number of entries */ 466 int sft_used; /* active count */ 467 uint32_t *sft_bitmap; /* active bitmap */ 468 siena_filter_spec_t *sft_spec; /* array of saved specs */ 469 } siena_filter_tbl_t; 470 471 typedef struct siena_filter_s { 472 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 473 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 474 } siena_filter_t; 475 476 #endif /* EFSYS_OPT_SIENA */ 477 478 typedef struct efx_filter_s { 479 #if EFSYS_OPT_SIENA 480 siena_filter_t *ef_siena_filter; 481 #endif /* EFSYS_OPT_SIENA */ 482 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 483 ef10_filter_table_t *ef_ef10_filter_table; 484 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 485 } efx_filter_t; 486 487 #if EFSYS_OPT_SIENA 488 489 LIBEFX_INTERNAL 490 extern void 491 siena_filter_tbl_clear( 492 __in efx_nic_t *enp, 493 __in siena_filter_tbl_id_t tbl); 494 495 #endif /* EFSYS_OPT_SIENA */ 496 497 #endif /* EFSYS_OPT_FILTER */ 498 499 #if EFSYS_OPT_MCDI 500 501 #define EFX_TUNNEL_MAXNENTRIES (16) 502 503 #if EFSYS_OPT_TUNNEL 504 505 /* State of a UDP tunnel table entry */ 506 typedef enum efx_tunnel_udp_entry_state_e { 507 EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */ 508 EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */ 509 EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */ 510 } efx_tunnel_udp_entry_state_t; 511 512 #if EFSYS_OPT_RIVERHEAD 513 typedef uint32_t efx_vnic_encap_rule_handle_t; 514 #endif /* EFSYS_OPT_RIVERHEAD */ 515 516 typedef struct efx_tunnel_udp_entry_s { 517 uint16_t etue_port; /* host/cpu-endian */ 518 uint16_t etue_protocol; 519 boolean_t etue_busy; 520 efx_tunnel_udp_entry_state_t etue_state; 521 #if EFSYS_OPT_RIVERHEAD 522 efx_vnic_encap_rule_handle_t etue_handle; 523 #endif /* EFSYS_OPT_RIVERHEAD */ 524 } efx_tunnel_udp_entry_t; 525 526 typedef struct efx_tunnel_cfg_s { 527 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 528 unsigned int etc_udp_entries_num; 529 } efx_tunnel_cfg_t; 530 531 #endif /* EFSYS_OPT_TUNNEL */ 532 533 typedef struct efx_mcdi_ops_s { 534 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 535 void (*emco_send_request)(efx_nic_t *, void *, size_t, 536 void *, size_t); 537 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 538 boolean_t (*emco_poll_response)(efx_nic_t *); 539 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 540 void (*emco_fini)(efx_nic_t *); 541 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 542 efx_mcdi_feature_id_t, boolean_t *); 543 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 544 uint32_t *); 545 } efx_mcdi_ops_t; 546 547 typedef struct efx_mcdi_s { 548 const efx_mcdi_ops_t *em_emcop; 549 const efx_mcdi_transport_t *em_emtp; 550 efx_mcdi_iface_t em_emip; 551 } efx_mcdi_t; 552 553 #endif /* EFSYS_OPT_MCDI */ 554 555 #if EFSYS_OPT_NVRAM 556 557 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 558 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 559 560 typedef struct efx_nvram_ops_s { 561 #if EFSYS_OPT_DIAG 562 efx_rc_t (*envo_test)(efx_nic_t *); 563 #endif /* EFSYS_OPT_DIAG */ 564 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 565 uint32_t *); 566 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 567 efx_nvram_info_t *); 568 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 569 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 570 unsigned int, caddr_t, size_t); 571 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 572 unsigned int, caddr_t, size_t); 573 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 574 unsigned int, size_t); 575 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 576 unsigned int, caddr_t, size_t); 577 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 578 uint32_t *); 579 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 580 uint32_t *, uint16_t *); 581 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 582 uint16_t *); 583 efx_rc_t (*envo_buffer_validate)(uint32_t, 584 caddr_t, size_t); 585 } efx_nvram_ops_t; 586 #endif /* EFSYS_OPT_NVRAM */ 587 588 #if EFSYS_OPT_VPD 589 typedef struct efx_vpd_ops_s { 590 efx_rc_t (*evpdo_init)(efx_nic_t *); 591 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 592 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 593 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 594 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 595 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 596 efx_vpd_value_t *); 597 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 598 efx_vpd_value_t *); 599 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 600 efx_vpd_value_t *, unsigned int *); 601 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 602 void (*evpdo_fini)(efx_nic_t *); 603 } efx_vpd_ops_t; 604 #endif /* EFSYS_OPT_VPD */ 605 606 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 607 608 LIBEFX_INTERNAL 609 extern __checkReturn efx_rc_t 610 efx_mcdi_nvram_partitions( 611 __in efx_nic_t *enp, 612 __out_bcount(size) caddr_t data, 613 __in size_t size, 614 __out unsigned int *npartnp); 615 616 LIBEFX_INTERNAL 617 extern __checkReturn efx_rc_t 618 efx_mcdi_nvram_metadata( 619 __in efx_nic_t *enp, 620 __in uint32_t partn, 621 __out uint32_t *subtypep, 622 __out_ecount(4) uint16_t version[4], 623 __out_bcount_opt(size) char *descp, 624 __in size_t size); 625 626 LIBEFX_INTERNAL 627 extern __checkReturn efx_rc_t 628 efx_mcdi_nvram_info( 629 __in efx_nic_t *enp, 630 __in uint32_t partn, 631 __out efx_nvram_info_t *eni); 632 633 LIBEFX_INTERNAL 634 extern __checkReturn efx_rc_t 635 efx_mcdi_nvram_update_start( 636 __in efx_nic_t *enp, 637 __in uint32_t partn); 638 639 LIBEFX_INTERNAL 640 extern __checkReturn efx_rc_t 641 efx_mcdi_nvram_read( 642 __in efx_nic_t *enp, 643 __in uint32_t partn, 644 __in uint32_t offset, 645 __out_bcount(size) caddr_t data, 646 __in size_t size, 647 __in uint32_t mode); 648 649 LIBEFX_INTERNAL 650 extern __checkReturn efx_rc_t 651 efx_mcdi_nvram_erase( 652 __in efx_nic_t *enp, 653 __in uint32_t partn, 654 __in uint32_t offset, 655 __in size_t size); 656 657 LIBEFX_INTERNAL 658 extern __checkReturn efx_rc_t 659 efx_mcdi_nvram_write( 660 __in efx_nic_t *enp, 661 __in uint32_t partn, 662 __in uint32_t offset, 663 __in_bcount(size) caddr_t data, 664 __in size_t size); 665 666 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 667 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 668 669 LIBEFX_INTERNAL 670 extern __checkReturn efx_rc_t 671 efx_mcdi_nvram_update_finish( 672 __in efx_nic_t *enp, 673 __in uint32_t partn, 674 __in boolean_t reboot, 675 __in uint32_t flags, 676 __out_opt uint32_t *verify_resultp); 677 678 #if EFSYS_OPT_DIAG 679 680 LIBEFX_INTERNAL 681 extern __checkReturn efx_rc_t 682 efx_mcdi_nvram_test( 683 __in efx_nic_t *enp, 684 __in uint32_t partn); 685 686 #endif /* EFSYS_OPT_DIAG */ 687 688 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 689 690 #if EFSYS_OPT_LICENSING 691 692 typedef struct efx_lic_ops_s { 693 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 694 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 695 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 696 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 697 size_t *, uint8_t *); 698 efx_rc_t (*elo_find_start) 699 (efx_nic_t *, caddr_t, size_t, uint32_t *); 700 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 701 uint32_t, uint32_t *); 702 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 703 uint32_t, uint32_t *, uint32_t *); 704 boolean_t (*elo_validate_key)(efx_nic_t *, 705 caddr_t, uint32_t); 706 efx_rc_t (*elo_read_key)(efx_nic_t *, 707 caddr_t, size_t, uint32_t, uint32_t, 708 caddr_t, size_t, uint32_t *); 709 efx_rc_t (*elo_write_key)(efx_nic_t *, 710 caddr_t, size_t, uint32_t, 711 caddr_t, uint32_t, uint32_t *); 712 efx_rc_t (*elo_delete_key)(efx_nic_t *, 713 caddr_t, size_t, uint32_t, 714 uint32_t, uint32_t, uint32_t *); 715 efx_rc_t (*elo_create_partition)(efx_nic_t *, 716 caddr_t, size_t); 717 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 718 caddr_t, size_t); 719 } efx_lic_ops_t; 720 721 #endif 722 723 #if EFSYS_OPT_EVB 724 725 struct efx_vswitch_s { 726 efx_nic_t *ev_enp; 727 efx_vswitch_id_t ev_vswitch_id; 728 uint32_t ev_num_vports; 729 /* 730 * Vport configuration array: index 0 to store PF configuration 731 * and next ev_num_vports-1 entries hold VFs configuration. 732 */ 733 efx_vport_config_t *ev_evcp; 734 }; 735 736 typedef struct efx_evb_ops_s { 737 efx_rc_t (*eeo_init)(efx_nic_t *); 738 void (*eeo_fini)(efx_nic_t *); 739 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 740 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 741 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 742 efx_vport_type_t, uint16_t, 743 boolean_t, efx_vport_id_t *); 744 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 745 efx_vport_id_t); 746 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 747 efx_vport_id_t, uint8_t *); 748 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 749 efx_vport_id_t, uint8_t *); 750 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 751 efx_vport_id_t); 752 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 753 efx_vport_id_t); 754 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 755 efx_vport_id_t, uint32_t); 756 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 757 efx_vport_id_t, 758 uint16_t *, uint8_t *, 759 boolean_t *); 760 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 761 efx_vport_id_t, efsys_mem_t *); 762 } efx_evb_ops_t; 763 764 LIBEFX_INTERNAL 765 extern __checkReturn boolean_t 766 efx_is_zero_eth_addr( 767 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 768 769 #endif /* EFSYS_OPT_EVB */ 770 771 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 772 773 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 774 775 776 typedef struct efx_proxy_ops_s { 777 efx_rc_t (*epo_init)(efx_nic_t *); 778 void (*epo_fini)(efx_nic_t *); 779 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 780 efsys_mem_t *, efsys_mem_t *, 781 uint32_t, uint32_t *, size_t); 782 efx_rc_t (*epo_disable)(efx_nic_t *); 783 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 784 uint32_t, uint32_t, uint32_t); 785 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 786 uint32_t, uint32_t); 787 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 788 uint32_t, uint32_t); 789 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 790 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 791 uint32_t, uint32_t *); 792 } efx_proxy_ops_t; 793 794 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 795 796 #if EFSYS_OPT_MAE 797 798 typedef struct efx_mae_field_cap_s { 799 uint32_t emfc_support; 800 boolean_t emfc_mask_affects_class; 801 boolean_t emfc_match_affects_class; 802 } efx_mae_field_cap_t; 803 804 typedef struct efx_mae_s { 805 uint32_t em_max_n_action_prios; 806 /* 807 * The number of MAE field IDs recognised by the FW implementation. 808 * Any field ID greater than or equal to this value is unsupported. 809 */ 810 uint32_t em_max_nfields; 811 /** Action rule match field capabilities. */ 812 efx_mae_field_cap_t *em_action_rule_field_caps; 813 size_t em_action_rule_field_caps_size; 814 uint32_t em_max_n_outer_prios; 815 uint32_t em_encap_types_supported; 816 /** Outer rule match field capabilities. */ 817 efx_mae_field_cap_t *em_outer_rule_field_caps; 818 size_t em_outer_rule_field_caps_size; 819 } efx_mae_t; 820 821 #endif /* EFSYS_OPT_MAE */ 822 823 #define EFX_DRV_VER_MAX 20 824 825 typedef struct efx_drv_cfg_s { 826 uint32_t edc_min_vi_count; 827 uint32_t edc_max_vi_count; 828 829 uint32_t edc_max_piobuf_count; 830 uint32_t edc_pio_alloc_size; 831 } efx_drv_cfg_t; 832 833 struct efx_nic_s { 834 uint32_t en_magic; 835 efx_family_t en_family; 836 uint32_t en_features; 837 efsys_identifier_t *en_esip; 838 efsys_lock_t *en_eslp; 839 efsys_bar_t *en_esbp; 840 unsigned int en_mod_flags; 841 unsigned int en_reset_flags; 842 efx_nic_cfg_t en_nic_cfg; 843 efx_drv_cfg_t en_drv_cfg; 844 efx_port_t en_port; 845 efx_mon_t en_mon; 846 efx_intr_t en_intr; 847 uint32_t en_ev_qcount; 848 uint32_t en_rx_qcount; 849 uint32_t en_tx_qcount; 850 const efx_nic_ops_t *en_enop; 851 const efx_ev_ops_t *en_eevop; 852 const efx_tx_ops_t *en_etxop; 853 const efx_rx_ops_t *en_erxop; 854 efx_fw_variant_t efv; 855 char en_drv_version[EFX_DRV_VER_MAX]; 856 #if EFSYS_OPT_FILTER 857 efx_filter_t en_filter; 858 const efx_filter_ops_t *en_efop; 859 #endif /* EFSYS_OPT_FILTER */ 860 #if EFSYS_OPT_TUNNEL 861 efx_tunnel_cfg_t en_tunnel_cfg; 862 const efx_tunnel_ops_t *en_etop; 863 #endif /* EFSYS_OPT_TUNNEL */ 864 #if EFSYS_OPT_MCDI 865 efx_mcdi_t en_mcdi; 866 #endif /* EFSYS_OPT_MCDI */ 867 #if EFSYS_OPT_NVRAM 868 uint32_t en_nvram_partn_locked; 869 const efx_nvram_ops_t *en_envop; 870 #endif /* EFSYS_OPT_NVRAM */ 871 #if EFSYS_OPT_VPD 872 const efx_vpd_ops_t *en_evpdop; 873 #endif /* EFSYS_OPT_VPD */ 874 #if EFSYS_OPT_VIRTIO 875 const efx_virtio_ops_t *en_evop; 876 #endif /* EFSYS_OPT_VPD */ 877 #if EFSYS_OPT_RX_SCALE 878 efx_rx_hash_support_t en_hash_support; 879 efx_rx_scale_context_type_t en_rss_context_type; 880 uint32_t en_rss_context; 881 #endif /* EFSYS_OPT_RX_SCALE */ 882 uint32_t en_vport_id; 883 #if EFSYS_OPT_LICENSING 884 const efx_lic_ops_t *en_elop; 885 boolean_t en_licensing_supported; 886 #endif 887 union { 888 #if EFSYS_OPT_SIENA 889 struct { 890 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 891 unsigned int enu_partn_mask; 892 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 893 #if EFSYS_OPT_VPD 894 caddr_t enu_svpd; 895 size_t enu_svpd_length; 896 #endif /* EFSYS_OPT_VPD */ 897 int enu_unused; 898 } siena; 899 #endif /* EFSYS_OPT_SIENA */ 900 int enu_unused; 901 } en_u; 902 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 903 union en_arch { 904 struct { 905 int ena_vi_base; 906 int ena_vi_count; 907 int ena_vi_shift; 908 uint32_t ena_fcw_base; 909 #if EFSYS_OPT_VPD 910 caddr_t ena_svpd; 911 size_t ena_svpd_length; 912 #endif /* EFSYS_OPT_VPD */ 913 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 914 uint32_t ena_piobuf_count; 915 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 916 uint32_t ena_pio_write_vi_base; 917 /* Memory BAR mapping regions */ 918 uint32_t ena_uc_mem_map_offset; 919 size_t ena_uc_mem_map_size; 920 uint32_t ena_wc_mem_map_offset; 921 size_t ena_wc_mem_map_size; 922 } ef10; 923 } en_arch; 924 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 925 #if EFSYS_OPT_EVB 926 const efx_evb_ops_t *en_eeop; 927 struct efx_vswitch_s *en_vswitchp; 928 #endif /* EFSYS_OPT_EVB */ 929 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 930 const efx_proxy_ops_t *en_epop; 931 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 932 #if EFSYS_OPT_MAE 933 efx_mae_t *en_maep; 934 #endif /* EFSYS_OPT_MAE */ 935 }; 936 937 #define EFX_FAMILY_IS_EF10(_enp) \ 938 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 939 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 940 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 941 942 #define EFX_FAMILY_IS_EF100(_enp) \ 943 ((_enp)->en_family == EFX_FAMILY_RIVERHEAD) 944 945 946 #define EFX_NIC_MAGIC 0x02121996 947 948 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 949 const efx_ev_callbacks_t *, void *); 950 951 #if EFSYS_OPT_EV_EXTENDED_WIDTH 952 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *, 953 const efx_ev_callbacks_t *, void *); 954 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */ 955 956 typedef struct efx_evq_rxq_state_s { 957 unsigned int eers_rx_read_ptr; 958 unsigned int eers_rx_mask; 959 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 960 unsigned int eers_rx_stream_npackets; 961 boolean_t eers_rx_packed_stream; 962 #endif 963 #if EFSYS_OPT_RX_PACKED_STREAM 964 unsigned int eers_rx_packed_stream_credits; 965 #endif 966 } efx_evq_rxq_state_t; 967 968 struct efx_evq_s { 969 uint32_t ee_magic; 970 uint32_t ee_flags; 971 efx_nic_t *ee_enp; 972 unsigned int ee_index; 973 unsigned int ee_mask; 974 efsys_mem_t *ee_esmp; 975 #if EFSYS_OPT_QSTATS 976 uint32_t ee_stat[EV_NQSTATS]; 977 #endif /* EFSYS_OPT_QSTATS */ 978 979 efx_ev_handler_t ee_rx; 980 efx_ev_handler_t ee_tx; 981 efx_ev_handler_t ee_driver; 982 efx_ev_handler_t ee_global; 983 efx_ev_handler_t ee_drv_gen; 984 #if EFSYS_OPT_MCDI 985 efx_ev_handler_t ee_mcdi; 986 #endif /* EFSYS_OPT_MCDI */ 987 988 #if EFSYS_OPT_DESC_PROXY 989 efx_ev_ew_handler_t ee_ew_txq_desc; 990 efx_ev_ew_handler_t ee_ew_virtq_desc; 991 #endif /* EFSYS_OPT_DESC_PROXY */ 992 993 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 994 }; 995 996 #define EFX_EVQ_MAGIC 0x08081997 997 998 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 999 1000 #if EFSYS_OPT_QSTATS 1001 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 1002 do { \ 1003 (_eep)->ee_stat[_stat]++; \ 1004 _NOTE(CONSTANTCONDITION) \ 1005 } while (B_FALSE) 1006 #else 1007 #define EFX_EV_QSTAT_INCR(_eep, _stat) 1008 #endif 1009 1010 struct efx_rxq_s { 1011 uint32_t er_magic; 1012 efx_nic_t *er_enp; 1013 efx_evq_t *er_eep; 1014 unsigned int er_index; 1015 unsigned int er_label; 1016 unsigned int er_mask; 1017 size_t er_buf_size; 1018 efsys_mem_t *er_esmp; 1019 efx_evq_rxq_state_t *er_ev_qstate; 1020 efx_rx_prefix_layout_t er_prefix_layout; 1021 }; 1022 1023 #define EFX_RXQ_MAGIC 0x15022005 1024 1025 struct efx_txq_s { 1026 uint32_t et_magic; 1027 efx_nic_t *et_enp; 1028 unsigned int et_index; 1029 unsigned int et_mask; 1030 efsys_mem_t *et_esmp; 1031 #if EFSYS_OPT_HUNTINGTON 1032 uint32_t et_pio_bufnum; 1033 uint32_t et_pio_blknum; 1034 uint32_t et_pio_write_offset; 1035 uint32_t et_pio_offset; 1036 size_t et_pio_size; 1037 #endif 1038 #if EFSYS_OPT_QSTATS 1039 uint32_t et_stat[TX_NQSTATS]; 1040 #endif /* EFSYS_OPT_QSTATS */ 1041 }; 1042 1043 #define EFX_TXQ_MAGIC 0x05092005 1044 1045 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 1046 do { \ 1047 (_dst)[0] = (_src)[0]; \ 1048 (_dst)[1] = (_src)[1]; \ 1049 (_dst)[2] = (_src)[2]; \ 1050 (_dst)[3] = (_src)[3]; \ 1051 (_dst)[4] = (_src)[4]; \ 1052 (_dst)[5] = (_src)[5]; \ 1053 _NOTE(CONSTANTCONDITION) \ 1054 } while (B_FALSE) 1055 1056 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 1057 do { \ 1058 uint16_t *_d = (uint16_t *)(_dst); \ 1059 _d[0] = 0xffff; \ 1060 _d[1] = 0xffff; \ 1061 _d[2] = 0xffff; \ 1062 _NOTE(CONSTANTCONDITION) \ 1063 } while (B_FALSE) 1064 1065 #if EFSYS_OPT_CHECK_REG 1066 #define EFX_CHECK_REG(_enp, _reg) \ 1067 do { \ 1068 const char *name = #_reg; \ 1069 char min = name[4]; \ 1070 char max = name[5]; \ 1071 char rev; \ 1072 \ 1073 switch ((_enp)->en_family) { \ 1074 case EFX_FAMILY_SIENA: \ 1075 rev = 'C'; \ 1076 break; \ 1077 \ 1078 case EFX_FAMILY_HUNTINGTON: \ 1079 rev = 'D'; \ 1080 break; \ 1081 \ 1082 case EFX_FAMILY_MEDFORD: \ 1083 rev = 'E'; \ 1084 break; \ 1085 \ 1086 case EFX_FAMILY_MEDFORD2: \ 1087 rev = 'F'; \ 1088 break; \ 1089 \ 1090 case EFX_FAMILY_RIVERHEAD: \ 1091 rev = 'G'; \ 1092 break; \ 1093 \ 1094 default: \ 1095 rev = '?'; \ 1096 break; \ 1097 } \ 1098 \ 1099 EFSYS_ASSERT3S(rev, >=, min); \ 1100 EFSYS_ASSERT3S(rev, <=, max); \ 1101 \ 1102 _NOTE(CONSTANTCONDITION) \ 1103 } while (B_FALSE) 1104 #else 1105 #define EFX_CHECK_REG(_enp, _reg) do { \ 1106 _NOTE(CONSTANTCONDITION) \ 1107 } while (B_FALSE) 1108 #endif 1109 1110 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1111 do { \ 1112 EFX_CHECK_REG((_enp), (_reg)); \ 1113 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1114 (_edp), (_lock)); \ 1115 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1116 uint32_t, _reg ## _OFST, \ 1117 uint32_t, (_edp)->ed_u32[0]); \ 1118 _NOTE(CONSTANTCONDITION) \ 1119 } while (B_FALSE) 1120 1121 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1122 do { \ 1123 EFX_CHECK_REG((_enp), (_reg)); \ 1124 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1125 uint32_t, _reg ## _OFST, \ 1126 uint32_t, (_edp)->ed_u32[0]); \ 1127 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1128 (_edp), (_lock)); \ 1129 _NOTE(CONSTANTCONDITION) \ 1130 } while (B_FALSE) 1131 1132 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1133 do { \ 1134 EFX_CHECK_REG((_enp), (_reg)); \ 1135 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1136 (_eqp)); \ 1137 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1138 uint32_t, _reg ## _OFST, \ 1139 uint32_t, (_eqp)->eq_u32[1], \ 1140 uint32_t, (_eqp)->eq_u32[0]); \ 1141 _NOTE(CONSTANTCONDITION) \ 1142 } while (B_FALSE) 1143 1144 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1145 do { \ 1146 EFX_CHECK_REG((_enp), (_reg)); \ 1147 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1148 uint32_t, _reg ## _OFST, \ 1149 uint32_t, (_eqp)->eq_u32[1], \ 1150 uint32_t, (_eqp)->eq_u32[0]); \ 1151 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1152 (_eqp)); \ 1153 _NOTE(CONSTANTCONDITION) \ 1154 } while (B_FALSE) 1155 1156 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1157 do { \ 1158 EFX_CHECK_REG((_enp), (_reg)); \ 1159 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1160 (_eop), B_TRUE); \ 1161 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1162 uint32_t, _reg ## _OFST, \ 1163 uint32_t, (_eop)->eo_u32[3], \ 1164 uint32_t, (_eop)->eo_u32[2], \ 1165 uint32_t, (_eop)->eo_u32[1], \ 1166 uint32_t, (_eop)->eo_u32[0]); \ 1167 _NOTE(CONSTANTCONDITION) \ 1168 } while (B_FALSE) 1169 1170 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1171 do { \ 1172 EFX_CHECK_REG((_enp), (_reg)); \ 1173 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1174 uint32_t, _reg ## _OFST, \ 1175 uint32_t, (_eop)->eo_u32[3], \ 1176 uint32_t, (_eop)->eo_u32[2], \ 1177 uint32_t, (_eop)->eo_u32[1], \ 1178 uint32_t, (_eop)->eo_u32[0]); \ 1179 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1180 (_eop), B_TRUE); \ 1181 _NOTE(CONSTANTCONDITION) \ 1182 } while (B_FALSE) 1183 1184 /* 1185 * Accessors for memory BAR non-VI tables. 1186 * 1187 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1188 * to ensure the correct runtime VI window size is used on Medford2. 1189 * 1190 * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control 1191 * window registers, to ensure the correct starting offset is used. 1192 * 1193 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1194 */ 1195 1196 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1197 do { \ 1198 EFX_CHECK_REG((_enp), (_reg)); \ 1199 EFSYS_BAR_READD((_enp)->en_esbp, \ 1200 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1201 (_edp), (_lock)); \ 1202 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1203 uint32_t, (_index), \ 1204 uint32_t, _reg ## _OFST, \ 1205 uint32_t, (_edp)->ed_u32[0]); \ 1206 _NOTE(CONSTANTCONDITION) \ 1207 } while (B_FALSE) 1208 1209 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1210 do { \ 1211 EFX_CHECK_REG((_enp), (_reg)); \ 1212 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1213 uint32_t, (_index), \ 1214 uint32_t, _reg ## _OFST, \ 1215 uint32_t, (_edp)->ed_u32[0]); \ 1216 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1217 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1218 (_edp), (_lock)); \ 1219 _NOTE(CONSTANTCONDITION) \ 1220 } while (B_FALSE) 1221 1222 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1223 do { \ 1224 EFX_CHECK_REG((_enp), (_reg)); \ 1225 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1226 uint32_t, (_index), \ 1227 uint32_t, _reg ## _OFST, \ 1228 uint32_t, (_edp)->ed_u32[0]); \ 1229 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1230 (_reg ## _OFST + \ 1231 (3 * sizeof (efx_dword_t)) + \ 1232 ((_index) * _reg ## _STEP)), \ 1233 (_edp), (_lock)); \ 1234 _NOTE(CONSTANTCONDITION) \ 1235 } while (B_FALSE) 1236 1237 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1238 do { \ 1239 EFX_CHECK_REG((_enp), (_reg)); \ 1240 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1241 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1242 (_eqp)); \ 1243 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1244 uint32_t, (_index), \ 1245 uint32_t, _reg ## _OFST, \ 1246 uint32_t, (_eqp)->eq_u32[1], \ 1247 uint32_t, (_eqp)->eq_u32[0]); \ 1248 _NOTE(CONSTANTCONDITION) \ 1249 } while (B_FALSE) 1250 1251 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1252 do { \ 1253 EFX_CHECK_REG((_enp), (_reg)); \ 1254 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1255 uint32_t, (_index), \ 1256 uint32_t, _reg ## _OFST, \ 1257 uint32_t, (_eqp)->eq_u32[1], \ 1258 uint32_t, (_eqp)->eq_u32[0]); \ 1259 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1260 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1261 (_eqp)); \ 1262 _NOTE(CONSTANTCONDITION) \ 1263 } while (B_FALSE) 1264 1265 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1266 do { \ 1267 EFX_CHECK_REG((_enp), (_reg)); \ 1268 EFSYS_BAR_READO((_enp)->en_esbp, \ 1269 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1270 (_eop), (_lock)); \ 1271 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1272 uint32_t, (_index), \ 1273 uint32_t, _reg ## _OFST, \ 1274 uint32_t, (_eop)->eo_u32[3], \ 1275 uint32_t, (_eop)->eo_u32[2], \ 1276 uint32_t, (_eop)->eo_u32[1], \ 1277 uint32_t, (_eop)->eo_u32[0]); \ 1278 _NOTE(CONSTANTCONDITION) \ 1279 } while (B_FALSE) 1280 1281 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1282 do { \ 1283 EFX_CHECK_REG((_enp), (_reg)); \ 1284 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1285 uint32_t, (_index), \ 1286 uint32_t, _reg ## _OFST, \ 1287 uint32_t, (_eop)->eo_u32[3], \ 1288 uint32_t, (_eop)->eo_u32[2], \ 1289 uint32_t, (_eop)->eo_u32[1], \ 1290 uint32_t, (_eop)->eo_u32[0]); \ 1291 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1292 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1293 (_eop), (_lock)); \ 1294 _NOTE(CONSTANTCONDITION) \ 1295 } while (B_FALSE) 1296 1297 /* 1298 * Accessors for memory BAR function control window registers. 1299 * 1300 * The function control window is located at an offset which can be 1301 * non-zero in case of Riverhead. 1302 */ 1303 1304 #if EFSYS_OPT_RIVERHEAD 1305 1306 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ 1307 do { \ 1308 EFX_CHECK_REG((_enp), (_reg)); \ 1309 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \ 1310 (_enp)->en_arch.ef10.ena_fcw_base, \ 1311 (_edp), B_FALSE); \ 1312 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \ 1313 uint32_t, _reg ## _OFST, \ 1314 uint32_t, (_edp)->ed_u32[0]); \ 1315 _NOTE(CONSTANTCONDITION) \ 1316 } while (B_FALSE) 1317 1318 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \ 1319 do { \ 1320 EFX_CHECK_REG((_enp), (_reg)); \ 1321 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \ 1322 uint32_t, _reg ## _OFST, \ 1323 uint32_t, (_edp)->ed_u32[0]); \ 1324 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \ 1325 (_enp)->en_arch.ef10.ena_fcw_base, \ 1326 (_edp), B_FALSE); \ 1327 _NOTE(CONSTANTCONDITION) \ 1328 } while (B_FALSE) 1329 1330 #endif /* EFSYS_OPT_RIVERHEAD */ 1331 1332 /* 1333 * Accessors for memory BAR per-VI registers. 1334 * 1335 * The VI window size is 8KB for Medford and all earlier controllers. 1336 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1337 */ 1338 1339 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1340 do { \ 1341 EFX_CHECK_REG((_enp), (_reg)); \ 1342 EFSYS_BAR_READD((_enp)->en_esbp, \ 1343 ((_reg ## _OFST) + \ 1344 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1345 (_edp), (_lock)); \ 1346 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1347 uint32_t, (_index), \ 1348 uint32_t, _reg ## _OFST, \ 1349 uint32_t, (_edp)->ed_u32[0]); \ 1350 _NOTE(CONSTANTCONDITION) \ 1351 } while (B_FALSE) 1352 1353 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1354 do { \ 1355 EFX_CHECK_REG((_enp), (_reg)); \ 1356 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1357 uint32_t, (_index), \ 1358 uint32_t, _reg ## _OFST, \ 1359 uint32_t, (_edp)->ed_u32[0]); \ 1360 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1361 ((_reg ## _OFST) + \ 1362 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1363 (_edp), (_lock)); \ 1364 _NOTE(CONSTANTCONDITION) \ 1365 } while (B_FALSE) 1366 1367 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1368 do { \ 1369 EFX_CHECK_REG((_enp), (_reg)); \ 1370 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1371 uint32_t, (_index), \ 1372 uint32_t, _reg ## _OFST, \ 1373 uint32_t, (_edp)->ed_u32[0]); \ 1374 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1375 ((_reg ## _OFST) + \ 1376 (2 * sizeof (efx_dword_t)) + \ 1377 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1378 (_edp), (_lock)); \ 1379 _NOTE(CONSTANTCONDITION) \ 1380 } while (B_FALSE) 1381 1382 /* 1383 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1384 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1385 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1386 * the need for locking in the host, and are the only ones known to be safe to 1387 * use 128-bites write with. 1388 */ 1389 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1390 do { \ 1391 EFX_CHECK_REG((_enp), (_reg)); \ 1392 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1393 const char *, #_reg, \ 1394 uint32_t, (_index), \ 1395 uint32_t, _reg ## _OFST, \ 1396 uint32_t, (_eop)->eo_u32[3], \ 1397 uint32_t, (_eop)->eo_u32[2], \ 1398 uint32_t, (_eop)->eo_u32[1], \ 1399 uint32_t, (_eop)->eo_u32[0]); \ 1400 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1401 (_reg ## _OFST + \ 1402 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1403 (_eop)); \ 1404 _NOTE(CONSTANTCONDITION) \ 1405 } while (B_FALSE) 1406 1407 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ 1408 _wptr, _owptr) \ 1409 do { \ 1410 unsigned int _new = (_wptr); \ 1411 unsigned int _old = (_owptr); \ 1412 \ 1413 if ((_new) >= (_old)) \ 1414 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1415 (_old) * (_desc_size), \ 1416 ((_new) - (_old)) * (_desc_size)); \ 1417 else \ 1418 /* \ 1419 * It is cheaper to sync entire map than sync \ 1420 * two parts especially when offset/size are \ 1421 * ignored and entire map is synced in any case.\ 1422 */ \ 1423 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1424 0, \ 1425 (_entries) * (_desc_size)); \ 1426 _NOTE(CONSTANTCONDITION) \ 1427 } while (B_FALSE) 1428 1429 LIBEFX_INTERNAL 1430 extern __checkReturn efx_rc_t 1431 efx_mac_select( 1432 __in efx_nic_t *enp); 1433 1434 LIBEFX_INTERNAL 1435 extern void 1436 efx_mac_multicast_hash_compute( 1437 __in_ecount(6*count) uint8_t const *addrs, 1438 __in int count, 1439 __out efx_oword_t *hash_low, 1440 __out efx_oword_t *hash_high); 1441 1442 LIBEFX_INTERNAL 1443 extern __checkReturn efx_rc_t 1444 efx_phy_probe( 1445 __in efx_nic_t *enp); 1446 1447 LIBEFX_INTERNAL 1448 extern void 1449 efx_phy_unprobe( 1450 __in efx_nic_t *enp); 1451 1452 #if EFSYS_OPT_VPD 1453 1454 /* VPD utility functions */ 1455 1456 LIBEFX_INTERNAL 1457 extern __checkReturn efx_rc_t 1458 efx_vpd_hunk_length( 1459 __in_bcount(size) caddr_t data, 1460 __in size_t size, 1461 __out size_t *lengthp); 1462 1463 LIBEFX_INTERNAL 1464 extern __checkReturn efx_rc_t 1465 efx_vpd_hunk_verify( 1466 __in_bcount(size) caddr_t data, 1467 __in size_t size, 1468 __out_opt boolean_t *cksummedp); 1469 1470 LIBEFX_INTERNAL 1471 extern __checkReturn efx_rc_t 1472 efx_vpd_hunk_reinit( 1473 __in_bcount(size) caddr_t data, 1474 __in size_t size, 1475 __in boolean_t wantpid); 1476 1477 LIBEFX_INTERNAL 1478 extern __checkReturn efx_rc_t 1479 efx_vpd_hunk_get( 1480 __in_bcount(size) caddr_t data, 1481 __in size_t size, 1482 __in efx_vpd_tag_t tag, 1483 __in efx_vpd_keyword_t keyword, 1484 __out unsigned int *payloadp, 1485 __out uint8_t *paylenp); 1486 1487 LIBEFX_INTERNAL 1488 extern __checkReturn efx_rc_t 1489 efx_vpd_hunk_next( 1490 __in_bcount(size) caddr_t data, 1491 __in size_t size, 1492 __out efx_vpd_tag_t *tagp, 1493 __out efx_vpd_keyword_t *keyword, 1494 __out_opt unsigned int *payloadp, 1495 __out_opt uint8_t *paylenp, 1496 __inout unsigned int *contp); 1497 1498 LIBEFX_INTERNAL 1499 extern __checkReturn efx_rc_t 1500 efx_vpd_hunk_set( 1501 __in_bcount(size) caddr_t data, 1502 __in size_t size, 1503 __in efx_vpd_value_t *evvp); 1504 1505 #endif /* EFSYS_OPT_VPD */ 1506 1507 #if EFSYS_OPT_MCDI 1508 1509 LIBEFX_INTERNAL 1510 extern __checkReturn efx_rc_t 1511 efx_mcdi_set_workaround( 1512 __in efx_nic_t *enp, 1513 __in uint32_t type, 1514 __in boolean_t enabled, 1515 __out_opt uint32_t *flagsp); 1516 1517 LIBEFX_INTERNAL 1518 extern __checkReturn efx_rc_t 1519 efx_mcdi_get_workarounds( 1520 __in efx_nic_t *enp, 1521 __out_opt uint32_t *implementedp, 1522 __out_opt uint32_t *enabledp); 1523 1524 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1525 1526 LIBEFX_INTERNAL 1527 extern __checkReturn efx_rc_t 1528 efx_mcdi_init_evq( 1529 __in efx_nic_t *enp, 1530 __in unsigned int instance, 1531 __in efsys_mem_t *esmp, 1532 __in size_t nevs, 1533 __in uint32_t irq, 1534 __in uint32_t us, 1535 __in uint32_t flags, 1536 __in boolean_t low_latency); 1537 1538 LIBEFX_INTERNAL 1539 extern __checkReturn efx_rc_t 1540 efx_mcdi_fini_evq( 1541 __in efx_nic_t *enp, 1542 __in uint32_t instance); 1543 1544 typedef struct efx_mcdi_init_rxq_params_s { 1545 boolean_t disable_scatter; 1546 boolean_t want_inner_classes; 1547 uint32_t buf_size; 1548 uint32_t ps_buf_size; 1549 uint32_t es_bufs_per_desc; 1550 uint32_t es_max_dma_len; 1551 uint32_t es_buf_stride; 1552 uint32_t hol_block_timeout; 1553 uint32_t prefix_id; 1554 } efx_mcdi_init_rxq_params_t; 1555 1556 LIBEFX_INTERNAL 1557 extern __checkReturn efx_rc_t 1558 efx_mcdi_init_rxq( 1559 __in efx_nic_t *enp, 1560 __in uint32_t ndescs, 1561 __in efx_evq_t *eep, 1562 __in uint32_t label, 1563 __in uint32_t instance, 1564 __in efsys_mem_t *esmp, 1565 __in const efx_mcdi_init_rxq_params_t *params); 1566 1567 LIBEFX_INTERNAL 1568 extern __checkReturn efx_rc_t 1569 efx_mcdi_fini_rxq( 1570 __in efx_nic_t *enp, 1571 __in uint32_t instance); 1572 1573 LIBEFX_INTERNAL 1574 extern __checkReturn efx_rc_t 1575 efx_mcdi_init_txq( 1576 __in efx_nic_t *enp, 1577 __in uint32_t ndescs, 1578 __in uint32_t target_evq, 1579 __in uint32_t label, 1580 __in uint32_t instance, 1581 __in uint16_t flags, 1582 __in efsys_mem_t *esmp); 1583 1584 LIBEFX_INTERNAL 1585 extern __checkReturn efx_rc_t 1586 efx_mcdi_fini_txq( 1587 __in efx_nic_t *enp, 1588 __in uint32_t instance); 1589 1590 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1591 1592 #endif /* EFSYS_OPT_MCDI */ 1593 1594 #if EFSYS_OPT_MAC_STATS 1595 1596 /* 1597 * Closed range of stats (i.e. the first and the last are included). 1598 * The last must be greater or equal (if the range is one item only) to 1599 * the first. 1600 */ 1601 struct efx_mac_stats_range { 1602 efx_mac_stat_t first; 1603 efx_mac_stat_t last; 1604 }; 1605 1606 typedef enum efx_stats_action_e { 1607 EFX_STATS_CLEAR, 1608 EFX_STATS_UPLOAD, 1609 EFX_STATS_ENABLE_NOEVENTS, 1610 EFX_STATS_ENABLE_EVENTS, 1611 EFX_STATS_DISABLE, 1612 } efx_stats_action_t; 1613 1614 LIBEFX_INTERNAL 1615 extern efx_rc_t 1616 efx_mac_stats_mask_add_ranges( 1617 __inout_bcount(mask_size) uint32_t *maskp, 1618 __in size_t mask_size, 1619 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1620 __in unsigned int rng_count); 1621 1622 LIBEFX_INTERNAL 1623 extern __checkReturn efx_rc_t 1624 efx_mcdi_mac_stats( 1625 __in efx_nic_t *enp, 1626 __in uint32_t vport_id, 1627 __in_opt efsys_mem_t *esmp, 1628 __in efx_stats_action_t action, 1629 __in uint16_t period_ms); 1630 1631 #endif /* EFSYS_OPT_MAC_STATS */ 1632 1633 #if EFSYS_OPT_PCI 1634 1635 /* 1636 * Find the next extended capability in a PCI device's config space 1637 * with specified capability id. 1638 * Passing 0 offset makes the function search from the start. 1639 * If search succeeds, found capability is in modified offset. 1640 * 1641 * Returns ENOENT if a capability is not found. 1642 */ 1643 LIBEFX_INTERNAL 1644 extern __checkReturn efx_rc_t 1645 efx_pci_config_find_next_ext_cap( 1646 __in efsys_pci_config_t *espcp, 1647 __in const efx_pci_ops_t *epop, 1648 __in uint16_t cap_id, 1649 __inout size_t *offsetp); 1650 1651 /* 1652 * Get the next extended capability in a PCI device's config space. 1653 * Passing 0 offset makes the function get the first capability. 1654 * If search succeeds, the capability is in modified offset. 1655 * 1656 * Returns ENOENT if there is no next capability. 1657 */ 1658 LIBEFX_INTERNAL 1659 extern __checkReturn efx_rc_t 1660 efx_pci_config_next_ext_cap( 1661 __in efsys_pci_config_t *espcp, 1662 __in const efx_pci_ops_t *epop, 1663 __inout size_t *offsetp); 1664 1665 /* 1666 * Find the next Xilinx capabilities table location by searching 1667 * PCI extended capabilities. 1668 * 1669 * Returns ENOENT if a table location is not found. 1670 */ 1671 LIBEFX_INTERNAL 1672 extern __checkReturn efx_rc_t 1673 efx_pci_find_next_xilinx_cap_table( 1674 __in efsys_pci_config_t *espcp, 1675 __in const efx_pci_ops_t *epop, 1676 __inout size_t *pci_cap_offsetp, 1677 __out unsigned int *xilinx_tbl_barp, 1678 __out efsys_dma_addr_t *xilinx_tbl_offsetp); 1679 1680 /* 1681 * Read a Xilinx extended PCI capability that gives the location 1682 * of a Xilinx capabilities table. 1683 * 1684 * Returns ENOENT if the extended PCI capability does not contain 1685 * Xilinx capabilities table locator. 1686 */ 1687 LIBEFX_INTERNAL 1688 extern __checkReturn efx_rc_t 1689 efx_pci_read_ext_cap_xilinx_table( 1690 __in efsys_pci_config_t *espcp, 1691 __in const efx_pci_ops_t *epop, 1692 __in size_t cap_offset, 1693 __out unsigned int *barp, 1694 __out efsys_dma_addr_t *offsetp); 1695 1696 /* 1697 * Find a capability with specified format_id in a Xilinx capabilities table. 1698 * Searching is started from provided offset, taking skip_first into account. 1699 * If search succeeds, found capability is in modified offset. 1700 * 1701 * Returns ENOENT if an entry with specified format id is not found. 1702 */ 1703 LIBEFX_INTERNAL 1704 extern __checkReturn efx_rc_t 1705 efx_pci_xilinx_cap_tbl_find( 1706 __in efsys_bar_t *esbp, 1707 __in uint32_t format_id, 1708 __in boolean_t skip_first, 1709 __inout efsys_dma_addr_t *entry_offsetp); 1710 1711 #endif /* EFSYS_OPT_PCI */ 1712 1713 #if EFSYS_OPT_MAE 1714 1715 struct efx_mae_match_spec_s { 1716 efx_mae_rule_type_t emms_type; 1717 uint32_t emms_prio; 1718 union emms_mask_value_pairs { 1719 uint8_t action[MAE_FIELD_MASK_VALUE_PAIRS_LEN]; 1720 uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN]; 1721 } emms_mask_value_pairs; 1722 }; 1723 1724 typedef enum efx_mae_action_e { 1725 /* These actions are strictly ordered. */ 1726 EFX_MAE_ACTION_VLAN_POP, 1727 EFX_MAE_ACTION_VLAN_PUSH, 1728 1729 /* 1730 * These actions are not strictly ordered and can 1731 * be passed by a client in any order (before DELIVER). 1732 * However, these enumerants must be kept compactly 1733 * in the end of the enumeration (before DELIVER). 1734 */ 1735 EFX_MAE_ACTION_FLAG, 1736 EFX_MAE_ACTION_MARK, 1737 1738 /* DELIVER is always the last action. */ 1739 EFX_MAE_ACTION_DELIVER, 1740 1741 EFX_MAE_NACTIONS 1742 } efx_mae_action_t; 1743 1744 /* MAE VLAN_POP action can handle 1 or 2 tags. */ 1745 #define EFX_MAE_VLAN_POP_MAX_NTAGS (2) 1746 1747 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */ 1748 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS (2) 1749 1750 typedef struct efx_mae_action_vlan_push_s { 1751 uint16_t emavp_tpid_be; 1752 uint16_t emavp_tci_be; 1753 } efx_mae_action_vlan_push_t; 1754 1755 struct efx_mae_actions_s { 1756 /* Bitmap of actions in spec, indexed by action type */ 1757 uint32_t ema_actions; 1758 1759 unsigned int ema_n_vlan_tags_to_pop; 1760 unsigned int ema_n_vlan_tags_to_push; 1761 efx_mae_action_vlan_push_t ema_vlan_push_descs[ 1762 EFX_MAE_VLAN_PUSH_MAX_NTAGS]; 1763 uint32_t ema_mark_value; 1764 efx_mport_sel_t ema_deliver_mport; 1765 }; 1766 1767 #endif /* EFSYS_OPT_MAE */ 1768 1769 #if EFSYS_OPT_VIRTIO 1770 1771 #define EFX_VQ_MAGIC 0x026011950 1772 1773 typedef enum efx_virtio_vq_state_e { 1774 EFX_VIRTIO_VQ_STATE_UNKNOWN = 0, 1775 EFX_VIRTIO_VQ_STATE_INITIALIZED, 1776 EFX_VIRTIO_VQ_STATE_STARTED, 1777 EFX_VIRTIO_VQ_NSTATES 1778 } efx_virtio_vq_state_t; 1779 1780 struct efx_virtio_vq_s { 1781 uint32_t evv_magic; 1782 efx_nic_t *evv_enp; 1783 efx_virtio_vq_state_t evv_state; 1784 uint32_t evv_vi_index; 1785 efx_virtio_vq_type_t evv_type; 1786 uint16_t evv_target_vf; 1787 }; 1788 1789 #endif /* EFSYS_OPT_VIRTIO */ 1790 1791 #ifdef __cplusplus 1792 } 1793 #endif 1794 1795 #endif /* _SYS_EFX_IMPL_H */ 1796