1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #include "efx_regs_ef100.h" 14 #if EFSYS_OPT_MCDI 15 #include "efx_mcdi.h" 16 #endif /* EFSYS_OPT_MCDI */ 17 18 /* FIXME: Add definition for driver generated software events */ 19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 21 #endif 22 23 24 #if EFSYS_OPT_SIENA 25 #include "siena_impl.h" 26 #endif /* EFSYS_OPT_SIENA */ 27 28 #if EFSYS_OPT_HUNTINGTON 29 #include "hunt_impl.h" 30 #endif /* EFSYS_OPT_HUNTINGTON */ 31 32 #if EFSYS_OPT_MEDFORD 33 #include "medford_impl.h" 34 #endif /* EFSYS_OPT_MEDFORD */ 35 36 #if EFSYS_OPT_MEDFORD2 37 #include "medford2_impl.h" 38 #endif /* EFSYS_OPT_MEDFORD2 */ 39 40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 41 #include "ef10_impl.h" 42 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 43 44 #if EFSYS_OPT_RIVERHEAD 45 #include "rhead_impl.h" 46 #endif /* EFSYS_OPT_RIVERHEAD */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define EFX_MOD_MCDI 0x00000001 53 #define EFX_MOD_PROBE 0x00000002 54 #define EFX_MOD_NVRAM 0x00000004 55 #define EFX_MOD_VPD 0x00000008 56 #define EFX_MOD_NIC 0x00000010 57 #define EFX_MOD_INTR 0x00000020 58 #define EFX_MOD_EV 0x00000040 59 #define EFX_MOD_RX 0x00000080 60 #define EFX_MOD_TX 0x00000100 61 #define EFX_MOD_PORT 0x00000200 62 #define EFX_MOD_MON 0x00000400 63 #define EFX_MOD_FILTER 0x00001000 64 #define EFX_MOD_LIC 0x00002000 65 #define EFX_MOD_TUNNEL 0x00004000 66 #define EFX_MOD_EVB 0x00008000 67 #define EFX_MOD_PROXY 0x00010000 68 #define EFX_MOD_VIRTIO 0x00020000 69 70 #define EFX_RESET_PHY 0x00000001 71 #define EFX_RESET_RXQ_ERR 0x00000002 72 #define EFX_RESET_TXQ_ERR 0x00000004 73 #define EFX_RESET_HW_UNAVAIL 0x00000008 74 75 typedef enum efx_mac_type_e { 76 EFX_MAC_INVALID = 0, 77 EFX_MAC_SIENA, 78 EFX_MAC_HUNTINGTON, 79 EFX_MAC_MEDFORD, 80 EFX_MAC_MEDFORD2, 81 EFX_MAC_RIVERHEAD, 82 EFX_MAC_NTYPES 83 } efx_mac_type_t; 84 85 typedef struct efx_ev_ops_s { 86 efx_rc_t (*eevo_init)(efx_nic_t *); 87 void (*eevo_fini)(efx_nic_t *); 88 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 89 efsys_mem_t *, size_t, uint32_t, 90 uint32_t, uint32_t, uint32_t, 91 efx_evq_t *); 92 void (*eevo_qdestroy)(efx_evq_t *); 93 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 94 void (*eevo_qpost)(efx_evq_t *, uint16_t); 95 void (*eevo_qpoll)(efx_evq_t *, unsigned int *, 96 const efx_ev_callbacks_t *, void *); 97 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 98 #if EFSYS_OPT_QSTATS 99 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 100 #endif 101 } efx_ev_ops_t; 102 103 typedef struct efx_tx_ops_s { 104 efx_rc_t (*etxo_init)(efx_nic_t *); 105 void (*etxo_fini)(efx_nic_t *); 106 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 107 unsigned int, unsigned int, 108 efsys_mem_t *, size_t, 109 uint32_t, uint16_t, 110 efx_evq_t *, efx_txq_t *, 111 unsigned int *); 112 void (*etxo_qdestroy)(efx_txq_t *); 113 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 114 unsigned int, unsigned int, 115 unsigned int *); 116 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 117 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 118 efx_rc_t (*etxo_qflush)(efx_txq_t *); 119 void (*etxo_qenable)(efx_txq_t *); 120 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 121 void (*etxo_qpio_disable)(efx_txq_t *); 122 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 123 size_t); 124 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 125 unsigned int *); 126 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 127 unsigned int, unsigned int, 128 unsigned int *); 129 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 130 size_t, boolean_t, 131 efx_desc_t *); 132 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 133 uint32_t, uint8_t, 134 efx_desc_t *); 135 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 136 uint16_t, uint32_t, uint16_t, 137 efx_desc_t *, int); 138 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 139 efx_desc_t *); 140 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 141 efx_desc_t *); 142 #if EFSYS_OPT_QSTATS 143 void (*etxo_qstats_update)(efx_txq_t *, 144 efsys_stat_t *); 145 #endif 146 } efx_tx_ops_t; 147 148 typedef union efx_rxq_type_data_u { 149 struct { 150 size_t ed_buf_size; 151 } ertd_default; 152 #if EFSYS_OPT_RX_PACKED_STREAM 153 struct { 154 uint32_t eps_buf_size; 155 } ertd_packed_stream; 156 #endif 157 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 158 struct { 159 uint32_t eessb_bufs_per_desc; 160 uint32_t eessb_max_dma_len; 161 uint32_t eessb_buf_stride; 162 uint32_t eessb_hol_block_timeout; 163 } ertd_es_super_buffer; 164 #endif 165 } efx_rxq_type_data_t; 166 167 typedef struct efx_rx_ops_s { 168 efx_rc_t (*erxo_init)(efx_nic_t *); 169 void (*erxo_fini)(efx_nic_t *); 170 #if EFSYS_OPT_RX_SCATTER 171 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 172 #endif 173 #if EFSYS_OPT_RX_SCALE 174 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 175 efx_rx_scale_context_type_t, 176 uint32_t, uint32_t *); 177 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 178 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 179 efx_rx_hash_alg_t, 180 efx_rx_hash_type_t, boolean_t); 181 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 182 uint8_t *, size_t); 183 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 184 unsigned int *, size_t); 185 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 186 uint8_t *); 187 #endif /* EFSYS_OPT_RX_SCALE */ 188 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 189 uint16_t *); 190 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 191 unsigned int, unsigned int, 192 unsigned int); 193 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 194 #if EFSYS_OPT_RX_PACKED_STREAM 195 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 196 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 197 uint32_t, uint32_t, 198 uint16_t *, uint32_t *, uint32_t *); 199 #endif 200 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 201 void (*erxo_qenable)(efx_rxq_t *); 202 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 203 unsigned int, efx_rxq_type_t, 204 const efx_rxq_type_data_t *, 205 efsys_mem_t *, size_t, uint32_t, 206 unsigned int, 207 efx_evq_t *, efx_rxq_t *); 208 void (*erxo_qdestroy)(efx_rxq_t *); 209 } efx_rx_ops_t; 210 211 typedef struct efx_mac_ops_s { 212 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 213 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 214 efx_rc_t (*emo_addr_set)(efx_nic_t *); 215 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 216 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 217 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 218 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 219 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 220 efx_rxq_t *, boolean_t); 221 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 222 #if EFSYS_OPT_LOOPBACK 223 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 224 efx_loopback_type_t); 225 #endif /* EFSYS_OPT_LOOPBACK */ 226 #if EFSYS_OPT_MAC_STATS 227 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 228 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 229 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 230 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 231 uint16_t, boolean_t); 232 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 233 efsys_stat_t *, uint32_t *); 234 #endif /* EFSYS_OPT_MAC_STATS */ 235 } efx_mac_ops_t; 236 237 typedef struct efx_phy_ops_s { 238 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 239 efx_rc_t (*epo_reset)(efx_nic_t *); 240 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 241 efx_rc_t (*epo_verify)(efx_nic_t *); 242 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 243 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 244 #if EFSYS_OPT_PHY_STATS 245 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 246 uint32_t *); 247 #endif /* EFSYS_OPT_PHY_STATS */ 248 #if EFSYS_OPT_BIST 249 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 250 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 251 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 252 efx_bist_result_t *, uint32_t *, 253 unsigned long *, size_t); 254 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 255 #endif /* EFSYS_OPT_BIST */ 256 } efx_phy_ops_t; 257 258 #if EFSYS_OPT_FILTER 259 260 /* 261 * Policy for replacing existing filter when inserting a new one. 262 * Note that all policies allow for storing the new lower priority 263 * filters as overridden by existing higher priority ones. It is needed 264 * to restore the lower priority filters on higher priority ones removal. 265 */ 266 typedef enum efx_filter_replacement_policy_e { 267 /* Cannot replace existing filter */ 268 EFX_FILTER_REPLACEMENT_NEVER, 269 /* Higher priority filters can replace lower priotiry ones */ 270 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 271 /* 272 * Higher priority filters can replace lower priority ones and 273 * equal priority filters can replace each other. 274 */ 275 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 276 } efx_filter_replacement_policy_t; 277 278 typedef struct efx_filter_ops_s { 279 efx_rc_t (*efo_init)(efx_nic_t *); 280 void (*efo_fini)(efx_nic_t *); 281 efx_rc_t (*efo_restore)(efx_nic_t *); 282 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 283 efx_filter_replacement_policy_t policy); 284 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 285 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 286 size_t, size_t *); 287 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 288 boolean_t, boolean_t, boolean_t, 289 uint8_t const *, uint32_t); 290 } efx_filter_ops_t; 291 292 LIBEFX_INTERNAL 293 extern __checkReturn efx_rc_t 294 efx_filter_reconfigure( 295 __in efx_nic_t *enp, 296 __in_ecount(6) uint8_t const *mac_addr, 297 __in boolean_t all_unicst, 298 __in boolean_t mulcst, 299 __in boolean_t all_mulcst, 300 __in boolean_t brdcst, 301 __in_ecount(6*count) uint8_t const *addrs, 302 __in uint32_t count); 303 304 #endif /* EFSYS_OPT_FILTER */ 305 306 #if EFSYS_OPT_TUNNEL 307 typedef struct efx_tunnel_ops_s { 308 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 309 void (*eto_fini)(efx_nic_t *); 310 } efx_tunnel_ops_t; 311 #endif /* EFSYS_OPT_TUNNEL */ 312 313 #if EFSYS_OPT_VIRTIO 314 typedef struct efx_virtio_ops_s { 315 efx_rc_t (*evo_virtio_qstart)(efx_virtio_vq_t *, 316 efx_virtio_vq_cfg_t *, 317 efx_virtio_vq_dyncfg_t *); 318 efx_rc_t (*evo_virtio_qstop)(efx_virtio_vq_t *, 319 efx_virtio_vq_dyncfg_t *); 320 efx_rc_t (*evo_get_doorbell_offset)(efx_virtio_vq_t *, 321 uint32_t *); 322 efx_rc_t (*evo_get_features)(efx_nic_t *, 323 efx_virtio_device_type_t, uint64_t *); 324 efx_rc_t (*evo_verify_features)(efx_nic_t *, 325 efx_virtio_device_type_t, uint64_t); 326 } efx_virtio_ops_t; 327 #endif /* EFSYS_OPT_VIRTIO */ 328 329 typedef struct efx_port_s { 330 efx_mac_type_t ep_mac_type; 331 uint32_t ep_phy_type; 332 uint8_t ep_port; 333 uint32_t ep_mac_pdu; 334 uint8_t ep_mac_addr[6]; 335 efx_link_mode_t ep_link_mode; 336 boolean_t ep_all_unicst; 337 boolean_t ep_all_unicst_inserted; 338 boolean_t ep_mulcst; 339 boolean_t ep_all_mulcst; 340 boolean_t ep_all_mulcst_inserted; 341 boolean_t ep_brdcst; 342 unsigned int ep_fcntl; 343 boolean_t ep_fcntl_autoneg; 344 efx_oword_t ep_multicst_hash[2]; 345 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 346 EFX_MAC_MULTICAST_LIST_MAX]; 347 uint32_t ep_mulcst_addr_count; 348 #if EFSYS_OPT_LOOPBACK 349 efx_loopback_type_t ep_loopback_type; 350 efx_link_mode_t ep_loopback_link_mode; 351 #endif /* EFSYS_OPT_LOOPBACK */ 352 #if EFSYS_OPT_PHY_FLAGS 353 uint32_t ep_phy_flags; 354 #endif /* EFSYS_OPT_PHY_FLAGS */ 355 #if EFSYS_OPT_PHY_LED_CONTROL 356 efx_phy_led_mode_t ep_phy_led_mode; 357 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 358 efx_phy_media_type_t ep_fixed_port_type; 359 efx_phy_media_type_t ep_module_type; 360 uint32_t ep_adv_cap_mask; 361 uint32_t ep_lp_cap_mask; 362 uint32_t ep_default_adv_cap_mask; 363 uint32_t ep_phy_cap_mask; 364 boolean_t ep_mac_drain; 365 #if EFSYS_OPT_BIST 366 efx_bist_type_t ep_current_bist; 367 #endif 368 const efx_mac_ops_t *ep_emop; 369 const efx_phy_ops_t *ep_epop; 370 } efx_port_t; 371 372 typedef struct efx_mon_ops_s { 373 #if EFSYS_OPT_MON_STATS 374 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 375 efx_mon_stat_value_t *); 376 efx_rc_t (*emo_limits_update)(efx_nic_t *, 377 efx_mon_stat_limits_t *); 378 #endif /* EFSYS_OPT_MON_STATS */ 379 } efx_mon_ops_t; 380 381 typedef struct efx_mon_s { 382 efx_mon_type_t em_type; 383 const efx_mon_ops_t *em_emop; 384 } efx_mon_t; 385 386 typedef struct efx_intr_ops_s { 387 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 388 void (*eio_enable)(efx_nic_t *); 389 void (*eio_disable)(efx_nic_t *); 390 void (*eio_disable_unlocked)(efx_nic_t *); 391 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 392 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 393 void (*eio_status_message)(efx_nic_t *, unsigned int, 394 boolean_t *); 395 void (*eio_fatal)(efx_nic_t *); 396 void (*eio_fini)(efx_nic_t *); 397 } efx_intr_ops_t; 398 399 typedef struct efx_intr_s { 400 const efx_intr_ops_t *ei_eiop; 401 efsys_mem_t *ei_esmp; 402 efx_intr_type_t ei_type; 403 unsigned int ei_level; 404 } efx_intr_t; 405 406 typedef struct efx_nic_ops_s { 407 efx_rc_t (*eno_probe)(efx_nic_t *); 408 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 409 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 410 efx_rc_t (*eno_reset)(efx_nic_t *); 411 efx_rc_t (*eno_init)(efx_nic_t *); 412 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 413 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 414 uint32_t *, size_t *); 415 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 416 void (*eno_set_hw_unavailable)(efx_nic_t *); 417 #if EFSYS_OPT_DIAG 418 efx_rc_t (*eno_register_test)(efx_nic_t *); 419 #endif /* EFSYS_OPT_DIAG */ 420 void (*eno_fini)(efx_nic_t *); 421 void (*eno_unprobe)(efx_nic_t *); 422 } efx_nic_ops_t; 423 424 #ifndef EFX_TXQ_LIMIT_TARGET 425 #define EFX_TXQ_LIMIT_TARGET 259 426 #endif 427 #ifndef EFX_RXQ_LIMIT_TARGET 428 #define EFX_RXQ_LIMIT_TARGET 512 429 #endif 430 431 432 #if EFSYS_OPT_FILTER 433 434 #if EFSYS_OPT_SIENA 435 436 typedef struct siena_filter_spec_s { 437 uint8_t sfs_type; 438 uint32_t sfs_flags; 439 uint32_t sfs_dmaq_id; 440 uint32_t sfs_dword[3]; 441 } siena_filter_spec_t; 442 443 typedef enum siena_filter_type_e { 444 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 445 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 446 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 447 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 448 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 449 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 450 451 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 452 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 453 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 454 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 455 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 456 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 457 458 EFX_SIENA_FILTER_NTYPES 459 } siena_filter_type_t; 460 461 typedef enum siena_filter_tbl_id_e { 462 EFX_SIENA_FILTER_TBL_RX_IP = 0, 463 EFX_SIENA_FILTER_TBL_RX_MAC, 464 EFX_SIENA_FILTER_TBL_TX_IP, 465 EFX_SIENA_FILTER_TBL_TX_MAC, 466 EFX_SIENA_FILTER_NTBLS 467 } siena_filter_tbl_id_t; 468 469 typedef struct siena_filter_tbl_s { 470 int sft_size; /* number of entries */ 471 int sft_used; /* active count */ 472 uint32_t *sft_bitmap; /* active bitmap */ 473 siena_filter_spec_t *sft_spec; /* array of saved specs */ 474 } siena_filter_tbl_t; 475 476 typedef struct siena_filter_s { 477 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 478 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 479 } siena_filter_t; 480 481 #endif /* EFSYS_OPT_SIENA */ 482 483 typedef struct efx_filter_s { 484 #if EFSYS_OPT_SIENA 485 siena_filter_t *ef_siena_filter; 486 #endif /* EFSYS_OPT_SIENA */ 487 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 488 ef10_filter_table_t *ef_ef10_filter_table; 489 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 490 } efx_filter_t; 491 492 #if EFSYS_OPT_SIENA 493 494 LIBEFX_INTERNAL 495 extern void 496 siena_filter_tbl_clear( 497 __in efx_nic_t *enp, 498 __in siena_filter_tbl_id_t tbl); 499 500 #endif /* EFSYS_OPT_SIENA */ 501 502 #endif /* EFSYS_OPT_FILTER */ 503 504 #if EFSYS_OPT_MCDI 505 506 #define EFX_TUNNEL_MAXNENTRIES (16) 507 508 #if EFSYS_OPT_TUNNEL 509 510 /* State of a UDP tunnel table entry */ 511 typedef enum efx_tunnel_udp_entry_state_e { 512 EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */ 513 EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */ 514 EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */ 515 } efx_tunnel_udp_entry_state_t; 516 517 #if EFSYS_OPT_RIVERHEAD 518 typedef uint32_t efx_vnic_encap_rule_handle_t; 519 #endif /* EFSYS_OPT_RIVERHEAD */ 520 521 typedef struct efx_tunnel_udp_entry_s { 522 uint16_t etue_port; /* host/cpu-endian */ 523 uint16_t etue_protocol; 524 boolean_t etue_busy; 525 efx_tunnel_udp_entry_state_t etue_state; 526 #if EFSYS_OPT_RIVERHEAD 527 efx_vnic_encap_rule_handle_t etue_handle; 528 #endif /* EFSYS_OPT_RIVERHEAD */ 529 } efx_tunnel_udp_entry_t; 530 531 typedef struct efx_tunnel_cfg_s { 532 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 533 unsigned int etc_udp_entries_num; 534 } efx_tunnel_cfg_t; 535 536 #endif /* EFSYS_OPT_TUNNEL */ 537 538 typedef struct efx_mcdi_ops_s { 539 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 540 void (*emco_send_request)(efx_nic_t *, void *, size_t, 541 void *, size_t); 542 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 543 boolean_t (*emco_poll_response)(efx_nic_t *); 544 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 545 void (*emco_fini)(efx_nic_t *); 546 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 547 efx_mcdi_feature_id_t, boolean_t *); 548 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 549 uint32_t *); 550 } efx_mcdi_ops_t; 551 552 typedef struct efx_mcdi_s { 553 const efx_mcdi_ops_t *em_emcop; 554 const efx_mcdi_transport_t *em_emtp; 555 efx_mcdi_iface_t em_emip; 556 } efx_mcdi_t; 557 558 #endif /* EFSYS_OPT_MCDI */ 559 560 #if EFSYS_OPT_NVRAM 561 562 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 563 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 564 565 typedef struct efx_nvram_ops_s { 566 #if EFSYS_OPT_DIAG 567 efx_rc_t (*envo_test)(efx_nic_t *); 568 #endif /* EFSYS_OPT_DIAG */ 569 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 570 uint32_t *); 571 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 572 efx_nvram_info_t *); 573 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 574 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 575 unsigned int, caddr_t, size_t); 576 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 577 unsigned int, caddr_t, size_t); 578 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 579 unsigned int, size_t); 580 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 581 unsigned int, caddr_t, size_t); 582 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 583 uint32_t *); 584 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 585 uint32_t *, uint16_t *); 586 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 587 uint16_t *); 588 efx_rc_t (*envo_buffer_validate)(uint32_t, 589 caddr_t, size_t); 590 } efx_nvram_ops_t; 591 #endif /* EFSYS_OPT_NVRAM */ 592 593 #if EFSYS_OPT_VPD 594 typedef struct efx_vpd_ops_s { 595 efx_rc_t (*evpdo_init)(efx_nic_t *); 596 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 597 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 598 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 599 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 600 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 601 efx_vpd_value_t *); 602 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 603 efx_vpd_value_t *); 604 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 605 efx_vpd_value_t *, unsigned int *); 606 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 607 void (*evpdo_fini)(efx_nic_t *); 608 } efx_vpd_ops_t; 609 #endif /* EFSYS_OPT_VPD */ 610 611 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 612 613 LIBEFX_INTERNAL 614 extern __checkReturn efx_rc_t 615 efx_mcdi_nvram_partitions( 616 __in efx_nic_t *enp, 617 __out_bcount(size) caddr_t data, 618 __in size_t size, 619 __out unsigned int *npartnp); 620 621 LIBEFX_INTERNAL 622 extern __checkReturn efx_rc_t 623 efx_mcdi_nvram_metadata( 624 __in efx_nic_t *enp, 625 __in uint32_t partn, 626 __out uint32_t *subtypep, 627 __out_ecount(4) uint16_t version[4], 628 __out_bcount_opt(size) char *descp, 629 __in size_t size); 630 631 LIBEFX_INTERNAL 632 extern __checkReturn efx_rc_t 633 efx_mcdi_nvram_info( 634 __in efx_nic_t *enp, 635 __in uint32_t partn, 636 __out efx_nvram_info_t *eni); 637 638 LIBEFX_INTERNAL 639 extern __checkReturn efx_rc_t 640 efx_mcdi_nvram_update_start( 641 __in efx_nic_t *enp, 642 __in uint32_t partn); 643 644 LIBEFX_INTERNAL 645 extern __checkReturn efx_rc_t 646 efx_mcdi_nvram_read( 647 __in efx_nic_t *enp, 648 __in uint32_t partn, 649 __in uint32_t offset, 650 __out_bcount(size) caddr_t data, 651 __in size_t size, 652 __in uint32_t mode); 653 654 LIBEFX_INTERNAL 655 extern __checkReturn efx_rc_t 656 efx_mcdi_nvram_erase( 657 __in efx_nic_t *enp, 658 __in uint32_t partn, 659 __in uint32_t offset, 660 __in size_t size); 661 662 LIBEFX_INTERNAL 663 extern __checkReturn efx_rc_t 664 efx_mcdi_nvram_write( 665 __in efx_nic_t *enp, 666 __in uint32_t partn, 667 __in uint32_t offset, 668 __in_bcount(size) caddr_t data, 669 __in size_t size); 670 671 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 672 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 673 674 LIBEFX_INTERNAL 675 extern __checkReturn efx_rc_t 676 efx_mcdi_nvram_update_finish( 677 __in efx_nic_t *enp, 678 __in uint32_t partn, 679 __in boolean_t reboot, 680 __in uint32_t flags, 681 __out_opt uint32_t *verify_resultp); 682 683 #if EFSYS_OPT_DIAG 684 685 LIBEFX_INTERNAL 686 extern __checkReturn efx_rc_t 687 efx_mcdi_nvram_test( 688 __in efx_nic_t *enp, 689 __in uint32_t partn); 690 691 #endif /* EFSYS_OPT_DIAG */ 692 693 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 694 695 #if EFSYS_OPT_LICENSING 696 697 typedef struct efx_lic_ops_s { 698 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 699 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 700 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 701 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 702 size_t *, uint8_t *); 703 efx_rc_t (*elo_find_start) 704 (efx_nic_t *, caddr_t, size_t, uint32_t *); 705 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 706 uint32_t, uint32_t *); 707 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 708 uint32_t, uint32_t *, uint32_t *); 709 boolean_t (*elo_validate_key)(efx_nic_t *, 710 caddr_t, uint32_t); 711 efx_rc_t (*elo_read_key)(efx_nic_t *, 712 caddr_t, size_t, uint32_t, uint32_t, 713 caddr_t, size_t, uint32_t *); 714 efx_rc_t (*elo_write_key)(efx_nic_t *, 715 caddr_t, size_t, uint32_t, 716 caddr_t, uint32_t, uint32_t *); 717 efx_rc_t (*elo_delete_key)(efx_nic_t *, 718 caddr_t, size_t, uint32_t, 719 uint32_t, uint32_t, uint32_t *); 720 efx_rc_t (*elo_create_partition)(efx_nic_t *, 721 caddr_t, size_t); 722 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 723 caddr_t, size_t); 724 } efx_lic_ops_t; 725 726 #endif 727 728 #if EFSYS_OPT_EVB 729 730 struct efx_vswitch_s { 731 efx_nic_t *ev_enp; 732 efx_vswitch_id_t ev_vswitch_id; 733 uint32_t ev_num_vports; 734 /* 735 * Vport configuration array: index 0 to store PF configuration 736 * and next ev_num_vports-1 entries hold VFs configuration. 737 */ 738 efx_vport_config_t *ev_evcp; 739 }; 740 741 typedef struct efx_evb_ops_s { 742 efx_rc_t (*eeo_init)(efx_nic_t *); 743 void (*eeo_fini)(efx_nic_t *); 744 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 745 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 746 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 747 efx_vport_type_t, uint16_t, 748 boolean_t, efx_vport_id_t *); 749 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 750 efx_vport_id_t); 751 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 752 efx_vport_id_t, uint8_t *); 753 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 754 efx_vport_id_t, uint8_t *); 755 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 756 efx_vport_id_t); 757 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 758 efx_vport_id_t); 759 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 760 efx_vport_id_t, uint32_t); 761 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 762 efx_vport_id_t, 763 uint16_t *, uint8_t *, 764 boolean_t *); 765 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 766 efx_vport_id_t, efsys_mem_t *); 767 } efx_evb_ops_t; 768 769 LIBEFX_INTERNAL 770 extern __checkReturn boolean_t 771 efx_is_zero_eth_addr( 772 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 773 774 #endif /* EFSYS_OPT_EVB */ 775 776 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 777 778 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 779 780 781 typedef struct efx_proxy_ops_s { 782 efx_rc_t (*epo_init)(efx_nic_t *); 783 void (*epo_fini)(efx_nic_t *); 784 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 785 efsys_mem_t *, efsys_mem_t *, 786 uint32_t, uint32_t *, size_t); 787 efx_rc_t (*epo_disable)(efx_nic_t *); 788 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 789 uint32_t, uint32_t, uint32_t); 790 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 791 uint32_t, uint32_t); 792 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 793 uint32_t, uint32_t); 794 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 795 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 796 uint32_t, uint32_t *); 797 } efx_proxy_ops_t; 798 799 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 800 801 #if EFSYS_OPT_MAE 802 803 typedef struct efx_mae_field_cap_s { 804 uint32_t emfc_support; 805 boolean_t emfc_mask_affects_class; 806 boolean_t emfc_match_affects_class; 807 } efx_mae_field_cap_t; 808 809 typedef struct efx_mae_s { 810 uint32_t em_max_n_action_prios; 811 /* 812 * The number of MAE field IDs recognised by the FW implementation. 813 * Any field ID greater than or equal to this value is unsupported. 814 */ 815 uint32_t em_max_nfields; 816 /** Action rule match field capabilities. */ 817 efx_mae_field_cap_t *em_action_rule_field_caps; 818 size_t em_action_rule_field_caps_size; 819 uint32_t em_max_n_outer_prios; 820 uint32_t em_encap_types_supported; 821 /** Outer rule match field capabilities. */ 822 efx_mae_field_cap_t *em_outer_rule_field_caps; 823 size_t em_outer_rule_field_caps_size; 824 } efx_mae_t; 825 826 #endif /* EFSYS_OPT_MAE */ 827 828 #define EFX_DRV_VER_MAX 20 829 830 typedef struct efx_drv_cfg_s { 831 uint32_t edc_min_vi_count; 832 uint32_t edc_max_vi_count; 833 834 uint32_t edc_max_piobuf_count; 835 uint32_t edc_pio_alloc_size; 836 } efx_drv_cfg_t; 837 838 struct efx_nic_s { 839 uint32_t en_magic; 840 efx_family_t en_family; 841 uint32_t en_features; 842 efsys_identifier_t *en_esip; 843 efsys_lock_t *en_eslp; 844 efsys_bar_t *en_esbp; 845 unsigned int en_mod_flags; 846 unsigned int en_reset_flags; 847 efx_nic_cfg_t en_nic_cfg; 848 efx_drv_cfg_t en_drv_cfg; 849 efx_port_t en_port; 850 efx_mon_t en_mon; 851 efx_intr_t en_intr; 852 uint32_t en_ev_qcount; 853 uint32_t en_rx_qcount; 854 uint32_t en_tx_qcount; 855 const efx_nic_ops_t *en_enop; 856 const efx_ev_ops_t *en_eevop; 857 const efx_tx_ops_t *en_etxop; 858 const efx_rx_ops_t *en_erxop; 859 efx_fw_variant_t efv; 860 char en_drv_version[EFX_DRV_VER_MAX]; 861 #if EFSYS_OPT_FILTER 862 efx_filter_t en_filter; 863 const efx_filter_ops_t *en_efop; 864 #endif /* EFSYS_OPT_FILTER */ 865 #if EFSYS_OPT_TUNNEL 866 efx_tunnel_cfg_t en_tunnel_cfg; 867 const efx_tunnel_ops_t *en_etop; 868 #endif /* EFSYS_OPT_TUNNEL */ 869 #if EFSYS_OPT_MCDI 870 efx_mcdi_t en_mcdi; 871 #endif /* EFSYS_OPT_MCDI */ 872 #if EFSYS_OPT_NVRAM 873 uint32_t en_nvram_partn_locked; 874 const efx_nvram_ops_t *en_envop; 875 #endif /* EFSYS_OPT_NVRAM */ 876 #if EFSYS_OPT_VPD 877 const efx_vpd_ops_t *en_evpdop; 878 #endif /* EFSYS_OPT_VPD */ 879 #if EFSYS_OPT_VIRTIO 880 const efx_virtio_ops_t *en_evop; 881 #endif /* EFSYS_OPT_VPD */ 882 #if EFSYS_OPT_RX_SCALE 883 efx_rx_hash_support_t en_hash_support; 884 efx_rx_scale_context_type_t en_rss_context_type; 885 uint32_t en_rss_context; 886 #endif /* EFSYS_OPT_RX_SCALE */ 887 uint32_t en_vport_id; 888 #if EFSYS_OPT_LICENSING 889 const efx_lic_ops_t *en_elop; 890 boolean_t en_licensing_supported; 891 #endif 892 union { 893 #if EFSYS_OPT_SIENA 894 struct { 895 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 896 unsigned int enu_partn_mask; 897 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 898 #if EFSYS_OPT_VPD 899 caddr_t enu_svpd; 900 size_t enu_svpd_length; 901 #endif /* EFSYS_OPT_VPD */ 902 int enu_unused; 903 } siena; 904 #endif /* EFSYS_OPT_SIENA */ 905 int enu_unused; 906 } en_u; 907 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 908 union en_arch { 909 struct { 910 int ena_vi_base; 911 int ena_vi_count; 912 int ena_vi_shift; 913 uint32_t ena_fcw_base; 914 #if EFSYS_OPT_VPD 915 caddr_t ena_svpd; 916 size_t ena_svpd_length; 917 #endif /* EFSYS_OPT_VPD */ 918 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 919 uint32_t ena_piobuf_count; 920 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 921 uint32_t ena_pio_write_vi_base; 922 /* Memory BAR mapping regions */ 923 uint32_t ena_uc_mem_map_offset; 924 size_t ena_uc_mem_map_size; 925 uint32_t ena_wc_mem_map_offset; 926 size_t ena_wc_mem_map_size; 927 } ef10; 928 } en_arch; 929 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 930 #if EFSYS_OPT_EVB 931 const efx_evb_ops_t *en_eeop; 932 struct efx_vswitch_s *en_vswitchp; 933 #endif /* EFSYS_OPT_EVB */ 934 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 935 const efx_proxy_ops_t *en_epop; 936 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 937 #if EFSYS_OPT_MAE 938 efx_mae_t *en_maep; 939 #endif /* EFSYS_OPT_MAE */ 940 }; 941 942 #define EFX_FAMILY_IS_EF10(_enp) \ 943 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 944 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 945 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 946 947 #define EFX_FAMILY_IS_EF100(_enp) \ 948 ((_enp)->en_family == EFX_FAMILY_RIVERHEAD) 949 950 951 #define EFX_NIC_MAGIC 0x02121996 952 953 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 954 const efx_ev_callbacks_t *, void *); 955 956 #if EFSYS_OPT_EV_EXTENDED_WIDTH 957 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *, 958 const efx_ev_callbacks_t *, void *); 959 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */ 960 961 typedef struct efx_evq_rxq_state_s { 962 unsigned int eers_rx_read_ptr; 963 unsigned int eers_rx_mask; 964 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 965 unsigned int eers_rx_stream_npackets; 966 boolean_t eers_rx_packed_stream; 967 #endif 968 #if EFSYS_OPT_RX_PACKED_STREAM 969 unsigned int eers_rx_packed_stream_credits; 970 #endif 971 } efx_evq_rxq_state_t; 972 973 struct efx_evq_s { 974 uint32_t ee_magic; 975 uint32_t ee_flags; 976 efx_nic_t *ee_enp; 977 unsigned int ee_index; 978 unsigned int ee_mask; 979 efsys_mem_t *ee_esmp; 980 #if EFSYS_OPT_QSTATS 981 uint32_t ee_stat[EV_NQSTATS]; 982 #endif /* EFSYS_OPT_QSTATS */ 983 984 efx_ev_handler_t ee_rx; 985 efx_ev_handler_t ee_tx; 986 efx_ev_handler_t ee_driver; 987 efx_ev_handler_t ee_global; 988 efx_ev_handler_t ee_drv_gen; 989 #if EFSYS_OPT_MCDI 990 efx_ev_handler_t ee_mcdi; 991 #endif /* EFSYS_OPT_MCDI */ 992 993 #if EFSYS_OPT_DESC_PROXY 994 efx_ev_ew_handler_t ee_ew_txq_desc; 995 efx_ev_ew_handler_t ee_ew_virtq_desc; 996 #endif /* EFSYS_OPT_DESC_PROXY */ 997 998 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 999 }; 1000 1001 #define EFX_EVQ_MAGIC 0x08081997 1002 1003 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 1004 1005 #if EFSYS_OPT_QSTATS 1006 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 1007 do { \ 1008 (_eep)->ee_stat[_stat]++; \ 1009 _NOTE(CONSTANTCONDITION) \ 1010 } while (B_FALSE) 1011 #else 1012 #define EFX_EV_QSTAT_INCR(_eep, _stat) 1013 #endif 1014 1015 struct efx_rxq_s { 1016 uint32_t er_magic; 1017 efx_nic_t *er_enp; 1018 efx_evq_t *er_eep; 1019 unsigned int er_index; 1020 unsigned int er_label; 1021 unsigned int er_mask; 1022 size_t er_buf_size; 1023 efsys_mem_t *er_esmp; 1024 efx_evq_rxq_state_t *er_ev_qstate; 1025 efx_rx_prefix_layout_t er_prefix_layout; 1026 }; 1027 1028 #define EFX_RXQ_MAGIC 0x15022005 1029 1030 struct efx_txq_s { 1031 uint32_t et_magic; 1032 efx_nic_t *et_enp; 1033 unsigned int et_index; 1034 unsigned int et_mask; 1035 efsys_mem_t *et_esmp; 1036 #if EFSYS_OPT_HUNTINGTON 1037 uint32_t et_pio_bufnum; 1038 uint32_t et_pio_blknum; 1039 uint32_t et_pio_write_offset; 1040 uint32_t et_pio_offset; 1041 size_t et_pio_size; 1042 #endif 1043 #if EFSYS_OPT_QSTATS 1044 uint32_t et_stat[TX_NQSTATS]; 1045 #endif /* EFSYS_OPT_QSTATS */ 1046 }; 1047 1048 #define EFX_TXQ_MAGIC 0x05092005 1049 1050 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 1051 do { \ 1052 (_dst)[0] = (_src)[0]; \ 1053 (_dst)[1] = (_src)[1]; \ 1054 (_dst)[2] = (_src)[2]; \ 1055 (_dst)[3] = (_src)[3]; \ 1056 (_dst)[4] = (_src)[4]; \ 1057 (_dst)[5] = (_src)[5]; \ 1058 _NOTE(CONSTANTCONDITION) \ 1059 } while (B_FALSE) 1060 1061 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 1062 do { \ 1063 uint16_t *_d = (uint16_t *)(_dst); \ 1064 _d[0] = 0xffff; \ 1065 _d[1] = 0xffff; \ 1066 _d[2] = 0xffff; \ 1067 _NOTE(CONSTANTCONDITION) \ 1068 } while (B_FALSE) 1069 1070 #if EFSYS_OPT_CHECK_REG 1071 #define EFX_CHECK_REG(_enp, _reg) \ 1072 do { \ 1073 const char *name = #_reg; \ 1074 char min = name[4]; \ 1075 char max = name[5]; \ 1076 char rev; \ 1077 \ 1078 switch ((_enp)->en_family) { \ 1079 case EFX_FAMILY_SIENA: \ 1080 rev = 'C'; \ 1081 break; \ 1082 \ 1083 case EFX_FAMILY_HUNTINGTON: \ 1084 rev = 'D'; \ 1085 break; \ 1086 \ 1087 case EFX_FAMILY_MEDFORD: \ 1088 rev = 'E'; \ 1089 break; \ 1090 \ 1091 case EFX_FAMILY_MEDFORD2: \ 1092 rev = 'F'; \ 1093 break; \ 1094 \ 1095 case EFX_FAMILY_RIVERHEAD: \ 1096 rev = 'G'; \ 1097 break; \ 1098 \ 1099 default: \ 1100 rev = '?'; \ 1101 break; \ 1102 } \ 1103 \ 1104 EFSYS_ASSERT3S(rev, >=, min); \ 1105 EFSYS_ASSERT3S(rev, <=, max); \ 1106 \ 1107 _NOTE(CONSTANTCONDITION) \ 1108 } while (B_FALSE) 1109 #else 1110 #define EFX_CHECK_REG(_enp, _reg) do { \ 1111 _NOTE(CONSTANTCONDITION) \ 1112 } while (B_FALSE) 1113 #endif 1114 1115 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1116 do { \ 1117 EFX_CHECK_REG((_enp), (_reg)); \ 1118 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1119 (_edp), (_lock)); \ 1120 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1121 uint32_t, _reg ## _OFST, \ 1122 uint32_t, (_edp)->ed_u32[0]); \ 1123 _NOTE(CONSTANTCONDITION) \ 1124 } while (B_FALSE) 1125 1126 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1127 do { \ 1128 EFX_CHECK_REG((_enp), (_reg)); \ 1129 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1130 uint32_t, _reg ## _OFST, \ 1131 uint32_t, (_edp)->ed_u32[0]); \ 1132 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1133 (_edp), (_lock)); \ 1134 _NOTE(CONSTANTCONDITION) \ 1135 } while (B_FALSE) 1136 1137 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1138 do { \ 1139 EFX_CHECK_REG((_enp), (_reg)); \ 1140 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1141 (_eqp)); \ 1142 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1143 uint32_t, _reg ## _OFST, \ 1144 uint32_t, (_eqp)->eq_u32[1], \ 1145 uint32_t, (_eqp)->eq_u32[0]); \ 1146 _NOTE(CONSTANTCONDITION) \ 1147 } while (B_FALSE) 1148 1149 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1150 do { \ 1151 EFX_CHECK_REG((_enp), (_reg)); \ 1152 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1153 uint32_t, _reg ## _OFST, \ 1154 uint32_t, (_eqp)->eq_u32[1], \ 1155 uint32_t, (_eqp)->eq_u32[0]); \ 1156 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1157 (_eqp)); \ 1158 _NOTE(CONSTANTCONDITION) \ 1159 } while (B_FALSE) 1160 1161 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1162 do { \ 1163 EFX_CHECK_REG((_enp), (_reg)); \ 1164 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1165 (_eop), B_TRUE); \ 1166 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1167 uint32_t, _reg ## _OFST, \ 1168 uint32_t, (_eop)->eo_u32[3], \ 1169 uint32_t, (_eop)->eo_u32[2], \ 1170 uint32_t, (_eop)->eo_u32[1], \ 1171 uint32_t, (_eop)->eo_u32[0]); \ 1172 _NOTE(CONSTANTCONDITION) \ 1173 } while (B_FALSE) 1174 1175 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1176 do { \ 1177 EFX_CHECK_REG((_enp), (_reg)); \ 1178 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1179 uint32_t, _reg ## _OFST, \ 1180 uint32_t, (_eop)->eo_u32[3], \ 1181 uint32_t, (_eop)->eo_u32[2], \ 1182 uint32_t, (_eop)->eo_u32[1], \ 1183 uint32_t, (_eop)->eo_u32[0]); \ 1184 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1185 (_eop), B_TRUE); \ 1186 _NOTE(CONSTANTCONDITION) \ 1187 } while (B_FALSE) 1188 1189 /* 1190 * Accessors for memory BAR non-VI tables. 1191 * 1192 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1193 * to ensure the correct runtime VI window size is used on Medford2. 1194 * 1195 * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control 1196 * window registers, to ensure the correct starting offset is used. 1197 * 1198 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1199 */ 1200 1201 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1202 do { \ 1203 EFX_CHECK_REG((_enp), (_reg)); \ 1204 EFSYS_BAR_READD((_enp)->en_esbp, \ 1205 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1206 (_edp), (_lock)); \ 1207 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1208 uint32_t, (_index), \ 1209 uint32_t, _reg ## _OFST, \ 1210 uint32_t, (_edp)->ed_u32[0]); \ 1211 _NOTE(CONSTANTCONDITION) \ 1212 } while (B_FALSE) 1213 1214 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1215 do { \ 1216 EFX_CHECK_REG((_enp), (_reg)); \ 1217 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1218 uint32_t, (_index), \ 1219 uint32_t, _reg ## _OFST, \ 1220 uint32_t, (_edp)->ed_u32[0]); \ 1221 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1222 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1223 (_edp), (_lock)); \ 1224 _NOTE(CONSTANTCONDITION) \ 1225 } while (B_FALSE) 1226 1227 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1228 do { \ 1229 EFX_CHECK_REG((_enp), (_reg)); \ 1230 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1231 uint32_t, (_index), \ 1232 uint32_t, _reg ## _OFST, \ 1233 uint32_t, (_edp)->ed_u32[0]); \ 1234 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1235 (_reg ## _OFST + \ 1236 (3 * sizeof (efx_dword_t)) + \ 1237 ((_index) * _reg ## _STEP)), \ 1238 (_edp), (_lock)); \ 1239 _NOTE(CONSTANTCONDITION) \ 1240 } while (B_FALSE) 1241 1242 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1243 do { \ 1244 EFX_CHECK_REG((_enp), (_reg)); \ 1245 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1246 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1247 (_eqp)); \ 1248 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1249 uint32_t, (_index), \ 1250 uint32_t, _reg ## _OFST, \ 1251 uint32_t, (_eqp)->eq_u32[1], \ 1252 uint32_t, (_eqp)->eq_u32[0]); \ 1253 _NOTE(CONSTANTCONDITION) \ 1254 } while (B_FALSE) 1255 1256 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1257 do { \ 1258 EFX_CHECK_REG((_enp), (_reg)); \ 1259 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1260 uint32_t, (_index), \ 1261 uint32_t, _reg ## _OFST, \ 1262 uint32_t, (_eqp)->eq_u32[1], \ 1263 uint32_t, (_eqp)->eq_u32[0]); \ 1264 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1265 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1266 (_eqp)); \ 1267 _NOTE(CONSTANTCONDITION) \ 1268 } while (B_FALSE) 1269 1270 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1271 do { \ 1272 EFX_CHECK_REG((_enp), (_reg)); \ 1273 EFSYS_BAR_READO((_enp)->en_esbp, \ 1274 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1275 (_eop), (_lock)); \ 1276 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1277 uint32_t, (_index), \ 1278 uint32_t, _reg ## _OFST, \ 1279 uint32_t, (_eop)->eo_u32[3], \ 1280 uint32_t, (_eop)->eo_u32[2], \ 1281 uint32_t, (_eop)->eo_u32[1], \ 1282 uint32_t, (_eop)->eo_u32[0]); \ 1283 _NOTE(CONSTANTCONDITION) \ 1284 } while (B_FALSE) 1285 1286 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1287 do { \ 1288 EFX_CHECK_REG((_enp), (_reg)); \ 1289 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1290 uint32_t, (_index), \ 1291 uint32_t, _reg ## _OFST, \ 1292 uint32_t, (_eop)->eo_u32[3], \ 1293 uint32_t, (_eop)->eo_u32[2], \ 1294 uint32_t, (_eop)->eo_u32[1], \ 1295 uint32_t, (_eop)->eo_u32[0]); \ 1296 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1297 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1298 (_eop), (_lock)); \ 1299 _NOTE(CONSTANTCONDITION) \ 1300 } while (B_FALSE) 1301 1302 /* 1303 * Accessors for memory BAR function control window registers. 1304 * 1305 * The function control window is located at an offset which can be 1306 * non-zero in case of Riverhead. 1307 */ 1308 1309 #if EFSYS_OPT_RIVERHEAD 1310 1311 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ 1312 do { \ 1313 EFX_CHECK_REG((_enp), (_reg)); \ 1314 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \ 1315 (_enp)->en_arch.ef10.ena_fcw_base, \ 1316 (_edp), B_FALSE); \ 1317 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \ 1318 uint32_t, _reg ## _OFST, \ 1319 uint32_t, (_edp)->ed_u32[0]); \ 1320 _NOTE(CONSTANTCONDITION) \ 1321 } while (B_FALSE) 1322 1323 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \ 1324 do { \ 1325 EFX_CHECK_REG((_enp), (_reg)); \ 1326 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \ 1327 uint32_t, _reg ## _OFST, \ 1328 uint32_t, (_edp)->ed_u32[0]); \ 1329 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \ 1330 (_enp)->en_arch.ef10.ena_fcw_base, \ 1331 (_edp), B_FALSE); \ 1332 _NOTE(CONSTANTCONDITION) \ 1333 } while (B_FALSE) 1334 1335 #endif /* EFSYS_OPT_RIVERHEAD */ 1336 1337 /* 1338 * Accessors for memory BAR per-VI registers. 1339 * 1340 * The VI window size is 8KB for Medford and all earlier controllers. 1341 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1342 */ 1343 1344 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1345 do { \ 1346 EFX_CHECK_REG((_enp), (_reg)); \ 1347 EFSYS_BAR_READD((_enp)->en_esbp, \ 1348 ((_reg ## _OFST) + \ 1349 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1350 (_edp), (_lock)); \ 1351 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1352 uint32_t, (_index), \ 1353 uint32_t, _reg ## _OFST, \ 1354 uint32_t, (_edp)->ed_u32[0]); \ 1355 _NOTE(CONSTANTCONDITION) \ 1356 } while (B_FALSE) 1357 1358 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1359 do { \ 1360 EFX_CHECK_REG((_enp), (_reg)); \ 1361 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1362 uint32_t, (_index), \ 1363 uint32_t, _reg ## _OFST, \ 1364 uint32_t, (_edp)->ed_u32[0]); \ 1365 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1366 ((_reg ## _OFST) + \ 1367 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1368 (_edp), (_lock)); \ 1369 _NOTE(CONSTANTCONDITION) \ 1370 } while (B_FALSE) 1371 1372 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1373 do { \ 1374 EFX_CHECK_REG((_enp), (_reg)); \ 1375 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1376 uint32_t, (_index), \ 1377 uint32_t, _reg ## _OFST, \ 1378 uint32_t, (_edp)->ed_u32[0]); \ 1379 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1380 ((_reg ## _OFST) + \ 1381 (2 * sizeof (efx_dword_t)) + \ 1382 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1383 (_edp), (_lock)); \ 1384 _NOTE(CONSTANTCONDITION) \ 1385 } while (B_FALSE) 1386 1387 /* 1388 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1389 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1390 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1391 * the need for locking in the host, and are the only ones known to be safe to 1392 * use 128-bites write with. 1393 */ 1394 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1395 do { \ 1396 EFX_CHECK_REG((_enp), (_reg)); \ 1397 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1398 const char *, #_reg, \ 1399 uint32_t, (_index), \ 1400 uint32_t, _reg ## _OFST, \ 1401 uint32_t, (_eop)->eo_u32[3], \ 1402 uint32_t, (_eop)->eo_u32[2], \ 1403 uint32_t, (_eop)->eo_u32[1], \ 1404 uint32_t, (_eop)->eo_u32[0]); \ 1405 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1406 (_reg ## _OFST + \ 1407 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1408 (_eop)); \ 1409 _NOTE(CONSTANTCONDITION) \ 1410 } while (B_FALSE) 1411 1412 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ 1413 _wptr, _owptr) \ 1414 do { \ 1415 unsigned int _new = (_wptr); \ 1416 unsigned int _old = (_owptr); \ 1417 \ 1418 if ((_new) >= (_old)) \ 1419 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1420 (_old) * (_desc_size), \ 1421 ((_new) - (_old)) * (_desc_size)); \ 1422 else \ 1423 /* \ 1424 * It is cheaper to sync entire map than sync \ 1425 * two parts especially when offset/size are \ 1426 * ignored and entire map is synced in any case.\ 1427 */ \ 1428 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1429 0, \ 1430 (_entries) * (_desc_size)); \ 1431 _NOTE(CONSTANTCONDITION) \ 1432 } while (B_FALSE) 1433 1434 LIBEFX_INTERNAL 1435 extern __checkReturn efx_rc_t 1436 efx_mac_select( 1437 __in efx_nic_t *enp); 1438 1439 LIBEFX_INTERNAL 1440 extern void 1441 efx_mac_multicast_hash_compute( 1442 __in_ecount(6*count) uint8_t const *addrs, 1443 __in int count, 1444 __out efx_oword_t *hash_low, 1445 __out efx_oword_t *hash_high); 1446 1447 LIBEFX_INTERNAL 1448 extern __checkReturn efx_rc_t 1449 efx_phy_probe( 1450 __in efx_nic_t *enp); 1451 1452 LIBEFX_INTERNAL 1453 extern void 1454 efx_phy_unprobe( 1455 __in efx_nic_t *enp); 1456 1457 #if EFSYS_OPT_VPD 1458 1459 /* VPD utility functions */ 1460 1461 LIBEFX_INTERNAL 1462 extern __checkReturn efx_rc_t 1463 efx_vpd_hunk_length( 1464 __in_bcount(size) caddr_t data, 1465 __in size_t size, 1466 __out size_t *lengthp); 1467 1468 LIBEFX_INTERNAL 1469 extern __checkReturn efx_rc_t 1470 efx_vpd_hunk_verify( 1471 __in_bcount(size) caddr_t data, 1472 __in size_t size, 1473 __out_opt boolean_t *cksummedp); 1474 1475 LIBEFX_INTERNAL 1476 extern __checkReturn efx_rc_t 1477 efx_vpd_hunk_reinit( 1478 __in_bcount(size) caddr_t data, 1479 __in size_t size, 1480 __in boolean_t wantpid); 1481 1482 LIBEFX_INTERNAL 1483 extern __checkReturn efx_rc_t 1484 efx_vpd_hunk_get( 1485 __in_bcount(size) caddr_t data, 1486 __in size_t size, 1487 __in efx_vpd_tag_t tag, 1488 __in efx_vpd_keyword_t keyword, 1489 __out unsigned int *payloadp, 1490 __out uint8_t *paylenp); 1491 1492 LIBEFX_INTERNAL 1493 extern __checkReturn efx_rc_t 1494 efx_vpd_hunk_next( 1495 __in_bcount(size) caddr_t data, 1496 __in size_t size, 1497 __out efx_vpd_tag_t *tagp, 1498 __out efx_vpd_keyword_t *keyword, 1499 __out_opt unsigned int *payloadp, 1500 __out_opt uint8_t *paylenp, 1501 __inout unsigned int *contp); 1502 1503 LIBEFX_INTERNAL 1504 extern __checkReturn efx_rc_t 1505 efx_vpd_hunk_set( 1506 __in_bcount(size) caddr_t data, 1507 __in size_t size, 1508 __in efx_vpd_value_t *evvp); 1509 1510 #endif /* EFSYS_OPT_VPD */ 1511 1512 #if EFSYS_OPT_MCDI 1513 1514 LIBEFX_INTERNAL 1515 extern __checkReturn efx_rc_t 1516 efx_mcdi_set_workaround( 1517 __in efx_nic_t *enp, 1518 __in uint32_t type, 1519 __in boolean_t enabled, 1520 __out_opt uint32_t *flagsp); 1521 1522 LIBEFX_INTERNAL 1523 extern __checkReturn efx_rc_t 1524 efx_mcdi_get_workarounds( 1525 __in efx_nic_t *enp, 1526 __out_opt uint32_t *implementedp, 1527 __out_opt uint32_t *enabledp); 1528 1529 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1530 1531 LIBEFX_INTERNAL 1532 extern __checkReturn efx_rc_t 1533 efx_mcdi_init_evq( 1534 __in efx_nic_t *enp, 1535 __in unsigned int instance, 1536 __in efsys_mem_t *esmp, 1537 __in size_t nevs, 1538 __in uint32_t irq, 1539 __in uint32_t target_evq, 1540 __in uint32_t us, 1541 __in uint32_t flags, 1542 __in boolean_t low_latency); 1543 1544 LIBEFX_INTERNAL 1545 extern __checkReturn efx_rc_t 1546 efx_mcdi_fini_evq( 1547 __in efx_nic_t *enp, 1548 __in uint32_t instance); 1549 1550 typedef struct efx_mcdi_init_rxq_params_s { 1551 boolean_t disable_scatter; 1552 boolean_t want_inner_classes; 1553 uint32_t buf_size; 1554 uint32_t ps_buf_size; 1555 uint32_t es_bufs_per_desc; 1556 uint32_t es_max_dma_len; 1557 uint32_t es_buf_stride; 1558 uint32_t hol_block_timeout; 1559 uint32_t prefix_id; 1560 } efx_mcdi_init_rxq_params_t; 1561 1562 LIBEFX_INTERNAL 1563 extern __checkReturn efx_rc_t 1564 efx_mcdi_init_rxq( 1565 __in efx_nic_t *enp, 1566 __in uint32_t ndescs, 1567 __in efx_evq_t *eep, 1568 __in uint32_t label, 1569 __in uint32_t instance, 1570 __in efsys_mem_t *esmp, 1571 __in const efx_mcdi_init_rxq_params_t *params); 1572 1573 LIBEFX_INTERNAL 1574 extern __checkReturn efx_rc_t 1575 efx_mcdi_fini_rxq( 1576 __in efx_nic_t *enp, 1577 __in uint32_t instance); 1578 1579 LIBEFX_INTERNAL 1580 extern __checkReturn efx_rc_t 1581 efx_mcdi_init_txq( 1582 __in efx_nic_t *enp, 1583 __in uint32_t ndescs, 1584 __in uint32_t target_evq, 1585 __in uint32_t label, 1586 __in uint32_t instance, 1587 __in uint16_t flags, 1588 __in efsys_mem_t *esmp); 1589 1590 LIBEFX_INTERNAL 1591 extern __checkReturn efx_rc_t 1592 efx_mcdi_fini_txq( 1593 __in efx_nic_t *enp, 1594 __in uint32_t instance); 1595 1596 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1597 1598 #endif /* EFSYS_OPT_MCDI */ 1599 1600 #if EFSYS_OPT_MAC_STATS 1601 1602 /* 1603 * Closed range of stats (i.e. the first and the last are included). 1604 * The last must be greater or equal (if the range is one item only) to 1605 * the first. 1606 */ 1607 struct efx_mac_stats_range { 1608 efx_mac_stat_t first; 1609 efx_mac_stat_t last; 1610 }; 1611 1612 typedef enum efx_stats_action_e { 1613 EFX_STATS_CLEAR, 1614 EFX_STATS_UPLOAD, 1615 EFX_STATS_ENABLE_NOEVENTS, 1616 EFX_STATS_ENABLE_EVENTS, 1617 EFX_STATS_DISABLE, 1618 } efx_stats_action_t; 1619 1620 LIBEFX_INTERNAL 1621 extern efx_rc_t 1622 efx_mac_stats_mask_add_ranges( 1623 __inout_bcount(mask_size) uint32_t *maskp, 1624 __in size_t mask_size, 1625 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1626 __in unsigned int rng_count); 1627 1628 LIBEFX_INTERNAL 1629 extern __checkReturn efx_rc_t 1630 efx_mcdi_mac_stats( 1631 __in efx_nic_t *enp, 1632 __in uint32_t vport_id, 1633 __in_opt efsys_mem_t *esmp, 1634 __in efx_stats_action_t action, 1635 __in uint16_t period_ms); 1636 1637 #endif /* EFSYS_OPT_MAC_STATS */ 1638 1639 #if EFSYS_OPT_PCI 1640 1641 /* 1642 * Find the next extended capability in a PCI device's config space 1643 * with specified capability id. 1644 * Passing 0 offset makes the function search from the start. 1645 * If search succeeds, found capability is in modified offset. 1646 * 1647 * Returns ENOENT if a capability is not found. 1648 */ 1649 LIBEFX_INTERNAL 1650 extern __checkReturn efx_rc_t 1651 efx_pci_config_find_next_ext_cap( 1652 __in efsys_pci_config_t *espcp, 1653 __in const efx_pci_ops_t *epop, 1654 __in uint16_t cap_id, 1655 __inout size_t *offsetp); 1656 1657 /* 1658 * Get the next extended capability in a PCI device's config space. 1659 * Passing 0 offset makes the function get the first capability. 1660 * If search succeeds, the capability is in modified offset. 1661 * 1662 * Returns ENOENT if there is no next capability. 1663 */ 1664 LIBEFX_INTERNAL 1665 extern __checkReturn efx_rc_t 1666 efx_pci_config_next_ext_cap( 1667 __in efsys_pci_config_t *espcp, 1668 __in const efx_pci_ops_t *epop, 1669 __inout size_t *offsetp); 1670 1671 /* 1672 * Find the next Xilinx capabilities table location by searching 1673 * PCI extended capabilities. 1674 * 1675 * Returns ENOENT if a table location is not found. 1676 */ 1677 LIBEFX_INTERNAL 1678 extern __checkReturn efx_rc_t 1679 efx_pci_find_next_xilinx_cap_table( 1680 __in efsys_pci_config_t *espcp, 1681 __in const efx_pci_ops_t *epop, 1682 __inout size_t *pci_cap_offsetp, 1683 __out unsigned int *xilinx_tbl_barp, 1684 __out efsys_dma_addr_t *xilinx_tbl_offsetp); 1685 1686 /* 1687 * Read a Xilinx extended PCI capability that gives the location 1688 * of a Xilinx capabilities table. 1689 * 1690 * Returns ENOENT if the extended PCI capability does not contain 1691 * Xilinx capabilities table locator. 1692 */ 1693 LIBEFX_INTERNAL 1694 extern __checkReturn efx_rc_t 1695 efx_pci_read_ext_cap_xilinx_table( 1696 __in efsys_pci_config_t *espcp, 1697 __in const efx_pci_ops_t *epop, 1698 __in size_t cap_offset, 1699 __out unsigned int *barp, 1700 __out efsys_dma_addr_t *offsetp); 1701 1702 /* 1703 * Find a capability with specified format_id in a Xilinx capabilities table. 1704 * Searching is started from provided offset, taking skip_first into account. 1705 * If search succeeds, found capability is in modified offset. 1706 * 1707 * Returns ENOENT if an entry with specified format id is not found. 1708 */ 1709 LIBEFX_INTERNAL 1710 extern __checkReturn efx_rc_t 1711 efx_pci_xilinx_cap_tbl_find( 1712 __in efsys_bar_t *esbp, 1713 __in uint32_t format_id, 1714 __in boolean_t skip_first, 1715 __inout efsys_dma_addr_t *entry_offsetp); 1716 1717 #endif /* EFSYS_OPT_PCI */ 1718 1719 #if EFSYS_OPT_MAE 1720 1721 struct efx_mae_match_spec_s { 1722 efx_mae_rule_type_t emms_type; 1723 uint32_t emms_prio; 1724 union emms_mask_value_pairs { 1725 uint8_t action[ 1726 MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN]; 1727 uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN]; 1728 } emms_mask_value_pairs; 1729 }; 1730 1731 typedef enum efx_mae_action_e { 1732 /* These actions are strictly ordered. */ 1733 EFX_MAE_ACTION_DECAP, 1734 EFX_MAE_ACTION_VLAN_POP, 1735 EFX_MAE_ACTION_VLAN_PUSH, 1736 EFX_MAE_ACTION_ENCAP, 1737 1738 /* 1739 * These actions are not strictly ordered and can 1740 * be passed by a client in any order (before DELIVER). 1741 * However, these enumerants must be kept compactly 1742 * in the end of the enumeration (before DELIVER). 1743 */ 1744 EFX_MAE_ACTION_FLAG, 1745 EFX_MAE_ACTION_MARK, 1746 1747 /* DELIVER is always the last action. */ 1748 EFX_MAE_ACTION_DELIVER, 1749 1750 EFX_MAE_NACTIONS 1751 } efx_mae_action_t; 1752 1753 /* MAE VLAN_POP action can handle 1 or 2 tags. */ 1754 #define EFX_MAE_VLAN_POP_MAX_NTAGS (2) 1755 1756 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */ 1757 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS (2) 1758 1759 typedef struct efx_mae_action_vlan_push_s { 1760 uint16_t emavp_tpid_be; 1761 uint16_t emavp_tci_be; 1762 } efx_mae_action_vlan_push_t; 1763 1764 typedef struct efx_mae_actions_rsrc_s { 1765 efx_mae_eh_id_t emar_eh_id; 1766 } efx_mae_actions_rsrc_t; 1767 1768 struct efx_mae_actions_s { 1769 /* Bitmap of actions in spec, indexed by action type */ 1770 uint32_t ema_actions; 1771 1772 unsigned int ema_n_vlan_tags_to_pop; 1773 unsigned int ema_n_vlan_tags_to_push; 1774 efx_mae_action_vlan_push_t ema_vlan_push_descs[ 1775 EFX_MAE_VLAN_PUSH_MAX_NTAGS]; 1776 uint32_t ema_mark_value; 1777 efx_mport_sel_t ema_deliver_mport; 1778 1779 /* 1780 * Always keep this at the end of the struct since 1781 * efx_mae_action_set_specs_equal() relies on that 1782 * to make sure that resource IDs are not compared. 1783 */ 1784 efx_mae_actions_rsrc_t ema_rsrc; 1785 }; 1786 1787 #endif /* EFSYS_OPT_MAE */ 1788 1789 #if EFSYS_OPT_VIRTIO 1790 1791 #define EFX_VQ_MAGIC 0x026011950 1792 1793 typedef enum efx_virtio_vq_state_e { 1794 EFX_VIRTIO_VQ_STATE_UNKNOWN = 0, 1795 EFX_VIRTIO_VQ_STATE_INITIALIZED, 1796 EFX_VIRTIO_VQ_STATE_STARTED, 1797 EFX_VIRTIO_VQ_NSTATES 1798 } efx_virtio_vq_state_t; 1799 1800 struct efx_virtio_vq_s { 1801 uint32_t evv_magic; 1802 efx_nic_t *evv_enp; 1803 efx_virtio_vq_state_t evv_state; 1804 uint32_t evv_vi_index; 1805 efx_virtio_vq_type_t evv_type; 1806 uint16_t evv_target_vf; 1807 }; 1808 1809 #endif /* EFSYS_OPT_VIRTIO */ 1810 1811 #ifdef __cplusplus 1812 } 1813 #endif 1814 1815 #endif /* _SYS_EFX_IMPL_H */ 1816