1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #if EFSYS_OPT_MCDI 14 #include "efx_mcdi.h" 15 #endif /* EFSYS_OPT_MCDI */ 16 17 /* FIXME: Add definition for driver generated software events */ 18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 20 #endif 21 22 23 #if EFSYS_OPT_SIENA 24 #include "siena_impl.h" 25 #endif /* EFSYS_OPT_SIENA */ 26 27 #if EFSYS_OPT_HUNTINGTON 28 #include "hunt_impl.h" 29 #endif /* EFSYS_OPT_HUNTINGTON */ 30 31 #if EFSYS_OPT_MEDFORD 32 #include "medford_impl.h" 33 #endif /* EFSYS_OPT_MEDFORD */ 34 35 #if EFSYS_OPT_MEDFORD2 36 #include "medford2_impl.h" 37 #endif /* EFSYS_OPT_MEDFORD2 */ 38 39 #if EFX_OPTS_EF10() 40 #include "ef10_impl.h" 41 #endif /* EFX_OPTS_EF10() */ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #define EFX_MOD_MCDI 0x00000001 48 #define EFX_MOD_PROBE 0x00000002 49 #define EFX_MOD_NVRAM 0x00000004 50 #define EFX_MOD_VPD 0x00000008 51 #define EFX_MOD_NIC 0x00000010 52 #define EFX_MOD_INTR 0x00000020 53 #define EFX_MOD_EV 0x00000040 54 #define EFX_MOD_RX 0x00000080 55 #define EFX_MOD_TX 0x00000100 56 #define EFX_MOD_PORT 0x00000200 57 #define EFX_MOD_MON 0x00000400 58 #define EFX_MOD_FILTER 0x00001000 59 #define EFX_MOD_LIC 0x00002000 60 #define EFX_MOD_TUNNEL 0x00004000 61 #define EFX_MOD_EVB 0x00008000 62 #define EFX_MOD_PROXY 0x00010000 63 64 #define EFX_RESET_PHY 0x00000001 65 #define EFX_RESET_RXQ_ERR 0x00000002 66 #define EFX_RESET_TXQ_ERR 0x00000004 67 #define EFX_RESET_HW_UNAVAIL 0x00000008 68 69 typedef enum efx_mac_type_e { 70 EFX_MAC_INVALID = 0, 71 EFX_MAC_SIENA, 72 EFX_MAC_HUNTINGTON, 73 EFX_MAC_MEDFORD, 74 EFX_MAC_MEDFORD2, 75 EFX_MAC_NTYPES 76 } efx_mac_type_t; 77 78 typedef struct efx_ev_ops_s { 79 efx_rc_t (*eevo_init)(efx_nic_t *); 80 void (*eevo_fini)(efx_nic_t *); 81 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 82 efsys_mem_t *, size_t, uint32_t, 83 uint32_t, uint32_t, efx_evq_t *); 84 void (*eevo_qdestroy)(efx_evq_t *); 85 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 86 void (*eevo_qpost)(efx_evq_t *, uint16_t); 87 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 88 #if EFSYS_OPT_QSTATS 89 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 90 #endif 91 } efx_ev_ops_t; 92 93 typedef struct efx_tx_ops_s { 94 efx_rc_t (*etxo_init)(efx_nic_t *); 95 void (*etxo_fini)(efx_nic_t *); 96 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 97 unsigned int, unsigned int, 98 efsys_mem_t *, size_t, 99 uint32_t, uint16_t, 100 efx_evq_t *, efx_txq_t *, 101 unsigned int *); 102 void (*etxo_qdestroy)(efx_txq_t *); 103 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 104 unsigned int, unsigned int, 105 unsigned int *); 106 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 107 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 108 efx_rc_t (*etxo_qflush)(efx_txq_t *); 109 void (*etxo_qenable)(efx_txq_t *); 110 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 111 void (*etxo_qpio_disable)(efx_txq_t *); 112 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 113 size_t); 114 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 115 unsigned int *); 116 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 117 unsigned int, unsigned int, 118 unsigned int *); 119 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 120 size_t, boolean_t, 121 efx_desc_t *); 122 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 123 uint32_t, uint8_t, 124 efx_desc_t *); 125 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 126 uint16_t, uint32_t, uint16_t, 127 efx_desc_t *, int); 128 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 129 efx_desc_t *); 130 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 131 efx_desc_t *); 132 #if EFSYS_OPT_QSTATS 133 void (*etxo_qstats_update)(efx_txq_t *, 134 efsys_stat_t *); 135 #endif 136 } efx_tx_ops_t; 137 138 typedef union efx_rxq_type_data_u { 139 struct { 140 size_t ed_buf_size; 141 } ertd_default; 142 #if EFSYS_OPT_RX_PACKED_STREAM 143 struct { 144 uint32_t eps_buf_size; 145 } ertd_packed_stream; 146 #endif 147 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 148 struct { 149 uint32_t eessb_bufs_per_desc; 150 uint32_t eessb_max_dma_len; 151 uint32_t eessb_buf_stride; 152 uint32_t eessb_hol_block_timeout; 153 } ertd_es_super_buffer; 154 #endif 155 } efx_rxq_type_data_t; 156 157 typedef struct efx_rx_ops_s { 158 efx_rc_t (*erxo_init)(efx_nic_t *); 159 void (*erxo_fini)(efx_nic_t *); 160 #if EFSYS_OPT_RX_SCATTER 161 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 162 #endif 163 #if EFSYS_OPT_RX_SCALE 164 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 165 efx_rx_scale_context_type_t, 166 uint32_t, uint32_t *); 167 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 168 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 169 efx_rx_hash_alg_t, 170 efx_rx_hash_type_t, boolean_t); 171 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 172 uint8_t *, size_t); 173 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 174 unsigned int *, size_t); 175 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 176 uint8_t *); 177 #endif /* EFSYS_OPT_RX_SCALE */ 178 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 179 uint16_t *); 180 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 181 unsigned int, unsigned int, 182 unsigned int); 183 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 184 #if EFSYS_OPT_RX_PACKED_STREAM 185 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 186 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 187 uint32_t, uint32_t, 188 uint16_t *, uint32_t *, uint32_t *); 189 #endif 190 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 191 void (*erxo_qenable)(efx_rxq_t *); 192 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 193 unsigned int, efx_rxq_type_t, 194 const efx_rxq_type_data_t *, 195 efsys_mem_t *, size_t, uint32_t, 196 unsigned int, 197 efx_evq_t *, efx_rxq_t *); 198 void (*erxo_qdestroy)(efx_rxq_t *); 199 } efx_rx_ops_t; 200 201 typedef struct efx_mac_ops_s { 202 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 203 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 204 efx_rc_t (*emo_addr_set)(efx_nic_t *); 205 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 206 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 207 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 208 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 209 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 210 efx_rxq_t *, boolean_t); 211 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 212 #if EFSYS_OPT_LOOPBACK 213 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 214 efx_loopback_type_t); 215 #endif /* EFSYS_OPT_LOOPBACK */ 216 #if EFSYS_OPT_MAC_STATS 217 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 218 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 219 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 220 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 221 uint16_t, boolean_t); 222 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 223 efsys_stat_t *, uint32_t *); 224 #endif /* EFSYS_OPT_MAC_STATS */ 225 } efx_mac_ops_t; 226 227 typedef struct efx_phy_ops_s { 228 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 229 efx_rc_t (*epo_reset)(efx_nic_t *); 230 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 231 efx_rc_t (*epo_verify)(efx_nic_t *); 232 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 233 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 234 #if EFSYS_OPT_PHY_STATS 235 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 236 uint32_t *); 237 #endif /* EFSYS_OPT_PHY_STATS */ 238 #if EFSYS_OPT_BIST 239 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 240 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 241 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 242 efx_bist_result_t *, uint32_t *, 243 unsigned long *, size_t); 244 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 245 #endif /* EFSYS_OPT_BIST */ 246 } efx_phy_ops_t; 247 248 #if EFSYS_OPT_FILTER 249 250 /* 251 * Policy for replacing existing filter when inserting a new one. 252 * Note that all policies allow for storing the new lower priority 253 * filters as overridden by existing higher priority ones. It is needed 254 * to restore the lower priority filters on higher priority ones removal. 255 */ 256 typedef enum efx_filter_replacement_policy_e { 257 /* Cannot replace existing filter */ 258 EFX_FILTER_REPLACEMENT_NEVER, 259 /* Higher priority filters can replace lower priotiry ones */ 260 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 261 /* 262 * Higher priority filters can replace lower priority ones and 263 * equal priority filters can replace each other. 264 */ 265 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 266 } efx_filter_replacement_policy_t; 267 268 typedef struct efx_filter_ops_s { 269 efx_rc_t (*efo_init)(efx_nic_t *); 270 void (*efo_fini)(efx_nic_t *); 271 efx_rc_t (*efo_restore)(efx_nic_t *); 272 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 273 efx_filter_replacement_policy_t policy); 274 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 275 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 276 size_t, size_t *); 277 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 278 boolean_t, boolean_t, boolean_t, 279 uint8_t const *, uint32_t); 280 } efx_filter_ops_t; 281 282 LIBEFX_INTERNAL 283 extern __checkReturn efx_rc_t 284 efx_filter_reconfigure( 285 __in efx_nic_t *enp, 286 __in_ecount(6) uint8_t const *mac_addr, 287 __in boolean_t all_unicst, 288 __in boolean_t mulcst, 289 __in boolean_t all_mulcst, 290 __in boolean_t brdcst, 291 __in_ecount(6*count) uint8_t const *addrs, 292 __in uint32_t count); 293 294 #endif /* EFSYS_OPT_FILTER */ 295 296 #if EFSYS_OPT_TUNNEL 297 typedef struct efx_tunnel_ops_s { 298 boolean_t (*eto_udp_encap_supported)(efx_nic_t *); 299 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 300 } efx_tunnel_ops_t; 301 #endif /* EFSYS_OPT_TUNNEL */ 302 303 typedef struct efx_port_s { 304 efx_mac_type_t ep_mac_type; 305 uint32_t ep_phy_type; 306 uint8_t ep_port; 307 uint32_t ep_mac_pdu; 308 uint8_t ep_mac_addr[6]; 309 efx_link_mode_t ep_link_mode; 310 boolean_t ep_all_unicst; 311 boolean_t ep_all_unicst_inserted; 312 boolean_t ep_mulcst; 313 boolean_t ep_all_mulcst; 314 boolean_t ep_all_mulcst_inserted; 315 boolean_t ep_brdcst; 316 unsigned int ep_fcntl; 317 boolean_t ep_fcntl_autoneg; 318 efx_oword_t ep_multicst_hash[2]; 319 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 320 EFX_MAC_MULTICAST_LIST_MAX]; 321 uint32_t ep_mulcst_addr_count; 322 #if EFSYS_OPT_LOOPBACK 323 efx_loopback_type_t ep_loopback_type; 324 efx_link_mode_t ep_loopback_link_mode; 325 #endif /* EFSYS_OPT_LOOPBACK */ 326 #if EFSYS_OPT_PHY_FLAGS 327 uint32_t ep_phy_flags; 328 #endif /* EFSYS_OPT_PHY_FLAGS */ 329 #if EFSYS_OPT_PHY_LED_CONTROL 330 efx_phy_led_mode_t ep_phy_led_mode; 331 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 332 efx_phy_media_type_t ep_fixed_port_type; 333 efx_phy_media_type_t ep_module_type; 334 uint32_t ep_adv_cap_mask; 335 uint32_t ep_lp_cap_mask; 336 uint32_t ep_default_adv_cap_mask; 337 uint32_t ep_phy_cap_mask; 338 boolean_t ep_mac_drain; 339 #if EFSYS_OPT_BIST 340 efx_bist_type_t ep_current_bist; 341 #endif 342 const efx_mac_ops_t *ep_emop; 343 const efx_phy_ops_t *ep_epop; 344 } efx_port_t; 345 346 typedef struct efx_mon_ops_s { 347 #if EFSYS_OPT_MON_STATS 348 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 349 efx_mon_stat_value_t *); 350 efx_rc_t (*emo_limits_update)(efx_nic_t *, 351 efx_mon_stat_limits_t *); 352 #endif /* EFSYS_OPT_MON_STATS */ 353 } efx_mon_ops_t; 354 355 typedef struct efx_mon_s { 356 efx_mon_type_t em_type; 357 const efx_mon_ops_t *em_emop; 358 } efx_mon_t; 359 360 typedef struct efx_intr_ops_s { 361 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 362 void (*eio_enable)(efx_nic_t *); 363 void (*eio_disable)(efx_nic_t *); 364 void (*eio_disable_unlocked)(efx_nic_t *); 365 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 366 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 367 void (*eio_status_message)(efx_nic_t *, unsigned int, 368 boolean_t *); 369 void (*eio_fatal)(efx_nic_t *); 370 void (*eio_fini)(efx_nic_t *); 371 } efx_intr_ops_t; 372 373 typedef struct efx_intr_s { 374 const efx_intr_ops_t *ei_eiop; 375 efsys_mem_t *ei_esmp; 376 efx_intr_type_t ei_type; 377 unsigned int ei_level; 378 } efx_intr_t; 379 380 typedef struct efx_nic_ops_s { 381 efx_rc_t (*eno_probe)(efx_nic_t *); 382 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 383 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 384 efx_rc_t (*eno_reset)(efx_nic_t *); 385 efx_rc_t (*eno_init)(efx_nic_t *); 386 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 387 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 388 uint32_t *, size_t *); 389 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 390 void (*eno_set_hw_unavailable)(efx_nic_t *); 391 #if EFSYS_OPT_DIAG 392 efx_rc_t (*eno_register_test)(efx_nic_t *); 393 #endif /* EFSYS_OPT_DIAG */ 394 void (*eno_fini)(efx_nic_t *); 395 void (*eno_unprobe)(efx_nic_t *); 396 } efx_nic_ops_t; 397 398 #ifndef EFX_TXQ_LIMIT_TARGET 399 #define EFX_TXQ_LIMIT_TARGET 259 400 #endif 401 #ifndef EFX_RXQ_LIMIT_TARGET 402 #define EFX_RXQ_LIMIT_TARGET 512 403 #endif 404 405 406 #if EFSYS_OPT_FILTER 407 408 #if EFSYS_OPT_SIENA 409 410 typedef struct siena_filter_spec_s { 411 uint8_t sfs_type; 412 uint32_t sfs_flags; 413 uint32_t sfs_dmaq_id; 414 uint32_t sfs_dword[3]; 415 } siena_filter_spec_t; 416 417 typedef enum siena_filter_type_e { 418 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 419 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 420 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 421 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 422 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 423 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 424 425 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 426 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 427 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 428 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 429 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 430 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 431 432 EFX_SIENA_FILTER_NTYPES 433 } siena_filter_type_t; 434 435 typedef enum siena_filter_tbl_id_e { 436 EFX_SIENA_FILTER_TBL_RX_IP = 0, 437 EFX_SIENA_FILTER_TBL_RX_MAC, 438 EFX_SIENA_FILTER_TBL_TX_IP, 439 EFX_SIENA_FILTER_TBL_TX_MAC, 440 EFX_SIENA_FILTER_NTBLS 441 } siena_filter_tbl_id_t; 442 443 typedef struct siena_filter_tbl_s { 444 int sft_size; /* number of entries */ 445 int sft_used; /* active count */ 446 uint32_t *sft_bitmap; /* active bitmap */ 447 siena_filter_spec_t *sft_spec; /* array of saved specs */ 448 } siena_filter_tbl_t; 449 450 typedef struct siena_filter_s { 451 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 452 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 453 } siena_filter_t; 454 455 #endif /* EFSYS_OPT_SIENA */ 456 457 typedef struct efx_filter_s { 458 #if EFSYS_OPT_SIENA 459 siena_filter_t *ef_siena_filter; 460 #endif /* EFSYS_OPT_SIENA */ 461 #if EFX_OPTS_EF10() 462 ef10_filter_table_t *ef_ef10_filter_table; 463 #endif /* EFX_OPTS_EF10() */ 464 } efx_filter_t; 465 466 #if EFSYS_OPT_SIENA 467 468 LIBEFX_INTERNAL 469 extern void 470 siena_filter_tbl_clear( 471 __in efx_nic_t *enp, 472 __in siena_filter_tbl_id_t tbl); 473 474 #endif /* EFSYS_OPT_SIENA */ 475 476 #endif /* EFSYS_OPT_FILTER */ 477 478 #if EFSYS_OPT_MCDI 479 480 #define EFX_TUNNEL_MAXNENTRIES (16) 481 482 #if EFSYS_OPT_TUNNEL 483 484 typedef struct efx_tunnel_udp_entry_s { 485 uint16_t etue_port; /* host/cpu-endian */ 486 uint16_t etue_protocol; 487 } efx_tunnel_udp_entry_t; 488 489 typedef struct efx_tunnel_cfg_s { 490 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 491 unsigned int etc_udp_entries_num; 492 } efx_tunnel_cfg_t; 493 494 #endif /* EFSYS_OPT_TUNNEL */ 495 496 typedef struct efx_mcdi_ops_s { 497 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 498 void (*emco_send_request)(efx_nic_t *, void *, size_t, 499 void *, size_t); 500 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 501 boolean_t (*emco_poll_response)(efx_nic_t *); 502 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 503 void (*emco_fini)(efx_nic_t *); 504 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 505 efx_mcdi_feature_id_t, boolean_t *); 506 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 507 uint32_t *); 508 } efx_mcdi_ops_t; 509 510 typedef struct efx_mcdi_s { 511 const efx_mcdi_ops_t *em_emcop; 512 const efx_mcdi_transport_t *em_emtp; 513 efx_mcdi_iface_t em_emip; 514 } efx_mcdi_t; 515 516 #endif /* EFSYS_OPT_MCDI */ 517 518 #if EFSYS_OPT_NVRAM 519 520 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 521 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 522 523 typedef struct efx_nvram_ops_s { 524 #if EFSYS_OPT_DIAG 525 efx_rc_t (*envo_test)(efx_nic_t *); 526 #endif /* EFSYS_OPT_DIAG */ 527 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 528 uint32_t *); 529 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 530 efx_nvram_info_t *); 531 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 532 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 533 unsigned int, caddr_t, size_t); 534 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 535 unsigned int, caddr_t, size_t); 536 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 537 unsigned int, size_t); 538 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 539 unsigned int, caddr_t, size_t); 540 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 541 uint32_t *); 542 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 543 uint32_t *, uint16_t *); 544 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 545 uint16_t *); 546 efx_rc_t (*envo_buffer_validate)(uint32_t, 547 caddr_t, size_t); 548 } efx_nvram_ops_t; 549 #endif /* EFSYS_OPT_NVRAM */ 550 551 #if EFSYS_OPT_VPD 552 typedef struct efx_vpd_ops_s { 553 efx_rc_t (*evpdo_init)(efx_nic_t *); 554 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 555 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 556 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 557 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 558 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 559 efx_vpd_value_t *); 560 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 561 efx_vpd_value_t *); 562 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 563 efx_vpd_value_t *, unsigned int *); 564 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 565 void (*evpdo_fini)(efx_nic_t *); 566 } efx_vpd_ops_t; 567 #endif /* EFSYS_OPT_VPD */ 568 569 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 570 571 LIBEFX_INTERNAL 572 extern __checkReturn efx_rc_t 573 efx_mcdi_nvram_partitions( 574 __in efx_nic_t *enp, 575 __out_bcount(size) caddr_t data, 576 __in size_t size, 577 __out unsigned int *npartnp); 578 579 LIBEFX_INTERNAL 580 extern __checkReturn efx_rc_t 581 efx_mcdi_nvram_metadata( 582 __in efx_nic_t *enp, 583 __in uint32_t partn, 584 __out uint32_t *subtypep, 585 __out_ecount(4) uint16_t version[4], 586 __out_bcount_opt(size) char *descp, 587 __in size_t size); 588 589 LIBEFX_INTERNAL 590 extern __checkReturn efx_rc_t 591 efx_mcdi_nvram_info( 592 __in efx_nic_t *enp, 593 __in uint32_t partn, 594 __out efx_nvram_info_t *eni); 595 596 LIBEFX_INTERNAL 597 extern __checkReturn efx_rc_t 598 efx_mcdi_nvram_update_start( 599 __in efx_nic_t *enp, 600 __in uint32_t partn); 601 602 LIBEFX_INTERNAL 603 extern __checkReturn efx_rc_t 604 efx_mcdi_nvram_read( 605 __in efx_nic_t *enp, 606 __in uint32_t partn, 607 __in uint32_t offset, 608 __out_bcount(size) caddr_t data, 609 __in size_t size, 610 __in uint32_t mode); 611 612 LIBEFX_INTERNAL 613 extern __checkReturn efx_rc_t 614 efx_mcdi_nvram_erase( 615 __in efx_nic_t *enp, 616 __in uint32_t partn, 617 __in uint32_t offset, 618 __in size_t size); 619 620 LIBEFX_INTERNAL 621 extern __checkReturn efx_rc_t 622 efx_mcdi_nvram_write( 623 __in efx_nic_t *enp, 624 __in uint32_t partn, 625 __in uint32_t offset, 626 __in_bcount(size) caddr_t data, 627 __in size_t size); 628 629 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 630 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 631 632 LIBEFX_INTERNAL 633 extern __checkReturn efx_rc_t 634 efx_mcdi_nvram_update_finish( 635 __in efx_nic_t *enp, 636 __in uint32_t partn, 637 __in boolean_t reboot, 638 __in uint32_t flags, 639 __out_opt uint32_t *verify_resultp); 640 641 #if EFSYS_OPT_DIAG 642 643 LIBEFX_INTERNAL 644 extern __checkReturn efx_rc_t 645 efx_mcdi_nvram_test( 646 __in efx_nic_t *enp, 647 __in uint32_t partn); 648 649 #endif /* EFSYS_OPT_DIAG */ 650 651 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 652 653 #if EFSYS_OPT_LICENSING 654 655 typedef struct efx_lic_ops_s { 656 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 657 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 658 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 659 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 660 size_t *, uint8_t *); 661 efx_rc_t (*elo_find_start) 662 (efx_nic_t *, caddr_t, size_t, uint32_t *); 663 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 664 uint32_t, uint32_t *); 665 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 666 uint32_t, uint32_t *, uint32_t *); 667 boolean_t (*elo_validate_key)(efx_nic_t *, 668 caddr_t, uint32_t); 669 efx_rc_t (*elo_read_key)(efx_nic_t *, 670 caddr_t, size_t, uint32_t, uint32_t, 671 caddr_t, size_t, uint32_t *); 672 efx_rc_t (*elo_write_key)(efx_nic_t *, 673 caddr_t, size_t, uint32_t, 674 caddr_t, uint32_t, uint32_t *); 675 efx_rc_t (*elo_delete_key)(efx_nic_t *, 676 caddr_t, size_t, uint32_t, 677 uint32_t, uint32_t, uint32_t *); 678 efx_rc_t (*elo_create_partition)(efx_nic_t *, 679 caddr_t, size_t); 680 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 681 caddr_t, size_t); 682 } efx_lic_ops_t; 683 684 #endif 685 686 #if EFSYS_OPT_EVB 687 688 struct efx_vswitch_s { 689 efx_nic_t *ev_enp; 690 efx_vswitch_id_t ev_vswitch_id; 691 uint32_t ev_num_vports; 692 /* 693 * Vport configuration array: index 0 to store PF configuration 694 * and next ev_num_vports-1 entries hold VFs configuration. 695 */ 696 efx_vport_config_t *ev_evcp; 697 }; 698 699 typedef struct efx_evb_ops_s { 700 efx_rc_t (*eeo_init)(efx_nic_t *); 701 void (*eeo_fini)(efx_nic_t *); 702 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 703 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 704 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 705 efx_vport_type_t, uint16_t, 706 boolean_t, efx_vport_id_t *); 707 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 708 efx_vport_id_t); 709 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 710 efx_vport_id_t, uint8_t *); 711 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 712 efx_vport_id_t, uint8_t *); 713 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 714 efx_vport_id_t); 715 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 716 efx_vport_id_t); 717 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 718 efx_vport_id_t, uint32_t); 719 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 720 efx_vport_id_t, 721 uint16_t *, uint8_t *, 722 boolean_t *); 723 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 724 efx_vport_id_t, efsys_mem_t *); 725 } efx_evb_ops_t; 726 727 LIBEFX_INTERNAL 728 extern __checkReturn boolean_t 729 efx_is_zero_eth_addr( 730 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 731 732 #endif /* EFSYS_OPT_EVB */ 733 734 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 735 736 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 737 738 739 typedef struct efx_proxy_ops_s { 740 efx_rc_t (*epo_init)(efx_nic_t *); 741 void (*epo_fini)(efx_nic_t *); 742 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 743 efsys_mem_t *, efsys_mem_t *, 744 uint32_t, uint32_t *, size_t); 745 efx_rc_t (*epo_disable)(efx_nic_t *); 746 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 747 uint32_t, uint32_t, uint32_t); 748 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 749 uint32_t, uint32_t); 750 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 751 uint32_t, uint32_t); 752 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 753 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 754 uint32_t, uint32_t *); 755 } efx_proxy_ops_t; 756 757 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 758 759 #define EFX_DRV_VER_MAX 20 760 761 typedef struct efx_drv_cfg_s { 762 uint32_t edc_min_vi_count; 763 uint32_t edc_max_vi_count; 764 765 uint32_t edc_max_piobuf_count; 766 uint32_t edc_pio_alloc_size; 767 } efx_drv_cfg_t; 768 769 struct efx_nic_s { 770 uint32_t en_magic; 771 efx_family_t en_family; 772 uint32_t en_features; 773 efsys_identifier_t *en_esip; 774 efsys_lock_t *en_eslp; 775 efsys_bar_t *en_esbp; 776 unsigned int en_mod_flags; 777 unsigned int en_reset_flags; 778 efx_nic_cfg_t en_nic_cfg; 779 efx_drv_cfg_t en_drv_cfg; 780 efx_port_t en_port; 781 efx_mon_t en_mon; 782 efx_intr_t en_intr; 783 uint32_t en_ev_qcount; 784 uint32_t en_rx_qcount; 785 uint32_t en_tx_qcount; 786 const efx_nic_ops_t *en_enop; 787 const efx_ev_ops_t *en_eevop; 788 const efx_tx_ops_t *en_etxop; 789 const efx_rx_ops_t *en_erxop; 790 efx_fw_variant_t efv; 791 char en_drv_version[EFX_DRV_VER_MAX]; 792 #if EFSYS_OPT_FILTER 793 efx_filter_t en_filter; 794 const efx_filter_ops_t *en_efop; 795 #endif /* EFSYS_OPT_FILTER */ 796 #if EFSYS_OPT_TUNNEL 797 efx_tunnel_cfg_t en_tunnel_cfg; 798 const efx_tunnel_ops_t *en_etop; 799 #endif /* EFSYS_OPT_TUNNEL */ 800 #if EFSYS_OPT_MCDI 801 efx_mcdi_t en_mcdi; 802 #endif /* EFSYS_OPT_MCDI */ 803 #if EFSYS_OPT_NVRAM 804 uint32_t en_nvram_partn_locked; 805 const efx_nvram_ops_t *en_envop; 806 #endif /* EFSYS_OPT_NVRAM */ 807 #if EFSYS_OPT_VPD 808 const efx_vpd_ops_t *en_evpdop; 809 #endif /* EFSYS_OPT_VPD */ 810 #if EFSYS_OPT_RX_SCALE 811 efx_rx_hash_support_t en_hash_support; 812 efx_rx_scale_context_type_t en_rss_context_type; 813 uint32_t en_rss_context; 814 #endif /* EFSYS_OPT_RX_SCALE */ 815 uint32_t en_vport_id; 816 #if EFSYS_OPT_LICENSING 817 const efx_lic_ops_t *en_elop; 818 boolean_t en_licensing_supported; 819 #endif 820 union { 821 #if EFSYS_OPT_SIENA 822 struct { 823 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 824 unsigned int enu_partn_mask; 825 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 826 #if EFSYS_OPT_VPD 827 caddr_t enu_svpd; 828 size_t enu_svpd_length; 829 #endif /* EFSYS_OPT_VPD */ 830 int enu_unused; 831 } siena; 832 #endif /* EFSYS_OPT_SIENA */ 833 int enu_unused; 834 } en_u; 835 #if EFX_OPTS_EF10() 836 union en_arch { 837 struct { 838 int ena_vi_base; 839 int ena_vi_count; 840 int ena_vi_shift; 841 #if EFSYS_OPT_VPD 842 caddr_t ena_svpd; 843 size_t ena_svpd_length; 844 #endif /* EFSYS_OPT_VPD */ 845 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 846 uint32_t ena_piobuf_count; 847 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 848 uint32_t ena_pio_write_vi_base; 849 /* Memory BAR mapping regions */ 850 uint32_t ena_uc_mem_map_offset; 851 size_t ena_uc_mem_map_size; 852 uint32_t ena_wc_mem_map_offset; 853 size_t ena_wc_mem_map_size; 854 } ef10; 855 } en_arch; 856 #endif /* EFX_OPTS_EF10() */ 857 #if EFSYS_OPT_EVB 858 const efx_evb_ops_t *en_eeop; 859 struct efx_vswitch_s *en_vswitchp; 860 #endif /* EFSYS_OPT_EVB */ 861 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 862 const efx_proxy_ops_t *en_epop; 863 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 864 }; 865 866 #define EFX_FAMILY_IS_EF10(_enp) \ 867 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 868 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 869 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 870 871 872 #define EFX_NIC_MAGIC 0x02121996 873 874 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 875 const efx_ev_callbacks_t *, void *); 876 877 typedef struct efx_evq_rxq_state_s { 878 unsigned int eers_rx_read_ptr; 879 unsigned int eers_rx_mask; 880 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 881 unsigned int eers_rx_stream_npackets; 882 boolean_t eers_rx_packed_stream; 883 #endif 884 #if EFSYS_OPT_RX_PACKED_STREAM 885 unsigned int eers_rx_packed_stream_credits; 886 #endif 887 } efx_evq_rxq_state_t; 888 889 struct efx_evq_s { 890 uint32_t ee_magic; 891 uint32_t ee_flags; 892 efx_nic_t *ee_enp; 893 unsigned int ee_index; 894 unsigned int ee_mask; 895 efsys_mem_t *ee_esmp; 896 #if EFSYS_OPT_QSTATS 897 uint32_t ee_stat[EV_NQSTATS]; 898 #endif /* EFSYS_OPT_QSTATS */ 899 900 efx_ev_handler_t ee_rx; 901 efx_ev_handler_t ee_tx; 902 efx_ev_handler_t ee_driver; 903 efx_ev_handler_t ee_global; 904 efx_ev_handler_t ee_drv_gen; 905 #if EFSYS_OPT_MCDI 906 efx_ev_handler_t ee_mcdi; 907 #endif /* EFSYS_OPT_MCDI */ 908 909 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 910 }; 911 912 #define EFX_EVQ_MAGIC 0x08081997 913 914 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 915 916 #if EFSYS_OPT_QSTATS 917 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 918 do { \ 919 (_eep)->ee_stat[_stat]++; \ 920 _NOTE(CONSTANTCONDITION) \ 921 } while (B_FALSE) 922 #else 923 #define EFX_EV_QSTAT_INCR(_eep, _stat) 924 #endif 925 926 struct efx_rxq_s { 927 uint32_t er_magic; 928 efx_nic_t *er_enp; 929 efx_evq_t *er_eep; 930 unsigned int er_index; 931 unsigned int er_label; 932 unsigned int er_mask; 933 size_t er_buf_size; 934 efsys_mem_t *er_esmp; 935 efx_evq_rxq_state_t *er_ev_qstate; 936 }; 937 938 #define EFX_RXQ_MAGIC 0x15022005 939 940 struct efx_txq_s { 941 uint32_t et_magic; 942 efx_nic_t *et_enp; 943 unsigned int et_index; 944 unsigned int et_mask; 945 efsys_mem_t *et_esmp; 946 #if EFSYS_OPT_HUNTINGTON 947 uint32_t et_pio_bufnum; 948 uint32_t et_pio_blknum; 949 uint32_t et_pio_write_offset; 950 uint32_t et_pio_offset; 951 size_t et_pio_size; 952 #endif 953 #if EFSYS_OPT_QSTATS 954 uint32_t et_stat[TX_NQSTATS]; 955 #endif /* EFSYS_OPT_QSTATS */ 956 }; 957 958 #define EFX_TXQ_MAGIC 0x05092005 959 960 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 961 do { \ 962 (_dst)[0] = (_src)[0]; \ 963 (_dst)[1] = (_src)[1]; \ 964 (_dst)[2] = (_src)[2]; \ 965 (_dst)[3] = (_src)[3]; \ 966 (_dst)[4] = (_src)[4]; \ 967 (_dst)[5] = (_src)[5]; \ 968 _NOTE(CONSTANTCONDITION) \ 969 } while (B_FALSE) 970 971 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 972 do { \ 973 uint16_t *_d = (uint16_t *)(_dst); \ 974 _d[0] = 0xffff; \ 975 _d[1] = 0xffff; \ 976 _d[2] = 0xffff; \ 977 _NOTE(CONSTANTCONDITION) \ 978 } while (B_FALSE) 979 980 #if EFSYS_OPT_CHECK_REG 981 #define EFX_CHECK_REG(_enp, _reg) \ 982 do { \ 983 const char *name = #_reg; \ 984 char min = name[4]; \ 985 char max = name[5]; \ 986 char rev; \ 987 \ 988 switch ((_enp)->en_family) { \ 989 case EFX_FAMILY_SIENA: \ 990 rev = 'C'; \ 991 break; \ 992 \ 993 case EFX_FAMILY_HUNTINGTON: \ 994 rev = 'D'; \ 995 break; \ 996 \ 997 case EFX_FAMILY_MEDFORD: \ 998 rev = 'E'; \ 999 break; \ 1000 \ 1001 case EFX_FAMILY_MEDFORD2: \ 1002 rev = 'F'; \ 1003 break; \ 1004 \ 1005 default: \ 1006 rev = '?'; \ 1007 break; \ 1008 } \ 1009 \ 1010 EFSYS_ASSERT3S(rev, >=, min); \ 1011 EFSYS_ASSERT3S(rev, <=, max); \ 1012 \ 1013 _NOTE(CONSTANTCONDITION) \ 1014 } while (B_FALSE) 1015 #else 1016 #define EFX_CHECK_REG(_enp, _reg) do { \ 1017 _NOTE(CONSTANTCONDITION) \ 1018 } while (B_FALSE) 1019 #endif 1020 1021 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1022 do { \ 1023 EFX_CHECK_REG((_enp), (_reg)); \ 1024 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1025 (_edp), (_lock)); \ 1026 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1027 uint32_t, _reg ## _OFST, \ 1028 uint32_t, (_edp)->ed_u32[0]); \ 1029 _NOTE(CONSTANTCONDITION) \ 1030 } while (B_FALSE) 1031 1032 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1033 do { \ 1034 EFX_CHECK_REG((_enp), (_reg)); \ 1035 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1036 uint32_t, _reg ## _OFST, \ 1037 uint32_t, (_edp)->ed_u32[0]); \ 1038 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1039 (_edp), (_lock)); \ 1040 _NOTE(CONSTANTCONDITION) \ 1041 } while (B_FALSE) 1042 1043 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1044 do { \ 1045 EFX_CHECK_REG((_enp), (_reg)); \ 1046 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1047 (_eqp)); \ 1048 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1049 uint32_t, _reg ## _OFST, \ 1050 uint32_t, (_eqp)->eq_u32[1], \ 1051 uint32_t, (_eqp)->eq_u32[0]); \ 1052 _NOTE(CONSTANTCONDITION) \ 1053 } while (B_FALSE) 1054 1055 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1056 do { \ 1057 EFX_CHECK_REG((_enp), (_reg)); \ 1058 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1059 uint32_t, _reg ## _OFST, \ 1060 uint32_t, (_eqp)->eq_u32[1], \ 1061 uint32_t, (_eqp)->eq_u32[0]); \ 1062 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1063 (_eqp)); \ 1064 _NOTE(CONSTANTCONDITION) \ 1065 } while (B_FALSE) 1066 1067 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1068 do { \ 1069 EFX_CHECK_REG((_enp), (_reg)); \ 1070 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1071 (_eop), B_TRUE); \ 1072 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1073 uint32_t, _reg ## _OFST, \ 1074 uint32_t, (_eop)->eo_u32[3], \ 1075 uint32_t, (_eop)->eo_u32[2], \ 1076 uint32_t, (_eop)->eo_u32[1], \ 1077 uint32_t, (_eop)->eo_u32[0]); \ 1078 _NOTE(CONSTANTCONDITION) \ 1079 } while (B_FALSE) 1080 1081 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1082 do { \ 1083 EFX_CHECK_REG((_enp), (_reg)); \ 1084 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1085 uint32_t, _reg ## _OFST, \ 1086 uint32_t, (_eop)->eo_u32[3], \ 1087 uint32_t, (_eop)->eo_u32[2], \ 1088 uint32_t, (_eop)->eo_u32[1], \ 1089 uint32_t, (_eop)->eo_u32[0]); \ 1090 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1091 (_eop), B_TRUE); \ 1092 _NOTE(CONSTANTCONDITION) \ 1093 } while (B_FALSE) 1094 1095 /* 1096 * Accessors for memory BAR non-VI tables. 1097 * 1098 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1099 * to ensure the correct runtime VI window size is used on Medford2. 1100 * 1101 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1102 */ 1103 1104 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1105 do { \ 1106 EFX_CHECK_REG((_enp), (_reg)); \ 1107 EFSYS_BAR_READD((_enp)->en_esbp, \ 1108 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1109 (_edp), (_lock)); \ 1110 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1111 uint32_t, (_index), \ 1112 uint32_t, _reg ## _OFST, \ 1113 uint32_t, (_edp)->ed_u32[0]); \ 1114 _NOTE(CONSTANTCONDITION) \ 1115 } while (B_FALSE) 1116 1117 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1118 do { \ 1119 EFX_CHECK_REG((_enp), (_reg)); \ 1120 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1121 uint32_t, (_index), \ 1122 uint32_t, _reg ## _OFST, \ 1123 uint32_t, (_edp)->ed_u32[0]); \ 1124 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1125 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1126 (_edp), (_lock)); \ 1127 _NOTE(CONSTANTCONDITION) \ 1128 } while (B_FALSE) 1129 1130 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1131 do { \ 1132 EFX_CHECK_REG((_enp), (_reg)); \ 1133 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1134 uint32_t, (_index), \ 1135 uint32_t, _reg ## _OFST, \ 1136 uint32_t, (_edp)->ed_u32[0]); \ 1137 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1138 (_reg ## _OFST + \ 1139 (3 * sizeof (efx_dword_t)) + \ 1140 ((_index) * _reg ## _STEP)), \ 1141 (_edp), (_lock)); \ 1142 _NOTE(CONSTANTCONDITION) \ 1143 } while (B_FALSE) 1144 1145 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1146 do { \ 1147 EFX_CHECK_REG((_enp), (_reg)); \ 1148 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1149 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1150 (_eqp)); \ 1151 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1152 uint32_t, (_index), \ 1153 uint32_t, _reg ## _OFST, \ 1154 uint32_t, (_eqp)->eq_u32[1], \ 1155 uint32_t, (_eqp)->eq_u32[0]); \ 1156 _NOTE(CONSTANTCONDITION) \ 1157 } while (B_FALSE) 1158 1159 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1160 do { \ 1161 EFX_CHECK_REG((_enp), (_reg)); \ 1162 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1163 uint32_t, (_index), \ 1164 uint32_t, _reg ## _OFST, \ 1165 uint32_t, (_eqp)->eq_u32[1], \ 1166 uint32_t, (_eqp)->eq_u32[0]); \ 1167 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1168 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1169 (_eqp)); \ 1170 _NOTE(CONSTANTCONDITION) \ 1171 } while (B_FALSE) 1172 1173 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1174 do { \ 1175 EFX_CHECK_REG((_enp), (_reg)); \ 1176 EFSYS_BAR_READO((_enp)->en_esbp, \ 1177 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1178 (_eop), (_lock)); \ 1179 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1180 uint32_t, (_index), \ 1181 uint32_t, _reg ## _OFST, \ 1182 uint32_t, (_eop)->eo_u32[3], \ 1183 uint32_t, (_eop)->eo_u32[2], \ 1184 uint32_t, (_eop)->eo_u32[1], \ 1185 uint32_t, (_eop)->eo_u32[0]); \ 1186 _NOTE(CONSTANTCONDITION) \ 1187 } while (B_FALSE) 1188 1189 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1190 do { \ 1191 EFX_CHECK_REG((_enp), (_reg)); \ 1192 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1193 uint32_t, (_index), \ 1194 uint32_t, _reg ## _OFST, \ 1195 uint32_t, (_eop)->eo_u32[3], \ 1196 uint32_t, (_eop)->eo_u32[2], \ 1197 uint32_t, (_eop)->eo_u32[1], \ 1198 uint32_t, (_eop)->eo_u32[0]); \ 1199 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1200 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1201 (_eop), (_lock)); \ 1202 _NOTE(CONSTANTCONDITION) \ 1203 } while (B_FALSE) 1204 1205 /* 1206 * Accessors for memory BAR per-VI registers. 1207 * 1208 * The VI window size is 8KB for Medford and all earlier controllers. 1209 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1210 */ 1211 1212 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1213 do { \ 1214 EFX_CHECK_REG((_enp), (_reg)); \ 1215 EFSYS_BAR_READD((_enp)->en_esbp, \ 1216 ((_reg ## _OFST) + \ 1217 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1218 (_edp), (_lock)); \ 1219 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1220 uint32_t, (_index), \ 1221 uint32_t, _reg ## _OFST, \ 1222 uint32_t, (_edp)->ed_u32[0]); \ 1223 _NOTE(CONSTANTCONDITION) \ 1224 } while (B_FALSE) 1225 1226 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1227 do { \ 1228 EFX_CHECK_REG((_enp), (_reg)); \ 1229 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1230 uint32_t, (_index), \ 1231 uint32_t, _reg ## _OFST, \ 1232 uint32_t, (_edp)->ed_u32[0]); \ 1233 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1234 ((_reg ## _OFST) + \ 1235 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1236 (_edp), (_lock)); \ 1237 _NOTE(CONSTANTCONDITION) \ 1238 } while (B_FALSE) 1239 1240 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1241 do { \ 1242 EFX_CHECK_REG((_enp), (_reg)); \ 1243 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1244 uint32_t, (_index), \ 1245 uint32_t, _reg ## _OFST, \ 1246 uint32_t, (_edp)->ed_u32[0]); \ 1247 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1248 ((_reg ## _OFST) + \ 1249 (2 * sizeof (efx_dword_t)) + \ 1250 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1251 (_edp), (_lock)); \ 1252 _NOTE(CONSTANTCONDITION) \ 1253 } while (B_FALSE) 1254 1255 /* 1256 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1257 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1258 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1259 * the need for locking in the host, and are the only ones known to be safe to 1260 * use 128-bites write with. 1261 */ 1262 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1263 do { \ 1264 EFX_CHECK_REG((_enp), (_reg)); \ 1265 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1266 const char *, #_reg, \ 1267 uint32_t, (_index), \ 1268 uint32_t, _reg ## _OFST, \ 1269 uint32_t, (_eop)->eo_u32[3], \ 1270 uint32_t, (_eop)->eo_u32[2], \ 1271 uint32_t, (_eop)->eo_u32[1], \ 1272 uint32_t, (_eop)->eo_u32[0]); \ 1273 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1274 (_reg ## _OFST + \ 1275 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1276 (_eop)); \ 1277 _NOTE(CONSTANTCONDITION) \ 1278 } while (B_FALSE) 1279 1280 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1281 do { \ 1282 unsigned int _new = (_wptr); \ 1283 unsigned int _old = (_owptr); \ 1284 \ 1285 if ((_new) >= (_old)) \ 1286 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1287 (_old) * sizeof (efx_desc_t), \ 1288 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1289 else \ 1290 /* \ 1291 * It is cheaper to sync entire map than sync \ 1292 * two parts especially when offset/size are \ 1293 * ignored and entire map is synced in any case.\ 1294 */ \ 1295 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1296 0, \ 1297 (_entries) * sizeof (efx_desc_t)); \ 1298 _NOTE(CONSTANTCONDITION) \ 1299 } while (B_FALSE) 1300 1301 LIBEFX_INTERNAL 1302 extern __checkReturn efx_rc_t 1303 efx_mac_select( 1304 __in efx_nic_t *enp); 1305 1306 LIBEFX_INTERNAL 1307 extern void 1308 efx_mac_multicast_hash_compute( 1309 __in_ecount(6*count) uint8_t const *addrs, 1310 __in int count, 1311 __out efx_oword_t *hash_low, 1312 __out efx_oword_t *hash_high); 1313 1314 LIBEFX_INTERNAL 1315 extern __checkReturn efx_rc_t 1316 efx_phy_probe( 1317 __in efx_nic_t *enp); 1318 1319 LIBEFX_INTERNAL 1320 extern void 1321 efx_phy_unprobe( 1322 __in efx_nic_t *enp); 1323 1324 #if EFSYS_OPT_VPD 1325 1326 /* VPD utility functions */ 1327 1328 LIBEFX_INTERNAL 1329 extern __checkReturn efx_rc_t 1330 efx_vpd_hunk_length( 1331 __in_bcount(size) caddr_t data, 1332 __in size_t size, 1333 __out size_t *lengthp); 1334 1335 LIBEFX_INTERNAL 1336 extern __checkReturn efx_rc_t 1337 efx_vpd_hunk_verify( 1338 __in_bcount(size) caddr_t data, 1339 __in size_t size, 1340 __out_opt boolean_t *cksummedp); 1341 1342 LIBEFX_INTERNAL 1343 extern __checkReturn efx_rc_t 1344 efx_vpd_hunk_reinit( 1345 __in_bcount(size) caddr_t data, 1346 __in size_t size, 1347 __in boolean_t wantpid); 1348 1349 LIBEFX_INTERNAL 1350 extern __checkReturn efx_rc_t 1351 efx_vpd_hunk_get( 1352 __in_bcount(size) caddr_t data, 1353 __in size_t size, 1354 __in efx_vpd_tag_t tag, 1355 __in efx_vpd_keyword_t keyword, 1356 __out unsigned int *payloadp, 1357 __out uint8_t *paylenp); 1358 1359 LIBEFX_INTERNAL 1360 extern __checkReturn efx_rc_t 1361 efx_vpd_hunk_next( 1362 __in_bcount(size) caddr_t data, 1363 __in size_t size, 1364 __out efx_vpd_tag_t *tagp, 1365 __out efx_vpd_keyword_t *keyword, 1366 __out_opt unsigned int *payloadp, 1367 __out_opt uint8_t *paylenp, 1368 __inout unsigned int *contp); 1369 1370 LIBEFX_INTERNAL 1371 extern __checkReturn efx_rc_t 1372 efx_vpd_hunk_set( 1373 __in_bcount(size) caddr_t data, 1374 __in size_t size, 1375 __in efx_vpd_value_t *evvp); 1376 1377 #endif /* EFSYS_OPT_VPD */ 1378 1379 #if EFSYS_OPT_MCDI 1380 1381 LIBEFX_INTERNAL 1382 extern __checkReturn efx_rc_t 1383 efx_mcdi_set_workaround( 1384 __in efx_nic_t *enp, 1385 __in uint32_t type, 1386 __in boolean_t enabled, 1387 __out_opt uint32_t *flagsp); 1388 1389 LIBEFX_INTERNAL 1390 extern __checkReturn efx_rc_t 1391 efx_mcdi_get_workarounds( 1392 __in efx_nic_t *enp, 1393 __out_opt uint32_t *implementedp, 1394 __out_opt uint32_t *enabledp); 1395 1396 #endif /* EFSYS_OPT_MCDI */ 1397 1398 #if EFSYS_OPT_MAC_STATS 1399 1400 /* 1401 * Closed range of stats (i.e. the first and the last are included). 1402 * The last must be greater or equal (if the range is one item only) to 1403 * the first. 1404 */ 1405 struct efx_mac_stats_range { 1406 efx_mac_stat_t first; 1407 efx_mac_stat_t last; 1408 }; 1409 1410 typedef enum efx_stats_action_e { 1411 EFX_STATS_CLEAR, 1412 EFX_STATS_UPLOAD, 1413 EFX_STATS_ENABLE_NOEVENTS, 1414 EFX_STATS_ENABLE_EVENTS, 1415 EFX_STATS_DISABLE, 1416 } efx_stats_action_t; 1417 1418 LIBEFX_INTERNAL 1419 extern efx_rc_t 1420 efx_mac_stats_mask_add_ranges( 1421 __inout_bcount(mask_size) uint32_t *maskp, 1422 __in size_t mask_size, 1423 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1424 __in unsigned int rng_count); 1425 1426 LIBEFX_INTERNAL 1427 extern __checkReturn efx_rc_t 1428 efx_mcdi_mac_stats( 1429 __in efx_nic_t *enp, 1430 __in uint32_t vport_id, 1431 __in_opt efsys_mem_t *esmp, 1432 __in efx_stats_action_t action, 1433 __in uint16_t period_ms); 1434 1435 #endif /* EFSYS_OPT_MAC_STATS */ 1436 1437 #ifdef __cplusplus 1438 } 1439 #endif 1440 1441 #endif /* _SYS_EFX_IMPL_H */ 1442