1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2006-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_H 8 #define _SYS_EFX_H 9 10 #include "efx_annote.h" 11 #include "efsys.h" 12 #include "efx_types.h" 13 #include "efx_check.h" 14 #include "efx_phy_ids.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define EFX_STATIC_ASSERT(_cond) \ 21 ((void)sizeof (char[(_cond) ? 1 : -1])) 22 23 #define EFX_ARRAY_SIZE(_array) \ 24 (sizeof (_array) / sizeof ((_array)[0])) 25 26 #define EFX_FIELD_OFFSET(_type, _field) \ 27 ((size_t)&(((_type *)0)->_field)) 28 29 /* The macro expands divider twice */ 30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 31 32 /* Round value up to the nearest power of two. */ 33 #define EFX_P2ROUNDUP(_type, _value, _align) \ 34 (-(-(_type)(_value) & -(_type)(_align))) 35 36 /* Align value down to the nearest power of two. */ 37 #define EFX_P2ALIGN(_type, _value, _align) \ 38 ((_type)(_value) & -(_type)(_align)) 39 40 /* Test if value is power of 2 aligned. */ 41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 43 44 /* Return codes */ 45 46 typedef __success(return == 0) int efx_rc_t; 47 48 49 /* Chip families */ 50 51 typedef enum efx_family_e { 52 EFX_FAMILY_INVALID, 53 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 54 EFX_FAMILY_SIENA, 55 EFX_FAMILY_HUNTINGTON, 56 EFX_FAMILY_MEDFORD, 57 EFX_FAMILY_MEDFORD2, 58 EFX_FAMILY_NTYPES 59 } efx_family_t; 60 61 LIBEFX_API 62 extern __checkReturn efx_rc_t 63 efx_family( 64 __in uint16_t venid, 65 __in uint16_t devid, 66 __out efx_family_t *efp, 67 __out unsigned int *membarp); 68 69 70 #define EFX_PCI_VENID_SFC 0x1924 71 72 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 73 74 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 75 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 76 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 77 78 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 79 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 80 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 81 82 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 83 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 84 85 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 86 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 87 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 88 89 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 90 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 91 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 92 93 94 #define EFX_MEM_BAR_SIENA 2 95 96 #define EFX_MEM_BAR_HUNTINGTON_PF 2 97 #define EFX_MEM_BAR_HUNTINGTON_VF 0 98 99 #define EFX_MEM_BAR_MEDFORD_PF 2 100 #define EFX_MEM_BAR_MEDFORD_VF 0 101 102 #define EFX_MEM_BAR_MEDFORD2 0 103 104 105 /* Error codes */ 106 107 enum { 108 EFX_ERR_INVALID, 109 EFX_ERR_SRAM_OOB, 110 EFX_ERR_BUFID_DC_OOB, 111 EFX_ERR_MEM_PERR, 112 EFX_ERR_RBUF_OWN, 113 EFX_ERR_TBUF_OWN, 114 EFX_ERR_RDESQ_OWN, 115 EFX_ERR_TDESQ_OWN, 116 EFX_ERR_EVQ_OWN, 117 EFX_ERR_EVFF_OFLO, 118 EFX_ERR_ILL_ADDR, 119 EFX_ERR_SRAM_PERR, 120 EFX_ERR_NCODES 121 }; 122 123 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 124 LIBEFX_API 125 extern __checkReturn uint32_t 126 efx_crc32_calculate( 127 __in uint32_t crc_init, 128 __in_ecount(length) uint8_t const *input, 129 __in int length); 130 131 132 /* Type prototypes */ 133 134 typedef struct efx_rxq_s efx_rxq_t; 135 136 /* NIC */ 137 138 typedef struct efx_nic_s efx_nic_t; 139 140 LIBEFX_API 141 extern __checkReturn efx_rc_t 142 efx_nic_create( 143 __in efx_family_t family, 144 __in efsys_identifier_t *esip, 145 __in efsys_bar_t *esbp, 146 __in efsys_lock_t *eslp, 147 __deref_out efx_nic_t **enpp); 148 149 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 150 typedef enum efx_fw_variant_e { 151 EFX_FW_VARIANT_FULL_FEATURED, 152 EFX_FW_VARIANT_LOW_LATENCY, 153 EFX_FW_VARIANT_PACKED_STREAM, 154 EFX_FW_VARIANT_HIGH_TX_RATE, 155 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 156 EFX_FW_VARIANT_RULES_ENGINE, 157 EFX_FW_VARIANT_DPDK, 158 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 159 } efx_fw_variant_t; 160 161 LIBEFX_API 162 extern __checkReturn efx_rc_t 163 efx_nic_probe( 164 __in efx_nic_t *enp, 165 __in efx_fw_variant_t efv); 166 167 LIBEFX_API 168 extern __checkReturn efx_rc_t 169 efx_nic_init( 170 __in efx_nic_t *enp); 171 172 LIBEFX_API 173 extern __checkReturn efx_rc_t 174 efx_nic_reset( 175 __in efx_nic_t *enp); 176 177 LIBEFX_API 178 extern __checkReturn boolean_t 179 efx_nic_hw_unavailable( 180 __in efx_nic_t *enp); 181 182 LIBEFX_API 183 extern void 184 efx_nic_set_hw_unavailable( 185 __in efx_nic_t *enp); 186 187 #if EFSYS_OPT_DIAG 188 189 LIBEFX_API 190 extern __checkReturn efx_rc_t 191 efx_nic_register_test( 192 __in efx_nic_t *enp); 193 194 #endif /* EFSYS_OPT_DIAG */ 195 196 LIBEFX_API 197 extern void 198 efx_nic_fini( 199 __in efx_nic_t *enp); 200 201 LIBEFX_API 202 extern void 203 efx_nic_unprobe( 204 __in efx_nic_t *enp); 205 206 LIBEFX_API 207 extern void 208 efx_nic_destroy( 209 __in efx_nic_t *enp); 210 211 #define EFX_PCIE_LINK_SPEED_GEN1 1 212 #define EFX_PCIE_LINK_SPEED_GEN2 2 213 #define EFX_PCIE_LINK_SPEED_GEN3 3 214 215 typedef enum efx_pcie_link_performance_e { 216 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 217 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 218 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 219 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 220 } efx_pcie_link_performance_t; 221 222 LIBEFX_API 223 extern __checkReturn efx_rc_t 224 efx_nic_calculate_pcie_link_bandwidth( 225 __in uint32_t pcie_link_width, 226 __in uint32_t pcie_link_gen, 227 __out uint32_t *bandwidth_mbpsp); 228 229 LIBEFX_API 230 extern __checkReturn efx_rc_t 231 efx_nic_check_pcie_link_speed( 232 __in efx_nic_t *enp, 233 __in uint32_t pcie_link_width, 234 __in uint32_t pcie_link_gen, 235 __out efx_pcie_link_performance_t *resultp); 236 237 #if EFSYS_OPT_MCDI 238 239 #if EFX_OPTS_EF10() 240 /* EF10 architecture NICs require MCDIv2 commands */ 241 #define WITH_MCDI_V2 1 242 #endif 243 244 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 245 246 typedef enum efx_mcdi_exception_e { 247 EFX_MCDI_EXCEPTION_MC_REBOOT, 248 EFX_MCDI_EXCEPTION_MC_BADASSERT, 249 } efx_mcdi_exception_t; 250 251 #if EFSYS_OPT_MCDI_LOGGING 252 typedef enum efx_log_msg_e { 253 EFX_LOG_INVALID, 254 EFX_LOG_MCDI_REQUEST, 255 EFX_LOG_MCDI_RESPONSE, 256 } efx_log_msg_t; 257 #endif /* EFSYS_OPT_MCDI_LOGGING */ 258 259 typedef struct efx_mcdi_transport_s { 260 void *emt_context; 261 efsys_mem_t *emt_dma_mem; 262 void (*emt_execute)(void *, efx_mcdi_req_t *); 263 void (*emt_ev_cpl)(void *); 264 void (*emt_exception)(void *, efx_mcdi_exception_t); 265 #if EFSYS_OPT_MCDI_LOGGING 266 void (*emt_logger)(void *, efx_log_msg_t, 267 void *, size_t, void *, size_t); 268 #endif /* EFSYS_OPT_MCDI_LOGGING */ 269 #if EFSYS_OPT_MCDI_PROXY_AUTH 270 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 271 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 272 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 273 void (*emt_ev_proxy_request)(void *, uint32_t); 274 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 275 } efx_mcdi_transport_t; 276 277 LIBEFX_API 278 extern __checkReturn efx_rc_t 279 efx_mcdi_init( 280 __in efx_nic_t *enp, 281 __in const efx_mcdi_transport_t *mtp); 282 283 LIBEFX_API 284 extern __checkReturn efx_rc_t 285 efx_mcdi_reboot( 286 __in efx_nic_t *enp); 287 288 LIBEFX_API 289 extern void 290 efx_mcdi_new_epoch( 291 __in efx_nic_t *enp); 292 293 LIBEFX_API 294 extern void 295 efx_mcdi_get_timeout( 296 __in efx_nic_t *enp, 297 __in efx_mcdi_req_t *emrp, 298 __out uint32_t *usec_timeoutp); 299 300 LIBEFX_API 301 extern void 302 efx_mcdi_request_start( 303 __in efx_nic_t *enp, 304 __in efx_mcdi_req_t *emrp, 305 __in boolean_t ev_cpl); 306 307 LIBEFX_API 308 extern __checkReturn boolean_t 309 efx_mcdi_request_poll( 310 __in efx_nic_t *enp); 311 312 LIBEFX_API 313 extern __checkReturn boolean_t 314 efx_mcdi_request_abort( 315 __in efx_nic_t *enp); 316 317 LIBEFX_API 318 extern void 319 efx_mcdi_fini( 320 __in efx_nic_t *enp); 321 322 #endif /* EFSYS_OPT_MCDI */ 323 324 /* INTR */ 325 326 #define EFX_NINTR_SIENA 1024 327 328 typedef enum efx_intr_type_e { 329 EFX_INTR_INVALID = 0, 330 EFX_INTR_LINE, 331 EFX_INTR_MESSAGE, 332 EFX_INTR_NTYPES 333 } efx_intr_type_t; 334 335 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 336 337 LIBEFX_API 338 extern __checkReturn efx_rc_t 339 efx_intr_init( 340 __in efx_nic_t *enp, 341 __in efx_intr_type_t type, 342 __in_opt efsys_mem_t *esmp); 343 344 LIBEFX_API 345 extern void 346 efx_intr_enable( 347 __in efx_nic_t *enp); 348 349 LIBEFX_API 350 extern void 351 efx_intr_disable( 352 __in efx_nic_t *enp); 353 354 LIBEFX_API 355 extern void 356 efx_intr_disable_unlocked( 357 __in efx_nic_t *enp); 358 359 #define EFX_INTR_NEVQS 32 360 361 LIBEFX_API 362 extern __checkReturn efx_rc_t 363 efx_intr_trigger( 364 __in efx_nic_t *enp, 365 __in unsigned int level); 366 367 LIBEFX_API 368 extern void 369 efx_intr_status_line( 370 __in efx_nic_t *enp, 371 __out boolean_t *fatalp, 372 __out uint32_t *maskp); 373 374 LIBEFX_API 375 extern void 376 efx_intr_status_message( 377 __in efx_nic_t *enp, 378 __in unsigned int message, 379 __out boolean_t *fatalp); 380 381 LIBEFX_API 382 extern void 383 efx_intr_fatal( 384 __in efx_nic_t *enp); 385 386 LIBEFX_API 387 extern void 388 efx_intr_fini( 389 __in efx_nic_t *enp); 390 391 /* MAC */ 392 393 #if EFSYS_OPT_MAC_STATS 394 395 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 396 typedef enum efx_mac_stat_e { 397 EFX_MAC_RX_OCTETS, 398 EFX_MAC_RX_PKTS, 399 EFX_MAC_RX_UNICST_PKTS, 400 EFX_MAC_RX_MULTICST_PKTS, 401 EFX_MAC_RX_BRDCST_PKTS, 402 EFX_MAC_RX_PAUSE_PKTS, 403 EFX_MAC_RX_LE_64_PKTS, 404 EFX_MAC_RX_65_TO_127_PKTS, 405 EFX_MAC_RX_128_TO_255_PKTS, 406 EFX_MAC_RX_256_TO_511_PKTS, 407 EFX_MAC_RX_512_TO_1023_PKTS, 408 EFX_MAC_RX_1024_TO_15XX_PKTS, 409 EFX_MAC_RX_GE_15XX_PKTS, 410 EFX_MAC_RX_ERRORS, 411 EFX_MAC_RX_FCS_ERRORS, 412 EFX_MAC_RX_DROP_EVENTS, 413 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 414 EFX_MAC_RX_SYMBOL_ERRORS, 415 EFX_MAC_RX_ALIGN_ERRORS, 416 EFX_MAC_RX_INTERNAL_ERRORS, 417 EFX_MAC_RX_JABBER_PKTS, 418 EFX_MAC_RX_LANE0_CHAR_ERR, 419 EFX_MAC_RX_LANE1_CHAR_ERR, 420 EFX_MAC_RX_LANE2_CHAR_ERR, 421 EFX_MAC_RX_LANE3_CHAR_ERR, 422 EFX_MAC_RX_LANE0_DISP_ERR, 423 EFX_MAC_RX_LANE1_DISP_ERR, 424 EFX_MAC_RX_LANE2_DISP_ERR, 425 EFX_MAC_RX_LANE3_DISP_ERR, 426 EFX_MAC_RX_MATCH_FAULT, 427 EFX_MAC_RX_NODESC_DROP_CNT, 428 EFX_MAC_TX_OCTETS, 429 EFX_MAC_TX_PKTS, 430 EFX_MAC_TX_UNICST_PKTS, 431 EFX_MAC_TX_MULTICST_PKTS, 432 EFX_MAC_TX_BRDCST_PKTS, 433 EFX_MAC_TX_PAUSE_PKTS, 434 EFX_MAC_TX_LE_64_PKTS, 435 EFX_MAC_TX_65_TO_127_PKTS, 436 EFX_MAC_TX_128_TO_255_PKTS, 437 EFX_MAC_TX_256_TO_511_PKTS, 438 EFX_MAC_TX_512_TO_1023_PKTS, 439 EFX_MAC_TX_1024_TO_15XX_PKTS, 440 EFX_MAC_TX_GE_15XX_PKTS, 441 EFX_MAC_TX_ERRORS, 442 EFX_MAC_TX_SGL_COL_PKTS, 443 EFX_MAC_TX_MULT_COL_PKTS, 444 EFX_MAC_TX_EX_COL_PKTS, 445 EFX_MAC_TX_LATE_COL_PKTS, 446 EFX_MAC_TX_DEF_PKTS, 447 EFX_MAC_TX_EX_DEF_PKTS, 448 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 449 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 450 EFX_MAC_PM_TRUNC_VFIFO_FULL, 451 EFX_MAC_PM_DISCARD_VFIFO_FULL, 452 EFX_MAC_PM_TRUNC_QBB, 453 EFX_MAC_PM_DISCARD_QBB, 454 EFX_MAC_PM_DISCARD_MAPPING, 455 EFX_MAC_RXDP_Q_DISABLED_PKTS, 456 EFX_MAC_RXDP_DI_DROPPED_PKTS, 457 EFX_MAC_RXDP_STREAMING_PKTS, 458 EFX_MAC_RXDP_HLB_FETCH, 459 EFX_MAC_RXDP_HLB_WAIT, 460 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 461 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 462 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 463 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 464 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 465 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 466 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 467 EFX_MAC_VADAPTER_RX_BAD_BYTES, 468 EFX_MAC_VADAPTER_RX_OVERFLOW, 469 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 470 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 471 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 472 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 473 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 474 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 475 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 476 EFX_MAC_VADAPTER_TX_BAD_BYTES, 477 EFX_MAC_VADAPTER_TX_OVERFLOW, 478 EFX_MAC_FEC_UNCORRECTED_ERRORS, 479 EFX_MAC_FEC_CORRECTED_ERRORS, 480 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 481 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 482 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 483 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 484 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 485 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 486 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 487 EFX_MAC_CTPIO_OVERFLOW_FAIL, 488 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 489 EFX_MAC_CTPIO_TIMEOUT_FAIL, 490 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 491 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 492 EFX_MAC_CTPIO_INVALID_WR_FAIL, 493 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 494 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 495 EFX_MAC_CTPIO_RUNT_FALLBACK, 496 EFX_MAC_CTPIO_SUCCESS, 497 EFX_MAC_CTPIO_FALLBACK, 498 EFX_MAC_CTPIO_POISON, 499 EFX_MAC_CTPIO_ERASE, 500 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 501 EFX_MAC_RXDP_HLB_IDLE, 502 EFX_MAC_RXDP_HLB_TIMEOUT, 503 EFX_MAC_NSTATS 504 } efx_mac_stat_t; 505 506 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 507 508 #endif /* EFSYS_OPT_MAC_STATS */ 509 510 typedef enum efx_link_mode_e { 511 EFX_LINK_UNKNOWN = 0, 512 EFX_LINK_DOWN, 513 EFX_LINK_10HDX, 514 EFX_LINK_10FDX, 515 EFX_LINK_100HDX, 516 EFX_LINK_100FDX, 517 EFX_LINK_1000HDX, 518 EFX_LINK_1000FDX, 519 EFX_LINK_10000FDX, 520 EFX_LINK_40000FDX, 521 EFX_LINK_25000FDX, 522 EFX_LINK_50000FDX, 523 EFX_LINK_100000FDX, 524 EFX_LINK_NMODES 525 } efx_link_mode_t; 526 527 #define EFX_MAC_ADDR_LEN 6 528 529 #define EFX_VNI_OR_VSID_LEN 3 530 531 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 532 533 #define EFX_MAC_MULTICAST_LIST_MAX 256 534 535 #define EFX_MAC_SDU_MAX 9202 536 537 #define EFX_MAC_PDU_ADJUSTMENT \ 538 (/* EtherII */ 14 \ 539 + /* VLAN */ 4 \ 540 + /* CRC */ 4 \ 541 + /* bug16011 */ 16) \ 542 543 #define EFX_MAC_PDU(_sdu) \ 544 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 545 546 /* 547 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 548 * the SDU rounded up slightly. 549 */ 550 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 551 552 #define EFX_MAC_PDU_MIN 60 553 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 554 555 LIBEFX_API 556 extern __checkReturn efx_rc_t 557 efx_mac_pdu_get( 558 __in efx_nic_t *enp, 559 __out size_t *pdu); 560 561 LIBEFX_API 562 extern __checkReturn efx_rc_t 563 efx_mac_pdu_set( 564 __in efx_nic_t *enp, 565 __in size_t pdu); 566 567 LIBEFX_API 568 extern __checkReturn efx_rc_t 569 efx_mac_addr_set( 570 __in efx_nic_t *enp, 571 __in uint8_t *addr); 572 573 LIBEFX_API 574 extern __checkReturn efx_rc_t 575 efx_mac_filter_set( 576 __in efx_nic_t *enp, 577 __in boolean_t all_unicst, 578 __in boolean_t mulcst, 579 __in boolean_t all_mulcst, 580 __in boolean_t brdcst); 581 582 LIBEFX_API 583 extern void 584 efx_mac_filter_get_all_ucast_mcast( 585 __in efx_nic_t *enp, 586 __out boolean_t *all_unicst, 587 __out boolean_t *all_mulcst); 588 589 LIBEFX_API 590 extern __checkReturn efx_rc_t 591 efx_mac_multicast_list_set( 592 __in efx_nic_t *enp, 593 __in_ecount(6*count) uint8_t const *addrs, 594 __in int count); 595 596 LIBEFX_API 597 extern __checkReturn efx_rc_t 598 efx_mac_filter_default_rxq_set( 599 __in efx_nic_t *enp, 600 __in efx_rxq_t *erp, 601 __in boolean_t using_rss); 602 603 LIBEFX_API 604 extern void 605 efx_mac_filter_default_rxq_clear( 606 __in efx_nic_t *enp); 607 608 LIBEFX_API 609 extern __checkReturn efx_rc_t 610 efx_mac_drain( 611 __in efx_nic_t *enp, 612 __in boolean_t enabled); 613 614 LIBEFX_API 615 extern __checkReturn efx_rc_t 616 efx_mac_up( 617 __in efx_nic_t *enp, 618 __out boolean_t *mac_upp); 619 620 #define EFX_FCNTL_RESPOND 0x00000001 621 #define EFX_FCNTL_GENERATE 0x00000002 622 623 LIBEFX_API 624 extern __checkReturn efx_rc_t 625 efx_mac_fcntl_set( 626 __in efx_nic_t *enp, 627 __in unsigned int fcntl, 628 __in boolean_t autoneg); 629 630 LIBEFX_API 631 extern void 632 efx_mac_fcntl_get( 633 __in efx_nic_t *enp, 634 __out unsigned int *fcntl_wantedp, 635 __out unsigned int *fcntl_linkp); 636 637 638 #if EFSYS_OPT_MAC_STATS 639 640 #if EFSYS_OPT_NAMES 641 642 LIBEFX_API 643 extern __checkReturn const char * 644 efx_mac_stat_name( 645 __in efx_nic_t *enp, 646 __in unsigned int id); 647 648 #endif /* EFSYS_OPT_NAMES */ 649 650 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 651 652 #define EFX_MAC_STATS_MASK_NPAGES \ 653 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 654 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 655 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 656 657 /* 658 * Get mask of MAC statistics supported by the hardware. 659 * 660 * If mask_size is insufficient to return the mask, EINVAL error is 661 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 662 * (which is sizeof (uint32_t)) is sufficient. 663 */ 664 LIBEFX_API 665 extern __checkReturn efx_rc_t 666 efx_mac_stats_get_mask( 667 __in efx_nic_t *enp, 668 __out_bcount(mask_size) uint32_t *maskp, 669 __in size_t mask_size); 670 671 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 672 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 673 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 674 675 676 LIBEFX_API 677 extern __checkReturn efx_rc_t 678 efx_mac_stats_clear( 679 __in efx_nic_t *enp); 680 681 /* 682 * Upload mac statistics supported by the hardware into the given buffer. 683 * 684 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 685 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 686 * 687 * The hardware will only DMA statistics that it understands (of course). 688 * Drivers should not make any assumptions about which statistics are 689 * supported, especially when the statistics are generated by firmware. 690 * 691 * Thus, drivers should zero this buffer before use, so that not-understood 692 * statistics read back as zero. 693 */ 694 LIBEFX_API 695 extern __checkReturn efx_rc_t 696 efx_mac_stats_upload( 697 __in efx_nic_t *enp, 698 __in efsys_mem_t *esmp); 699 700 LIBEFX_API 701 extern __checkReturn efx_rc_t 702 efx_mac_stats_periodic( 703 __in efx_nic_t *enp, 704 __in efsys_mem_t *esmp, 705 __in uint16_t period_ms, 706 __in boolean_t events); 707 708 LIBEFX_API 709 extern __checkReturn efx_rc_t 710 efx_mac_stats_update( 711 __in efx_nic_t *enp, 712 __in efsys_mem_t *esmp, 713 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 714 __inout_opt uint32_t *generationp); 715 716 #endif /* EFSYS_OPT_MAC_STATS */ 717 718 /* MON */ 719 720 typedef enum efx_mon_type_e { 721 EFX_MON_INVALID = 0, 722 EFX_MON_SFC90X0, 723 EFX_MON_SFC91X0, 724 EFX_MON_SFC92X0, 725 EFX_MON_NTYPES 726 } efx_mon_type_t; 727 728 #if EFSYS_OPT_NAMES 729 730 LIBEFX_API 731 extern const char * 732 efx_mon_name( 733 __in efx_nic_t *enp); 734 735 #endif /* EFSYS_OPT_NAMES */ 736 737 LIBEFX_API 738 extern __checkReturn efx_rc_t 739 efx_mon_init( 740 __in efx_nic_t *enp); 741 742 #if EFSYS_OPT_MON_STATS 743 744 #define EFX_MON_STATS_PAGE_SIZE 0x100 745 #define EFX_MON_MASK_ELEMENT_SIZE 32 746 747 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 748 typedef enum efx_mon_stat_e { 749 EFX_MON_STAT_CONTROLLER_TEMP, 750 EFX_MON_STAT_PHY_COMMON_TEMP, 751 EFX_MON_STAT_CONTROLLER_COOLING, 752 EFX_MON_STAT_PHY0_TEMP, 753 EFX_MON_STAT_PHY0_COOLING, 754 EFX_MON_STAT_PHY1_TEMP, 755 EFX_MON_STAT_PHY1_COOLING, 756 EFX_MON_STAT_IN_1V0, 757 EFX_MON_STAT_IN_1V2, 758 EFX_MON_STAT_IN_1V8, 759 EFX_MON_STAT_IN_2V5, 760 EFX_MON_STAT_IN_3V3, 761 EFX_MON_STAT_IN_12V0, 762 EFX_MON_STAT_IN_1V2A, 763 EFX_MON_STAT_IN_VREF, 764 EFX_MON_STAT_OUT_VAOE, 765 EFX_MON_STAT_AOE_TEMP, 766 EFX_MON_STAT_PSU_AOE_TEMP, 767 EFX_MON_STAT_PSU_TEMP, 768 EFX_MON_STAT_FAN_0, 769 EFX_MON_STAT_FAN_1, 770 EFX_MON_STAT_FAN_2, 771 EFX_MON_STAT_FAN_3, 772 EFX_MON_STAT_FAN_4, 773 EFX_MON_STAT_IN_VAOE, 774 EFX_MON_STAT_OUT_IAOE, 775 EFX_MON_STAT_IN_IAOE, 776 EFX_MON_STAT_NIC_POWER, 777 EFX_MON_STAT_IN_0V9, 778 EFX_MON_STAT_IN_I0V9, 779 EFX_MON_STAT_IN_I1V2, 780 EFX_MON_STAT_IN_0V9_ADC, 781 EFX_MON_STAT_CONTROLLER_2_TEMP, 782 EFX_MON_STAT_VREG_INTERNAL_TEMP, 783 EFX_MON_STAT_VREG_0V9_TEMP, 784 EFX_MON_STAT_VREG_1V2_TEMP, 785 EFX_MON_STAT_CONTROLLER_VPTAT, 786 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 787 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 788 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 789 EFX_MON_STAT_AMBIENT_TEMP, 790 EFX_MON_STAT_AIRFLOW, 791 EFX_MON_STAT_VDD08D_VSS08D_CSR, 792 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 793 EFX_MON_STAT_HOTPOINT_TEMP, 794 EFX_MON_STAT_PHY_POWER_PORT0, 795 EFX_MON_STAT_PHY_POWER_PORT1, 796 EFX_MON_STAT_MUM_VCC, 797 EFX_MON_STAT_IN_0V9_A, 798 EFX_MON_STAT_IN_I0V9_A, 799 EFX_MON_STAT_VREG_0V9_A_TEMP, 800 EFX_MON_STAT_IN_0V9_B, 801 EFX_MON_STAT_IN_I0V9_B, 802 EFX_MON_STAT_VREG_0V9_B_TEMP, 803 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 804 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 805 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 806 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 807 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 808 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 809 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 810 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 811 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 812 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 813 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 814 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 815 EFX_MON_STAT_SODIMM_VOUT, 816 EFX_MON_STAT_SODIMM_0_TEMP, 817 EFX_MON_STAT_SODIMM_1_TEMP, 818 EFX_MON_STAT_PHY0_VCC, 819 EFX_MON_STAT_PHY1_VCC, 820 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 821 EFX_MON_STAT_BOARD_FRONT_TEMP, 822 EFX_MON_STAT_BOARD_BACK_TEMP, 823 EFX_MON_STAT_IN_I1V8, 824 EFX_MON_STAT_IN_I2V5, 825 EFX_MON_STAT_IN_I3V3, 826 EFX_MON_STAT_IN_I12V0, 827 EFX_MON_STAT_IN_1V3, 828 EFX_MON_STAT_IN_I1V3, 829 EFX_MON_NSTATS 830 } efx_mon_stat_t; 831 832 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 833 834 typedef enum efx_mon_stat_state_e { 835 EFX_MON_STAT_STATE_OK = 0, 836 EFX_MON_STAT_STATE_WARNING = 1, 837 EFX_MON_STAT_STATE_FATAL = 2, 838 EFX_MON_STAT_STATE_BROKEN = 3, 839 EFX_MON_STAT_STATE_NO_READING = 4, 840 } efx_mon_stat_state_t; 841 842 typedef enum efx_mon_stat_unit_e { 843 EFX_MON_STAT_UNIT_UNKNOWN = 0, 844 EFX_MON_STAT_UNIT_BOOL, 845 EFX_MON_STAT_UNIT_TEMP_C, 846 EFX_MON_STAT_UNIT_VOLTAGE_MV, 847 EFX_MON_STAT_UNIT_CURRENT_MA, 848 EFX_MON_STAT_UNIT_POWER_W, 849 EFX_MON_STAT_UNIT_RPM, 850 EFX_MON_NUNITS 851 } efx_mon_stat_unit_t; 852 853 typedef struct efx_mon_stat_value_s { 854 uint16_t emsv_value; 855 efx_mon_stat_state_t emsv_state; 856 efx_mon_stat_unit_t emsv_unit; 857 } efx_mon_stat_value_t; 858 859 typedef struct efx_mon_limit_value_s { 860 uint16_t emlv_warning_min; 861 uint16_t emlv_warning_max; 862 uint16_t emlv_fatal_min; 863 uint16_t emlv_fatal_max; 864 } efx_mon_stat_limits_t; 865 866 typedef enum efx_mon_stat_portmask_e { 867 EFX_MON_STAT_PORTMAP_NONE = 0, 868 EFX_MON_STAT_PORTMAP_PORT0 = 1, 869 EFX_MON_STAT_PORTMAP_PORT1 = 2, 870 EFX_MON_STAT_PORTMAP_PORT2 = 3, 871 EFX_MON_STAT_PORTMAP_PORT3 = 4, 872 EFX_MON_STAT_PORTMAP_ALL = (-1), 873 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 874 } efx_mon_stat_portmask_t; 875 876 #if EFSYS_OPT_NAMES 877 878 LIBEFX_API 879 extern const char * 880 efx_mon_stat_name( 881 __in efx_nic_t *enp, 882 __in efx_mon_stat_t id); 883 884 LIBEFX_API 885 extern const char * 886 efx_mon_stat_description( 887 __in efx_nic_t *enp, 888 __in efx_mon_stat_t id); 889 890 #endif /* EFSYS_OPT_NAMES */ 891 892 LIBEFX_API 893 extern __checkReturn boolean_t 894 efx_mon_mcdi_to_efx_stat( 895 __in int mcdi_index, 896 __out efx_mon_stat_t *statp); 897 898 LIBEFX_API 899 extern __checkReturn boolean_t 900 efx_mon_get_stat_unit( 901 __in efx_mon_stat_t stat, 902 __out efx_mon_stat_unit_t *unitp); 903 904 LIBEFX_API 905 extern __checkReturn boolean_t 906 efx_mon_get_stat_portmap( 907 __in efx_mon_stat_t stat, 908 __out efx_mon_stat_portmask_t *maskp); 909 910 LIBEFX_API 911 extern __checkReturn efx_rc_t 912 efx_mon_stats_update( 913 __in efx_nic_t *enp, 914 __in efsys_mem_t *esmp, 915 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 916 917 LIBEFX_API 918 extern __checkReturn efx_rc_t 919 efx_mon_limits_update( 920 __in efx_nic_t *enp, 921 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 922 923 #endif /* EFSYS_OPT_MON_STATS */ 924 925 LIBEFX_API 926 extern void 927 efx_mon_fini( 928 __in efx_nic_t *enp); 929 930 /* PHY */ 931 932 LIBEFX_API 933 extern __checkReturn efx_rc_t 934 efx_phy_verify( 935 __in efx_nic_t *enp); 936 937 #if EFSYS_OPT_PHY_LED_CONTROL 938 939 typedef enum efx_phy_led_mode_e { 940 EFX_PHY_LED_DEFAULT = 0, 941 EFX_PHY_LED_OFF, 942 EFX_PHY_LED_ON, 943 EFX_PHY_LED_FLASH, 944 EFX_PHY_LED_NMODES 945 } efx_phy_led_mode_t; 946 947 LIBEFX_API 948 extern __checkReturn efx_rc_t 949 efx_phy_led_set( 950 __in efx_nic_t *enp, 951 __in efx_phy_led_mode_t mode); 952 953 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 954 955 LIBEFX_API 956 extern __checkReturn efx_rc_t 957 efx_port_init( 958 __in efx_nic_t *enp); 959 960 #if EFSYS_OPT_LOOPBACK 961 962 typedef enum efx_loopback_type_e { 963 EFX_LOOPBACK_OFF = 0, 964 EFX_LOOPBACK_DATA = 1, 965 EFX_LOOPBACK_GMAC = 2, 966 EFX_LOOPBACK_XGMII = 3, 967 EFX_LOOPBACK_XGXS = 4, 968 EFX_LOOPBACK_XAUI = 5, 969 EFX_LOOPBACK_GMII = 6, 970 EFX_LOOPBACK_SGMII = 7, 971 EFX_LOOPBACK_XGBR = 8, 972 EFX_LOOPBACK_XFI = 9, 973 EFX_LOOPBACK_XAUI_FAR = 10, 974 EFX_LOOPBACK_GMII_FAR = 11, 975 EFX_LOOPBACK_SGMII_FAR = 12, 976 EFX_LOOPBACK_XFI_FAR = 13, 977 EFX_LOOPBACK_GPHY = 14, 978 EFX_LOOPBACK_PHY_XS = 15, 979 EFX_LOOPBACK_PCS = 16, 980 EFX_LOOPBACK_PMA_PMD = 17, 981 EFX_LOOPBACK_XPORT = 18, 982 EFX_LOOPBACK_XGMII_WS = 19, 983 EFX_LOOPBACK_XAUI_WS = 20, 984 EFX_LOOPBACK_XAUI_WS_FAR = 21, 985 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 986 EFX_LOOPBACK_GMII_WS = 23, 987 EFX_LOOPBACK_XFI_WS = 24, 988 EFX_LOOPBACK_XFI_WS_FAR = 25, 989 EFX_LOOPBACK_PHYXS_WS = 26, 990 EFX_LOOPBACK_PMA_INT = 27, 991 EFX_LOOPBACK_SD_NEAR = 28, 992 EFX_LOOPBACK_SD_FAR = 29, 993 EFX_LOOPBACK_PMA_INT_WS = 30, 994 EFX_LOOPBACK_SD_FEP2_WS = 31, 995 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 996 EFX_LOOPBACK_SD_FEP_WS = 33, 997 EFX_LOOPBACK_SD_FES_WS = 34, 998 EFX_LOOPBACK_AOE_INT_NEAR = 35, 999 EFX_LOOPBACK_DATA_WS = 36, 1000 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 1001 EFX_LOOPBACK_NTYPES 1002 } efx_loopback_type_t; 1003 1004 typedef enum efx_loopback_kind_e { 1005 EFX_LOOPBACK_KIND_OFF = 0, 1006 EFX_LOOPBACK_KIND_ALL, 1007 EFX_LOOPBACK_KIND_MAC, 1008 EFX_LOOPBACK_KIND_PHY, 1009 EFX_LOOPBACK_NKINDS 1010 } efx_loopback_kind_t; 1011 1012 LIBEFX_API 1013 extern void 1014 efx_loopback_mask( 1015 __in efx_loopback_kind_t loopback_kind, 1016 __out efx_qword_t *maskp); 1017 1018 LIBEFX_API 1019 extern __checkReturn efx_rc_t 1020 efx_port_loopback_set( 1021 __in efx_nic_t *enp, 1022 __in efx_link_mode_t link_mode, 1023 __in efx_loopback_type_t type); 1024 1025 #if EFSYS_OPT_NAMES 1026 1027 LIBEFX_API 1028 extern __checkReturn const char * 1029 efx_loopback_type_name( 1030 __in efx_nic_t *enp, 1031 __in efx_loopback_type_t type); 1032 1033 #endif /* EFSYS_OPT_NAMES */ 1034 1035 #endif /* EFSYS_OPT_LOOPBACK */ 1036 1037 LIBEFX_API 1038 extern __checkReturn efx_rc_t 1039 efx_port_poll( 1040 __in efx_nic_t *enp, 1041 __out_opt efx_link_mode_t *link_modep); 1042 1043 LIBEFX_API 1044 extern void 1045 efx_port_fini( 1046 __in efx_nic_t *enp); 1047 1048 typedef enum efx_phy_cap_type_e { 1049 EFX_PHY_CAP_INVALID = 0, 1050 EFX_PHY_CAP_10HDX, 1051 EFX_PHY_CAP_10FDX, 1052 EFX_PHY_CAP_100HDX, 1053 EFX_PHY_CAP_100FDX, 1054 EFX_PHY_CAP_1000HDX, 1055 EFX_PHY_CAP_1000FDX, 1056 EFX_PHY_CAP_10000FDX, 1057 EFX_PHY_CAP_PAUSE, 1058 EFX_PHY_CAP_ASYM, 1059 EFX_PHY_CAP_AN, 1060 EFX_PHY_CAP_40000FDX, 1061 EFX_PHY_CAP_DDM, 1062 EFX_PHY_CAP_100000FDX, 1063 EFX_PHY_CAP_25000FDX, 1064 EFX_PHY_CAP_50000FDX, 1065 EFX_PHY_CAP_BASER_FEC, 1066 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1067 EFX_PHY_CAP_RS_FEC, 1068 EFX_PHY_CAP_RS_FEC_REQUESTED, 1069 EFX_PHY_CAP_25G_BASER_FEC, 1070 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1071 EFX_PHY_CAP_NTYPES 1072 } efx_phy_cap_type_t; 1073 1074 1075 #define EFX_PHY_CAP_CURRENT 0x00000000 1076 #define EFX_PHY_CAP_DEFAULT 0x00000001 1077 #define EFX_PHY_CAP_PERM 0x00000002 1078 1079 LIBEFX_API 1080 extern void 1081 efx_phy_adv_cap_get( 1082 __in efx_nic_t *enp, 1083 __in uint32_t flag, 1084 __out uint32_t *maskp); 1085 1086 LIBEFX_API 1087 extern __checkReturn efx_rc_t 1088 efx_phy_adv_cap_set( 1089 __in efx_nic_t *enp, 1090 __in uint32_t mask); 1091 1092 LIBEFX_API 1093 extern void 1094 efx_phy_lp_cap_get( 1095 __in efx_nic_t *enp, 1096 __out uint32_t *maskp); 1097 1098 LIBEFX_API 1099 extern __checkReturn efx_rc_t 1100 efx_phy_oui_get( 1101 __in efx_nic_t *enp, 1102 __out uint32_t *ouip); 1103 1104 typedef enum efx_phy_media_type_e { 1105 EFX_PHY_MEDIA_INVALID = 0, 1106 EFX_PHY_MEDIA_XAUI, 1107 EFX_PHY_MEDIA_CX4, 1108 EFX_PHY_MEDIA_KX4, 1109 EFX_PHY_MEDIA_XFP, 1110 EFX_PHY_MEDIA_SFP_PLUS, 1111 EFX_PHY_MEDIA_BASE_T, 1112 EFX_PHY_MEDIA_QSFP_PLUS, 1113 EFX_PHY_MEDIA_NTYPES 1114 } efx_phy_media_type_t; 1115 1116 /* 1117 * Get the type of medium currently used. If the board has ports for 1118 * modules, a module is present, and we recognise the media type of 1119 * the module, then this will be the media type of the module. 1120 * Otherwise it will be the media type of the port. 1121 */ 1122 LIBEFX_API 1123 extern void 1124 efx_phy_media_type_get( 1125 __in efx_nic_t *enp, 1126 __out efx_phy_media_type_t *typep); 1127 1128 /* 1129 * 2-wire device address of the base information in accordance with SFF-8472 1130 * Diagnostic Monitoring Interface for Optical Transceivers section 1131 * 4 Memory Organization. 1132 */ 1133 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1134 1135 /* 1136 * 2-wire device address of the digital diagnostics monitoring interface 1137 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1138 * Transceivers section 4 Memory Organization. 1139 */ 1140 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1141 1142 /* 1143 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1144 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1145 * Operation. 1146 */ 1147 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1148 1149 /* 1150 * Maximum accessible data offset for PHY module information. 1151 */ 1152 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1153 1154 1155 LIBEFX_API 1156 extern __checkReturn efx_rc_t 1157 efx_phy_module_get_info( 1158 __in efx_nic_t *enp, 1159 __in uint8_t dev_addr, 1160 __in size_t offset, 1161 __in size_t len, 1162 __out_bcount(len) uint8_t *data); 1163 1164 #if EFSYS_OPT_PHY_STATS 1165 1166 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1167 typedef enum efx_phy_stat_e { 1168 EFX_PHY_STAT_OUI, 1169 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1170 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1171 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1172 EFX_PHY_STAT_PMA_PMD_REV_A, 1173 EFX_PHY_STAT_PMA_PMD_REV_B, 1174 EFX_PHY_STAT_PMA_PMD_REV_C, 1175 EFX_PHY_STAT_PMA_PMD_REV_D, 1176 EFX_PHY_STAT_PCS_LINK_UP, 1177 EFX_PHY_STAT_PCS_RX_FAULT, 1178 EFX_PHY_STAT_PCS_TX_FAULT, 1179 EFX_PHY_STAT_PCS_BER, 1180 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1181 EFX_PHY_STAT_PHY_XS_LINK_UP, 1182 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1183 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1184 EFX_PHY_STAT_PHY_XS_ALIGN, 1185 EFX_PHY_STAT_PHY_XS_SYNC_A, 1186 EFX_PHY_STAT_PHY_XS_SYNC_B, 1187 EFX_PHY_STAT_PHY_XS_SYNC_C, 1188 EFX_PHY_STAT_PHY_XS_SYNC_D, 1189 EFX_PHY_STAT_AN_LINK_UP, 1190 EFX_PHY_STAT_AN_MASTER, 1191 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1192 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1193 EFX_PHY_STAT_CL22EXT_LINK_UP, 1194 EFX_PHY_STAT_SNR_A, 1195 EFX_PHY_STAT_SNR_B, 1196 EFX_PHY_STAT_SNR_C, 1197 EFX_PHY_STAT_SNR_D, 1198 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1199 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1200 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1201 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1202 EFX_PHY_STAT_AN_COMPLETE, 1203 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1204 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1205 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1206 EFX_PHY_STAT_PCS_FW_VERSION_0, 1207 EFX_PHY_STAT_PCS_FW_VERSION_1, 1208 EFX_PHY_STAT_PCS_FW_VERSION_2, 1209 EFX_PHY_STAT_PCS_FW_VERSION_3, 1210 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1211 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1212 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1213 EFX_PHY_STAT_PCS_OP_MODE, 1214 EFX_PHY_NSTATS 1215 } efx_phy_stat_t; 1216 1217 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1218 1219 #if EFSYS_OPT_NAMES 1220 1221 LIBEFX_API 1222 extern const char * 1223 efx_phy_stat_name( 1224 __in efx_nic_t *enp, 1225 __in efx_phy_stat_t stat); 1226 1227 #endif /* EFSYS_OPT_NAMES */ 1228 1229 #define EFX_PHY_STATS_SIZE 0x100 1230 1231 LIBEFX_API 1232 extern __checkReturn efx_rc_t 1233 efx_phy_stats_update( 1234 __in efx_nic_t *enp, 1235 __in efsys_mem_t *esmp, 1236 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1237 1238 #endif /* EFSYS_OPT_PHY_STATS */ 1239 1240 1241 #if EFSYS_OPT_BIST 1242 1243 typedef enum efx_bist_type_e { 1244 EFX_BIST_TYPE_UNKNOWN, 1245 EFX_BIST_TYPE_PHY_NORMAL, 1246 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1247 EFX_BIST_TYPE_PHY_CABLE_LONG, 1248 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1249 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1250 EFX_BIST_TYPE_REG, /* Test the register memories */ 1251 EFX_BIST_TYPE_NTYPES, 1252 } efx_bist_type_t; 1253 1254 typedef enum efx_bist_result_e { 1255 EFX_BIST_RESULT_UNKNOWN, 1256 EFX_BIST_RESULT_RUNNING, 1257 EFX_BIST_RESULT_PASSED, 1258 EFX_BIST_RESULT_FAILED, 1259 } efx_bist_result_t; 1260 1261 typedef enum efx_phy_cable_status_e { 1262 EFX_PHY_CABLE_STATUS_OK, 1263 EFX_PHY_CABLE_STATUS_INVALID, 1264 EFX_PHY_CABLE_STATUS_OPEN, 1265 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1266 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1267 EFX_PHY_CABLE_STATUS_BUSY, 1268 } efx_phy_cable_status_t; 1269 1270 typedef enum efx_bist_value_e { 1271 EFX_BIST_PHY_CABLE_LENGTH_A, 1272 EFX_BIST_PHY_CABLE_LENGTH_B, 1273 EFX_BIST_PHY_CABLE_LENGTH_C, 1274 EFX_BIST_PHY_CABLE_LENGTH_D, 1275 EFX_BIST_PHY_CABLE_STATUS_A, 1276 EFX_BIST_PHY_CABLE_STATUS_B, 1277 EFX_BIST_PHY_CABLE_STATUS_C, 1278 EFX_BIST_PHY_CABLE_STATUS_D, 1279 EFX_BIST_FAULT_CODE, 1280 /* 1281 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1282 * response. 1283 */ 1284 EFX_BIST_MEM_TEST, 1285 EFX_BIST_MEM_ADDR, 1286 EFX_BIST_MEM_BUS, 1287 EFX_BIST_MEM_EXPECT, 1288 EFX_BIST_MEM_ACTUAL, 1289 EFX_BIST_MEM_ECC, 1290 EFX_BIST_MEM_ECC_PARITY, 1291 EFX_BIST_MEM_ECC_FATAL, 1292 EFX_BIST_NVALUES, 1293 } efx_bist_value_t; 1294 1295 LIBEFX_API 1296 extern __checkReturn efx_rc_t 1297 efx_bist_enable_offline( 1298 __in efx_nic_t *enp); 1299 1300 LIBEFX_API 1301 extern __checkReturn efx_rc_t 1302 efx_bist_start( 1303 __in efx_nic_t *enp, 1304 __in efx_bist_type_t type); 1305 1306 LIBEFX_API 1307 extern __checkReturn efx_rc_t 1308 efx_bist_poll( 1309 __in efx_nic_t *enp, 1310 __in efx_bist_type_t type, 1311 __out efx_bist_result_t *resultp, 1312 __out_opt uint32_t *value_maskp, 1313 __out_ecount_opt(count) unsigned long *valuesp, 1314 __in size_t count); 1315 1316 LIBEFX_API 1317 extern void 1318 efx_bist_stop( 1319 __in efx_nic_t *enp, 1320 __in efx_bist_type_t type); 1321 1322 #endif /* EFSYS_OPT_BIST */ 1323 1324 #define EFX_FEATURE_IPV6 0x00000001 1325 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1326 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1327 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1328 #define EFX_FEATURE_MCDI 0x00000020 1329 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1330 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1331 #define EFX_FEATURE_TURBO 0x00000100 1332 #define EFX_FEATURE_MCDI_DMA 0x00000200 1333 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1334 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1335 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1336 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1337 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1338 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1339 1340 typedef enum efx_tunnel_protocol_e { 1341 EFX_TUNNEL_PROTOCOL_NONE = 0, 1342 EFX_TUNNEL_PROTOCOL_VXLAN, 1343 EFX_TUNNEL_PROTOCOL_GENEVE, 1344 EFX_TUNNEL_PROTOCOL_NVGRE, 1345 EFX_TUNNEL_NPROTOS 1346 } efx_tunnel_protocol_t; 1347 1348 typedef enum efx_vi_window_shift_e { 1349 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1350 EFX_VI_WINDOW_SHIFT_8K = 13, 1351 EFX_VI_WINDOW_SHIFT_16K = 14, 1352 EFX_VI_WINDOW_SHIFT_64K = 16, 1353 } efx_vi_window_shift_t; 1354 1355 typedef struct efx_nic_cfg_s { 1356 uint32_t enc_board_type; 1357 uint32_t enc_phy_type; 1358 #if EFSYS_OPT_NAMES 1359 char enc_phy_name[21]; 1360 #endif 1361 char enc_phy_revision[21]; 1362 efx_mon_type_t enc_mon_type; 1363 #if EFSYS_OPT_MON_STATS 1364 uint32_t enc_mon_stat_dma_buf_size; 1365 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1366 #endif 1367 unsigned int enc_features; 1368 efx_vi_window_shift_t enc_vi_window_shift; 1369 uint8_t enc_mac_addr[6]; 1370 uint8_t enc_port; /* PHY port number */ 1371 uint32_t enc_intr_vec_base; 1372 uint32_t enc_intr_limit; 1373 uint32_t enc_evq_limit; 1374 uint32_t enc_txq_limit; 1375 uint32_t enc_rxq_limit; 1376 uint32_t enc_evq_max_nevs; 1377 uint32_t enc_evq_min_nevs; 1378 uint32_t enc_rxq_max_ndescs; 1379 uint32_t enc_rxq_min_ndescs; 1380 uint32_t enc_txq_max_ndescs; 1381 uint32_t enc_txq_min_ndescs; 1382 uint32_t enc_buftbl_limit; 1383 uint32_t enc_piobuf_limit; 1384 uint32_t enc_piobuf_size; 1385 uint32_t enc_piobuf_min_alloc_size; 1386 uint32_t enc_evq_timer_quantum_ns; 1387 uint32_t enc_evq_timer_max_us; 1388 uint32_t enc_clk_mult; 1389 uint32_t enc_ev_desc_size; 1390 uint32_t enc_rx_desc_size; 1391 uint32_t enc_tx_desc_size; 1392 uint32_t enc_rx_prefix_size; 1393 uint32_t enc_rx_buf_align_start; 1394 uint32_t enc_rx_buf_align_end; 1395 #if EFSYS_OPT_RX_SCALE 1396 uint32_t enc_rx_scale_max_exclusive_contexts; 1397 /* 1398 * Mask of supported hash algorithms. 1399 * Hash algorithm types are used as the bit indices. 1400 */ 1401 uint32_t enc_rx_scale_hash_alg_mask; 1402 /* 1403 * Indicates whether port numbers can be included to the 1404 * input data for hash computation. 1405 */ 1406 boolean_t enc_rx_scale_l4_hash_supported; 1407 boolean_t enc_rx_scale_additional_modes_supported; 1408 #endif /* EFSYS_OPT_RX_SCALE */ 1409 #if EFSYS_OPT_LOOPBACK 1410 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1411 #endif /* EFSYS_OPT_LOOPBACK */ 1412 #if EFSYS_OPT_PHY_FLAGS 1413 uint32_t enc_phy_flags_mask; 1414 #endif /* EFSYS_OPT_PHY_FLAGS */ 1415 #if EFSYS_OPT_PHY_LED_CONTROL 1416 uint32_t enc_led_mask; 1417 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1418 #if EFSYS_OPT_PHY_STATS 1419 uint64_t enc_phy_stat_mask; 1420 #endif /* EFSYS_OPT_PHY_STATS */ 1421 #if EFSYS_OPT_MCDI 1422 uint8_t enc_mcdi_mdio_channel; 1423 #if EFSYS_OPT_PHY_STATS 1424 uint32_t enc_mcdi_phy_stat_mask; 1425 #endif /* EFSYS_OPT_PHY_STATS */ 1426 #if EFSYS_OPT_MON_STATS 1427 uint32_t *enc_mcdi_sensor_maskp; 1428 uint32_t enc_mcdi_sensor_mask_size; 1429 #endif /* EFSYS_OPT_MON_STATS */ 1430 #endif /* EFSYS_OPT_MCDI */ 1431 #if EFSYS_OPT_BIST 1432 uint32_t enc_bist_mask; 1433 #endif /* EFSYS_OPT_BIST */ 1434 #if EFX_OPTS_EF10() 1435 uint32_t enc_pf; 1436 uint32_t enc_vf; 1437 uint32_t enc_privilege_mask; 1438 #endif /* EFX_OPTS_EF10() */ 1439 boolean_t enc_bug26807_workaround; 1440 boolean_t enc_bug35388_workaround; 1441 boolean_t enc_bug41750_workaround; 1442 boolean_t enc_bug61265_workaround; 1443 boolean_t enc_bug61297_workaround; 1444 boolean_t enc_rx_batching_enabled; 1445 /* Maximum number of descriptors completed in an rx event. */ 1446 uint32_t enc_rx_batch_max; 1447 /* Number of rx descriptors the hardware requires for a push. */ 1448 uint32_t enc_rx_push_align; 1449 /* Maximum amount of data in DMA descriptor */ 1450 uint32_t enc_tx_dma_desc_size_max; 1451 /* 1452 * Boundary which DMA descriptor data must not cross or 0 if no 1453 * limitation. 1454 */ 1455 uint32_t enc_tx_dma_desc_boundary; 1456 /* 1457 * Maximum number of bytes into the packet the TCP header can start for 1458 * the hardware to apply TSO packet edits. 1459 */ 1460 uint32_t enc_tx_tso_tcp_header_offset_limit; 1461 boolean_t enc_fw_assisted_tso_enabled; 1462 boolean_t enc_fw_assisted_tso_v2_enabled; 1463 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1464 /* Number of TSO contexts on the NIC (FATSOv2) */ 1465 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1466 boolean_t enc_hw_tx_insert_vlan_enabled; 1467 /* Number of PFs on the NIC */ 1468 uint32_t enc_hw_pf_count; 1469 /* Datapath firmware vadapter/vport/vswitch support */ 1470 boolean_t enc_datapath_cap_evb; 1471 /* Datapath firmware vport reconfigure support */ 1472 boolean_t enc_vport_reconfigure_supported; 1473 boolean_t enc_rx_disable_scatter_supported; 1474 boolean_t enc_allow_set_mac_with_installed_filters; 1475 boolean_t enc_enhanced_set_mac_supported; 1476 boolean_t enc_init_evq_v2_supported; 1477 boolean_t enc_no_cont_ev_mode_supported; 1478 boolean_t enc_init_rxq_with_buffer_size; 1479 boolean_t enc_rx_packed_stream_supported; 1480 boolean_t enc_rx_var_packed_stream_supported; 1481 boolean_t enc_rx_es_super_buffer_supported; 1482 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1483 boolean_t enc_pm_and_rxdp_counters; 1484 boolean_t enc_mac_stats_40g_tx_size_bins; 1485 uint32_t enc_tunnel_encapsulations_supported; 1486 /* 1487 * NIC global maximum for unique UDP tunnel ports shared by all 1488 * functions. 1489 */ 1490 uint32_t enc_tunnel_config_udp_entries_max; 1491 /* External port identifier */ 1492 uint8_t enc_external_port; 1493 uint32_t enc_mcdi_max_payload_length; 1494 /* VPD may be per-PF or global */ 1495 boolean_t enc_vpd_is_global; 1496 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1497 uint32_t enc_required_pcie_bandwidth_mbps; 1498 uint32_t enc_max_pcie_link_gen; 1499 /* Firmware verifies integrity of NVRAM updates */ 1500 boolean_t enc_nvram_update_verify_result_supported; 1501 /* Firmware supports polled NVRAM updates on select partitions */ 1502 boolean_t enc_nvram_update_poll_verify_result_supported; 1503 /* Firmware accepts updates via the BUNDLE partition */ 1504 boolean_t enc_nvram_bundle_update_supported; 1505 /* Firmware support for extended MAC_STATS buffer */ 1506 uint32_t enc_mac_stats_nstats; 1507 boolean_t enc_fec_counters; 1508 boolean_t enc_hlb_counters; 1509 /* Firmware support for "FLAG" and "MARK" filter actions */ 1510 boolean_t enc_filter_action_flag_supported; 1511 boolean_t enc_filter_action_mark_supported; 1512 uint32_t enc_filter_action_mark_max; 1513 /* Port assigned to this PCI function */ 1514 uint32_t enc_assigned_port; 1515 } efx_nic_cfg_t; 1516 1517 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ 1518 ((configp)->evc_function == 0xffff) 1519 1520 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1521 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1522 1523 #define EFX_PCI_FUNCTION(_encp) \ 1524 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1525 1526 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1527 1528 LIBEFX_API 1529 extern const efx_nic_cfg_t * 1530 efx_nic_cfg_get( 1531 __in const efx_nic_t *enp); 1532 1533 /* RxDPCPU firmware id values by which FW variant can be identified */ 1534 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1535 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1536 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1537 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1538 #define EFX_RXDP_DPDK_FW_ID 0x6 1539 1540 typedef struct efx_nic_fw_info_s { 1541 /* Basic FW version information */ 1542 uint16_t enfi_mc_fw_version[4]; 1543 /* 1544 * If datapath capabilities can be detected, 1545 * additional FW information is to be shown 1546 */ 1547 boolean_t enfi_dpcpu_fw_ids_valid; 1548 /* Rx and Tx datapath CPU FW IDs */ 1549 uint16_t enfi_rx_dpcpu_fw_id; 1550 uint16_t enfi_tx_dpcpu_fw_id; 1551 } efx_nic_fw_info_t; 1552 1553 LIBEFX_API 1554 extern __checkReturn efx_rc_t 1555 efx_nic_get_fw_version( 1556 __in efx_nic_t *enp, 1557 __out efx_nic_fw_info_t *enfip); 1558 1559 /* Driver resource limits (minimum required/maximum usable). */ 1560 typedef struct efx_drv_limits_s { 1561 uint32_t edl_min_evq_count; 1562 uint32_t edl_max_evq_count; 1563 1564 uint32_t edl_min_rxq_count; 1565 uint32_t edl_max_rxq_count; 1566 1567 uint32_t edl_min_txq_count; 1568 uint32_t edl_max_txq_count; 1569 1570 /* PIO blocks (sub-allocated from piobuf) */ 1571 uint32_t edl_min_pio_alloc_size; 1572 uint32_t edl_max_pio_alloc_count; 1573 } efx_drv_limits_t; 1574 1575 LIBEFX_API 1576 extern __checkReturn efx_rc_t 1577 efx_nic_set_drv_limits( 1578 __inout efx_nic_t *enp, 1579 __in efx_drv_limits_t *edlp); 1580 1581 /* 1582 * Register the OS driver version string for management agents 1583 * (e.g. via NC-SI). The content length is provided (i.e. no 1584 * NUL terminator). Use length 0 to indicate no version string 1585 * should be advertised. It is valid to set the version string 1586 * only before efx_nic_probe() is called. 1587 */ 1588 LIBEFX_API 1589 extern __checkReturn efx_rc_t 1590 efx_nic_set_drv_version( 1591 __inout efx_nic_t *enp, 1592 __in_ecount(length) char const *verp, 1593 __in size_t length); 1594 1595 typedef enum efx_nic_region_e { 1596 EFX_REGION_VI, /* Memory BAR UC mapping */ 1597 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1598 } efx_nic_region_t; 1599 1600 LIBEFX_API 1601 extern __checkReturn efx_rc_t 1602 efx_nic_get_bar_region( 1603 __in efx_nic_t *enp, 1604 __in efx_nic_region_t region, 1605 __out uint32_t *offsetp, 1606 __out size_t *sizep); 1607 1608 LIBEFX_API 1609 extern __checkReturn efx_rc_t 1610 efx_nic_get_vi_pool( 1611 __in efx_nic_t *enp, 1612 __out uint32_t *evq_countp, 1613 __out uint32_t *rxq_countp, 1614 __out uint32_t *txq_countp); 1615 1616 1617 #if EFSYS_OPT_VPD 1618 1619 typedef enum efx_vpd_tag_e { 1620 EFX_VPD_ID = 0x02, 1621 EFX_VPD_END = 0x0f, 1622 EFX_VPD_RO = 0x10, 1623 EFX_VPD_RW = 0x11, 1624 } efx_vpd_tag_t; 1625 1626 typedef uint16_t efx_vpd_keyword_t; 1627 1628 typedef struct efx_vpd_value_s { 1629 efx_vpd_tag_t evv_tag; 1630 efx_vpd_keyword_t evv_keyword; 1631 uint8_t evv_length; 1632 uint8_t evv_value[0x100]; 1633 } efx_vpd_value_t; 1634 1635 1636 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1637 1638 LIBEFX_API 1639 extern __checkReturn efx_rc_t 1640 efx_vpd_init( 1641 __in efx_nic_t *enp); 1642 1643 LIBEFX_API 1644 extern __checkReturn efx_rc_t 1645 efx_vpd_size( 1646 __in efx_nic_t *enp, 1647 __out size_t *sizep); 1648 1649 LIBEFX_API 1650 extern __checkReturn efx_rc_t 1651 efx_vpd_read( 1652 __in efx_nic_t *enp, 1653 __out_bcount(size) caddr_t data, 1654 __in size_t size); 1655 1656 LIBEFX_API 1657 extern __checkReturn efx_rc_t 1658 efx_vpd_verify( 1659 __in efx_nic_t *enp, 1660 __in_bcount(size) caddr_t data, 1661 __in size_t size); 1662 1663 LIBEFX_API 1664 extern __checkReturn efx_rc_t 1665 efx_vpd_reinit( 1666 __in efx_nic_t *enp, 1667 __in_bcount(size) caddr_t data, 1668 __in size_t size); 1669 1670 LIBEFX_API 1671 extern __checkReturn efx_rc_t 1672 efx_vpd_get( 1673 __in efx_nic_t *enp, 1674 __in_bcount(size) caddr_t data, 1675 __in size_t size, 1676 __inout efx_vpd_value_t *evvp); 1677 1678 LIBEFX_API 1679 extern __checkReturn efx_rc_t 1680 efx_vpd_set( 1681 __in efx_nic_t *enp, 1682 __inout_bcount(size) caddr_t data, 1683 __in size_t size, 1684 __in efx_vpd_value_t *evvp); 1685 1686 LIBEFX_API 1687 extern __checkReturn efx_rc_t 1688 efx_vpd_next( 1689 __in efx_nic_t *enp, 1690 __inout_bcount(size) caddr_t data, 1691 __in size_t size, 1692 __out efx_vpd_value_t *evvp, 1693 __inout unsigned int *contp); 1694 1695 LIBEFX_API 1696 extern __checkReturn efx_rc_t 1697 efx_vpd_write( 1698 __in efx_nic_t *enp, 1699 __in_bcount(size) caddr_t data, 1700 __in size_t size); 1701 1702 LIBEFX_API 1703 extern void 1704 efx_vpd_fini( 1705 __in efx_nic_t *enp); 1706 1707 #endif /* EFSYS_OPT_VPD */ 1708 1709 /* NVRAM */ 1710 1711 #if EFSYS_OPT_NVRAM 1712 1713 typedef enum efx_nvram_type_e { 1714 EFX_NVRAM_INVALID = 0, 1715 EFX_NVRAM_BOOTROM, 1716 EFX_NVRAM_BOOTROM_CFG, 1717 EFX_NVRAM_MC_FIRMWARE, 1718 EFX_NVRAM_MC_GOLDEN, 1719 EFX_NVRAM_PHY, 1720 EFX_NVRAM_NULLPHY, 1721 EFX_NVRAM_FPGA, 1722 EFX_NVRAM_FCFW, 1723 EFX_NVRAM_CPLD, 1724 EFX_NVRAM_FPGA_BACKUP, 1725 EFX_NVRAM_DYNAMIC_CFG, 1726 EFX_NVRAM_LICENSE, 1727 EFX_NVRAM_UEFIROM, 1728 EFX_NVRAM_MUM_FIRMWARE, 1729 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1730 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1731 EFX_NVRAM_BUNDLE, 1732 EFX_NVRAM_BUNDLE_METADATA, 1733 EFX_NVRAM_NTYPES, 1734 } efx_nvram_type_t; 1735 1736 typedef struct efx_nvram_info_s { 1737 uint32_t eni_flags; 1738 uint32_t eni_partn_size; 1739 uint32_t eni_address; 1740 uint32_t eni_erase_size; 1741 uint32_t eni_write_size; 1742 } efx_nvram_info_t; 1743 1744 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) 1745 1746 LIBEFX_API 1747 extern __checkReturn efx_rc_t 1748 efx_nvram_init( 1749 __in efx_nic_t *enp); 1750 1751 #if EFSYS_OPT_DIAG 1752 1753 LIBEFX_API 1754 extern __checkReturn efx_rc_t 1755 efx_nvram_test( 1756 __in efx_nic_t *enp); 1757 1758 #endif /* EFSYS_OPT_DIAG */ 1759 1760 LIBEFX_API 1761 extern __checkReturn efx_rc_t 1762 efx_nvram_size( 1763 __in efx_nic_t *enp, 1764 __in efx_nvram_type_t type, 1765 __out size_t *sizep); 1766 1767 LIBEFX_API 1768 extern __checkReturn efx_rc_t 1769 efx_nvram_info( 1770 __in efx_nic_t *enp, 1771 __in efx_nvram_type_t type, 1772 __out efx_nvram_info_t *enip); 1773 1774 LIBEFX_API 1775 extern __checkReturn efx_rc_t 1776 efx_nvram_rw_start( 1777 __in efx_nic_t *enp, 1778 __in efx_nvram_type_t type, 1779 __out_opt size_t *pref_chunkp); 1780 1781 LIBEFX_API 1782 extern __checkReturn efx_rc_t 1783 efx_nvram_rw_finish( 1784 __in efx_nic_t *enp, 1785 __in efx_nvram_type_t type, 1786 __out_opt uint32_t *verify_resultp); 1787 1788 LIBEFX_API 1789 extern __checkReturn efx_rc_t 1790 efx_nvram_get_version( 1791 __in efx_nic_t *enp, 1792 __in efx_nvram_type_t type, 1793 __out uint32_t *subtypep, 1794 __out_ecount(4) uint16_t version[4]); 1795 1796 LIBEFX_API 1797 extern __checkReturn efx_rc_t 1798 efx_nvram_read_chunk( 1799 __in efx_nic_t *enp, 1800 __in efx_nvram_type_t type, 1801 __in unsigned int offset, 1802 __out_bcount(size) caddr_t data, 1803 __in size_t size); 1804 1805 LIBEFX_API 1806 extern __checkReturn efx_rc_t 1807 efx_nvram_read_backup( 1808 __in efx_nic_t *enp, 1809 __in efx_nvram_type_t type, 1810 __in unsigned int offset, 1811 __out_bcount(size) caddr_t data, 1812 __in size_t size); 1813 1814 LIBEFX_API 1815 extern __checkReturn efx_rc_t 1816 efx_nvram_set_version( 1817 __in efx_nic_t *enp, 1818 __in efx_nvram_type_t type, 1819 __in_ecount(4) uint16_t version[4]); 1820 1821 LIBEFX_API 1822 extern __checkReturn efx_rc_t 1823 efx_nvram_validate( 1824 __in efx_nic_t *enp, 1825 __in efx_nvram_type_t type, 1826 __in_bcount(partn_size) caddr_t partn_data, 1827 __in size_t partn_size); 1828 1829 LIBEFX_API 1830 extern __checkReturn efx_rc_t 1831 efx_nvram_erase( 1832 __in efx_nic_t *enp, 1833 __in efx_nvram_type_t type); 1834 1835 LIBEFX_API 1836 extern __checkReturn efx_rc_t 1837 efx_nvram_write_chunk( 1838 __in efx_nic_t *enp, 1839 __in efx_nvram_type_t type, 1840 __in unsigned int offset, 1841 __in_bcount(size) caddr_t data, 1842 __in size_t size); 1843 1844 LIBEFX_API 1845 extern void 1846 efx_nvram_fini( 1847 __in efx_nic_t *enp); 1848 1849 #endif /* EFSYS_OPT_NVRAM */ 1850 1851 #if EFSYS_OPT_BOOTCFG 1852 1853 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1854 LIBEFX_API 1855 extern __checkReturn efx_rc_t 1856 efx_bootcfg_sector_info( 1857 __in efx_nic_t *enp, 1858 __in uint32_t pf, 1859 __out_opt uint32_t *sector_countp, 1860 __out size_t *offsetp, 1861 __out size_t *max_sizep); 1862 1863 /* 1864 * Copy bootcfg sector data to a target buffer which may differ in size. 1865 * Optionally corrects format errors in source buffer. 1866 */ 1867 LIBEFX_API 1868 extern efx_rc_t 1869 efx_bootcfg_copy_sector( 1870 __in efx_nic_t *enp, 1871 __inout_bcount(sector_length) 1872 uint8_t *sector, 1873 __in size_t sector_length, 1874 __out_bcount(data_size) uint8_t *data, 1875 __in size_t data_size, 1876 __in boolean_t handle_format_errors); 1877 1878 LIBEFX_API 1879 extern efx_rc_t 1880 efx_bootcfg_read( 1881 __in efx_nic_t *enp, 1882 __out_bcount(size) uint8_t *data, 1883 __in size_t size); 1884 1885 LIBEFX_API 1886 extern efx_rc_t 1887 efx_bootcfg_write( 1888 __in efx_nic_t *enp, 1889 __in_bcount(size) uint8_t *data, 1890 __in size_t size); 1891 1892 1893 /* 1894 * Processing routines for buffers arranged in the DHCP/BOOTP option format 1895 * (see https://tools.ietf.org/html/rfc1533) 1896 * 1897 * Summarising the format: the buffer is a sequence of options. All options 1898 * begin with a tag octet, which uniquely identifies the option. Fixed- 1899 * length options without data consist of only a tag octet. Only options PAD 1900 * (0) and END (255) are fixed length. All other options are variable-length 1901 * with a length octet following the tag octet. The value of the length 1902 * octet does not include the two octets specifying the tag and length. The 1903 * length octet is followed by "length" octets of data. 1904 * 1905 * Option data may be a sequence of sub-options in the same format. The data 1906 * content of the encapsulating option is one or more encapsulated sub-options, 1907 * with no terminating END tag is required. 1908 * 1909 * To be valid, the top-level sequence of options should be terminated by an 1910 * END tag. The buffer should be padded with the PAD byte. 1911 * 1912 * When stored to NVRAM, the DHCP option format buffer is preceded by a 1913 * checksum octet. The full buffer (including after the END tag) contributes 1914 * to the checksum, hence the need to fill the buffer to the end with PAD. 1915 */ 1916 1917 #define EFX_DHCP_END ((uint8_t)0xff) 1918 #define EFX_DHCP_PAD ((uint8_t)0) 1919 1920 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 1921 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 1922 1923 LIBEFX_API 1924 extern __checkReturn uint8_t 1925 efx_dhcp_csum( 1926 __in_bcount(size) uint8_t const *data, 1927 __in size_t size); 1928 1929 LIBEFX_API 1930 extern __checkReturn efx_rc_t 1931 efx_dhcp_verify( 1932 __in_bcount(size) uint8_t const *data, 1933 __in size_t size, 1934 __out_opt size_t *usedp); 1935 1936 LIBEFX_API 1937 extern __checkReturn efx_rc_t 1938 efx_dhcp_find_tag( 1939 __in_bcount(buffer_length) uint8_t *bufferp, 1940 __in size_t buffer_length, 1941 __in uint16_t opt, 1942 __deref_out uint8_t **valuepp, 1943 __out size_t *value_lengthp); 1944 1945 LIBEFX_API 1946 extern __checkReturn efx_rc_t 1947 efx_dhcp_find_end( 1948 __in_bcount(buffer_length) uint8_t *bufferp, 1949 __in size_t buffer_length, 1950 __deref_out uint8_t **endpp); 1951 1952 1953 LIBEFX_API 1954 extern __checkReturn efx_rc_t 1955 efx_dhcp_delete_tag( 1956 __inout_bcount(buffer_length) uint8_t *bufferp, 1957 __in size_t buffer_length, 1958 __in uint16_t opt); 1959 1960 LIBEFX_API 1961 extern __checkReturn efx_rc_t 1962 efx_dhcp_add_tag( 1963 __inout_bcount(buffer_length) uint8_t *bufferp, 1964 __in size_t buffer_length, 1965 __in uint16_t opt, 1966 __in_bcount_opt(value_length) uint8_t *valuep, 1967 __in size_t value_length); 1968 1969 LIBEFX_API 1970 extern __checkReturn efx_rc_t 1971 efx_dhcp_update_tag( 1972 __inout_bcount(buffer_length) uint8_t *bufferp, 1973 __in size_t buffer_length, 1974 __in uint16_t opt, 1975 __in uint8_t *value_locationp, 1976 __in_bcount_opt(value_length) uint8_t *valuep, 1977 __in size_t value_length); 1978 1979 1980 #endif /* EFSYS_OPT_BOOTCFG */ 1981 1982 #if EFSYS_OPT_IMAGE_LAYOUT 1983 1984 #include "ef10_signed_image_layout.h" 1985 1986 /* 1987 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 1988 * 1989 * NOTE: 1990 * The image header format is extensible. However, older drivers require an 1991 * exact match of image header version and header length when validating and 1992 * writing firmware images. 1993 * 1994 * To avoid breaking backward compatibility, we use the upper bits of the 1995 * controller version fields to contain an extra version number used for 1996 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 1997 * version). See bug39254 and SF-102785-PS for details. 1998 */ 1999 typedef struct efx_image_header_s { 2000 uint32_t eih_magic; 2001 uint32_t eih_version; 2002 uint32_t eih_type; 2003 uint32_t eih_subtype; 2004 uint32_t eih_code_size; 2005 uint32_t eih_size; 2006 union { 2007 uint32_t eih_controller_version_min; 2008 struct { 2009 uint16_t eih_controller_version_min_short; 2010 uint8_t eih_extra_version_a; 2011 uint8_t eih_extra_version_b; 2012 }; 2013 }; 2014 union { 2015 uint32_t eih_controller_version_max; 2016 struct { 2017 uint16_t eih_controller_version_max_short; 2018 uint8_t eih_extra_version_c; 2019 uint8_t eih_extra_version_d; 2020 }; 2021 }; 2022 uint16_t eih_code_version_a; 2023 uint16_t eih_code_version_b; 2024 uint16_t eih_code_version_c; 2025 uint16_t eih_code_version_d; 2026 } efx_image_header_t; 2027 2028 #define EFX_IMAGE_HEADER_SIZE (40) 2029 #define EFX_IMAGE_HEADER_VERSION (4) 2030 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 2031 2032 2033 typedef struct efx_image_trailer_s { 2034 uint32_t eit_crc; 2035 } efx_image_trailer_t; 2036 2037 #define EFX_IMAGE_TRAILER_SIZE (4) 2038 2039 typedef enum efx_image_format_e { 2040 EFX_IMAGE_FORMAT_NO_IMAGE, 2041 EFX_IMAGE_FORMAT_INVALID, 2042 EFX_IMAGE_FORMAT_UNSIGNED, 2043 EFX_IMAGE_FORMAT_SIGNED, 2044 EFX_IMAGE_FORMAT_SIGNED_PACKAGE 2045 } efx_image_format_t; 2046 2047 typedef struct efx_image_info_s { 2048 efx_image_format_t eii_format; 2049 uint8_t * eii_imagep; 2050 size_t eii_image_size; 2051 efx_image_header_t * eii_headerp; 2052 } efx_image_info_t; 2053 2054 LIBEFX_API 2055 extern __checkReturn efx_rc_t 2056 efx_check_reflash_image( 2057 __in void *bufferp, 2058 __in uint32_t buffer_size, 2059 __out efx_image_info_t *infop); 2060 2061 LIBEFX_API 2062 extern __checkReturn efx_rc_t 2063 efx_build_signed_image_write_buffer( 2064 __out_bcount(buffer_size) 2065 uint8_t *bufferp, 2066 __in uint32_t buffer_size, 2067 __in efx_image_info_t *infop, 2068 __out efx_image_header_t **headerpp); 2069 2070 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 2071 2072 #if EFSYS_OPT_DIAG 2073 2074 typedef enum efx_pattern_type_t { 2075 EFX_PATTERN_BYTE_INCREMENT = 0, 2076 EFX_PATTERN_ALL_THE_SAME, 2077 EFX_PATTERN_BIT_ALTERNATE, 2078 EFX_PATTERN_BYTE_ALTERNATE, 2079 EFX_PATTERN_BYTE_CHANGING, 2080 EFX_PATTERN_BIT_SWEEP, 2081 EFX_PATTERN_NTYPES 2082 } efx_pattern_type_t; 2083 2084 typedef void 2085 (*efx_sram_pattern_fn_t)( 2086 __in size_t row, 2087 __in boolean_t negate, 2088 __out efx_qword_t *eqp); 2089 2090 LIBEFX_API 2091 extern __checkReturn efx_rc_t 2092 efx_sram_test( 2093 __in efx_nic_t *enp, 2094 __in efx_pattern_type_t type); 2095 2096 #endif /* EFSYS_OPT_DIAG */ 2097 2098 LIBEFX_API 2099 extern __checkReturn efx_rc_t 2100 efx_sram_buf_tbl_set( 2101 __in efx_nic_t *enp, 2102 __in uint32_t id, 2103 __in efsys_mem_t *esmp, 2104 __in size_t n); 2105 2106 LIBEFX_API 2107 extern void 2108 efx_sram_buf_tbl_clear( 2109 __in efx_nic_t *enp, 2110 __in uint32_t id, 2111 __in size_t n); 2112 2113 #define EFX_BUF_TBL_SIZE 0x20000 2114 2115 #define EFX_BUF_SIZE 4096 2116 2117 /* EV */ 2118 2119 typedef struct efx_evq_s efx_evq_t; 2120 2121 #if EFSYS_OPT_QSTATS 2122 2123 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ 2124 typedef enum efx_ev_qstat_e { 2125 EV_ALL, 2126 EV_RX, 2127 EV_RX_OK, 2128 EV_RX_FRM_TRUNC, 2129 EV_RX_TOBE_DISC, 2130 EV_RX_PAUSE_FRM_ERR, 2131 EV_RX_BUF_OWNER_ID_ERR, 2132 EV_RX_IPV4_HDR_CHKSUM_ERR, 2133 EV_RX_TCP_UDP_CHKSUM_ERR, 2134 EV_RX_ETH_CRC_ERR, 2135 EV_RX_IP_FRAG_ERR, 2136 EV_RX_MCAST_PKT, 2137 EV_RX_MCAST_HASH_MATCH, 2138 EV_RX_TCP_IPV4, 2139 EV_RX_TCP_IPV6, 2140 EV_RX_UDP_IPV4, 2141 EV_RX_UDP_IPV6, 2142 EV_RX_OTHER_IPV4, 2143 EV_RX_OTHER_IPV6, 2144 EV_RX_NON_IP, 2145 EV_RX_BATCH, 2146 EV_TX, 2147 EV_TX_WQ_FF_FULL, 2148 EV_TX_PKT_ERR, 2149 EV_TX_PKT_TOO_BIG, 2150 EV_TX_UNEXPECTED, 2151 EV_GLOBAL, 2152 EV_GLOBAL_MNT, 2153 EV_DRIVER, 2154 EV_DRIVER_SRM_UPD_DONE, 2155 EV_DRIVER_TX_DESCQ_FLS_DONE, 2156 EV_DRIVER_RX_DESCQ_FLS_DONE, 2157 EV_DRIVER_RX_DESCQ_FLS_FAILED, 2158 EV_DRIVER_RX_DSC_ERROR, 2159 EV_DRIVER_TX_DSC_ERROR, 2160 EV_DRV_GEN, 2161 EV_MCDI_RESPONSE, 2162 EV_RX_PARSE_INCOMPLETE, 2163 EV_NQSTATS 2164 } efx_ev_qstat_t; 2165 2166 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2167 2168 #endif /* EFSYS_OPT_QSTATS */ 2169 2170 LIBEFX_API 2171 extern __checkReturn efx_rc_t 2172 efx_ev_init( 2173 __in efx_nic_t *enp); 2174 2175 LIBEFX_API 2176 extern void 2177 efx_ev_fini( 2178 __in efx_nic_t *enp); 2179 2180 LIBEFX_API 2181 extern __checkReturn size_t 2182 efx_evq_size( 2183 __in const efx_nic_t *enp, 2184 __in unsigned int ndescs); 2185 2186 LIBEFX_API 2187 extern __checkReturn unsigned int 2188 efx_evq_nbufs( 2189 __in const efx_nic_t *enp, 2190 __in unsigned int ndescs); 2191 2192 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2193 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2194 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2195 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2196 2197 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2198 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2199 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2200 2201 /* 2202 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more 2203 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in 2204 * NO_CONT_EV mode". 2205 * 2206 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, 2207 * which is the case when an event queue is set to THROUGHPUT mode. 2208 */ 2209 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) 2210 2211 LIBEFX_API 2212 extern __checkReturn efx_rc_t 2213 efx_ev_qcreate( 2214 __in efx_nic_t *enp, 2215 __in unsigned int index, 2216 __in efsys_mem_t *esmp, 2217 __in size_t ndescs, 2218 __in uint32_t id, 2219 __in uint32_t us, 2220 __in uint32_t flags, 2221 __deref_out efx_evq_t **eepp); 2222 2223 LIBEFX_API 2224 extern void 2225 efx_ev_qpost( 2226 __in efx_evq_t *eep, 2227 __in uint16_t data); 2228 2229 typedef __checkReturn boolean_t 2230 (*efx_initialized_ev_t)( 2231 __in_opt void *arg); 2232 2233 #define EFX_PKT_UNICAST 0x0004 2234 #define EFX_PKT_START 0x0008 2235 2236 #define EFX_PKT_VLAN_TAGGED 0x0010 2237 #define EFX_CKSUM_TCPUDP 0x0020 2238 #define EFX_CKSUM_IPV4 0x0040 2239 #define EFX_PKT_CONT 0x0080 2240 2241 #define EFX_CHECK_VLAN 0x0100 2242 #define EFX_PKT_TCP 0x0200 2243 #define EFX_PKT_UDP 0x0400 2244 #define EFX_PKT_IPV4 0x0800 2245 2246 #define EFX_PKT_IPV6 0x1000 2247 #define EFX_PKT_PREFIX_LEN 0x2000 2248 #define EFX_ADDR_MISMATCH 0x4000 2249 #define EFX_DISCARD 0x8000 2250 2251 /* 2252 * The following flags are used only for packed stream 2253 * mode. The values for the flags are reused to fit into 16 bit, 2254 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2255 * packed stream mode 2256 */ 2257 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2258 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2259 2260 2261 #define EFX_EV_RX_NLABELS 32 2262 #define EFX_EV_TX_NLABELS 32 2263 2264 typedef __checkReturn boolean_t 2265 (*efx_rx_ev_t)( 2266 __in_opt void *arg, 2267 __in uint32_t label, 2268 __in uint32_t id, 2269 __in uint32_t size, 2270 __in uint16_t flags); 2271 2272 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2273 2274 /* 2275 * Packed stream mode is documented in SF-112241-TC. 2276 * The general idea is that, instead of putting each incoming 2277 * packet into a separate buffer which is specified in a RX 2278 * descriptor, a large buffer is provided to the hardware and 2279 * packets are put there in a continuous stream. 2280 * The main advantage of such an approach is that RX queue refilling 2281 * happens much less frequently. 2282 * 2283 * Equal stride packed stream mode is documented in SF-119419-TC. 2284 * The general idea is to utilize advantages of the packed stream, 2285 * but avoid indirection in packets representation. 2286 * The main advantage of such an approach is that RX queue refilling 2287 * happens much less frequently and packets buffers are independent 2288 * from upper layers point of view. 2289 */ 2290 2291 typedef __checkReturn boolean_t 2292 (*efx_rx_ps_ev_t)( 2293 __in_opt void *arg, 2294 __in uint32_t label, 2295 __in uint32_t id, 2296 __in uint32_t pkt_count, 2297 __in uint16_t flags); 2298 2299 #endif 2300 2301 typedef __checkReturn boolean_t 2302 (*efx_tx_ev_t)( 2303 __in_opt void *arg, 2304 __in uint32_t label, 2305 __in uint32_t id); 2306 2307 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2308 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2309 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2310 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2311 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2312 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2313 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2314 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2315 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2316 2317 typedef __checkReturn boolean_t 2318 (*efx_exception_ev_t)( 2319 __in_opt void *arg, 2320 __in uint32_t label, 2321 __in uint32_t data); 2322 2323 typedef __checkReturn boolean_t 2324 (*efx_rxq_flush_done_ev_t)( 2325 __in_opt void *arg, 2326 __in uint32_t rxq_index); 2327 2328 typedef __checkReturn boolean_t 2329 (*efx_rxq_flush_failed_ev_t)( 2330 __in_opt void *arg, 2331 __in uint32_t rxq_index); 2332 2333 typedef __checkReturn boolean_t 2334 (*efx_txq_flush_done_ev_t)( 2335 __in_opt void *arg, 2336 __in uint32_t txq_index); 2337 2338 typedef __checkReturn boolean_t 2339 (*efx_software_ev_t)( 2340 __in_opt void *arg, 2341 __in uint16_t magic); 2342 2343 typedef __checkReturn boolean_t 2344 (*efx_sram_ev_t)( 2345 __in_opt void *arg, 2346 __in uint32_t code); 2347 2348 #define EFX_SRAM_CLEAR 0 2349 #define EFX_SRAM_UPDATE 1 2350 #define EFX_SRAM_ILLEGAL_CLEAR 2 2351 2352 typedef __checkReturn boolean_t 2353 (*efx_wake_up_ev_t)( 2354 __in_opt void *arg, 2355 __in uint32_t label); 2356 2357 typedef __checkReturn boolean_t 2358 (*efx_timer_ev_t)( 2359 __in_opt void *arg, 2360 __in uint32_t label); 2361 2362 typedef __checkReturn boolean_t 2363 (*efx_link_change_ev_t)( 2364 __in_opt void *arg, 2365 __in efx_link_mode_t link_mode); 2366 2367 #if EFSYS_OPT_MON_STATS 2368 2369 typedef __checkReturn boolean_t 2370 (*efx_monitor_ev_t)( 2371 __in_opt void *arg, 2372 __in efx_mon_stat_t id, 2373 __in efx_mon_stat_value_t value); 2374 2375 #endif /* EFSYS_OPT_MON_STATS */ 2376 2377 #if EFSYS_OPT_MAC_STATS 2378 2379 typedef __checkReturn boolean_t 2380 (*efx_mac_stats_ev_t)( 2381 __in_opt void *arg, 2382 __in uint32_t generation); 2383 2384 #endif /* EFSYS_OPT_MAC_STATS */ 2385 2386 typedef struct efx_ev_callbacks_s { 2387 efx_initialized_ev_t eec_initialized; 2388 efx_rx_ev_t eec_rx; 2389 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2390 efx_rx_ps_ev_t eec_rx_ps; 2391 #endif 2392 efx_tx_ev_t eec_tx; 2393 efx_exception_ev_t eec_exception; 2394 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2395 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2396 efx_txq_flush_done_ev_t eec_txq_flush_done; 2397 efx_software_ev_t eec_software; 2398 efx_sram_ev_t eec_sram; 2399 efx_wake_up_ev_t eec_wake_up; 2400 efx_timer_ev_t eec_timer; 2401 efx_link_change_ev_t eec_link_change; 2402 #if EFSYS_OPT_MON_STATS 2403 efx_monitor_ev_t eec_monitor; 2404 #endif /* EFSYS_OPT_MON_STATS */ 2405 #if EFSYS_OPT_MAC_STATS 2406 efx_mac_stats_ev_t eec_mac_stats; 2407 #endif /* EFSYS_OPT_MAC_STATS */ 2408 } efx_ev_callbacks_t; 2409 2410 LIBEFX_API 2411 extern __checkReturn boolean_t 2412 efx_ev_qpending( 2413 __in efx_evq_t *eep, 2414 __in unsigned int count); 2415 2416 #if EFSYS_OPT_EV_PREFETCH 2417 2418 LIBEFX_API 2419 extern void 2420 efx_ev_qprefetch( 2421 __in efx_evq_t *eep, 2422 __in unsigned int count); 2423 2424 #endif /* EFSYS_OPT_EV_PREFETCH */ 2425 2426 LIBEFX_API 2427 extern void 2428 efx_ev_qpoll( 2429 __in efx_evq_t *eep, 2430 __inout unsigned int *countp, 2431 __in const efx_ev_callbacks_t *eecp, 2432 __in_opt void *arg); 2433 2434 LIBEFX_API 2435 extern __checkReturn efx_rc_t 2436 efx_ev_usecs_to_ticks( 2437 __in efx_nic_t *enp, 2438 __in unsigned int usecs, 2439 __out unsigned int *ticksp); 2440 2441 LIBEFX_API 2442 extern __checkReturn efx_rc_t 2443 efx_ev_qmoderate( 2444 __in efx_evq_t *eep, 2445 __in unsigned int us); 2446 2447 LIBEFX_API 2448 extern __checkReturn efx_rc_t 2449 efx_ev_qprime( 2450 __in efx_evq_t *eep, 2451 __in unsigned int count); 2452 2453 #if EFSYS_OPT_QSTATS 2454 2455 #if EFSYS_OPT_NAMES 2456 2457 LIBEFX_API 2458 extern const char * 2459 efx_ev_qstat_name( 2460 __in efx_nic_t *enp, 2461 __in unsigned int id); 2462 2463 #endif /* EFSYS_OPT_NAMES */ 2464 2465 LIBEFX_API 2466 extern void 2467 efx_ev_qstats_update( 2468 __in efx_evq_t *eep, 2469 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2470 2471 #endif /* EFSYS_OPT_QSTATS */ 2472 2473 LIBEFX_API 2474 extern void 2475 efx_ev_qdestroy( 2476 __in efx_evq_t *eep); 2477 2478 /* RX */ 2479 2480 LIBEFX_API 2481 extern __checkReturn efx_rc_t 2482 efx_rx_init( 2483 __inout efx_nic_t *enp); 2484 2485 LIBEFX_API 2486 extern void 2487 efx_rx_fini( 2488 __in efx_nic_t *enp); 2489 2490 #if EFSYS_OPT_RX_SCATTER 2491 LIBEFX_API 2492 extern __checkReturn efx_rc_t 2493 efx_rx_scatter_enable( 2494 __in efx_nic_t *enp, 2495 __in unsigned int buf_size); 2496 #endif /* EFSYS_OPT_RX_SCATTER */ 2497 2498 /* Handle to represent use of the default RSS context. */ 2499 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2500 2501 #if EFSYS_OPT_RX_SCALE 2502 2503 typedef enum efx_rx_hash_alg_e { 2504 EFX_RX_HASHALG_LFSR = 0, 2505 EFX_RX_HASHALG_TOEPLITZ, 2506 EFX_RX_HASHALG_PACKED_STREAM, 2507 EFX_RX_NHASHALGS 2508 } efx_rx_hash_alg_t; 2509 2510 /* 2511 * Legacy hash type flags. 2512 * 2513 * They represent standard tuples for distinct traffic classes. 2514 */ 2515 #define EFX_RX_HASH_IPV4 (1U << 0) 2516 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2517 #define EFX_RX_HASH_IPV6 (1U << 2) 2518 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2519 2520 #define EFX_RX_HASH_LEGACY_MASK \ 2521 (EFX_RX_HASH_IPV4 | \ 2522 EFX_RX_HASH_TCPIPV4 | \ 2523 EFX_RX_HASH_IPV6 | \ 2524 EFX_RX_HASH_TCPIPV6) 2525 2526 /* 2527 * The type of the argument used by efx_rx_scale_mode_set() to 2528 * provide a means for the client drivers to configure hashing. 2529 * 2530 * A properly constructed value can either be: 2531 * - a combination of legacy flags 2532 * - a combination of EFX_RX_HASH() flags 2533 */ 2534 typedef uint32_t efx_rx_hash_type_t; 2535 2536 typedef enum efx_rx_hash_support_e { 2537 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2538 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2539 } efx_rx_hash_support_t; 2540 2541 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2542 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2543 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2544 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2545 2546 typedef enum efx_rx_scale_context_type_e { 2547 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2548 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2549 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2550 } efx_rx_scale_context_type_t; 2551 2552 /* 2553 * Traffic classes eligible for hash computation. 2554 * 2555 * Select packet headers used in computing the receive hash. 2556 * This uses the same encoding as the RSS_MODES field of 2557 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2558 */ 2559 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2560 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2561 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2562 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2563 #define EFX_RX_CLASS_IPV4_LBN 16 2564 #define EFX_RX_CLASS_IPV4_WIDTH 4 2565 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2566 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2567 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2568 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2569 #define EFX_RX_CLASS_IPV6_LBN 28 2570 #define EFX_RX_CLASS_IPV6_WIDTH 4 2571 2572 #define EFX_RX_NCLASSES 6 2573 2574 /* 2575 * Ancillary flags used to construct generic hash tuples. 2576 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2577 */ 2578 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2579 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2580 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2581 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2582 2583 /* 2584 * Generic hash tuples. 2585 * 2586 * They express combinations of packet fields 2587 * which can contribute to the hash value for 2588 * a particular traffic class. 2589 */ 2590 #define EFX_RX_CLASS_HASH_DISABLE 0 2591 2592 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2593 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2594 2595 #define EFX_RX_CLASS_HASH_2TUPLE \ 2596 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2597 EFX_RX_CLASS_HASH_DST_ADDR) 2598 2599 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2600 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2601 EFX_RX_CLASS_HASH_SRC_PORT) 2602 2603 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2604 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2605 EFX_RX_CLASS_HASH_DST_PORT) 2606 2607 #define EFX_RX_CLASS_HASH_4TUPLE \ 2608 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2609 EFX_RX_CLASS_HASH_DST_ADDR | \ 2610 EFX_RX_CLASS_HASH_SRC_PORT | \ 2611 EFX_RX_CLASS_HASH_DST_PORT) 2612 2613 #define EFX_RX_CLASS_HASH_NTUPLES 7 2614 2615 /* 2616 * Hash flag constructor. 2617 * 2618 * Resulting flags encode hash tuples for specific traffic classes. 2619 * The client drivers are encouraged to use these flags to form 2620 * a hash type value. 2621 */ 2622 #define EFX_RX_HASH(_class, _tuple) \ 2623 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2624 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2625 2626 /* 2627 * The maximum number of EFX_RX_HASH() flags. 2628 */ 2629 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2630 2631 LIBEFX_API 2632 extern __checkReturn efx_rc_t 2633 efx_rx_scale_hash_flags_get( 2634 __in efx_nic_t *enp, 2635 __in efx_rx_hash_alg_t hash_alg, 2636 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2637 __in unsigned int max_nflags, 2638 __out unsigned int *nflagsp); 2639 2640 LIBEFX_API 2641 extern __checkReturn efx_rc_t 2642 efx_rx_hash_default_support_get( 2643 __in efx_nic_t *enp, 2644 __out efx_rx_hash_support_t *supportp); 2645 2646 2647 LIBEFX_API 2648 extern __checkReturn efx_rc_t 2649 efx_rx_scale_default_support_get( 2650 __in efx_nic_t *enp, 2651 __out efx_rx_scale_context_type_t *typep); 2652 2653 LIBEFX_API 2654 extern __checkReturn efx_rc_t 2655 efx_rx_scale_context_alloc( 2656 __in efx_nic_t *enp, 2657 __in efx_rx_scale_context_type_t type, 2658 __in uint32_t num_queues, 2659 __out uint32_t *rss_contextp); 2660 2661 LIBEFX_API 2662 extern __checkReturn efx_rc_t 2663 efx_rx_scale_context_free( 2664 __in efx_nic_t *enp, 2665 __in uint32_t rss_context); 2666 2667 LIBEFX_API 2668 extern __checkReturn efx_rc_t 2669 efx_rx_scale_mode_set( 2670 __in efx_nic_t *enp, 2671 __in uint32_t rss_context, 2672 __in efx_rx_hash_alg_t alg, 2673 __in efx_rx_hash_type_t type, 2674 __in boolean_t insert); 2675 2676 LIBEFX_API 2677 extern __checkReturn efx_rc_t 2678 efx_rx_scale_tbl_set( 2679 __in efx_nic_t *enp, 2680 __in uint32_t rss_context, 2681 __in_ecount(n) unsigned int *table, 2682 __in size_t n); 2683 2684 LIBEFX_API 2685 extern __checkReturn efx_rc_t 2686 efx_rx_scale_key_set( 2687 __in efx_nic_t *enp, 2688 __in uint32_t rss_context, 2689 __in_ecount(n) uint8_t *key, 2690 __in size_t n); 2691 2692 LIBEFX_API 2693 extern __checkReturn uint32_t 2694 efx_pseudo_hdr_hash_get( 2695 __in efx_rxq_t *erp, 2696 __in efx_rx_hash_alg_t func, 2697 __in uint8_t *buffer); 2698 2699 #endif /* EFSYS_OPT_RX_SCALE */ 2700 2701 LIBEFX_API 2702 extern __checkReturn efx_rc_t 2703 efx_pseudo_hdr_pkt_length_get( 2704 __in efx_rxq_t *erp, 2705 __in uint8_t *buffer, 2706 __out uint16_t *pkt_lengthp); 2707 2708 LIBEFX_API 2709 extern __checkReturn size_t 2710 efx_rxq_size( 2711 __in const efx_nic_t *enp, 2712 __in unsigned int ndescs); 2713 2714 LIBEFX_API 2715 extern __checkReturn unsigned int 2716 efx_rxq_nbufs( 2717 __in const efx_nic_t *enp, 2718 __in unsigned int ndescs); 2719 2720 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2721 2722 typedef enum efx_rxq_type_e { 2723 EFX_RXQ_TYPE_DEFAULT, 2724 EFX_RXQ_TYPE_PACKED_STREAM, 2725 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 2726 EFX_RXQ_NTYPES 2727 } efx_rxq_type_t; 2728 2729 /* 2730 * Dummy flag to be used instead of 0 to make it clear that the argument 2731 * is receive queue flags. 2732 */ 2733 #define EFX_RXQ_FLAG_NONE 0x0 2734 #define EFX_RXQ_FLAG_SCATTER 0x1 2735 /* 2736 * If tunnels are supported and Rx event can provide information about 2737 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2738 * full-feature firmware variant running), outer classes are requested by 2739 * default. However, if the driver supports tunnels, the flag allows to 2740 * request inner classes which are required to be able to interpret inner 2741 * Rx checksum offload results. 2742 */ 2743 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2744 2745 LIBEFX_API 2746 extern __checkReturn efx_rc_t 2747 efx_rx_qcreate( 2748 __in efx_nic_t *enp, 2749 __in unsigned int index, 2750 __in unsigned int label, 2751 __in efx_rxq_type_t type, 2752 __in size_t buf_size, 2753 __in efsys_mem_t *esmp, 2754 __in size_t ndescs, 2755 __in uint32_t id, 2756 __in unsigned int flags, 2757 __in efx_evq_t *eep, 2758 __deref_out efx_rxq_t **erpp); 2759 2760 #if EFSYS_OPT_RX_PACKED_STREAM 2761 2762 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2763 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2764 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2765 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2766 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2767 2768 LIBEFX_API 2769 extern __checkReturn efx_rc_t 2770 efx_rx_qcreate_packed_stream( 2771 __in efx_nic_t *enp, 2772 __in unsigned int index, 2773 __in unsigned int label, 2774 __in uint32_t ps_buf_size, 2775 __in efsys_mem_t *esmp, 2776 __in size_t ndescs, 2777 __in efx_evq_t *eep, 2778 __deref_out efx_rxq_t **erpp); 2779 2780 #endif 2781 2782 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 2783 2784 /* Maximum head-of-line block timeout in nanoseconds */ 2785 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 2786 2787 LIBEFX_API 2788 extern __checkReturn efx_rc_t 2789 efx_rx_qcreate_es_super_buffer( 2790 __in efx_nic_t *enp, 2791 __in unsigned int index, 2792 __in unsigned int label, 2793 __in uint32_t n_bufs_per_desc, 2794 __in uint32_t max_dma_len, 2795 __in uint32_t buf_stride, 2796 __in uint32_t hol_block_timeout, 2797 __in efsys_mem_t *esmp, 2798 __in size_t ndescs, 2799 __in unsigned int flags, 2800 __in efx_evq_t *eep, 2801 __deref_out efx_rxq_t **erpp); 2802 2803 #endif 2804 2805 typedef struct efx_buffer_s { 2806 efsys_dma_addr_t eb_addr; 2807 size_t eb_size; 2808 boolean_t eb_eop; 2809 } efx_buffer_t; 2810 2811 typedef struct efx_desc_s { 2812 efx_qword_t ed_eq; 2813 } efx_desc_t; 2814 2815 LIBEFX_API 2816 extern void 2817 efx_rx_qpost( 2818 __in efx_rxq_t *erp, 2819 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 2820 __in size_t size, 2821 __in unsigned int ndescs, 2822 __in unsigned int completed, 2823 __in unsigned int added); 2824 2825 LIBEFX_API 2826 extern void 2827 efx_rx_qpush( 2828 __in efx_rxq_t *erp, 2829 __in unsigned int added, 2830 __inout unsigned int *pushedp); 2831 2832 #if EFSYS_OPT_RX_PACKED_STREAM 2833 2834 LIBEFX_API 2835 extern void 2836 efx_rx_qpush_ps_credits( 2837 __in efx_rxq_t *erp); 2838 2839 LIBEFX_API 2840 extern __checkReturn uint8_t * 2841 efx_rx_qps_packet_info( 2842 __in efx_rxq_t *erp, 2843 __in uint8_t *buffer, 2844 __in uint32_t buffer_length, 2845 __in uint32_t current_offset, 2846 __out uint16_t *lengthp, 2847 __out uint32_t *next_offsetp, 2848 __out uint32_t *timestamp); 2849 #endif 2850 2851 LIBEFX_API 2852 extern __checkReturn efx_rc_t 2853 efx_rx_qflush( 2854 __in efx_rxq_t *erp); 2855 2856 LIBEFX_API 2857 extern void 2858 efx_rx_qenable( 2859 __in efx_rxq_t *erp); 2860 2861 LIBEFX_API 2862 extern void 2863 efx_rx_qdestroy( 2864 __in efx_rxq_t *erp); 2865 2866 /* TX */ 2867 2868 typedef struct efx_txq_s efx_txq_t; 2869 2870 #if EFSYS_OPT_QSTATS 2871 2872 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2873 typedef enum efx_tx_qstat_e { 2874 TX_POST, 2875 TX_POST_PIO, 2876 TX_NQSTATS 2877 } efx_tx_qstat_t; 2878 2879 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2880 2881 #endif /* EFSYS_OPT_QSTATS */ 2882 2883 LIBEFX_API 2884 extern __checkReturn efx_rc_t 2885 efx_tx_init( 2886 __in efx_nic_t *enp); 2887 2888 LIBEFX_API 2889 extern void 2890 efx_tx_fini( 2891 __in efx_nic_t *enp); 2892 2893 LIBEFX_API 2894 extern __checkReturn size_t 2895 efx_txq_size( 2896 __in const efx_nic_t *enp, 2897 __in unsigned int ndescs); 2898 2899 LIBEFX_API 2900 extern __checkReturn unsigned int 2901 efx_txq_nbufs( 2902 __in const efx_nic_t *enp, 2903 __in unsigned int ndescs); 2904 2905 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2906 2907 #define EFX_TXQ_CKSUM_IPV4 0x0001 2908 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2909 #define EFX_TXQ_FATSOV2 0x0004 2910 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2911 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2912 2913 LIBEFX_API 2914 extern __checkReturn efx_rc_t 2915 efx_tx_qcreate( 2916 __in efx_nic_t *enp, 2917 __in unsigned int index, 2918 __in unsigned int label, 2919 __in efsys_mem_t *esmp, 2920 __in size_t n, 2921 __in uint32_t id, 2922 __in uint16_t flags, 2923 __in efx_evq_t *eep, 2924 __deref_out efx_txq_t **etpp, 2925 __out unsigned int *addedp); 2926 2927 LIBEFX_API 2928 extern __checkReturn efx_rc_t 2929 efx_tx_qpost( 2930 __in efx_txq_t *etp, 2931 __in_ecount(ndescs) efx_buffer_t *eb, 2932 __in unsigned int ndescs, 2933 __in unsigned int completed, 2934 __inout unsigned int *addedp); 2935 2936 LIBEFX_API 2937 extern __checkReturn efx_rc_t 2938 efx_tx_qpace( 2939 __in efx_txq_t *etp, 2940 __in unsigned int ns); 2941 2942 LIBEFX_API 2943 extern void 2944 efx_tx_qpush( 2945 __in efx_txq_t *etp, 2946 __in unsigned int added, 2947 __in unsigned int pushed); 2948 2949 LIBEFX_API 2950 extern __checkReturn efx_rc_t 2951 efx_tx_qflush( 2952 __in efx_txq_t *etp); 2953 2954 LIBEFX_API 2955 extern void 2956 efx_tx_qenable( 2957 __in efx_txq_t *etp); 2958 2959 LIBEFX_API 2960 extern __checkReturn efx_rc_t 2961 efx_tx_qpio_enable( 2962 __in efx_txq_t *etp); 2963 2964 LIBEFX_API 2965 extern void 2966 efx_tx_qpio_disable( 2967 __in efx_txq_t *etp); 2968 2969 LIBEFX_API 2970 extern __checkReturn efx_rc_t 2971 efx_tx_qpio_write( 2972 __in efx_txq_t *etp, 2973 __in_ecount(buf_length) uint8_t *buffer, 2974 __in size_t buf_length, 2975 __in size_t pio_buf_offset); 2976 2977 LIBEFX_API 2978 extern __checkReturn efx_rc_t 2979 efx_tx_qpio_post( 2980 __in efx_txq_t *etp, 2981 __in size_t pkt_length, 2982 __in unsigned int completed, 2983 __inout unsigned int *addedp); 2984 2985 LIBEFX_API 2986 extern __checkReturn efx_rc_t 2987 efx_tx_qdesc_post( 2988 __in efx_txq_t *etp, 2989 __in_ecount(n) efx_desc_t *ed, 2990 __in unsigned int n, 2991 __in unsigned int completed, 2992 __inout unsigned int *addedp); 2993 2994 LIBEFX_API 2995 extern void 2996 efx_tx_qdesc_dma_create( 2997 __in efx_txq_t *etp, 2998 __in efsys_dma_addr_t addr, 2999 __in size_t size, 3000 __in boolean_t eop, 3001 __out efx_desc_t *edp); 3002 3003 LIBEFX_API 3004 extern void 3005 efx_tx_qdesc_tso_create( 3006 __in efx_txq_t *etp, 3007 __in uint16_t ipv4_id, 3008 __in uint32_t tcp_seq, 3009 __in uint8_t tcp_flags, 3010 __out efx_desc_t *edp); 3011 3012 /* Number of FATSOv2 option descriptors */ 3013 #define EFX_TX_FATSOV2_OPT_NDESCS 2 3014 3015 /* Maximum number of DMA segments per TSO packet (not superframe) */ 3016 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 3017 3018 LIBEFX_API 3019 extern void 3020 efx_tx_qdesc_tso2_create( 3021 __in efx_txq_t *etp, 3022 __in uint16_t ipv4_id, 3023 __in uint16_t outer_ipv4_id, 3024 __in uint32_t tcp_seq, 3025 __in uint16_t tcp_mss, 3026 __out_ecount(count) efx_desc_t *edp, 3027 __in int count); 3028 3029 LIBEFX_API 3030 extern void 3031 efx_tx_qdesc_vlantci_create( 3032 __in efx_txq_t *etp, 3033 __in uint16_t tci, 3034 __out efx_desc_t *edp); 3035 3036 LIBEFX_API 3037 extern void 3038 efx_tx_qdesc_checksum_create( 3039 __in efx_txq_t *etp, 3040 __in uint16_t flags, 3041 __out efx_desc_t *edp); 3042 3043 #if EFSYS_OPT_QSTATS 3044 3045 #if EFSYS_OPT_NAMES 3046 3047 LIBEFX_API 3048 extern const char * 3049 efx_tx_qstat_name( 3050 __in efx_nic_t *etp, 3051 __in unsigned int id); 3052 3053 #endif /* EFSYS_OPT_NAMES */ 3054 3055 LIBEFX_API 3056 extern void 3057 efx_tx_qstats_update( 3058 __in efx_txq_t *etp, 3059 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 3060 3061 #endif /* EFSYS_OPT_QSTATS */ 3062 3063 LIBEFX_API 3064 extern void 3065 efx_tx_qdestroy( 3066 __in efx_txq_t *etp); 3067 3068 3069 /* FILTER */ 3070 3071 #if EFSYS_OPT_FILTER 3072 3073 #define EFX_ETHER_TYPE_IPV4 0x0800 3074 #define EFX_ETHER_TYPE_IPV6 0x86DD 3075 3076 #define EFX_IPPROTO_TCP 6 3077 #define EFX_IPPROTO_UDP 17 3078 #define EFX_IPPROTO_GRE 47 3079 3080 /* Use RSS to spread across multiple queues */ 3081 #define EFX_FILTER_FLAG_RX_RSS 0x01 3082 /* Enable RX scatter */ 3083 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 3084 /* 3085 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 3086 * May only be set by the filter implementation for each type. 3087 * A removal request will restore the automatic filter in its place. 3088 */ 3089 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 3090 /* Filter is for RX */ 3091 #define EFX_FILTER_FLAG_RX 0x08 3092 /* Filter is for TX */ 3093 #define EFX_FILTER_FLAG_TX 0x10 3094 /* Set match flag on the received packet */ 3095 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 3096 /* Set match mark on the received packet */ 3097 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 3098 3099 typedef uint8_t efx_filter_flags_t; 3100 3101 /* 3102 * Flags which specify the fields to match on. The values are the same as in the 3103 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 3104 */ 3105 3106 /* Match by remote IP host address */ 3107 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 3108 /* Match by local IP host address */ 3109 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 3110 /* Match by remote MAC address */ 3111 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 3112 /* Match by remote TCP/UDP port */ 3113 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 3114 /* Match by remote TCP/UDP port */ 3115 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 3116 /* Match by local TCP/UDP port */ 3117 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 3118 /* Match by Ether-type */ 3119 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 3120 /* Match by inner VLAN ID */ 3121 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 3122 /* Match by outer VLAN ID */ 3123 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 3124 /* Match by IP transport protocol */ 3125 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 3126 /* Match by VNI or VSID */ 3127 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 3128 /* For encapsulated packets, match by inner frame local MAC address */ 3129 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 3130 /* For encapsulated packets, match all multicast inner frames */ 3131 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 3132 /* For encapsulated packets, match all unicast inner frames */ 3133 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 3134 /* 3135 * Match by encap type, this flag does not correspond to 3136 * the MCDI match flags and any unoccupied value may be used 3137 */ 3138 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 3139 /* Match otherwise-unmatched multicast and broadcast packets */ 3140 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 3141 /* Match otherwise-unmatched unicast packets */ 3142 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 3143 3144 typedef uint32_t efx_filter_match_flags_t; 3145 3146 /* Filter priority from lowest to highest */ 3147 typedef enum efx_filter_priority_s { 3148 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device 3149 * address list or hardware 3150 * requirements. This may only be used 3151 * by the filter implementation for 3152 * each NIC type. */ 3153 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 3154 EFX_FILTER_NPRI, 3155 } efx_filter_priority_t; 3156 3157 /* 3158 * FIXME: All these fields are assumed to be in little-endian byte order. 3159 * It may be better for some to be big-endian. See bug42804. 3160 */ 3161 3162 typedef struct efx_filter_spec_s { 3163 efx_filter_match_flags_t efs_match_flags; 3164 uint8_t efs_priority; 3165 efx_filter_flags_t efs_flags; 3166 uint16_t efs_dmaq_id; 3167 uint32_t efs_rss_context; 3168 uint32_t efs_mark; 3169 /* 3170 * Saved lower-priority filter. If it is set, it is restored on 3171 * filter delete operation. 3172 */ 3173 struct efx_filter_spec_s *efs_overridden_spec; 3174 /* Fields below here are hashed for software filter lookup */ 3175 uint16_t efs_outer_vid; 3176 uint16_t efs_inner_vid; 3177 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 3178 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 3179 uint16_t efs_ether_type; 3180 uint8_t efs_ip_proto; 3181 efx_tunnel_protocol_t efs_encap_type; 3182 uint16_t efs_loc_port; 3183 uint16_t efs_rem_port; 3184 efx_oword_t efs_rem_host; 3185 efx_oword_t efs_loc_host; 3186 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 3187 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 3188 } efx_filter_spec_t; 3189 3190 3191 /* Default values for use in filter specifications */ 3192 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 3193 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 3194 3195 LIBEFX_API 3196 extern __checkReturn efx_rc_t 3197 efx_filter_init( 3198 __in efx_nic_t *enp); 3199 3200 LIBEFX_API 3201 extern void 3202 efx_filter_fini( 3203 __in efx_nic_t *enp); 3204 3205 LIBEFX_API 3206 extern __checkReturn efx_rc_t 3207 efx_filter_insert( 3208 __in efx_nic_t *enp, 3209 __inout efx_filter_spec_t *spec); 3210 3211 LIBEFX_API 3212 extern __checkReturn efx_rc_t 3213 efx_filter_remove( 3214 __in efx_nic_t *enp, 3215 __inout efx_filter_spec_t *spec); 3216 3217 LIBEFX_API 3218 extern __checkReturn efx_rc_t 3219 efx_filter_restore( 3220 __in efx_nic_t *enp); 3221 3222 LIBEFX_API 3223 extern __checkReturn efx_rc_t 3224 efx_filter_supported_filters( 3225 __in efx_nic_t *enp, 3226 __out_ecount(buffer_length) uint32_t *buffer, 3227 __in size_t buffer_length, 3228 __out size_t *list_lengthp); 3229 3230 LIBEFX_API 3231 extern void 3232 efx_filter_spec_init_rx( 3233 __out efx_filter_spec_t *spec, 3234 __in efx_filter_priority_t priority, 3235 __in efx_filter_flags_t flags, 3236 __in efx_rxq_t *erp); 3237 3238 LIBEFX_API 3239 extern void 3240 efx_filter_spec_init_tx( 3241 __out efx_filter_spec_t *spec, 3242 __in efx_txq_t *etp); 3243 3244 LIBEFX_API 3245 extern __checkReturn efx_rc_t 3246 efx_filter_spec_set_ipv4_local( 3247 __inout efx_filter_spec_t *spec, 3248 __in uint8_t proto, 3249 __in uint32_t host, 3250 __in uint16_t port); 3251 3252 LIBEFX_API 3253 extern __checkReturn efx_rc_t 3254 efx_filter_spec_set_ipv4_full( 3255 __inout efx_filter_spec_t *spec, 3256 __in uint8_t proto, 3257 __in uint32_t lhost, 3258 __in uint16_t lport, 3259 __in uint32_t rhost, 3260 __in uint16_t rport); 3261 3262 LIBEFX_API 3263 extern __checkReturn efx_rc_t 3264 efx_filter_spec_set_eth_local( 3265 __inout efx_filter_spec_t *spec, 3266 __in uint16_t vid, 3267 __in const uint8_t *addr); 3268 3269 LIBEFX_API 3270 extern void 3271 efx_filter_spec_set_ether_type( 3272 __inout efx_filter_spec_t *spec, 3273 __in uint16_t ether_type); 3274 3275 LIBEFX_API 3276 extern __checkReturn efx_rc_t 3277 efx_filter_spec_set_uc_def( 3278 __inout efx_filter_spec_t *spec); 3279 3280 LIBEFX_API 3281 extern __checkReturn efx_rc_t 3282 efx_filter_spec_set_mc_def( 3283 __inout efx_filter_spec_t *spec); 3284 3285 typedef enum efx_filter_inner_frame_match_e { 3286 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3287 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3288 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3289 } efx_filter_inner_frame_match_t; 3290 3291 LIBEFX_API 3292 extern __checkReturn efx_rc_t 3293 efx_filter_spec_set_encap_type( 3294 __inout efx_filter_spec_t *spec, 3295 __in efx_tunnel_protocol_t encap_type, 3296 __in efx_filter_inner_frame_match_t inner_frame_match); 3297 3298 LIBEFX_API 3299 extern __checkReturn efx_rc_t 3300 efx_filter_spec_set_vxlan( 3301 __inout efx_filter_spec_t *spec, 3302 __in const uint8_t *vni, 3303 __in const uint8_t *inner_addr, 3304 __in const uint8_t *outer_addr); 3305 3306 LIBEFX_API 3307 extern __checkReturn efx_rc_t 3308 efx_filter_spec_set_geneve( 3309 __inout efx_filter_spec_t *spec, 3310 __in const uint8_t *vni, 3311 __in const uint8_t *inner_addr, 3312 __in const uint8_t *outer_addr); 3313 3314 LIBEFX_API 3315 extern __checkReturn efx_rc_t 3316 efx_filter_spec_set_nvgre( 3317 __inout efx_filter_spec_t *spec, 3318 __in const uint8_t *vsid, 3319 __in const uint8_t *inner_addr, 3320 __in const uint8_t *outer_addr); 3321 3322 #if EFSYS_OPT_RX_SCALE 3323 LIBEFX_API 3324 extern __checkReturn efx_rc_t 3325 efx_filter_spec_set_rss_context( 3326 __inout efx_filter_spec_t *spec, 3327 __in uint32_t rss_context); 3328 #endif 3329 #endif /* EFSYS_OPT_FILTER */ 3330 3331 /* HASH */ 3332 3333 LIBEFX_API 3334 extern __checkReturn uint32_t 3335 efx_hash_dwords( 3336 __in_ecount(count) uint32_t const *input, 3337 __in size_t count, 3338 __in uint32_t init); 3339 3340 LIBEFX_API 3341 extern __checkReturn uint32_t 3342 efx_hash_bytes( 3343 __in_ecount(length) uint8_t const *input, 3344 __in size_t length, 3345 __in uint32_t init); 3346 3347 #if EFSYS_OPT_LICENSING 3348 3349 /* LICENSING */ 3350 3351 typedef struct efx_key_stats_s { 3352 uint32_t eks_valid; 3353 uint32_t eks_invalid; 3354 uint32_t eks_blacklisted; 3355 uint32_t eks_unverifiable; 3356 uint32_t eks_wrong_node; 3357 uint32_t eks_licensed_apps_lo; 3358 uint32_t eks_licensed_apps_hi; 3359 uint32_t eks_licensed_features_lo; 3360 uint32_t eks_licensed_features_hi; 3361 } efx_key_stats_t; 3362 3363 LIBEFX_API 3364 extern __checkReturn efx_rc_t 3365 efx_lic_init( 3366 __in efx_nic_t *enp); 3367 3368 LIBEFX_API 3369 extern void 3370 efx_lic_fini( 3371 __in efx_nic_t *enp); 3372 3373 LIBEFX_API 3374 extern __checkReturn boolean_t 3375 efx_lic_check_support( 3376 __in efx_nic_t *enp); 3377 3378 LIBEFX_API 3379 extern __checkReturn efx_rc_t 3380 efx_lic_update_licenses( 3381 __in efx_nic_t *enp); 3382 3383 LIBEFX_API 3384 extern __checkReturn efx_rc_t 3385 efx_lic_get_key_stats( 3386 __in efx_nic_t *enp, 3387 __out efx_key_stats_t *ksp); 3388 3389 LIBEFX_API 3390 extern __checkReturn efx_rc_t 3391 efx_lic_app_state( 3392 __in efx_nic_t *enp, 3393 __in uint64_t app_id, 3394 __out boolean_t *licensedp); 3395 3396 LIBEFX_API 3397 extern __checkReturn efx_rc_t 3398 efx_lic_get_id( 3399 __in efx_nic_t *enp, 3400 __in size_t buffer_size, 3401 __out uint32_t *typep, 3402 __out size_t *lengthp, 3403 __out_opt uint8_t *bufferp); 3404 3405 3406 LIBEFX_API 3407 extern __checkReturn efx_rc_t 3408 efx_lic_find_start( 3409 __in efx_nic_t *enp, 3410 __in_bcount(buffer_size) 3411 caddr_t bufferp, 3412 __in size_t buffer_size, 3413 __out uint32_t *startp); 3414 3415 LIBEFX_API 3416 extern __checkReturn efx_rc_t 3417 efx_lic_find_end( 3418 __in efx_nic_t *enp, 3419 __in_bcount(buffer_size) 3420 caddr_t bufferp, 3421 __in size_t buffer_size, 3422 __in uint32_t offset, 3423 __out uint32_t *endp); 3424 3425 LIBEFX_API 3426 extern __checkReturn __success(return != B_FALSE) boolean_t 3427 efx_lic_find_key( 3428 __in efx_nic_t *enp, 3429 __in_bcount(buffer_size) 3430 caddr_t bufferp, 3431 __in size_t buffer_size, 3432 __in uint32_t offset, 3433 __out uint32_t *startp, 3434 __out uint32_t *lengthp); 3435 3436 LIBEFX_API 3437 extern __checkReturn __success(return != B_FALSE) boolean_t 3438 efx_lic_validate_key( 3439 __in efx_nic_t *enp, 3440 __in_bcount(length) caddr_t keyp, 3441 __in uint32_t length); 3442 3443 LIBEFX_API 3444 extern __checkReturn efx_rc_t 3445 efx_lic_read_key( 3446 __in efx_nic_t *enp, 3447 __in_bcount(buffer_size) 3448 caddr_t bufferp, 3449 __in size_t buffer_size, 3450 __in uint32_t offset, 3451 __in uint32_t length, 3452 __out_bcount_part(key_max_size, *lengthp) 3453 caddr_t keyp, 3454 __in size_t key_max_size, 3455 __out uint32_t *lengthp); 3456 3457 LIBEFX_API 3458 extern __checkReturn efx_rc_t 3459 efx_lic_write_key( 3460 __in efx_nic_t *enp, 3461 __in_bcount(buffer_size) 3462 caddr_t bufferp, 3463 __in size_t buffer_size, 3464 __in uint32_t offset, 3465 __in_bcount(length) caddr_t keyp, 3466 __in uint32_t length, 3467 __out uint32_t *lengthp); 3468 3469 LIBEFX_API 3470 extern __checkReturn efx_rc_t 3471 efx_lic_delete_key( 3472 __in efx_nic_t *enp, 3473 __in_bcount(buffer_size) 3474 caddr_t bufferp, 3475 __in size_t buffer_size, 3476 __in uint32_t offset, 3477 __in uint32_t length, 3478 __in uint32_t end, 3479 __out uint32_t *deltap); 3480 3481 LIBEFX_API 3482 extern __checkReturn efx_rc_t 3483 efx_lic_create_partition( 3484 __in efx_nic_t *enp, 3485 __in_bcount(buffer_size) 3486 caddr_t bufferp, 3487 __in size_t buffer_size); 3488 3489 extern __checkReturn efx_rc_t 3490 efx_lic_finish_partition( 3491 __in efx_nic_t *enp, 3492 __in_bcount(buffer_size) 3493 caddr_t bufferp, 3494 __in size_t buffer_size); 3495 3496 #endif /* EFSYS_OPT_LICENSING */ 3497 3498 /* TUNNEL */ 3499 3500 #if EFSYS_OPT_TUNNEL 3501 3502 LIBEFX_API 3503 extern __checkReturn efx_rc_t 3504 efx_tunnel_init( 3505 __in efx_nic_t *enp); 3506 3507 LIBEFX_API 3508 extern void 3509 efx_tunnel_fini( 3510 __in efx_nic_t *enp); 3511 3512 /* 3513 * For overlay network encapsulation using UDP, the firmware needs to know 3514 * the configured UDP port for the overlay so it can decode encapsulated 3515 * frames correctly. 3516 * The UDP port/protocol list is global. 3517 */ 3518 3519 LIBEFX_API 3520 extern __checkReturn efx_rc_t 3521 efx_tunnel_config_udp_add( 3522 __in efx_nic_t *enp, 3523 __in uint16_t port /* host/cpu-endian */, 3524 __in efx_tunnel_protocol_t protocol); 3525 3526 LIBEFX_API 3527 extern __checkReturn efx_rc_t 3528 efx_tunnel_config_udp_remove( 3529 __in efx_nic_t *enp, 3530 __in uint16_t port /* host/cpu-endian */, 3531 __in efx_tunnel_protocol_t protocol); 3532 3533 LIBEFX_API 3534 extern void 3535 efx_tunnel_config_clear( 3536 __in efx_nic_t *enp); 3537 3538 /** 3539 * Apply tunnel UDP ports configuration to hardware. 3540 * 3541 * EAGAIN is returned if hardware will be reset (datapath and managment CPU 3542 * reboot). 3543 */ 3544 LIBEFX_API 3545 extern __checkReturn efx_rc_t 3546 efx_tunnel_reconfigure( 3547 __in efx_nic_t *enp); 3548 3549 #endif /* EFSYS_OPT_TUNNEL */ 3550 3551 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3552 3553 /** 3554 * Firmware subvariant choice options. 3555 * 3556 * It may be switched to no Tx checksum if attached drivers are either 3557 * preboot or firmware subvariant aware and no VIS are allocated. 3558 * If may be always switched to default explicitly using set request or 3559 * implicitly if unaware driver is attaching. If switching is done when 3560 * a driver is attached, it gets MC_REBOOT event and should recreate its 3561 * datapath. 3562 * 3563 * See SF-119419-TC DPDK Firmware Driver Interface and 3564 * SF-109306-TC EF10 for Driver Writers for details. 3565 */ 3566 typedef enum efx_nic_fw_subvariant_e { 3567 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3568 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3569 EFX_NIC_FW_SUBVARIANT_NTYPES 3570 } efx_nic_fw_subvariant_t; 3571 3572 LIBEFX_API 3573 extern __checkReturn efx_rc_t 3574 efx_nic_get_fw_subvariant( 3575 __in efx_nic_t *enp, 3576 __out efx_nic_fw_subvariant_t *subvariantp); 3577 3578 LIBEFX_API 3579 extern __checkReturn efx_rc_t 3580 efx_nic_set_fw_subvariant( 3581 __in efx_nic_t *enp, 3582 __in efx_nic_fw_subvariant_t subvariant); 3583 3584 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3585 3586 typedef enum efx_phy_fec_type_e { 3587 EFX_PHY_FEC_NONE = 0, 3588 EFX_PHY_FEC_BASER, 3589 EFX_PHY_FEC_RS 3590 } efx_phy_fec_type_t; 3591 3592 LIBEFX_API 3593 extern __checkReturn efx_rc_t 3594 efx_phy_fec_type_get( 3595 __in efx_nic_t *enp, 3596 __out efx_phy_fec_type_t *typep); 3597 3598 typedef struct efx_phy_link_state_s { 3599 uint32_t epls_adv_cap_mask; 3600 uint32_t epls_lp_cap_mask; 3601 uint32_t epls_ld_cap_mask; 3602 unsigned int epls_fcntl; 3603 efx_phy_fec_type_t epls_fec; 3604 efx_link_mode_t epls_link_mode; 3605 } efx_phy_link_state_t; 3606 3607 LIBEFX_API 3608 extern __checkReturn efx_rc_t 3609 efx_phy_link_state_get( 3610 __in efx_nic_t *enp, 3611 __out efx_phy_link_state_t *eplsp); 3612 3613 3614 #if EFSYS_OPT_EVB 3615 3616 typedef uint32_t efx_vswitch_id_t; 3617 typedef uint32_t efx_vport_id_t; 3618 3619 typedef enum efx_vswitch_type_e { 3620 EFX_VSWITCH_TYPE_VLAN = 1, 3621 EFX_VSWITCH_TYPE_VEB, 3622 /* VSWITCH_TYPE_VEPA: obsolete */ 3623 EFX_VSWITCH_TYPE_MUX = 4, 3624 } efx_vswitch_type_t; 3625 3626 typedef enum efx_vport_type_e { 3627 EFX_VPORT_TYPE_NORMAL = 4, 3628 EFX_VPORT_TYPE_EXPANSION, 3629 EFX_VPORT_TYPE_TEST, 3630 } efx_vport_type_t; 3631 3632 /* Unspecified VLAN ID to support disabling of VLAN filtering */ 3633 #define EFX_FILTER_VID_UNSPEC 0xffff 3634 #define EFX_DEFAULT_VSWITCH_ID 1 3635 3636 /* Default VF VLAN ID on creation */ 3637 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC 3638 #define EFX_VPORT_ID_INVALID 0 3639 3640 typedef struct efx_vport_config_s { 3641 /* Either VF index or 0xffff for PF */ 3642 uint16_t evc_function; 3643 /* VLAN ID of the associated function */ 3644 uint16_t evc_vid; 3645 /* vport id shared with client driver */ 3646 efx_vport_id_t evc_vport_id; 3647 /* MAC address of the associated function */ 3648 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; 3649 /* 3650 * vports created with this flag set may only transfer traffic on the 3651 * VLANs permitted by the vport. Also, an attempt to install filter with 3652 * VLAN will be refused unless requesting function has VLAN privilege. 3653 */ 3654 boolean_t evc_vlan_restrict; 3655 /* Whether this function is assigned or not */ 3656 boolean_t evc_vport_assigned; 3657 } efx_vport_config_t; 3658 3659 typedef struct efx_vswitch_s efx_vswitch_t; 3660 3661 LIBEFX_API 3662 extern __checkReturn efx_rc_t 3663 efx_evb_init( 3664 __in efx_nic_t *enp); 3665 3666 LIBEFX_API 3667 extern void 3668 efx_evb_fini( 3669 __in efx_nic_t *enp); 3670 3671 LIBEFX_API 3672 extern __checkReturn efx_rc_t 3673 efx_evb_vswitch_create( 3674 __in efx_nic_t *enp, 3675 __in uint32_t num_vports, 3676 __inout_ecount(num_vports) efx_vport_config_t *vport_configp, 3677 __deref_out efx_vswitch_t **evpp); 3678 3679 LIBEFX_API 3680 extern __checkReturn efx_rc_t 3681 efx_evb_vswitch_destroy( 3682 __in efx_nic_t *enp, 3683 __in efx_vswitch_t *evp); 3684 3685 LIBEFX_API 3686 extern __checkReturn efx_rc_t 3687 efx_evb_vport_mac_set( 3688 __in efx_nic_t *enp, 3689 __in efx_vswitch_t *evp, 3690 __in efx_vport_id_t vport_id, 3691 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); 3692 3693 LIBEFX_API 3694 extern __checkReturn efx_rc_t 3695 efx_evb_vport_vlan_set( 3696 __in efx_nic_t *enp, 3697 __in efx_vswitch_t *evp, 3698 __in efx_vport_id_t vport_id, 3699 __in uint16_t vid); 3700 3701 LIBEFX_API 3702 extern __checkReturn efx_rc_t 3703 efx_evb_vport_reset( 3704 __in efx_nic_t *enp, 3705 __in efx_vswitch_t *evp, 3706 __in efx_vport_id_t vport_id, 3707 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, 3708 __in uint16_t vid, 3709 __out boolean_t *is_fn_resetp); 3710 3711 LIBEFX_API 3712 extern __checkReturn efx_rc_t 3713 efx_evb_vport_stats( 3714 __in efx_nic_t *enp, 3715 __in efx_vswitch_t *evp, 3716 __in efx_vport_id_t vport_id, 3717 __out efsys_mem_t *stats_bufferp); 3718 3719 #endif /* EFSYS_OPT_EVB */ 3720 3721 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 3722 3723 typedef struct efx_proxy_auth_config_s { 3724 efsys_mem_t *request_bufferp; 3725 efsys_mem_t *response_bufferp; 3726 efsys_mem_t *status_bufferp; 3727 uint32_t block_cnt; 3728 uint32_t *op_listp; 3729 size_t op_count; 3730 uint32_t handled_privileges; 3731 } efx_proxy_auth_config_t; 3732 3733 typedef struct efx_proxy_cmd_params_s { 3734 uint32_t pf_index; 3735 uint32_t vf_index; 3736 uint8_t *request_bufferp; 3737 size_t request_size; 3738 uint8_t *response_bufferp; 3739 size_t response_size; 3740 size_t *response_size_actualp; 3741 } efx_proxy_cmd_params_t; 3742 3743 LIBEFX_API 3744 extern __checkReturn efx_rc_t 3745 efx_proxy_auth_init( 3746 __in efx_nic_t *enp); 3747 3748 LIBEFX_API 3749 extern void 3750 efx_proxy_auth_fini( 3751 __in efx_nic_t *enp); 3752 3753 LIBEFX_API 3754 extern __checkReturn efx_rc_t 3755 efx_proxy_auth_configure( 3756 __in efx_nic_t *enp, 3757 __in efx_proxy_auth_config_t *configp); 3758 3759 LIBEFX_API 3760 extern __checkReturn efx_rc_t 3761 efx_proxy_auth_destroy( 3762 __in efx_nic_t *enp, 3763 __in uint32_t handled_privileges); 3764 3765 LIBEFX_API 3766 extern __checkReturn efx_rc_t 3767 efx_proxy_auth_complete_request( 3768 __in efx_nic_t *enp, 3769 __in uint32_t fn_index, 3770 __in uint32_t proxy_result, 3771 __in uint32_t handle); 3772 3773 LIBEFX_API 3774 extern __checkReturn efx_rc_t 3775 efx_proxy_auth_exec_cmd( 3776 __in efx_nic_t *enp, 3777 __inout efx_proxy_cmd_params_t *paramsp); 3778 3779 LIBEFX_API 3780 extern __checkReturn efx_rc_t 3781 efx_proxy_auth_set_privilege_mask( 3782 __in efx_nic_t *enp, 3783 __in uint32_t vf_index, 3784 __in uint32_t mask, 3785 __in uint32_t value); 3786 3787 LIBEFX_API 3788 extern __checkReturn efx_rc_t 3789 efx_proxy_auth_privilege_mask_get( 3790 __in efx_nic_t *enp, 3791 __in uint32_t pf_index, 3792 __in uint32_t vf_index, 3793 __out uint32_t *maskp); 3794 3795 LIBEFX_API 3796 extern __checkReturn efx_rc_t 3797 efx_proxy_auth_privilege_modify( 3798 __in efx_nic_t *enp, 3799 __in uint32_t pf_index, 3800 __in uint32_t vf_index, 3801 __in uint32_t add_privileges_mask, 3802 __in uint32_t remove_privileges_mask); 3803 3804 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 3805 3806 #ifdef __cplusplus 3807 } 3808 #endif 3809 3810 #endif /* _SYS_EFX_H */ 3811