1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2006-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_H 8 #define _SYS_EFX_H 9 10 #include "efx_annote.h" 11 #include "efsys.h" 12 #include "efx_types.h" 13 #include "efx_check.h" 14 #include "efx_phy_ids.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define EFX_STATIC_ASSERT(_cond) \ 21 ((void)sizeof (char[(_cond) ? 1 : -1])) 22 23 #define EFX_ARRAY_SIZE(_array) \ 24 (sizeof (_array) / sizeof ((_array)[0])) 25 26 #define EFX_FIELD_OFFSET(_type, _field) \ 27 ((size_t)&(((_type *)0)->_field)) 28 29 /* The macro expands divider twice */ 30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 31 32 /* Round value up to the nearest power of two. */ 33 #define EFX_P2ROUNDUP(_type, _value, _align) \ 34 (-(-(_type)(_value) & -(_type)(_align))) 35 36 /* Align value down to the nearest power of two. */ 37 #define EFX_P2ALIGN(_type, _value, _align) \ 38 ((_type)(_value) & -(_type)(_align)) 39 40 /* Test if value is power of 2 aligned. */ 41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 43 44 /* Return codes */ 45 46 typedef __success(return == 0) int efx_rc_t; 47 48 49 /* Chip families */ 50 51 typedef enum efx_family_e { 52 EFX_FAMILY_INVALID, 53 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 54 EFX_FAMILY_SIENA, 55 EFX_FAMILY_HUNTINGTON, 56 EFX_FAMILY_MEDFORD, 57 EFX_FAMILY_MEDFORD2, 58 EFX_FAMILY_RIVERHEAD, 59 EFX_FAMILY_NTYPES 60 } efx_family_t; 61 62 typedef enum efx_bar_type_e { 63 EFX_BAR_TYPE_MEM, 64 EFX_BAR_TYPE_IO 65 } efx_bar_type_t; 66 67 typedef struct efx_bar_region_s { 68 efx_bar_type_t ebr_type; 69 int ebr_index; 70 efsys_dma_addr_t ebr_offset; 71 efsys_dma_addr_t ebr_length; 72 } efx_bar_region_t; 73 74 /* The function is deprecated. It is used only if Riverhead is not supported. */ 75 LIBEFX_API 76 extern __checkReturn efx_rc_t 77 efx_family( 78 __in uint16_t venid, 79 __in uint16_t devid, 80 __out efx_family_t *efp, 81 __out unsigned int *membarp); 82 83 #if EFSYS_OPT_PCI 84 85 /* PCIe interface numbers for multi-host configurations. */ 86 typedef enum efx_pcie_interface_e { 87 EFX_PCIE_INTERFACE_CALLER = 1000, 88 EFX_PCIE_INTERFACE_HOST_PRIMARY, 89 EFX_PCIE_INTERFACE_NIC_EMBEDDED, 90 } efx_pcie_interface_t; 91 92 typedef struct efx_pci_ops_s { 93 /* 94 * Function for reading PCIe configuration space. 95 * 96 * espcp System-specific PCIe device handle; 97 * offset Offset inside PCIe configuration space to start reading 98 * from; 99 * edp EFX DWORD structure that should be populated by function 100 * in little-endian order; 101 * 102 * Returns status code, 0 on success, any other value on error. 103 */ 104 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp, 105 uint32_t offset, efx_dword_t *edp); 106 /* 107 * Function for finding PCIe memory bar handle by its index from a PCIe 108 * device handle. The found memory bar is available in read-only mode. 109 * 110 * configp System-specific PCIe device handle; 111 * index Memory bar index; 112 * memp Pointer to the found memory bar handle; 113 * 114 * Returns status code, 0 on success, any other value on error. 115 */ 116 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp, 117 int index, efsys_bar_t *memp); 118 } efx_pci_ops_t; 119 120 /* Determine EFX family and perform lookup of the function control window 121 * 122 * The function requires PCI config handle from which all memory bars can 123 * be accessed. 124 * A user of the API must be aware of memory bars indexes (not available 125 * on Windows). 126 */ 127 LIBEFX_API 128 extern __checkReturn efx_rc_t 129 efx_family_probe_bar( 130 __in uint16_t venid, 131 __in uint16_t devid, 132 __in efsys_pci_config_t *espcp, 133 __in const efx_pci_ops_t *epop, 134 __out efx_family_t *efp, 135 __out efx_bar_region_t *ebrp); 136 137 #endif /* EFSYS_OPT_PCI */ 138 139 140 #define EFX_PCI_VENID_SFC 0x1924 141 #define EFX_PCI_VENID_XILINX 0x10EE 142 143 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 144 145 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 146 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 147 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 148 149 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 150 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 151 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 152 153 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 154 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 155 156 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 157 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 158 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 159 160 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 161 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 162 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 163 164 #define EFX_PCI_DEVID_RIVERHEAD 0x0100 165 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100 166 167 #define EFX_MEM_BAR_SIENA 2 168 169 #define EFX_MEM_BAR_HUNTINGTON_PF 2 170 #define EFX_MEM_BAR_HUNTINGTON_VF 0 171 172 #define EFX_MEM_BAR_MEDFORD_PF 2 173 #define EFX_MEM_BAR_MEDFORD_VF 0 174 175 #define EFX_MEM_BAR_MEDFORD2 0 176 177 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */ 178 #define EFX_MEM_BAR_RIVERHEAD 2 179 180 181 /* Error codes */ 182 183 enum { 184 EFX_ERR_INVALID, 185 EFX_ERR_SRAM_OOB, 186 EFX_ERR_BUFID_DC_OOB, 187 EFX_ERR_MEM_PERR, 188 EFX_ERR_RBUF_OWN, 189 EFX_ERR_TBUF_OWN, 190 EFX_ERR_RDESQ_OWN, 191 EFX_ERR_TDESQ_OWN, 192 EFX_ERR_EVQ_OWN, 193 EFX_ERR_EVFF_OFLO, 194 EFX_ERR_ILL_ADDR, 195 EFX_ERR_SRAM_PERR, 196 EFX_ERR_NCODES 197 }; 198 199 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 200 LIBEFX_API 201 extern __checkReturn uint32_t 202 efx_crc32_calculate( 203 __in uint32_t crc_init, 204 __in_ecount(length) uint8_t const *input, 205 __in int length); 206 207 208 /* Type prototypes */ 209 210 typedef struct efx_rxq_s efx_rxq_t; 211 212 /* NIC */ 213 214 typedef struct efx_nic_s efx_nic_t; 215 216 LIBEFX_API 217 extern __checkReturn efx_rc_t 218 efx_nic_create( 219 __in efx_family_t family, 220 __in efsys_identifier_t *esip, 221 __in efsys_bar_t *esbp, 222 __in uint32_t fcw_offset, 223 __in efsys_lock_t *eslp, 224 __deref_out efx_nic_t **enpp); 225 226 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 227 typedef enum efx_fw_variant_e { 228 EFX_FW_VARIANT_FULL_FEATURED, 229 EFX_FW_VARIANT_LOW_LATENCY, 230 EFX_FW_VARIANT_PACKED_STREAM, 231 EFX_FW_VARIANT_HIGH_TX_RATE, 232 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 233 EFX_FW_VARIANT_RULES_ENGINE, 234 EFX_FW_VARIANT_DPDK, 235 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 236 } efx_fw_variant_t; 237 238 LIBEFX_API 239 extern __checkReturn efx_rc_t 240 efx_nic_probe( 241 __in efx_nic_t *enp, 242 __in efx_fw_variant_t efv); 243 244 LIBEFX_API 245 extern __checkReturn efx_rc_t 246 efx_nic_init( 247 __in efx_nic_t *enp); 248 249 LIBEFX_API 250 extern __checkReturn efx_rc_t 251 efx_nic_reset( 252 __in efx_nic_t *enp); 253 254 LIBEFX_API 255 extern __checkReturn boolean_t 256 efx_nic_hw_unavailable( 257 __in efx_nic_t *enp); 258 259 LIBEFX_API 260 extern void 261 efx_nic_set_hw_unavailable( 262 __in efx_nic_t *enp); 263 264 #if EFSYS_OPT_DIAG 265 266 LIBEFX_API 267 extern __checkReturn efx_rc_t 268 efx_nic_register_test( 269 __in efx_nic_t *enp); 270 271 #endif /* EFSYS_OPT_DIAG */ 272 273 LIBEFX_API 274 extern void 275 efx_nic_fini( 276 __in efx_nic_t *enp); 277 278 LIBEFX_API 279 extern void 280 efx_nic_unprobe( 281 __in efx_nic_t *enp); 282 283 LIBEFX_API 284 extern void 285 efx_nic_destroy( 286 __in efx_nic_t *enp); 287 288 #define EFX_PCIE_LINK_SPEED_GEN1 1 289 #define EFX_PCIE_LINK_SPEED_GEN2 2 290 #define EFX_PCIE_LINK_SPEED_GEN3 3 291 292 typedef enum efx_pcie_link_performance_e { 293 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 294 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 295 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 296 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 297 } efx_pcie_link_performance_t; 298 299 LIBEFX_API 300 extern __checkReturn efx_rc_t 301 efx_nic_calculate_pcie_link_bandwidth( 302 __in uint32_t pcie_link_width, 303 __in uint32_t pcie_link_gen, 304 __out uint32_t *bandwidth_mbpsp); 305 306 LIBEFX_API 307 extern __checkReturn efx_rc_t 308 efx_nic_check_pcie_link_speed( 309 __in efx_nic_t *enp, 310 __in uint32_t pcie_link_width, 311 __in uint32_t pcie_link_gen, 312 __out efx_pcie_link_performance_t *resultp); 313 314 #if EFSYS_OPT_MCDI 315 316 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 317 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */ 318 #define WITH_MCDI_V2 1 319 #endif 320 321 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 322 323 typedef enum efx_mcdi_exception_e { 324 EFX_MCDI_EXCEPTION_MC_REBOOT, 325 EFX_MCDI_EXCEPTION_MC_BADASSERT, 326 } efx_mcdi_exception_t; 327 328 #if EFSYS_OPT_MCDI_LOGGING 329 typedef enum efx_log_msg_e { 330 EFX_LOG_INVALID, 331 EFX_LOG_MCDI_REQUEST, 332 EFX_LOG_MCDI_RESPONSE, 333 } efx_log_msg_t; 334 #endif /* EFSYS_OPT_MCDI_LOGGING */ 335 336 typedef struct efx_mcdi_transport_s { 337 void *emt_context; 338 efsys_mem_t *emt_dma_mem; 339 void (*emt_execute)(void *, efx_mcdi_req_t *); 340 void (*emt_ev_cpl)(void *); 341 void (*emt_exception)(void *, efx_mcdi_exception_t); 342 #if EFSYS_OPT_MCDI_LOGGING 343 void (*emt_logger)(void *, efx_log_msg_t, 344 void *, size_t, void *, size_t); 345 #endif /* EFSYS_OPT_MCDI_LOGGING */ 346 #if EFSYS_OPT_MCDI_PROXY_AUTH 347 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 348 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 349 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 350 void (*emt_ev_proxy_request)(void *, uint32_t); 351 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 352 } efx_mcdi_transport_t; 353 354 LIBEFX_API 355 extern __checkReturn efx_rc_t 356 efx_mcdi_init( 357 __in efx_nic_t *enp, 358 __in const efx_mcdi_transport_t *mtp); 359 360 LIBEFX_API 361 extern __checkReturn efx_rc_t 362 efx_mcdi_reboot( 363 __in efx_nic_t *enp); 364 365 LIBEFX_API 366 extern void 367 efx_mcdi_new_epoch( 368 __in efx_nic_t *enp); 369 370 LIBEFX_API 371 extern void 372 efx_mcdi_get_timeout( 373 __in efx_nic_t *enp, 374 __in efx_mcdi_req_t *emrp, 375 __out uint32_t *usec_timeoutp); 376 377 LIBEFX_API 378 extern void 379 efx_mcdi_request_start( 380 __in efx_nic_t *enp, 381 __in efx_mcdi_req_t *emrp, 382 __in boolean_t ev_cpl); 383 384 LIBEFX_API 385 extern __checkReturn boolean_t 386 efx_mcdi_request_poll( 387 __in efx_nic_t *enp); 388 389 LIBEFX_API 390 extern __checkReturn boolean_t 391 efx_mcdi_request_abort( 392 __in efx_nic_t *enp); 393 394 LIBEFX_API 395 extern __checkReturn efx_rc_t 396 efx_mcdi_get_client_handle( 397 __in efx_nic_t *enp, 398 __in efx_pcie_interface_t intf, 399 __in uint16_t pf, 400 __in uint16_t vf, 401 __out uint32_t *handle); 402 403 LIBEFX_API 404 extern __checkReturn efx_rc_t 405 efx_mcdi_get_own_client_handle( 406 __in efx_nic_t *enp, 407 __out uint32_t *handle); 408 409 LIBEFX_API 410 extern void 411 efx_mcdi_fini( 412 __in efx_nic_t *enp); 413 414 #endif /* EFSYS_OPT_MCDI */ 415 416 /* INTR */ 417 418 #define EFX_NINTR_SIENA 1024 419 420 typedef enum efx_intr_type_e { 421 EFX_INTR_INVALID = 0, 422 EFX_INTR_LINE, 423 EFX_INTR_MESSAGE, 424 EFX_INTR_NTYPES 425 } efx_intr_type_t; 426 427 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 428 429 LIBEFX_API 430 extern __checkReturn efx_rc_t 431 efx_intr_init( 432 __in efx_nic_t *enp, 433 __in efx_intr_type_t type, 434 __in_opt efsys_mem_t *esmp); 435 436 LIBEFX_API 437 extern void 438 efx_intr_enable( 439 __in efx_nic_t *enp); 440 441 LIBEFX_API 442 extern void 443 efx_intr_disable( 444 __in efx_nic_t *enp); 445 446 LIBEFX_API 447 extern void 448 efx_intr_disable_unlocked( 449 __in efx_nic_t *enp); 450 451 #define EFX_INTR_NEVQS 32 452 453 LIBEFX_API 454 extern __checkReturn efx_rc_t 455 efx_intr_trigger( 456 __in efx_nic_t *enp, 457 __in unsigned int level); 458 459 LIBEFX_API 460 extern void 461 efx_intr_status_line( 462 __in efx_nic_t *enp, 463 __out boolean_t *fatalp, 464 __out uint32_t *maskp); 465 466 LIBEFX_API 467 extern void 468 efx_intr_status_message( 469 __in efx_nic_t *enp, 470 __in unsigned int message, 471 __out boolean_t *fatalp); 472 473 LIBEFX_API 474 extern void 475 efx_intr_fatal( 476 __in efx_nic_t *enp); 477 478 LIBEFX_API 479 extern void 480 efx_intr_fini( 481 __in efx_nic_t *enp); 482 483 /* MAC */ 484 485 #if EFSYS_OPT_MAC_STATS 486 487 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 488 typedef enum efx_mac_stat_e { 489 EFX_MAC_RX_OCTETS, 490 EFX_MAC_RX_PKTS, 491 EFX_MAC_RX_UNICST_PKTS, 492 EFX_MAC_RX_MULTICST_PKTS, 493 EFX_MAC_RX_BRDCST_PKTS, 494 EFX_MAC_RX_PAUSE_PKTS, 495 EFX_MAC_RX_LE_64_PKTS, 496 EFX_MAC_RX_65_TO_127_PKTS, 497 EFX_MAC_RX_128_TO_255_PKTS, 498 EFX_MAC_RX_256_TO_511_PKTS, 499 EFX_MAC_RX_512_TO_1023_PKTS, 500 EFX_MAC_RX_1024_TO_15XX_PKTS, 501 EFX_MAC_RX_GE_15XX_PKTS, 502 EFX_MAC_RX_ERRORS, 503 EFX_MAC_RX_FCS_ERRORS, 504 EFX_MAC_RX_DROP_EVENTS, 505 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 506 EFX_MAC_RX_SYMBOL_ERRORS, 507 EFX_MAC_RX_ALIGN_ERRORS, 508 EFX_MAC_RX_INTERNAL_ERRORS, 509 EFX_MAC_RX_JABBER_PKTS, 510 EFX_MAC_RX_LANE0_CHAR_ERR, 511 EFX_MAC_RX_LANE1_CHAR_ERR, 512 EFX_MAC_RX_LANE2_CHAR_ERR, 513 EFX_MAC_RX_LANE3_CHAR_ERR, 514 EFX_MAC_RX_LANE0_DISP_ERR, 515 EFX_MAC_RX_LANE1_DISP_ERR, 516 EFX_MAC_RX_LANE2_DISP_ERR, 517 EFX_MAC_RX_LANE3_DISP_ERR, 518 EFX_MAC_RX_MATCH_FAULT, 519 EFX_MAC_RX_NODESC_DROP_CNT, 520 EFX_MAC_TX_OCTETS, 521 EFX_MAC_TX_PKTS, 522 EFX_MAC_TX_UNICST_PKTS, 523 EFX_MAC_TX_MULTICST_PKTS, 524 EFX_MAC_TX_BRDCST_PKTS, 525 EFX_MAC_TX_PAUSE_PKTS, 526 EFX_MAC_TX_LE_64_PKTS, 527 EFX_MAC_TX_65_TO_127_PKTS, 528 EFX_MAC_TX_128_TO_255_PKTS, 529 EFX_MAC_TX_256_TO_511_PKTS, 530 EFX_MAC_TX_512_TO_1023_PKTS, 531 EFX_MAC_TX_1024_TO_15XX_PKTS, 532 EFX_MAC_TX_GE_15XX_PKTS, 533 EFX_MAC_TX_ERRORS, 534 EFX_MAC_TX_SGL_COL_PKTS, 535 EFX_MAC_TX_MULT_COL_PKTS, 536 EFX_MAC_TX_EX_COL_PKTS, 537 EFX_MAC_TX_LATE_COL_PKTS, 538 EFX_MAC_TX_DEF_PKTS, 539 EFX_MAC_TX_EX_DEF_PKTS, 540 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 541 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 542 EFX_MAC_PM_TRUNC_VFIFO_FULL, 543 EFX_MAC_PM_DISCARD_VFIFO_FULL, 544 EFX_MAC_PM_TRUNC_QBB, 545 EFX_MAC_PM_DISCARD_QBB, 546 EFX_MAC_PM_DISCARD_MAPPING, 547 EFX_MAC_RXDP_Q_DISABLED_PKTS, 548 EFX_MAC_RXDP_DI_DROPPED_PKTS, 549 EFX_MAC_RXDP_STREAMING_PKTS, 550 EFX_MAC_RXDP_HLB_FETCH, 551 EFX_MAC_RXDP_HLB_WAIT, 552 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 553 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 554 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 555 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 556 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 557 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 558 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 559 EFX_MAC_VADAPTER_RX_BAD_BYTES, 560 EFX_MAC_VADAPTER_RX_OVERFLOW, 561 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 562 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 563 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 564 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 565 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 566 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 567 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 568 EFX_MAC_VADAPTER_TX_BAD_BYTES, 569 EFX_MAC_VADAPTER_TX_OVERFLOW, 570 EFX_MAC_FEC_UNCORRECTED_ERRORS, 571 EFX_MAC_FEC_CORRECTED_ERRORS, 572 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 573 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 574 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 575 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 576 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 577 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 578 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 579 EFX_MAC_CTPIO_OVERFLOW_FAIL, 580 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 581 EFX_MAC_CTPIO_TIMEOUT_FAIL, 582 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 583 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 584 EFX_MAC_CTPIO_INVALID_WR_FAIL, 585 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 586 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 587 EFX_MAC_CTPIO_RUNT_FALLBACK, 588 EFX_MAC_CTPIO_SUCCESS, 589 EFX_MAC_CTPIO_FALLBACK, 590 EFX_MAC_CTPIO_POISON, 591 EFX_MAC_CTPIO_ERASE, 592 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 593 EFX_MAC_RXDP_HLB_IDLE, 594 EFX_MAC_RXDP_HLB_TIMEOUT, 595 EFX_MAC_NSTATS 596 } efx_mac_stat_t; 597 598 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 599 600 #endif /* EFSYS_OPT_MAC_STATS */ 601 602 typedef enum efx_link_mode_e { 603 EFX_LINK_UNKNOWN = 0, 604 EFX_LINK_DOWN, 605 EFX_LINK_10HDX, 606 EFX_LINK_10FDX, 607 EFX_LINK_100HDX, 608 EFX_LINK_100FDX, 609 EFX_LINK_1000HDX, 610 EFX_LINK_1000FDX, 611 EFX_LINK_10000FDX, 612 EFX_LINK_40000FDX, 613 EFX_LINK_25000FDX, 614 EFX_LINK_50000FDX, 615 EFX_LINK_100000FDX, 616 EFX_LINK_NMODES 617 } efx_link_mode_t; 618 619 #define EFX_MAC_ADDR_LEN 6 620 621 #define EFX_VNI_OR_VSID_LEN 3 622 623 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 624 625 #define EFX_MAC_MULTICAST_LIST_MAX 256 626 627 #define EFX_MAC_SDU_MAX 9202 628 629 #define EFX_MAC_PDU_ADJUSTMENT \ 630 (/* EtherII */ 14 \ 631 + /* VLAN */ 4 \ 632 + /* CRC */ 4 \ 633 + /* bug16011 */ 16) \ 634 635 #define EFX_MAC_PDU(_sdu) \ 636 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 637 638 /* 639 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 640 * the SDU rounded up slightly. 641 */ 642 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 643 644 #define EFX_MAC_PDU_MIN 60 645 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 646 647 LIBEFX_API 648 extern __checkReturn efx_rc_t 649 efx_mac_pdu_get( 650 __in efx_nic_t *enp, 651 __out size_t *pdu); 652 653 LIBEFX_API 654 extern __checkReturn efx_rc_t 655 efx_mac_pdu_set( 656 __in efx_nic_t *enp, 657 __in size_t pdu); 658 659 LIBEFX_API 660 extern __checkReturn efx_rc_t 661 efx_mac_addr_set( 662 __in efx_nic_t *enp, 663 __in uint8_t *addr); 664 665 LIBEFX_API 666 extern __checkReturn efx_rc_t 667 efx_mac_filter_set( 668 __in efx_nic_t *enp, 669 __in boolean_t all_unicst, 670 __in boolean_t mulcst, 671 __in boolean_t all_mulcst, 672 __in boolean_t brdcst); 673 674 LIBEFX_API 675 extern void 676 efx_mac_filter_get_all_ucast_mcast( 677 __in efx_nic_t *enp, 678 __out boolean_t *all_unicst, 679 __out boolean_t *all_mulcst); 680 681 LIBEFX_API 682 extern __checkReturn efx_rc_t 683 efx_mac_multicast_list_set( 684 __in efx_nic_t *enp, 685 __in_ecount(6*count) uint8_t const *addrs, 686 __in int count); 687 688 LIBEFX_API 689 extern __checkReturn efx_rc_t 690 efx_mac_filter_default_rxq_set( 691 __in efx_nic_t *enp, 692 __in efx_rxq_t *erp, 693 __in boolean_t using_rss); 694 695 LIBEFX_API 696 extern void 697 efx_mac_filter_default_rxq_clear( 698 __in efx_nic_t *enp); 699 700 LIBEFX_API 701 extern __checkReturn efx_rc_t 702 efx_mac_drain( 703 __in efx_nic_t *enp, 704 __in boolean_t enabled); 705 706 LIBEFX_API 707 extern __checkReturn efx_rc_t 708 efx_mac_up( 709 __in efx_nic_t *enp, 710 __out boolean_t *mac_upp); 711 712 #define EFX_FCNTL_RESPOND 0x00000001 713 #define EFX_FCNTL_GENERATE 0x00000002 714 715 LIBEFX_API 716 extern __checkReturn efx_rc_t 717 efx_mac_fcntl_set( 718 __in efx_nic_t *enp, 719 __in unsigned int fcntl, 720 __in boolean_t autoneg); 721 722 LIBEFX_API 723 extern void 724 efx_mac_fcntl_get( 725 __in efx_nic_t *enp, 726 __out unsigned int *fcntl_wantedp, 727 __out unsigned int *fcntl_linkp); 728 729 730 #if EFSYS_OPT_MAC_STATS 731 732 #if EFSYS_OPT_NAMES 733 734 LIBEFX_API 735 extern __checkReturn const char * 736 efx_mac_stat_name( 737 __in efx_nic_t *enp, 738 __in unsigned int id); 739 740 #endif /* EFSYS_OPT_NAMES */ 741 742 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 743 744 #define EFX_MAC_STATS_MASK_NPAGES \ 745 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 746 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 747 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 748 749 /* 750 * Get mask of MAC statistics supported by the hardware. 751 * 752 * If mask_size is insufficient to return the mask, EINVAL error is 753 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 754 * (which is sizeof (uint32_t)) is sufficient. 755 */ 756 LIBEFX_API 757 extern __checkReturn efx_rc_t 758 efx_mac_stats_get_mask( 759 __in efx_nic_t *enp, 760 __out_bcount(mask_size) uint32_t *maskp, 761 __in size_t mask_size); 762 763 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 764 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 765 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 766 767 768 LIBEFX_API 769 extern __checkReturn efx_rc_t 770 efx_mac_stats_clear( 771 __in efx_nic_t *enp); 772 773 /* 774 * Upload mac statistics supported by the hardware into the given buffer. 775 * 776 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 777 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 778 * 779 * The hardware will only DMA statistics that it understands (of course). 780 * Drivers should not make any assumptions about which statistics are 781 * supported, especially when the statistics are generated by firmware. 782 * 783 * Thus, drivers should zero this buffer before use, so that not-understood 784 * statistics read back as zero. 785 */ 786 LIBEFX_API 787 extern __checkReturn efx_rc_t 788 efx_mac_stats_upload( 789 __in efx_nic_t *enp, 790 __in efsys_mem_t *esmp); 791 792 LIBEFX_API 793 extern __checkReturn efx_rc_t 794 efx_mac_stats_periodic( 795 __in efx_nic_t *enp, 796 __in efsys_mem_t *esmp, 797 __in uint16_t period_ms, 798 __in boolean_t events); 799 800 LIBEFX_API 801 extern __checkReturn efx_rc_t 802 efx_mac_stats_update( 803 __in efx_nic_t *enp, 804 __in efsys_mem_t *esmp, 805 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 806 __inout_opt uint32_t *generationp); 807 808 #endif /* EFSYS_OPT_MAC_STATS */ 809 810 /* MON */ 811 812 typedef enum efx_mon_type_e { 813 EFX_MON_INVALID = 0, 814 EFX_MON_SFC90X0, 815 EFX_MON_SFC91X0, 816 EFX_MON_SFC92X0, 817 EFX_MON_NTYPES 818 } efx_mon_type_t; 819 820 #if EFSYS_OPT_NAMES 821 822 LIBEFX_API 823 extern const char * 824 efx_mon_name( 825 __in efx_nic_t *enp); 826 827 #endif /* EFSYS_OPT_NAMES */ 828 829 LIBEFX_API 830 extern __checkReturn efx_rc_t 831 efx_mon_init( 832 __in efx_nic_t *enp); 833 834 #if EFSYS_OPT_MON_STATS 835 836 #define EFX_MON_STATS_PAGE_SIZE 0x100 837 #define EFX_MON_MASK_ELEMENT_SIZE 32 838 839 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 840 typedef enum efx_mon_stat_e { 841 EFX_MON_STAT_CONTROLLER_TEMP, 842 EFX_MON_STAT_PHY_COMMON_TEMP, 843 EFX_MON_STAT_CONTROLLER_COOLING, 844 EFX_MON_STAT_PHY0_TEMP, 845 EFX_MON_STAT_PHY0_COOLING, 846 EFX_MON_STAT_PHY1_TEMP, 847 EFX_MON_STAT_PHY1_COOLING, 848 EFX_MON_STAT_IN_1V0, 849 EFX_MON_STAT_IN_1V2, 850 EFX_MON_STAT_IN_1V8, 851 EFX_MON_STAT_IN_2V5, 852 EFX_MON_STAT_IN_3V3, 853 EFX_MON_STAT_IN_12V0, 854 EFX_MON_STAT_IN_1V2A, 855 EFX_MON_STAT_IN_VREF, 856 EFX_MON_STAT_OUT_VAOE, 857 EFX_MON_STAT_AOE_TEMP, 858 EFX_MON_STAT_PSU_AOE_TEMP, 859 EFX_MON_STAT_PSU_TEMP, 860 EFX_MON_STAT_FAN_0, 861 EFX_MON_STAT_FAN_1, 862 EFX_MON_STAT_FAN_2, 863 EFX_MON_STAT_FAN_3, 864 EFX_MON_STAT_FAN_4, 865 EFX_MON_STAT_IN_VAOE, 866 EFX_MON_STAT_OUT_IAOE, 867 EFX_MON_STAT_IN_IAOE, 868 EFX_MON_STAT_NIC_POWER, 869 EFX_MON_STAT_IN_0V9, 870 EFX_MON_STAT_IN_I0V9, 871 EFX_MON_STAT_IN_I1V2, 872 EFX_MON_STAT_IN_0V9_ADC, 873 EFX_MON_STAT_CONTROLLER_2_TEMP, 874 EFX_MON_STAT_VREG_INTERNAL_TEMP, 875 EFX_MON_STAT_VREG_0V9_TEMP, 876 EFX_MON_STAT_VREG_1V2_TEMP, 877 EFX_MON_STAT_CONTROLLER_VPTAT, 878 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 879 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 880 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 881 EFX_MON_STAT_AMBIENT_TEMP, 882 EFX_MON_STAT_AIRFLOW, 883 EFX_MON_STAT_VDD08D_VSS08D_CSR, 884 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 885 EFX_MON_STAT_HOTPOINT_TEMP, 886 EFX_MON_STAT_PHY_POWER_PORT0, 887 EFX_MON_STAT_PHY_POWER_PORT1, 888 EFX_MON_STAT_MUM_VCC, 889 EFX_MON_STAT_IN_0V9_A, 890 EFX_MON_STAT_IN_I0V9_A, 891 EFX_MON_STAT_VREG_0V9_A_TEMP, 892 EFX_MON_STAT_IN_0V9_B, 893 EFX_MON_STAT_IN_I0V9_B, 894 EFX_MON_STAT_VREG_0V9_B_TEMP, 895 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 896 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 897 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 898 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 899 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 900 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 901 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 902 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 903 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 904 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 905 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 906 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 907 EFX_MON_STAT_SODIMM_VOUT, 908 EFX_MON_STAT_SODIMM_0_TEMP, 909 EFX_MON_STAT_SODIMM_1_TEMP, 910 EFX_MON_STAT_PHY0_VCC, 911 EFX_MON_STAT_PHY1_VCC, 912 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 913 EFX_MON_STAT_BOARD_FRONT_TEMP, 914 EFX_MON_STAT_BOARD_BACK_TEMP, 915 EFX_MON_STAT_IN_I1V8, 916 EFX_MON_STAT_IN_I2V5, 917 EFX_MON_STAT_IN_I3V3, 918 EFX_MON_STAT_IN_I12V0, 919 EFX_MON_STAT_IN_1V3, 920 EFX_MON_STAT_IN_I1V3, 921 EFX_MON_NSTATS 922 } efx_mon_stat_t; 923 924 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 925 926 typedef enum efx_mon_stat_state_e { 927 EFX_MON_STAT_STATE_OK = 0, 928 EFX_MON_STAT_STATE_WARNING = 1, 929 EFX_MON_STAT_STATE_FATAL = 2, 930 EFX_MON_STAT_STATE_BROKEN = 3, 931 EFX_MON_STAT_STATE_NO_READING = 4, 932 } efx_mon_stat_state_t; 933 934 typedef enum efx_mon_stat_unit_e { 935 EFX_MON_STAT_UNIT_UNKNOWN = 0, 936 EFX_MON_STAT_UNIT_BOOL, 937 EFX_MON_STAT_UNIT_TEMP_C, 938 EFX_MON_STAT_UNIT_VOLTAGE_MV, 939 EFX_MON_STAT_UNIT_CURRENT_MA, 940 EFX_MON_STAT_UNIT_POWER_W, 941 EFX_MON_STAT_UNIT_RPM, 942 EFX_MON_NUNITS 943 } efx_mon_stat_unit_t; 944 945 typedef struct efx_mon_stat_value_s { 946 uint16_t emsv_value; 947 efx_mon_stat_state_t emsv_state; 948 efx_mon_stat_unit_t emsv_unit; 949 } efx_mon_stat_value_t; 950 951 typedef struct efx_mon_limit_value_s { 952 uint16_t emlv_warning_min; 953 uint16_t emlv_warning_max; 954 uint16_t emlv_fatal_min; 955 uint16_t emlv_fatal_max; 956 } efx_mon_stat_limits_t; 957 958 typedef enum efx_mon_stat_portmask_e { 959 EFX_MON_STAT_PORTMAP_NONE = 0, 960 EFX_MON_STAT_PORTMAP_PORT0 = 1, 961 EFX_MON_STAT_PORTMAP_PORT1 = 2, 962 EFX_MON_STAT_PORTMAP_PORT2 = 3, 963 EFX_MON_STAT_PORTMAP_PORT3 = 4, 964 EFX_MON_STAT_PORTMAP_ALL = (-1), 965 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 966 } efx_mon_stat_portmask_t; 967 968 #if EFSYS_OPT_NAMES 969 970 LIBEFX_API 971 extern const char * 972 efx_mon_stat_name( 973 __in efx_nic_t *enp, 974 __in efx_mon_stat_t id); 975 976 LIBEFX_API 977 extern const char * 978 efx_mon_stat_description( 979 __in efx_nic_t *enp, 980 __in efx_mon_stat_t id); 981 982 #endif /* EFSYS_OPT_NAMES */ 983 984 LIBEFX_API 985 extern __checkReturn boolean_t 986 efx_mon_mcdi_to_efx_stat( 987 __in int mcdi_index, 988 __out efx_mon_stat_t *statp); 989 990 LIBEFX_API 991 extern __checkReturn boolean_t 992 efx_mon_get_stat_unit( 993 __in efx_mon_stat_t stat, 994 __out efx_mon_stat_unit_t *unitp); 995 996 LIBEFX_API 997 extern __checkReturn boolean_t 998 efx_mon_get_stat_portmap( 999 __in efx_mon_stat_t stat, 1000 __out efx_mon_stat_portmask_t *maskp); 1001 1002 LIBEFX_API 1003 extern __checkReturn efx_rc_t 1004 efx_mon_stats_update( 1005 __in efx_nic_t *enp, 1006 __in efsys_mem_t *esmp, 1007 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 1008 1009 LIBEFX_API 1010 extern __checkReturn efx_rc_t 1011 efx_mon_limits_update( 1012 __in efx_nic_t *enp, 1013 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 1014 1015 #endif /* EFSYS_OPT_MON_STATS */ 1016 1017 LIBEFX_API 1018 extern void 1019 efx_mon_fini( 1020 __in efx_nic_t *enp); 1021 1022 /* PHY */ 1023 1024 LIBEFX_API 1025 extern __checkReturn efx_rc_t 1026 efx_phy_verify( 1027 __in efx_nic_t *enp); 1028 1029 typedef enum efx_phy_led_mode_e { 1030 EFX_PHY_LED_DEFAULT = 0, 1031 EFX_PHY_LED_OFF, 1032 EFX_PHY_LED_ON, 1033 EFX_PHY_LED_FLASH, 1034 EFX_PHY_LED_NMODES 1035 } efx_phy_led_mode_t; 1036 1037 #if EFSYS_OPT_PHY_LED_CONTROL 1038 1039 LIBEFX_API 1040 extern __checkReturn efx_rc_t 1041 efx_phy_led_set( 1042 __in efx_nic_t *enp, 1043 __in efx_phy_led_mode_t mode); 1044 1045 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1046 1047 LIBEFX_API 1048 extern __checkReturn efx_rc_t 1049 efx_port_init( 1050 __in efx_nic_t *enp); 1051 1052 #if EFSYS_OPT_LOOPBACK 1053 1054 typedef enum efx_loopback_type_e { 1055 EFX_LOOPBACK_OFF = 0, 1056 EFX_LOOPBACK_DATA = 1, 1057 EFX_LOOPBACK_GMAC = 2, 1058 EFX_LOOPBACK_XGMII = 3, 1059 EFX_LOOPBACK_XGXS = 4, 1060 EFX_LOOPBACK_XAUI = 5, 1061 EFX_LOOPBACK_GMII = 6, 1062 EFX_LOOPBACK_SGMII = 7, 1063 EFX_LOOPBACK_XGBR = 8, 1064 EFX_LOOPBACK_XFI = 9, 1065 EFX_LOOPBACK_XAUI_FAR = 10, 1066 EFX_LOOPBACK_GMII_FAR = 11, 1067 EFX_LOOPBACK_SGMII_FAR = 12, 1068 EFX_LOOPBACK_XFI_FAR = 13, 1069 EFX_LOOPBACK_GPHY = 14, 1070 EFX_LOOPBACK_PHY_XS = 15, 1071 EFX_LOOPBACK_PCS = 16, 1072 EFX_LOOPBACK_PMA_PMD = 17, 1073 EFX_LOOPBACK_XPORT = 18, 1074 EFX_LOOPBACK_XGMII_WS = 19, 1075 EFX_LOOPBACK_XAUI_WS = 20, 1076 EFX_LOOPBACK_XAUI_WS_FAR = 21, 1077 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 1078 EFX_LOOPBACK_GMII_WS = 23, 1079 EFX_LOOPBACK_XFI_WS = 24, 1080 EFX_LOOPBACK_XFI_WS_FAR = 25, 1081 EFX_LOOPBACK_PHYXS_WS = 26, 1082 EFX_LOOPBACK_PMA_INT = 27, 1083 EFX_LOOPBACK_SD_NEAR = 28, 1084 EFX_LOOPBACK_SD_FAR = 29, 1085 EFX_LOOPBACK_PMA_INT_WS = 30, 1086 EFX_LOOPBACK_SD_FEP2_WS = 31, 1087 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 1088 EFX_LOOPBACK_SD_FEP_WS = 33, 1089 EFX_LOOPBACK_SD_FES_WS = 34, 1090 EFX_LOOPBACK_AOE_INT_NEAR = 35, 1091 EFX_LOOPBACK_DATA_WS = 36, 1092 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 1093 EFX_LOOPBACK_NTYPES 1094 } efx_loopback_type_t; 1095 1096 typedef enum efx_loopback_kind_e { 1097 EFX_LOOPBACK_KIND_OFF = 0, 1098 EFX_LOOPBACK_KIND_ALL, 1099 EFX_LOOPBACK_KIND_MAC, 1100 EFX_LOOPBACK_KIND_PHY, 1101 EFX_LOOPBACK_NKINDS 1102 } efx_loopback_kind_t; 1103 1104 LIBEFX_API 1105 extern void 1106 efx_loopback_mask( 1107 __in efx_loopback_kind_t loopback_kind, 1108 __out efx_qword_t *maskp); 1109 1110 LIBEFX_API 1111 extern __checkReturn efx_rc_t 1112 efx_port_loopback_set( 1113 __in efx_nic_t *enp, 1114 __in efx_link_mode_t link_mode, 1115 __in efx_loopback_type_t type); 1116 1117 #if EFSYS_OPT_NAMES 1118 1119 LIBEFX_API 1120 extern __checkReturn const char * 1121 efx_loopback_type_name( 1122 __in efx_nic_t *enp, 1123 __in efx_loopback_type_t type); 1124 1125 #endif /* EFSYS_OPT_NAMES */ 1126 1127 #endif /* EFSYS_OPT_LOOPBACK */ 1128 1129 LIBEFX_API 1130 extern __checkReturn efx_rc_t 1131 efx_port_poll( 1132 __in efx_nic_t *enp, 1133 __out_opt efx_link_mode_t *link_modep); 1134 1135 LIBEFX_API 1136 extern void 1137 efx_port_fini( 1138 __in efx_nic_t *enp); 1139 1140 typedef enum efx_phy_cap_type_e { 1141 EFX_PHY_CAP_INVALID = 0, 1142 EFX_PHY_CAP_10HDX, 1143 EFX_PHY_CAP_10FDX, 1144 EFX_PHY_CAP_100HDX, 1145 EFX_PHY_CAP_100FDX, 1146 EFX_PHY_CAP_1000HDX, 1147 EFX_PHY_CAP_1000FDX, 1148 EFX_PHY_CAP_10000FDX, 1149 EFX_PHY_CAP_PAUSE, 1150 EFX_PHY_CAP_ASYM, 1151 EFX_PHY_CAP_AN, 1152 EFX_PHY_CAP_40000FDX, 1153 EFX_PHY_CAP_DDM, 1154 EFX_PHY_CAP_100000FDX, 1155 EFX_PHY_CAP_25000FDX, 1156 EFX_PHY_CAP_50000FDX, 1157 EFX_PHY_CAP_BASER_FEC, 1158 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1159 EFX_PHY_CAP_RS_FEC, 1160 EFX_PHY_CAP_RS_FEC_REQUESTED, 1161 EFX_PHY_CAP_25G_BASER_FEC, 1162 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1163 EFX_PHY_CAP_NTYPES 1164 } efx_phy_cap_type_t; 1165 1166 1167 #define EFX_PHY_CAP_CURRENT 0x00000000 1168 #define EFX_PHY_CAP_DEFAULT 0x00000001 1169 #define EFX_PHY_CAP_PERM 0x00000002 1170 1171 LIBEFX_API 1172 extern void 1173 efx_phy_adv_cap_get( 1174 __in efx_nic_t *enp, 1175 __in uint32_t flag, 1176 __out uint32_t *maskp); 1177 1178 LIBEFX_API 1179 extern __checkReturn efx_rc_t 1180 efx_phy_adv_cap_set( 1181 __in efx_nic_t *enp, 1182 __in uint32_t mask); 1183 1184 LIBEFX_API 1185 extern void 1186 efx_phy_lp_cap_get( 1187 __in efx_nic_t *enp, 1188 __out uint32_t *maskp); 1189 1190 LIBEFX_API 1191 extern __checkReturn efx_rc_t 1192 efx_phy_oui_get( 1193 __in efx_nic_t *enp, 1194 __out uint32_t *ouip); 1195 1196 typedef enum efx_phy_media_type_e { 1197 EFX_PHY_MEDIA_INVALID = 0, 1198 EFX_PHY_MEDIA_XAUI, 1199 EFX_PHY_MEDIA_CX4, 1200 EFX_PHY_MEDIA_KX4, 1201 EFX_PHY_MEDIA_XFP, 1202 EFX_PHY_MEDIA_SFP_PLUS, 1203 EFX_PHY_MEDIA_BASE_T, 1204 EFX_PHY_MEDIA_QSFP_PLUS, 1205 EFX_PHY_MEDIA_NTYPES 1206 } efx_phy_media_type_t; 1207 1208 /* 1209 * Get the type of medium currently used. If the board has ports for 1210 * modules, a module is present, and we recognise the media type of 1211 * the module, then this will be the media type of the module. 1212 * Otherwise it will be the media type of the port. 1213 */ 1214 LIBEFX_API 1215 extern void 1216 efx_phy_media_type_get( 1217 __in efx_nic_t *enp, 1218 __out efx_phy_media_type_t *typep); 1219 1220 /* 1221 * 2-wire device address of the base information in accordance with SFF-8472 1222 * Diagnostic Monitoring Interface for Optical Transceivers section 1223 * 4 Memory Organization. 1224 */ 1225 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1226 1227 /* 1228 * 2-wire device address of the digital diagnostics monitoring interface 1229 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1230 * Transceivers section 4 Memory Organization. 1231 */ 1232 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1233 1234 /* 1235 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1236 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1237 * Operation. 1238 */ 1239 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1240 1241 /* 1242 * Maximum accessible data offset for PHY module information. 1243 */ 1244 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1245 1246 1247 LIBEFX_API 1248 extern __checkReturn efx_rc_t 1249 efx_phy_module_get_info( 1250 __in efx_nic_t *enp, 1251 __in uint8_t dev_addr, 1252 __in size_t offset, 1253 __in size_t len, 1254 __out_bcount(len) uint8_t *data); 1255 1256 #if EFSYS_OPT_PHY_STATS 1257 1258 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1259 typedef enum efx_phy_stat_e { 1260 EFX_PHY_STAT_OUI, 1261 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1262 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1263 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1264 EFX_PHY_STAT_PMA_PMD_REV_A, 1265 EFX_PHY_STAT_PMA_PMD_REV_B, 1266 EFX_PHY_STAT_PMA_PMD_REV_C, 1267 EFX_PHY_STAT_PMA_PMD_REV_D, 1268 EFX_PHY_STAT_PCS_LINK_UP, 1269 EFX_PHY_STAT_PCS_RX_FAULT, 1270 EFX_PHY_STAT_PCS_TX_FAULT, 1271 EFX_PHY_STAT_PCS_BER, 1272 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1273 EFX_PHY_STAT_PHY_XS_LINK_UP, 1274 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1275 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1276 EFX_PHY_STAT_PHY_XS_ALIGN, 1277 EFX_PHY_STAT_PHY_XS_SYNC_A, 1278 EFX_PHY_STAT_PHY_XS_SYNC_B, 1279 EFX_PHY_STAT_PHY_XS_SYNC_C, 1280 EFX_PHY_STAT_PHY_XS_SYNC_D, 1281 EFX_PHY_STAT_AN_LINK_UP, 1282 EFX_PHY_STAT_AN_MASTER, 1283 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1284 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1285 EFX_PHY_STAT_CL22EXT_LINK_UP, 1286 EFX_PHY_STAT_SNR_A, 1287 EFX_PHY_STAT_SNR_B, 1288 EFX_PHY_STAT_SNR_C, 1289 EFX_PHY_STAT_SNR_D, 1290 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1291 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1292 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1293 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1294 EFX_PHY_STAT_AN_COMPLETE, 1295 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1296 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1297 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1298 EFX_PHY_STAT_PCS_FW_VERSION_0, 1299 EFX_PHY_STAT_PCS_FW_VERSION_1, 1300 EFX_PHY_STAT_PCS_FW_VERSION_2, 1301 EFX_PHY_STAT_PCS_FW_VERSION_3, 1302 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1303 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1304 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1305 EFX_PHY_STAT_PCS_OP_MODE, 1306 EFX_PHY_NSTATS 1307 } efx_phy_stat_t; 1308 1309 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1310 1311 #if EFSYS_OPT_NAMES 1312 1313 LIBEFX_API 1314 extern const char * 1315 efx_phy_stat_name( 1316 __in efx_nic_t *enp, 1317 __in efx_phy_stat_t stat); 1318 1319 #endif /* EFSYS_OPT_NAMES */ 1320 1321 #define EFX_PHY_STATS_SIZE 0x100 1322 1323 LIBEFX_API 1324 extern __checkReturn efx_rc_t 1325 efx_phy_stats_update( 1326 __in efx_nic_t *enp, 1327 __in efsys_mem_t *esmp, 1328 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1329 1330 #endif /* EFSYS_OPT_PHY_STATS */ 1331 1332 1333 #if EFSYS_OPT_BIST 1334 1335 typedef enum efx_bist_type_e { 1336 EFX_BIST_TYPE_UNKNOWN, 1337 EFX_BIST_TYPE_PHY_NORMAL, 1338 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1339 EFX_BIST_TYPE_PHY_CABLE_LONG, 1340 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1341 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1342 EFX_BIST_TYPE_REG, /* Test the register memories */ 1343 EFX_BIST_TYPE_NTYPES, 1344 } efx_bist_type_t; 1345 1346 typedef enum efx_bist_result_e { 1347 EFX_BIST_RESULT_UNKNOWN, 1348 EFX_BIST_RESULT_RUNNING, 1349 EFX_BIST_RESULT_PASSED, 1350 EFX_BIST_RESULT_FAILED, 1351 } efx_bist_result_t; 1352 1353 typedef enum efx_phy_cable_status_e { 1354 EFX_PHY_CABLE_STATUS_OK, 1355 EFX_PHY_CABLE_STATUS_INVALID, 1356 EFX_PHY_CABLE_STATUS_OPEN, 1357 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1358 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1359 EFX_PHY_CABLE_STATUS_BUSY, 1360 } efx_phy_cable_status_t; 1361 1362 typedef enum efx_bist_value_e { 1363 EFX_BIST_PHY_CABLE_LENGTH_A, 1364 EFX_BIST_PHY_CABLE_LENGTH_B, 1365 EFX_BIST_PHY_CABLE_LENGTH_C, 1366 EFX_BIST_PHY_CABLE_LENGTH_D, 1367 EFX_BIST_PHY_CABLE_STATUS_A, 1368 EFX_BIST_PHY_CABLE_STATUS_B, 1369 EFX_BIST_PHY_CABLE_STATUS_C, 1370 EFX_BIST_PHY_CABLE_STATUS_D, 1371 EFX_BIST_FAULT_CODE, 1372 /* 1373 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1374 * response. 1375 */ 1376 EFX_BIST_MEM_TEST, 1377 EFX_BIST_MEM_ADDR, 1378 EFX_BIST_MEM_BUS, 1379 EFX_BIST_MEM_EXPECT, 1380 EFX_BIST_MEM_ACTUAL, 1381 EFX_BIST_MEM_ECC, 1382 EFX_BIST_MEM_ECC_PARITY, 1383 EFX_BIST_MEM_ECC_FATAL, 1384 EFX_BIST_NVALUES, 1385 } efx_bist_value_t; 1386 1387 LIBEFX_API 1388 extern __checkReturn efx_rc_t 1389 efx_bist_enable_offline( 1390 __in efx_nic_t *enp); 1391 1392 LIBEFX_API 1393 extern __checkReturn efx_rc_t 1394 efx_bist_start( 1395 __in efx_nic_t *enp, 1396 __in efx_bist_type_t type); 1397 1398 LIBEFX_API 1399 extern __checkReturn efx_rc_t 1400 efx_bist_poll( 1401 __in efx_nic_t *enp, 1402 __in efx_bist_type_t type, 1403 __out efx_bist_result_t *resultp, 1404 __out_opt uint32_t *value_maskp, 1405 __out_ecount_opt(count) unsigned long *valuesp, 1406 __in size_t count); 1407 1408 LIBEFX_API 1409 extern void 1410 efx_bist_stop( 1411 __in efx_nic_t *enp, 1412 __in efx_bist_type_t type); 1413 1414 #endif /* EFSYS_OPT_BIST */ 1415 1416 #define EFX_FEATURE_IPV6 0x00000001 1417 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1418 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1419 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1420 #define EFX_FEATURE_MCDI 0x00000020 1421 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1422 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1423 #define EFX_FEATURE_TURBO 0x00000100 1424 #define EFX_FEATURE_MCDI_DMA 0x00000200 1425 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1426 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1427 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1428 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1429 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1430 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1431 1432 typedef enum efx_tunnel_protocol_e { 1433 EFX_TUNNEL_PROTOCOL_NONE = 0, 1434 EFX_TUNNEL_PROTOCOL_VXLAN, 1435 EFX_TUNNEL_PROTOCOL_GENEVE, 1436 EFX_TUNNEL_PROTOCOL_NVGRE, 1437 EFX_TUNNEL_NPROTOS 1438 } efx_tunnel_protocol_t; 1439 1440 typedef enum efx_vi_window_shift_e { 1441 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1442 EFX_VI_WINDOW_SHIFT_8K = 13, 1443 EFX_VI_WINDOW_SHIFT_16K = 14, 1444 EFX_VI_WINDOW_SHIFT_64K = 16, 1445 } efx_vi_window_shift_t; 1446 1447 typedef struct efx_nic_cfg_s { 1448 uint32_t enc_board_type; 1449 uint32_t enc_phy_type; 1450 #if EFSYS_OPT_NAMES 1451 char enc_phy_name[21]; 1452 #endif 1453 char enc_phy_revision[21]; 1454 efx_mon_type_t enc_mon_type; 1455 #if EFSYS_OPT_MON_STATS 1456 uint32_t enc_mon_stat_dma_buf_size; 1457 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1458 #endif 1459 unsigned int enc_features; 1460 efx_vi_window_shift_t enc_vi_window_shift; 1461 uint8_t enc_mac_addr[6]; 1462 uint8_t enc_port; /* PHY port number */ 1463 uint32_t enc_intr_vec_base; 1464 uint32_t enc_intr_limit; 1465 uint32_t enc_evq_limit; 1466 uint32_t enc_txq_limit; 1467 uint32_t enc_rxq_limit; 1468 uint32_t enc_evq_max_nevs; 1469 uint32_t enc_evq_min_nevs; 1470 uint32_t enc_rxq_max_ndescs; 1471 uint32_t enc_rxq_min_ndescs; 1472 uint32_t enc_txq_max_ndescs; 1473 uint32_t enc_txq_min_ndescs; 1474 uint32_t enc_buftbl_limit; 1475 uint32_t enc_piobuf_limit; 1476 uint32_t enc_piobuf_size; 1477 uint32_t enc_piobuf_min_alloc_size; 1478 uint32_t enc_evq_timer_quantum_ns; 1479 uint32_t enc_evq_timer_max_us; 1480 uint32_t enc_clk_mult; 1481 uint32_t enc_ev_ew_desc_size; 1482 uint32_t enc_ev_desc_size; 1483 uint32_t enc_rx_desc_size; 1484 uint32_t enc_tx_desc_size; 1485 /* Maximum Rx prefix size if many Rx prefixes are supported */ 1486 uint32_t enc_rx_prefix_size; 1487 uint32_t enc_rx_buf_align_start; 1488 uint32_t enc_rx_buf_align_end; 1489 #if EFSYS_OPT_RX_SCALE 1490 uint32_t enc_rx_scale_max_exclusive_contexts; 1491 /* 1492 * Mask of supported hash algorithms. 1493 * Hash algorithm types are used as the bit indices. 1494 */ 1495 uint32_t enc_rx_scale_hash_alg_mask; 1496 /* 1497 * Indicates whether port numbers can be included to the 1498 * input data for hash computation. 1499 */ 1500 boolean_t enc_rx_scale_l4_hash_supported; 1501 boolean_t enc_rx_scale_additional_modes_supported; 1502 #endif /* EFSYS_OPT_RX_SCALE */ 1503 #if EFSYS_OPT_LOOPBACK 1504 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1505 #endif /* EFSYS_OPT_LOOPBACK */ 1506 #if EFSYS_OPT_PHY_FLAGS 1507 uint32_t enc_phy_flags_mask; 1508 #endif /* EFSYS_OPT_PHY_FLAGS */ 1509 #if EFSYS_OPT_PHY_LED_CONTROL 1510 uint32_t enc_led_mask; 1511 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1512 #if EFSYS_OPT_PHY_STATS 1513 uint64_t enc_phy_stat_mask; 1514 #endif /* EFSYS_OPT_PHY_STATS */ 1515 #if EFSYS_OPT_MCDI 1516 uint8_t enc_mcdi_mdio_channel; 1517 #if EFSYS_OPT_PHY_STATS 1518 uint32_t enc_mcdi_phy_stat_mask; 1519 #endif /* EFSYS_OPT_PHY_STATS */ 1520 #if EFSYS_OPT_MON_STATS 1521 uint32_t *enc_mcdi_sensor_maskp; 1522 uint32_t enc_mcdi_sensor_mask_size; 1523 #endif /* EFSYS_OPT_MON_STATS */ 1524 #endif /* EFSYS_OPT_MCDI */ 1525 #if EFSYS_OPT_BIST 1526 uint32_t enc_bist_mask; 1527 #endif /* EFSYS_OPT_BIST */ 1528 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1529 efx_pcie_interface_t enc_intf; 1530 uint32_t enc_pf; 1531 uint32_t enc_vf; 1532 uint32_t enc_privilege_mask; 1533 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1534 boolean_t enc_evq_init_done_ev_supported; 1535 boolean_t enc_bug26807_workaround; 1536 boolean_t enc_bug35388_workaround; 1537 boolean_t enc_bug41750_workaround; 1538 boolean_t enc_bug61265_workaround; 1539 boolean_t enc_bug61297_workaround; 1540 boolean_t enc_rx_batching_enabled; 1541 /* Maximum number of descriptors completed in an rx event. */ 1542 uint32_t enc_rx_batch_max; 1543 /* Number of rx descriptors the hardware requires for a push. */ 1544 uint32_t enc_rx_push_align; 1545 /* Maximum amount of data in DMA descriptor */ 1546 uint32_t enc_tx_dma_desc_size_max; 1547 /* 1548 * Boundary which DMA descriptor data must not cross or 0 if no 1549 * limitation. 1550 */ 1551 uint32_t enc_tx_dma_desc_boundary; 1552 /* 1553 * Maximum number of bytes into the packet the TCP header can start for 1554 * the hardware to apply TSO packet edits. 1555 */ 1556 uint32_t enc_tx_tso_tcp_header_offset_limit; 1557 /* Maximum number of header DMA descriptors per TSO transaction. */ 1558 uint32_t enc_tx_tso_max_header_ndescs; 1559 /* Maximum header length acceptable by TSO transaction. */ 1560 uint32_t enc_tx_tso_max_header_length; 1561 /* Maximum number of payload DMA descriptors per TSO transaction. */ 1562 uint32_t enc_tx_tso_max_payload_ndescs; 1563 /* Maximum payload length per TSO transaction. */ 1564 uint32_t enc_tx_tso_max_payload_length; 1565 /* Maximum number of frames to be generated per TSO transaction. */ 1566 uint32_t enc_tx_tso_max_nframes; 1567 boolean_t enc_fw_assisted_tso_enabled; 1568 boolean_t enc_fw_assisted_tso_v2_enabled; 1569 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1570 boolean_t enc_tso_v3_enabled; 1571 /* Number of TSO contexts on the NIC (FATSOv2) */ 1572 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1573 boolean_t enc_hw_tx_insert_vlan_enabled; 1574 /* Number of PFs on the NIC */ 1575 uint32_t enc_hw_pf_count; 1576 /* Datapath firmware vadapter/vport/vswitch support */ 1577 boolean_t enc_datapath_cap_evb; 1578 /* Datapath firmware vport reconfigure support */ 1579 boolean_t enc_vport_reconfigure_supported; 1580 boolean_t enc_rx_disable_scatter_supported; 1581 /* Maximum number of Rx scatter segments supported by HW */ 1582 uint32_t enc_rx_scatter_max; 1583 boolean_t enc_allow_set_mac_with_installed_filters; 1584 boolean_t enc_enhanced_set_mac_supported; 1585 boolean_t enc_init_evq_v2_supported; 1586 boolean_t enc_init_evq_extended_width_supported; 1587 boolean_t enc_no_cont_ev_mode_supported; 1588 boolean_t enc_init_rxq_with_buffer_size; 1589 boolean_t enc_rx_packed_stream_supported; 1590 boolean_t enc_rx_var_packed_stream_supported; 1591 boolean_t enc_rx_es_super_buffer_supported; 1592 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1593 boolean_t enc_pm_and_rxdp_counters; 1594 boolean_t enc_mac_stats_40g_tx_size_bins; 1595 uint32_t enc_tunnel_encapsulations_supported; 1596 /* 1597 * NIC global maximum for unique UDP tunnel ports shared by all 1598 * functions. 1599 */ 1600 uint32_t enc_tunnel_config_udp_entries_max; 1601 /* External port identifier */ 1602 uint8_t enc_external_port; 1603 uint32_t enc_mcdi_max_payload_length; 1604 /* VPD may be per-PF or global */ 1605 boolean_t enc_vpd_is_global; 1606 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1607 uint32_t enc_required_pcie_bandwidth_mbps; 1608 uint32_t enc_max_pcie_link_gen; 1609 /* Firmware verifies integrity of NVRAM updates */ 1610 boolean_t enc_nvram_update_verify_result_supported; 1611 /* Firmware supports polled NVRAM updates on select partitions */ 1612 boolean_t enc_nvram_update_poll_verify_result_supported; 1613 /* Firmware accepts updates via the BUNDLE partition */ 1614 boolean_t enc_nvram_bundle_update_supported; 1615 /* Firmware support for extended MAC_STATS buffer */ 1616 uint32_t enc_mac_stats_nstats; 1617 boolean_t enc_fec_counters; 1618 boolean_t enc_hlb_counters; 1619 /* NIC support for Match-Action Engine (MAE). */ 1620 boolean_t enc_mae_supported; 1621 /* 1622 * NIC is privileged, i.e. it is the MAE admin. 1623 * Only privileged MAE clients can manage MAE flow rules, 1624 * for example, modify, count and route traffic to selected 1625 * destination (a MAE client or network port). 1626 */ 1627 boolean_t enc_mae_admin; 1628 /* NIC support for MAE action set v2 features. */ 1629 boolean_t enc_mae_aset_v2_supported; 1630 /* Firmware support for "FLAG" and "MARK" filter actions */ 1631 boolean_t enc_filter_action_flag_supported; 1632 boolean_t enc_filter_action_mark_supported; 1633 uint32_t enc_filter_action_mark_max; 1634 /* Port assigned to this PCI function */ 1635 uint32_t enc_assigned_port; 1636 } efx_nic_cfg_t; 1637 1638 #define EFX_PCI_VF_INVALID 0xffff 1639 1640 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ 1641 ((configp)->evc_function == EFX_PCI_VF_INVALID) 1642 1643 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID) 1644 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID) 1645 1646 #define EFX_PCI_FUNCTION(_encp) \ 1647 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1648 1649 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1650 1651 LIBEFX_API 1652 extern const efx_nic_cfg_t * 1653 efx_nic_cfg_get( 1654 __in const efx_nic_t *enp); 1655 1656 /* RxDPCPU firmware id values by which FW variant can be identified */ 1657 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1658 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1659 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1660 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1661 #define EFX_RXDP_DPDK_FW_ID 0x6 1662 1663 typedef struct efx_nic_fw_info_s { 1664 /* Basic FW version information */ 1665 uint16_t enfi_mc_fw_version[4]; 1666 /* 1667 * If datapath capabilities can be detected, 1668 * additional FW information is to be shown 1669 */ 1670 boolean_t enfi_dpcpu_fw_ids_valid; 1671 /* Rx and Tx datapath CPU FW IDs */ 1672 uint16_t enfi_rx_dpcpu_fw_id; 1673 uint16_t enfi_tx_dpcpu_fw_id; 1674 } efx_nic_fw_info_t; 1675 1676 LIBEFX_API 1677 extern __checkReturn efx_rc_t 1678 efx_nic_get_fw_version( 1679 __in efx_nic_t *enp, 1680 __out efx_nic_fw_info_t *enfip); 1681 1682 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64) 1683 #define EFX_NIC_BOARD_INFO_NAME_LEN (16) 1684 1685 typedef struct efx_nic_board_info_s { 1686 /* The following two fields are NUL-terminated ASCII strings. */ 1687 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN]; 1688 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN]; 1689 uint32_t enbi_revision; 1690 } efx_nic_board_info_t; 1691 1692 LIBEFX_API 1693 extern __checkReturn efx_rc_t 1694 efx_nic_get_board_info( 1695 __in efx_nic_t *enp, 1696 __out efx_nic_board_info_t *board_infop); 1697 1698 /* Driver resource limits (minimum required/maximum usable). */ 1699 typedef struct efx_drv_limits_s { 1700 uint32_t edl_min_evq_count; 1701 uint32_t edl_max_evq_count; 1702 1703 uint32_t edl_min_rxq_count; 1704 uint32_t edl_max_rxq_count; 1705 1706 uint32_t edl_min_txq_count; 1707 uint32_t edl_max_txq_count; 1708 1709 /* PIO blocks (sub-allocated from piobuf) */ 1710 uint32_t edl_min_pio_alloc_size; 1711 uint32_t edl_max_pio_alloc_count; 1712 } efx_drv_limits_t; 1713 1714 LIBEFX_API 1715 extern __checkReturn efx_rc_t 1716 efx_nic_set_drv_limits( 1717 __inout efx_nic_t *enp, 1718 __in efx_drv_limits_t *edlp); 1719 1720 /* 1721 * Register the OS driver version string for management agents 1722 * (e.g. via NC-SI). The content length is provided (i.e. no 1723 * NUL terminator). Use length 0 to indicate no version string 1724 * should be advertised. It is valid to set the version string 1725 * only before efx_nic_probe() is called. 1726 */ 1727 LIBEFX_API 1728 extern __checkReturn efx_rc_t 1729 efx_nic_set_drv_version( 1730 __inout efx_nic_t *enp, 1731 __in_ecount(length) char const *verp, 1732 __in size_t length); 1733 1734 typedef enum efx_nic_region_e { 1735 EFX_REGION_VI, /* Memory BAR UC mapping */ 1736 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1737 } efx_nic_region_t; 1738 1739 LIBEFX_API 1740 extern __checkReturn efx_rc_t 1741 efx_nic_get_bar_region( 1742 __in efx_nic_t *enp, 1743 __in efx_nic_region_t region, 1744 __out uint32_t *offsetp, 1745 __out size_t *sizep); 1746 1747 LIBEFX_API 1748 extern __checkReturn efx_rc_t 1749 efx_nic_get_vi_pool( 1750 __in efx_nic_t *enp, 1751 __out uint32_t *evq_countp, 1752 __out uint32_t *rxq_countp, 1753 __out uint32_t *txq_countp); 1754 1755 1756 #if EFSYS_OPT_VPD 1757 1758 typedef enum efx_vpd_tag_e { 1759 EFX_VPD_ID = 0x02, 1760 EFX_VPD_END = 0x0f, 1761 EFX_VPD_RO = 0x10, 1762 EFX_VPD_RW = 0x11, 1763 } efx_vpd_tag_t; 1764 1765 typedef uint16_t efx_vpd_keyword_t; 1766 1767 typedef struct efx_vpd_value_s { 1768 efx_vpd_tag_t evv_tag; 1769 efx_vpd_keyword_t evv_keyword; 1770 uint8_t evv_length; 1771 uint8_t evv_value[0x100]; 1772 } efx_vpd_value_t; 1773 1774 1775 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1776 1777 LIBEFX_API 1778 extern __checkReturn efx_rc_t 1779 efx_vpd_init( 1780 __in efx_nic_t *enp); 1781 1782 LIBEFX_API 1783 extern __checkReturn efx_rc_t 1784 efx_vpd_size( 1785 __in efx_nic_t *enp, 1786 __out size_t *sizep); 1787 1788 LIBEFX_API 1789 extern __checkReturn efx_rc_t 1790 efx_vpd_read( 1791 __in efx_nic_t *enp, 1792 __out_bcount(size) caddr_t data, 1793 __in size_t size); 1794 1795 LIBEFX_API 1796 extern __checkReturn efx_rc_t 1797 efx_vpd_verify( 1798 __in efx_nic_t *enp, 1799 __in_bcount(size) caddr_t data, 1800 __in size_t size); 1801 1802 LIBEFX_API 1803 extern __checkReturn efx_rc_t 1804 efx_vpd_reinit( 1805 __in efx_nic_t *enp, 1806 __in_bcount(size) caddr_t data, 1807 __in size_t size); 1808 1809 LIBEFX_API 1810 extern __checkReturn efx_rc_t 1811 efx_vpd_get( 1812 __in efx_nic_t *enp, 1813 __in_bcount(size) caddr_t data, 1814 __in size_t size, 1815 __inout efx_vpd_value_t *evvp); 1816 1817 LIBEFX_API 1818 extern __checkReturn efx_rc_t 1819 efx_vpd_set( 1820 __in efx_nic_t *enp, 1821 __inout_bcount(size) caddr_t data, 1822 __in size_t size, 1823 __in efx_vpd_value_t *evvp); 1824 1825 LIBEFX_API 1826 extern __checkReturn efx_rc_t 1827 efx_vpd_next( 1828 __in efx_nic_t *enp, 1829 __inout_bcount(size) caddr_t data, 1830 __in size_t size, 1831 __out efx_vpd_value_t *evvp, 1832 __inout unsigned int *contp); 1833 1834 LIBEFX_API 1835 extern __checkReturn efx_rc_t 1836 efx_vpd_write( 1837 __in efx_nic_t *enp, 1838 __in_bcount(size) caddr_t data, 1839 __in size_t size); 1840 1841 LIBEFX_API 1842 extern void 1843 efx_vpd_fini( 1844 __in efx_nic_t *enp); 1845 1846 #endif /* EFSYS_OPT_VPD */ 1847 1848 /* NVRAM */ 1849 1850 #if EFSYS_OPT_NVRAM 1851 1852 typedef enum efx_nvram_type_e { 1853 EFX_NVRAM_INVALID = 0, 1854 EFX_NVRAM_BOOTROM, 1855 EFX_NVRAM_BOOTROM_CFG, 1856 EFX_NVRAM_MC_FIRMWARE, 1857 EFX_NVRAM_MC_GOLDEN, 1858 EFX_NVRAM_PHY, 1859 EFX_NVRAM_NULLPHY, 1860 EFX_NVRAM_FPGA, 1861 EFX_NVRAM_FCFW, 1862 EFX_NVRAM_CPLD, 1863 EFX_NVRAM_FPGA_BACKUP, 1864 EFX_NVRAM_DYNAMIC_CFG, 1865 EFX_NVRAM_LICENSE, 1866 EFX_NVRAM_UEFIROM, 1867 EFX_NVRAM_MUM_FIRMWARE, 1868 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1869 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1870 EFX_NVRAM_BUNDLE, 1871 EFX_NVRAM_BUNDLE_METADATA, 1872 EFX_NVRAM_NTYPES, 1873 } efx_nvram_type_t; 1874 1875 typedef struct efx_nvram_info_s { 1876 uint32_t eni_flags; 1877 uint32_t eni_partn_size; 1878 uint32_t eni_address; 1879 uint32_t eni_erase_size; 1880 uint32_t eni_write_size; 1881 } efx_nvram_info_t; 1882 1883 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) 1884 1885 LIBEFX_API 1886 extern __checkReturn efx_rc_t 1887 efx_nvram_init( 1888 __in efx_nic_t *enp); 1889 1890 #if EFSYS_OPT_DIAG 1891 1892 LIBEFX_API 1893 extern __checkReturn efx_rc_t 1894 efx_nvram_test( 1895 __in efx_nic_t *enp); 1896 1897 #endif /* EFSYS_OPT_DIAG */ 1898 1899 LIBEFX_API 1900 extern __checkReturn efx_rc_t 1901 efx_nvram_size( 1902 __in efx_nic_t *enp, 1903 __in efx_nvram_type_t type, 1904 __out size_t *sizep); 1905 1906 LIBEFX_API 1907 extern __checkReturn efx_rc_t 1908 efx_nvram_info( 1909 __in efx_nic_t *enp, 1910 __in efx_nvram_type_t type, 1911 __out efx_nvram_info_t *enip); 1912 1913 LIBEFX_API 1914 extern __checkReturn efx_rc_t 1915 efx_nvram_rw_start( 1916 __in efx_nic_t *enp, 1917 __in efx_nvram_type_t type, 1918 __out_opt size_t *pref_chunkp); 1919 1920 LIBEFX_API 1921 extern __checkReturn efx_rc_t 1922 efx_nvram_rw_finish( 1923 __in efx_nic_t *enp, 1924 __in efx_nvram_type_t type, 1925 __out_opt uint32_t *verify_resultp); 1926 1927 LIBEFX_API 1928 extern __checkReturn efx_rc_t 1929 efx_nvram_get_version( 1930 __in efx_nic_t *enp, 1931 __in efx_nvram_type_t type, 1932 __out uint32_t *subtypep, 1933 __out_ecount(4) uint16_t version[4]); 1934 1935 LIBEFX_API 1936 extern __checkReturn efx_rc_t 1937 efx_nvram_read_chunk( 1938 __in efx_nic_t *enp, 1939 __in efx_nvram_type_t type, 1940 __in unsigned int offset, 1941 __out_bcount(size) caddr_t data, 1942 __in size_t size); 1943 1944 LIBEFX_API 1945 extern __checkReturn efx_rc_t 1946 efx_nvram_read_backup( 1947 __in efx_nic_t *enp, 1948 __in efx_nvram_type_t type, 1949 __in unsigned int offset, 1950 __out_bcount(size) caddr_t data, 1951 __in size_t size); 1952 1953 LIBEFX_API 1954 extern __checkReturn efx_rc_t 1955 efx_nvram_set_version( 1956 __in efx_nic_t *enp, 1957 __in efx_nvram_type_t type, 1958 __in_ecount(4) uint16_t version[4]); 1959 1960 LIBEFX_API 1961 extern __checkReturn efx_rc_t 1962 efx_nvram_validate( 1963 __in efx_nic_t *enp, 1964 __in efx_nvram_type_t type, 1965 __in_bcount(partn_size) caddr_t partn_data, 1966 __in size_t partn_size); 1967 1968 LIBEFX_API 1969 extern __checkReturn efx_rc_t 1970 efx_nvram_erase( 1971 __in efx_nic_t *enp, 1972 __in efx_nvram_type_t type); 1973 1974 LIBEFX_API 1975 extern __checkReturn efx_rc_t 1976 efx_nvram_write_chunk( 1977 __in efx_nic_t *enp, 1978 __in efx_nvram_type_t type, 1979 __in unsigned int offset, 1980 __in_bcount(size) caddr_t data, 1981 __in size_t size); 1982 1983 LIBEFX_API 1984 extern void 1985 efx_nvram_fini( 1986 __in efx_nic_t *enp); 1987 1988 #endif /* EFSYS_OPT_NVRAM */ 1989 1990 #if EFSYS_OPT_BOOTCFG 1991 1992 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1993 LIBEFX_API 1994 extern __checkReturn efx_rc_t 1995 efx_bootcfg_sector_info( 1996 __in efx_nic_t *enp, 1997 __in uint32_t pf, 1998 __out_opt uint32_t *sector_countp, 1999 __out size_t *offsetp, 2000 __out size_t *max_sizep); 2001 2002 /* 2003 * Copy bootcfg sector data to a target buffer which may differ in size. 2004 * Optionally corrects format errors in source buffer. 2005 */ 2006 LIBEFX_API 2007 extern efx_rc_t 2008 efx_bootcfg_copy_sector( 2009 __in efx_nic_t *enp, 2010 __inout_bcount(sector_length) 2011 uint8_t *sector, 2012 __in size_t sector_length, 2013 __out_bcount(data_size) uint8_t *data, 2014 __in size_t data_size, 2015 __in boolean_t handle_format_errors); 2016 2017 LIBEFX_API 2018 extern efx_rc_t 2019 efx_bootcfg_read( 2020 __in efx_nic_t *enp, 2021 __out_bcount(size) uint8_t *data, 2022 __in size_t size); 2023 2024 LIBEFX_API 2025 extern efx_rc_t 2026 efx_bootcfg_write( 2027 __in efx_nic_t *enp, 2028 __in_bcount(size) uint8_t *data, 2029 __in size_t size); 2030 2031 2032 /* 2033 * Processing routines for buffers arranged in the DHCP/BOOTP option format 2034 * (see https://tools.ietf.org/html/rfc1533) 2035 * 2036 * Summarising the format: the buffer is a sequence of options. All options 2037 * begin with a tag octet, which uniquely identifies the option. Fixed- 2038 * length options without data consist of only a tag octet. Only options PAD 2039 * (0) and END (255) are fixed length. All other options are variable-length 2040 * with a length octet following the tag octet. The value of the length 2041 * octet does not include the two octets specifying the tag and length. The 2042 * length octet is followed by "length" octets of data. 2043 * 2044 * Option data may be a sequence of sub-options in the same format. The data 2045 * content of the encapsulating option is one or more encapsulated sub-options, 2046 * with no terminating END tag is required. 2047 * 2048 * To be valid, the top-level sequence of options should be terminated by an 2049 * END tag. The buffer should be padded with the PAD byte. 2050 * 2051 * When stored to NVRAM, the DHCP option format buffer is preceded by a 2052 * checksum octet. The full buffer (including after the END tag) contributes 2053 * to the checksum, hence the need to fill the buffer to the end with PAD. 2054 */ 2055 2056 #define EFX_DHCP_END ((uint8_t)0xff) 2057 #define EFX_DHCP_PAD ((uint8_t)0) 2058 2059 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 2060 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 2061 2062 LIBEFX_API 2063 extern __checkReturn uint8_t 2064 efx_dhcp_csum( 2065 __in_bcount(size) uint8_t const *data, 2066 __in size_t size); 2067 2068 LIBEFX_API 2069 extern __checkReturn efx_rc_t 2070 efx_dhcp_verify( 2071 __in_bcount(size) uint8_t const *data, 2072 __in size_t size, 2073 __out_opt size_t *usedp); 2074 2075 LIBEFX_API 2076 extern __checkReturn efx_rc_t 2077 efx_dhcp_find_tag( 2078 __in_bcount(buffer_length) uint8_t *bufferp, 2079 __in size_t buffer_length, 2080 __in uint16_t opt, 2081 __deref_out uint8_t **valuepp, 2082 __out size_t *value_lengthp); 2083 2084 LIBEFX_API 2085 extern __checkReturn efx_rc_t 2086 efx_dhcp_find_end( 2087 __in_bcount(buffer_length) uint8_t *bufferp, 2088 __in size_t buffer_length, 2089 __deref_out uint8_t **endpp); 2090 2091 2092 LIBEFX_API 2093 extern __checkReturn efx_rc_t 2094 efx_dhcp_delete_tag( 2095 __inout_bcount(buffer_length) uint8_t *bufferp, 2096 __in size_t buffer_length, 2097 __in uint16_t opt); 2098 2099 LIBEFX_API 2100 extern __checkReturn efx_rc_t 2101 efx_dhcp_add_tag( 2102 __inout_bcount(buffer_length) uint8_t *bufferp, 2103 __in size_t buffer_length, 2104 __in uint16_t opt, 2105 __in_bcount_opt(value_length) uint8_t *valuep, 2106 __in size_t value_length); 2107 2108 LIBEFX_API 2109 extern __checkReturn efx_rc_t 2110 efx_dhcp_update_tag( 2111 __inout_bcount(buffer_length) uint8_t *bufferp, 2112 __in size_t buffer_length, 2113 __in uint16_t opt, 2114 __in uint8_t *value_locationp, 2115 __in_bcount_opt(value_length) uint8_t *valuep, 2116 __in size_t value_length); 2117 2118 2119 #endif /* EFSYS_OPT_BOOTCFG */ 2120 2121 #if EFSYS_OPT_IMAGE_LAYOUT 2122 2123 #include "ef10_signed_image_layout.h" 2124 2125 /* 2126 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 2127 * 2128 * NOTE: 2129 * The image header format is extensible. However, older drivers require an 2130 * exact match of image header version and header length when validating and 2131 * writing firmware images. 2132 * 2133 * To avoid breaking backward compatibility, we use the upper bits of the 2134 * controller version fields to contain an extra version number used for 2135 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 2136 * version). See bug39254 and SF-102785-PS for details. 2137 */ 2138 typedef struct efx_image_header_s { 2139 uint32_t eih_magic; 2140 uint32_t eih_version; 2141 uint32_t eih_type; 2142 uint32_t eih_subtype; 2143 uint32_t eih_code_size; 2144 uint32_t eih_size; 2145 union { 2146 uint32_t eih_controller_version_min; 2147 struct { 2148 uint16_t eih_controller_version_min_short; 2149 uint8_t eih_extra_version_a; 2150 uint8_t eih_extra_version_b; 2151 }; 2152 }; 2153 union { 2154 uint32_t eih_controller_version_max; 2155 struct { 2156 uint16_t eih_controller_version_max_short; 2157 uint8_t eih_extra_version_c; 2158 uint8_t eih_extra_version_d; 2159 }; 2160 }; 2161 uint16_t eih_code_version_a; 2162 uint16_t eih_code_version_b; 2163 uint16_t eih_code_version_c; 2164 uint16_t eih_code_version_d; 2165 } efx_image_header_t; 2166 2167 #define EFX_IMAGE_HEADER_SIZE (40) 2168 #define EFX_IMAGE_HEADER_VERSION (4) 2169 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 2170 2171 2172 typedef struct efx_image_trailer_s { 2173 uint32_t eit_crc; 2174 } efx_image_trailer_t; 2175 2176 #define EFX_IMAGE_TRAILER_SIZE (4) 2177 2178 typedef enum efx_image_format_e { 2179 EFX_IMAGE_FORMAT_NO_IMAGE, 2180 EFX_IMAGE_FORMAT_INVALID, 2181 EFX_IMAGE_FORMAT_UNSIGNED, 2182 EFX_IMAGE_FORMAT_SIGNED, 2183 EFX_IMAGE_FORMAT_SIGNED_PACKAGE 2184 } efx_image_format_t; 2185 2186 typedef struct efx_image_info_s { 2187 efx_image_format_t eii_format; 2188 uint8_t * eii_imagep; 2189 size_t eii_image_size; 2190 efx_image_header_t * eii_headerp; 2191 } efx_image_info_t; 2192 2193 LIBEFX_API 2194 extern __checkReturn efx_rc_t 2195 efx_check_reflash_image( 2196 __in void *bufferp, 2197 __in uint32_t buffer_size, 2198 __out efx_image_info_t *infop); 2199 2200 LIBEFX_API 2201 extern __checkReturn efx_rc_t 2202 efx_build_signed_image_write_buffer( 2203 __out_bcount(buffer_size) 2204 uint8_t *bufferp, 2205 __in uint32_t buffer_size, 2206 __in efx_image_info_t *infop, 2207 __out efx_image_header_t **headerpp); 2208 2209 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 2210 2211 #if EFSYS_OPT_DIAG 2212 2213 typedef enum efx_pattern_type_t { 2214 EFX_PATTERN_BYTE_INCREMENT = 0, 2215 EFX_PATTERN_ALL_THE_SAME, 2216 EFX_PATTERN_BIT_ALTERNATE, 2217 EFX_PATTERN_BYTE_ALTERNATE, 2218 EFX_PATTERN_BYTE_CHANGING, 2219 EFX_PATTERN_BIT_SWEEP, 2220 EFX_PATTERN_NTYPES 2221 } efx_pattern_type_t; 2222 2223 typedef void 2224 (*efx_sram_pattern_fn_t)( 2225 __in size_t row, 2226 __in boolean_t negate, 2227 __out efx_qword_t *eqp); 2228 2229 LIBEFX_API 2230 extern __checkReturn efx_rc_t 2231 efx_sram_test( 2232 __in efx_nic_t *enp, 2233 __in efx_pattern_type_t type); 2234 2235 #endif /* EFSYS_OPT_DIAG */ 2236 2237 LIBEFX_API 2238 extern __checkReturn efx_rc_t 2239 efx_sram_buf_tbl_set( 2240 __in efx_nic_t *enp, 2241 __in uint32_t id, 2242 __in efsys_mem_t *esmp, 2243 __in size_t n); 2244 2245 LIBEFX_API 2246 extern void 2247 efx_sram_buf_tbl_clear( 2248 __in efx_nic_t *enp, 2249 __in uint32_t id, 2250 __in size_t n); 2251 2252 #define EFX_BUF_TBL_SIZE 0x20000 2253 2254 #define EFX_BUF_SIZE 4096 2255 2256 /* EV */ 2257 2258 typedef struct efx_evq_s efx_evq_t; 2259 2260 #if EFSYS_OPT_QSTATS 2261 2262 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ 2263 typedef enum efx_ev_qstat_e { 2264 EV_ALL, 2265 EV_RX, 2266 EV_RX_OK, 2267 EV_RX_FRM_TRUNC, 2268 EV_RX_TOBE_DISC, 2269 EV_RX_PAUSE_FRM_ERR, 2270 EV_RX_BUF_OWNER_ID_ERR, 2271 EV_RX_IPV4_HDR_CHKSUM_ERR, 2272 EV_RX_TCP_UDP_CHKSUM_ERR, 2273 EV_RX_ETH_CRC_ERR, 2274 EV_RX_IP_FRAG_ERR, 2275 EV_RX_MCAST_PKT, 2276 EV_RX_MCAST_HASH_MATCH, 2277 EV_RX_TCP_IPV4, 2278 EV_RX_TCP_IPV6, 2279 EV_RX_UDP_IPV4, 2280 EV_RX_UDP_IPV6, 2281 EV_RX_OTHER_IPV4, 2282 EV_RX_OTHER_IPV6, 2283 EV_RX_NON_IP, 2284 EV_RX_BATCH, 2285 EV_TX, 2286 EV_TX_WQ_FF_FULL, 2287 EV_TX_PKT_ERR, 2288 EV_TX_PKT_TOO_BIG, 2289 EV_TX_UNEXPECTED, 2290 EV_GLOBAL, 2291 EV_GLOBAL_MNT, 2292 EV_DRIVER, 2293 EV_DRIVER_SRM_UPD_DONE, 2294 EV_DRIVER_TX_DESCQ_FLS_DONE, 2295 EV_DRIVER_RX_DESCQ_FLS_DONE, 2296 EV_DRIVER_RX_DESCQ_FLS_FAILED, 2297 EV_DRIVER_RX_DSC_ERROR, 2298 EV_DRIVER_TX_DSC_ERROR, 2299 EV_DRV_GEN, 2300 EV_MCDI_RESPONSE, 2301 EV_RX_PARSE_INCOMPLETE, 2302 EV_NQSTATS 2303 } efx_ev_qstat_t; 2304 2305 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2306 2307 #endif /* EFSYS_OPT_QSTATS */ 2308 2309 LIBEFX_API 2310 extern __checkReturn efx_rc_t 2311 efx_ev_init( 2312 __in efx_nic_t *enp); 2313 2314 LIBEFX_API 2315 extern void 2316 efx_ev_fini( 2317 __in efx_nic_t *enp); 2318 2319 LIBEFX_API 2320 extern __checkReturn size_t 2321 efx_evq_size( 2322 __in const efx_nic_t *enp, 2323 __in unsigned int ndescs, 2324 __in uint32_t flags); 2325 2326 LIBEFX_API 2327 extern __checkReturn unsigned int 2328 efx_evq_nbufs( 2329 __in const efx_nic_t *enp, 2330 __in unsigned int ndescs, 2331 __in uint32_t flags); 2332 2333 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2334 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2335 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2336 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2337 2338 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2339 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2340 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2341 2342 /* 2343 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more 2344 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in 2345 * NO_CONT_EV mode". 2346 * 2347 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, 2348 * which is the case when an event queue is set to THROUGHPUT mode. 2349 */ 2350 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) 2351 2352 /* Configure EVQ for extended width events (EF100 only) */ 2353 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20) 2354 2355 2356 LIBEFX_API 2357 extern __checkReturn efx_rc_t 2358 efx_ev_qcreate( 2359 __in efx_nic_t *enp, 2360 __in unsigned int index, 2361 __in efsys_mem_t *esmp, 2362 __in size_t ndescs, 2363 __in uint32_t id, 2364 __in uint32_t us, 2365 __in uint32_t flags, 2366 __deref_out efx_evq_t **eepp); 2367 2368 LIBEFX_API 2369 extern __checkReturn efx_rc_t 2370 efx_ev_qcreate_irq( 2371 __in efx_nic_t *enp, 2372 __in unsigned int index, 2373 __in efsys_mem_t *esmp, 2374 __in size_t ndescs, 2375 __in uint32_t id, 2376 __in uint32_t us, 2377 __in uint32_t flags, 2378 __in uint32_t irq, 2379 __deref_out efx_evq_t **eepp); 2380 2381 LIBEFX_API 2382 extern void 2383 efx_ev_qpost( 2384 __in efx_evq_t *eep, 2385 __in uint16_t data); 2386 2387 typedef __checkReturn boolean_t 2388 (*efx_initialized_ev_t)( 2389 __in_opt void *arg); 2390 2391 #define EFX_PKT_UNICAST 0x0004 2392 #define EFX_PKT_START 0x0008 2393 2394 #define EFX_PKT_VLAN_TAGGED 0x0010 2395 #define EFX_CKSUM_TCPUDP 0x0020 2396 #define EFX_CKSUM_IPV4 0x0040 2397 #define EFX_PKT_CONT 0x0080 2398 2399 #define EFX_CHECK_VLAN 0x0100 2400 #define EFX_PKT_TCP 0x0200 2401 #define EFX_PKT_UDP 0x0400 2402 #define EFX_PKT_IPV4 0x0800 2403 2404 #define EFX_PKT_IPV6 0x1000 2405 #define EFX_PKT_PREFIX_LEN 0x2000 2406 #define EFX_ADDR_MISMATCH 0x4000 2407 #define EFX_DISCARD 0x8000 2408 2409 /* 2410 * The following flags are used only for packed stream 2411 * mode. The values for the flags are reused to fit into 16 bit, 2412 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2413 * packed stream mode 2414 */ 2415 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2416 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2417 2418 2419 #define EFX_EV_RX_NLABELS 32 2420 #define EFX_EV_TX_NLABELS 32 2421 2422 typedef __checkReturn boolean_t 2423 (*efx_rx_ev_t)( 2424 __in_opt void *arg, 2425 __in uint32_t label, 2426 __in uint32_t id, 2427 __in uint32_t size, 2428 __in uint16_t flags); 2429 2430 typedef __checkReturn boolean_t 2431 (*efx_rx_packets_ev_t)( 2432 __in_opt void *arg, 2433 __in uint32_t label, 2434 __in unsigned int num_packets, 2435 __in uint32_t flags); 2436 2437 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2438 2439 /* 2440 * Packed stream mode is documented in SF-112241-TC. 2441 * The general idea is that, instead of putting each incoming 2442 * packet into a separate buffer which is specified in a RX 2443 * descriptor, a large buffer is provided to the hardware and 2444 * packets are put there in a continuous stream. 2445 * The main advantage of such an approach is that RX queue refilling 2446 * happens much less frequently. 2447 * 2448 * Equal stride packed stream mode is documented in SF-119419-TC. 2449 * The general idea is to utilize advantages of the packed stream, 2450 * but avoid indirection in packets representation. 2451 * The main advantage of such an approach is that RX queue refilling 2452 * happens much less frequently and packets buffers are independent 2453 * from upper layers point of view. 2454 */ 2455 2456 typedef __checkReturn boolean_t 2457 (*efx_rx_ps_ev_t)( 2458 __in_opt void *arg, 2459 __in uint32_t label, 2460 __in uint32_t id, 2461 __in uint32_t pkt_count, 2462 __in uint16_t flags); 2463 2464 #endif 2465 2466 typedef __checkReturn boolean_t 2467 (*efx_tx_ev_t)( 2468 __in_opt void *arg, 2469 __in uint32_t label, 2470 __in uint32_t id); 2471 2472 typedef __checkReturn boolean_t 2473 (*efx_tx_ndescs_ev_t)( 2474 __in_opt void *arg, 2475 __in uint32_t label, 2476 __in unsigned int ndescs); 2477 2478 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2479 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2480 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2481 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2482 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2483 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2484 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2485 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2486 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2487 2488 typedef __checkReturn boolean_t 2489 (*efx_exception_ev_t)( 2490 __in_opt void *arg, 2491 __in uint32_t label, 2492 __in uint32_t data); 2493 2494 typedef __checkReturn boolean_t 2495 (*efx_rxq_flush_done_ev_t)( 2496 __in_opt void *arg, 2497 __in uint32_t rxq_index); 2498 2499 typedef __checkReturn boolean_t 2500 (*efx_rxq_flush_failed_ev_t)( 2501 __in_opt void *arg, 2502 __in uint32_t rxq_index); 2503 2504 typedef __checkReturn boolean_t 2505 (*efx_txq_flush_done_ev_t)( 2506 __in_opt void *arg, 2507 __in uint32_t txq_index); 2508 2509 typedef __checkReturn boolean_t 2510 (*efx_software_ev_t)( 2511 __in_opt void *arg, 2512 __in uint16_t magic); 2513 2514 typedef __checkReturn boolean_t 2515 (*efx_sram_ev_t)( 2516 __in_opt void *arg, 2517 __in uint32_t code); 2518 2519 #define EFX_SRAM_CLEAR 0 2520 #define EFX_SRAM_UPDATE 1 2521 #define EFX_SRAM_ILLEGAL_CLEAR 2 2522 2523 typedef __checkReturn boolean_t 2524 (*efx_wake_up_ev_t)( 2525 __in_opt void *arg, 2526 __in uint32_t label); 2527 2528 typedef __checkReturn boolean_t 2529 (*efx_timer_ev_t)( 2530 __in_opt void *arg, 2531 __in uint32_t label); 2532 2533 typedef __checkReturn boolean_t 2534 (*efx_link_change_ev_t)( 2535 __in_opt void *arg, 2536 __in efx_link_mode_t link_mode); 2537 2538 #if EFSYS_OPT_MON_STATS 2539 2540 typedef __checkReturn boolean_t 2541 (*efx_monitor_ev_t)( 2542 __in_opt void *arg, 2543 __in efx_mon_stat_t id, 2544 __in efx_mon_stat_value_t value); 2545 2546 #endif /* EFSYS_OPT_MON_STATS */ 2547 2548 #if EFSYS_OPT_MAC_STATS 2549 2550 typedef __checkReturn boolean_t 2551 (*efx_mac_stats_ev_t)( 2552 __in_opt void *arg, 2553 __in uint32_t generation); 2554 2555 #endif /* EFSYS_OPT_MAC_STATS */ 2556 2557 #if EFSYS_OPT_DESC_PROXY 2558 2559 /* 2560 * NOTE: This callback returns the raw descriptor data, which has not been 2561 * converted to host endian. The callback must use the EFX_OWORD macros 2562 * to extract the descriptor fields as host endian values. 2563 */ 2564 typedef __checkReturn boolean_t 2565 (*efx_desc_proxy_txq_desc_ev_t)( 2566 __in_opt void *arg, 2567 __in uint16_t vi_id, 2568 __in efx_oword_t txq_desc); 2569 2570 /* 2571 * NOTE: This callback returns the raw descriptor data, which has not been 2572 * converted to host endian. The callback must use the EFX_OWORD macros 2573 * to extract the descriptor fields as host endian values. 2574 */ 2575 typedef __checkReturn boolean_t 2576 (*efx_desc_proxy_virtq_desc_ev_t)( 2577 __in_opt void *arg, 2578 __in uint16_t vi_id, 2579 __in uint16_t avail, 2580 __in efx_oword_t virtq_desc); 2581 2582 #endif /* EFSYS_OPT_DESC_PROXY */ 2583 2584 typedef struct efx_ev_callbacks_s { 2585 efx_initialized_ev_t eec_initialized; 2586 efx_rx_ev_t eec_rx; 2587 efx_rx_packets_ev_t eec_rx_packets; 2588 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2589 efx_rx_ps_ev_t eec_rx_ps; 2590 #endif 2591 efx_tx_ev_t eec_tx; 2592 efx_tx_ndescs_ev_t eec_tx_ndescs; 2593 efx_exception_ev_t eec_exception; 2594 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2595 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2596 efx_txq_flush_done_ev_t eec_txq_flush_done; 2597 efx_software_ev_t eec_software; 2598 efx_sram_ev_t eec_sram; 2599 efx_wake_up_ev_t eec_wake_up; 2600 efx_timer_ev_t eec_timer; 2601 efx_link_change_ev_t eec_link_change; 2602 #if EFSYS_OPT_MON_STATS 2603 efx_monitor_ev_t eec_monitor; 2604 #endif /* EFSYS_OPT_MON_STATS */ 2605 #if EFSYS_OPT_MAC_STATS 2606 efx_mac_stats_ev_t eec_mac_stats; 2607 #endif /* EFSYS_OPT_MAC_STATS */ 2608 #if EFSYS_OPT_DESC_PROXY 2609 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc; 2610 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc; 2611 #endif /* EFSYS_OPT_DESC_PROXY */ 2612 2613 } efx_ev_callbacks_t; 2614 2615 LIBEFX_API 2616 extern __checkReturn boolean_t 2617 efx_ev_qpending( 2618 __in efx_evq_t *eep, 2619 __in unsigned int count); 2620 2621 #if EFSYS_OPT_EV_PREFETCH 2622 2623 LIBEFX_API 2624 extern void 2625 efx_ev_qprefetch( 2626 __in efx_evq_t *eep, 2627 __in unsigned int count); 2628 2629 #endif /* EFSYS_OPT_EV_PREFETCH */ 2630 2631 LIBEFX_API 2632 extern void 2633 efx_ev_qcreate_check_init_done( 2634 __in efx_evq_t *eep, 2635 __in const efx_ev_callbacks_t *eecp, 2636 __in_opt void *arg); 2637 2638 LIBEFX_API 2639 extern void 2640 efx_ev_qpoll( 2641 __in efx_evq_t *eep, 2642 __inout unsigned int *countp, 2643 __in const efx_ev_callbacks_t *eecp, 2644 __in_opt void *arg); 2645 2646 LIBEFX_API 2647 extern __checkReturn efx_rc_t 2648 efx_ev_usecs_to_ticks( 2649 __in efx_nic_t *enp, 2650 __in unsigned int usecs, 2651 __out unsigned int *ticksp); 2652 2653 LIBEFX_API 2654 extern __checkReturn efx_rc_t 2655 efx_ev_qmoderate( 2656 __in efx_evq_t *eep, 2657 __in unsigned int us); 2658 2659 LIBEFX_API 2660 extern __checkReturn efx_rc_t 2661 efx_ev_qprime( 2662 __in efx_evq_t *eep, 2663 __in unsigned int count); 2664 2665 #if EFSYS_OPT_QSTATS 2666 2667 #if EFSYS_OPT_NAMES 2668 2669 LIBEFX_API 2670 extern const char * 2671 efx_ev_qstat_name( 2672 __in efx_nic_t *enp, 2673 __in unsigned int id); 2674 2675 #endif /* EFSYS_OPT_NAMES */ 2676 2677 LIBEFX_API 2678 extern void 2679 efx_ev_qstats_update( 2680 __in efx_evq_t *eep, 2681 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2682 2683 #endif /* EFSYS_OPT_QSTATS */ 2684 2685 LIBEFX_API 2686 extern void 2687 efx_ev_qdestroy( 2688 __in efx_evq_t *eep); 2689 2690 /* RX */ 2691 2692 LIBEFX_API 2693 extern __checkReturn efx_rc_t 2694 efx_rx_init( 2695 __inout efx_nic_t *enp); 2696 2697 LIBEFX_API 2698 extern void 2699 efx_rx_fini( 2700 __in efx_nic_t *enp); 2701 2702 #if EFSYS_OPT_RX_SCATTER 2703 LIBEFX_API 2704 extern __checkReturn efx_rc_t 2705 efx_rx_scatter_enable( 2706 __in efx_nic_t *enp, 2707 __in unsigned int buf_size); 2708 #endif /* EFSYS_OPT_RX_SCATTER */ 2709 2710 /* Handle to represent use of the default RSS context. */ 2711 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2712 2713 #if EFSYS_OPT_RX_SCALE 2714 2715 typedef enum efx_rx_hash_alg_e { 2716 EFX_RX_HASHALG_LFSR = 0, 2717 EFX_RX_HASHALG_TOEPLITZ, 2718 EFX_RX_HASHALG_PACKED_STREAM, 2719 EFX_RX_NHASHALGS 2720 } efx_rx_hash_alg_t; 2721 2722 /* 2723 * Legacy hash type flags. 2724 * 2725 * They represent standard tuples for distinct traffic classes. 2726 */ 2727 #define EFX_RX_HASH_IPV4 (1U << 0) 2728 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2729 #define EFX_RX_HASH_IPV6 (1U << 2) 2730 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2731 2732 #define EFX_RX_HASH_LEGACY_MASK \ 2733 (EFX_RX_HASH_IPV4 | \ 2734 EFX_RX_HASH_TCPIPV4 | \ 2735 EFX_RX_HASH_IPV6 | \ 2736 EFX_RX_HASH_TCPIPV6) 2737 2738 /* 2739 * The type of the argument used by efx_rx_scale_mode_set() to 2740 * provide a means for the client drivers to configure hashing. 2741 * 2742 * A properly constructed value can either be: 2743 * - a combination of legacy flags 2744 * - a combination of EFX_RX_HASH() flags 2745 */ 2746 typedef uint32_t efx_rx_hash_type_t; 2747 2748 typedef enum efx_rx_hash_support_e { 2749 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2750 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2751 } efx_rx_hash_support_t; 2752 2753 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2754 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2755 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2756 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2757 2758 typedef enum efx_rx_scale_context_type_e { 2759 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2760 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2761 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2762 } efx_rx_scale_context_type_t; 2763 2764 /* 2765 * Traffic classes eligible for hash computation. 2766 * 2767 * Select packet headers used in computing the receive hash. 2768 * This uses the same encoding as the RSS_MODES field of 2769 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2770 */ 2771 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2772 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2773 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2774 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2775 #define EFX_RX_CLASS_IPV4_LBN 16 2776 #define EFX_RX_CLASS_IPV4_WIDTH 4 2777 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2778 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2779 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2780 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2781 #define EFX_RX_CLASS_IPV6_LBN 28 2782 #define EFX_RX_CLASS_IPV6_WIDTH 4 2783 2784 #define EFX_RX_NCLASSES 6 2785 2786 /* 2787 * Ancillary flags used to construct generic hash tuples. 2788 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2789 */ 2790 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2791 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2792 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2793 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2794 2795 /* 2796 * Generic hash tuples. 2797 * 2798 * They express combinations of packet fields 2799 * which can contribute to the hash value for 2800 * a particular traffic class. 2801 */ 2802 #define EFX_RX_CLASS_HASH_DISABLE 0 2803 2804 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2805 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2806 2807 #define EFX_RX_CLASS_HASH_2TUPLE \ 2808 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2809 EFX_RX_CLASS_HASH_DST_ADDR) 2810 2811 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2812 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2813 EFX_RX_CLASS_HASH_SRC_PORT) 2814 2815 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2816 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2817 EFX_RX_CLASS_HASH_DST_PORT) 2818 2819 #define EFX_RX_CLASS_HASH_4TUPLE \ 2820 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2821 EFX_RX_CLASS_HASH_DST_ADDR | \ 2822 EFX_RX_CLASS_HASH_SRC_PORT | \ 2823 EFX_RX_CLASS_HASH_DST_PORT) 2824 2825 #define EFX_RX_CLASS_HASH_NTUPLES 7 2826 2827 /* 2828 * Hash flag constructor. 2829 * 2830 * Resulting flags encode hash tuples for specific traffic classes. 2831 * The client drivers are encouraged to use these flags to form 2832 * a hash type value. 2833 */ 2834 #define EFX_RX_HASH(_class, _tuple) \ 2835 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2836 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2837 2838 /* 2839 * The maximum number of EFX_RX_HASH() flags. 2840 */ 2841 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2842 2843 LIBEFX_API 2844 extern __checkReturn efx_rc_t 2845 efx_rx_scale_hash_flags_get( 2846 __in efx_nic_t *enp, 2847 __in efx_rx_hash_alg_t hash_alg, 2848 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2849 __in unsigned int max_nflags, 2850 __out unsigned int *nflagsp); 2851 2852 LIBEFX_API 2853 extern __checkReturn efx_rc_t 2854 efx_rx_hash_default_support_get( 2855 __in efx_nic_t *enp, 2856 __out efx_rx_hash_support_t *supportp); 2857 2858 2859 LIBEFX_API 2860 extern __checkReturn efx_rc_t 2861 efx_rx_scale_default_support_get( 2862 __in efx_nic_t *enp, 2863 __out efx_rx_scale_context_type_t *typep); 2864 2865 LIBEFX_API 2866 extern __checkReturn efx_rc_t 2867 efx_rx_scale_context_alloc( 2868 __in efx_nic_t *enp, 2869 __in efx_rx_scale_context_type_t type, 2870 __in uint32_t num_queues, 2871 __out uint32_t *rss_contextp); 2872 2873 LIBEFX_API 2874 extern __checkReturn efx_rc_t 2875 efx_rx_scale_context_free( 2876 __in efx_nic_t *enp, 2877 __in uint32_t rss_context); 2878 2879 LIBEFX_API 2880 extern __checkReturn efx_rc_t 2881 efx_rx_scale_mode_set( 2882 __in efx_nic_t *enp, 2883 __in uint32_t rss_context, 2884 __in efx_rx_hash_alg_t alg, 2885 __in efx_rx_hash_type_t type, 2886 __in boolean_t insert); 2887 2888 LIBEFX_API 2889 extern __checkReturn efx_rc_t 2890 efx_rx_scale_tbl_set( 2891 __in efx_nic_t *enp, 2892 __in uint32_t rss_context, 2893 __in_ecount(n) unsigned int *table, 2894 __in size_t n); 2895 2896 LIBEFX_API 2897 extern __checkReturn efx_rc_t 2898 efx_rx_scale_key_set( 2899 __in efx_nic_t *enp, 2900 __in uint32_t rss_context, 2901 __in_ecount(n) uint8_t *key, 2902 __in size_t n); 2903 2904 LIBEFX_API 2905 extern __checkReturn uint32_t 2906 efx_pseudo_hdr_hash_get( 2907 __in efx_rxq_t *erp, 2908 __in efx_rx_hash_alg_t func, 2909 __in uint8_t *buffer); 2910 2911 #endif /* EFSYS_OPT_RX_SCALE */ 2912 2913 LIBEFX_API 2914 extern __checkReturn efx_rc_t 2915 efx_pseudo_hdr_pkt_length_get( 2916 __in efx_rxq_t *erp, 2917 __in uint8_t *buffer, 2918 __out uint16_t *pkt_lengthp); 2919 2920 LIBEFX_API 2921 extern __checkReturn size_t 2922 efx_rxq_size( 2923 __in const efx_nic_t *enp, 2924 __in unsigned int ndescs); 2925 2926 LIBEFX_API 2927 extern __checkReturn unsigned int 2928 efx_rxq_nbufs( 2929 __in const efx_nic_t *enp, 2930 __in unsigned int ndescs); 2931 2932 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2933 2934 /* 2935 * libefx representation of the Rx prefix layout information. 2936 * 2937 * The information may be used inside libefx to implement Rx prefix fields 2938 * accessors and by drivers which process Rx prefix itself. 2939 */ 2940 2941 /* 2942 * All known Rx prefix fields. 2943 * 2944 * An Rx prefix may have a subset of these fields. 2945 */ 2946 typedef enum efx_rx_prefix_field_e { 2947 EFX_RX_PREFIX_FIELD_LENGTH = 0, 2948 EFX_RX_PREFIX_FIELD_ORIG_LENGTH, 2949 EFX_RX_PREFIX_FIELD_CLASS, 2950 EFX_RX_PREFIX_FIELD_RSS_HASH, 2951 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID, 2952 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP, 2953 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI, 2954 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI, 2955 EFX_RX_PREFIX_FIELD_USER_FLAG, 2956 EFX_RX_PREFIX_FIELD_USER_MARK, 2957 EFX_RX_PREFIX_FIELD_USER_MARK_VALID, 2958 EFX_RX_PREFIX_FIELD_CSUM_FRAME, 2959 EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 2960 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 2961 EFX_RX_PREFIX_NFIELDS 2962 } efx_rx_prefix_field_t; 2963 2964 /* 2965 * Location and endianness of a field in Rx prefix. 2966 * 2967 * If width is zero, the field is not present. 2968 */ 2969 typedef struct efx_rx_prefix_field_info_s { 2970 uint16_t erpfi_offset_bits; 2971 uint8_t erpfi_width_bits; 2972 boolean_t erpfi_big_endian; 2973 } efx_rx_prefix_field_info_t; 2974 2975 /* Helper macro to define Rx prefix fields */ 2976 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \ 2977 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \ 2978 .erpfi_offset_bits = EFX_LOW_BIT(_field), \ 2979 .erpfi_width_bits = EFX_WIDTH(_field), \ 2980 .erpfi_big_endian = (_big_endian), \ 2981 } 2982 2983 typedef struct efx_rx_prefix_layout_s { 2984 uint32_t erpl_id; 2985 uint8_t erpl_length; 2986 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS]; 2987 } efx_rx_prefix_layout_t; 2988 2989 /* 2990 * Helper function to find out a bit mask of wanted but not available 2991 * Rx prefix fields. 2992 * 2993 * A field is considered as not available if any parameter mismatch. 2994 */ 2995 LIBEFX_API 2996 extern __checkReturn uint32_t 2997 efx_rx_prefix_layout_check( 2998 __in const efx_rx_prefix_layout_t *available, 2999 __in const efx_rx_prefix_layout_t *wanted); 3000 3001 LIBEFX_API 3002 extern __checkReturn efx_rc_t 3003 efx_rx_prefix_get_layout( 3004 __in const efx_rxq_t *erp, 3005 __out efx_rx_prefix_layout_t *erplp); 3006 3007 typedef enum efx_rxq_type_e { 3008 EFX_RXQ_TYPE_DEFAULT, 3009 EFX_RXQ_TYPE_PACKED_STREAM, 3010 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 3011 EFX_RXQ_NTYPES 3012 } efx_rxq_type_t; 3013 3014 /* 3015 * Dummy flag to be used instead of 0 to make it clear that the argument 3016 * is receive queue flags. 3017 */ 3018 #define EFX_RXQ_FLAG_NONE 0x0 3019 #define EFX_RXQ_FLAG_SCATTER 0x1 3020 /* 3021 * If tunnels are supported and Rx event can provide information about 3022 * either outer or inner packet classes (e.g. SFN8xxx adapters with 3023 * full-feature firmware variant running), outer classes are requested by 3024 * default. However, if the driver supports tunnels, the flag allows to 3025 * request inner classes which are required to be able to interpret inner 3026 * Rx checksum offload results. 3027 */ 3028 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 3029 /* 3030 * Request delivery of the RSS hash calculated by HW to be used by 3031 * the driver. 3032 */ 3033 #define EFX_RXQ_FLAG_RSS_HASH 0x4 3034 /* 3035 * Request ingress mport field in the Rx prefix of a queue. 3036 */ 3037 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8 3038 /* 3039 * Request user mark field in the Rx prefix of a queue. 3040 */ 3041 #define EFX_RXQ_FLAG_USER_MARK 0x10 3042 /* 3043 * Request user flag field in the Rx prefix of a queue. 3044 */ 3045 #define EFX_RXQ_FLAG_USER_FLAG 0x20 3046 3047 LIBEFX_API 3048 extern __checkReturn efx_rc_t 3049 efx_rx_qcreate( 3050 __in efx_nic_t *enp, 3051 __in unsigned int index, 3052 __in unsigned int label, 3053 __in efx_rxq_type_t type, 3054 __in size_t buf_size, 3055 __in efsys_mem_t *esmp, 3056 __in size_t ndescs, 3057 __in uint32_t id, 3058 __in unsigned int flags, 3059 __in efx_evq_t *eep, 3060 __deref_out efx_rxq_t **erpp); 3061 3062 #if EFSYS_OPT_RX_PACKED_STREAM 3063 3064 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 3065 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 3066 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 3067 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 3068 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 3069 3070 LIBEFX_API 3071 extern __checkReturn efx_rc_t 3072 efx_rx_qcreate_packed_stream( 3073 __in efx_nic_t *enp, 3074 __in unsigned int index, 3075 __in unsigned int label, 3076 __in uint32_t ps_buf_size, 3077 __in efsys_mem_t *esmp, 3078 __in size_t ndescs, 3079 __in efx_evq_t *eep, 3080 __deref_out efx_rxq_t **erpp); 3081 3082 #endif 3083 3084 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 3085 3086 /* Maximum head-of-line block timeout in nanoseconds */ 3087 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 3088 3089 LIBEFX_API 3090 extern __checkReturn efx_rc_t 3091 efx_rx_qcreate_es_super_buffer( 3092 __in efx_nic_t *enp, 3093 __in unsigned int index, 3094 __in unsigned int label, 3095 __in uint32_t n_bufs_per_desc, 3096 __in uint32_t max_dma_len, 3097 __in uint32_t buf_stride, 3098 __in uint32_t hol_block_timeout, 3099 __in efsys_mem_t *esmp, 3100 __in size_t ndescs, 3101 __in unsigned int flags, 3102 __in efx_evq_t *eep, 3103 __deref_out efx_rxq_t **erpp); 3104 3105 #endif 3106 3107 typedef struct efx_buffer_s { 3108 efsys_dma_addr_t eb_addr; 3109 size_t eb_size; 3110 boolean_t eb_eop; 3111 } efx_buffer_t; 3112 3113 typedef struct efx_desc_s { 3114 efx_qword_t ed_eq; 3115 } efx_desc_t; 3116 3117 LIBEFX_API 3118 extern void 3119 efx_rx_qpost( 3120 __in efx_rxq_t *erp, 3121 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 3122 __in size_t size, 3123 __in unsigned int ndescs, 3124 __in unsigned int completed, 3125 __in unsigned int added); 3126 3127 LIBEFX_API 3128 extern void 3129 efx_rx_qpush( 3130 __in efx_rxq_t *erp, 3131 __in unsigned int added, 3132 __inout unsigned int *pushedp); 3133 3134 #if EFSYS_OPT_RX_PACKED_STREAM 3135 3136 LIBEFX_API 3137 extern void 3138 efx_rx_qpush_ps_credits( 3139 __in efx_rxq_t *erp); 3140 3141 LIBEFX_API 3142 extern __checkReturn uint8_t * 3143 efx_rx_qps_packet_info( 3144 __in efx_rxq_t *erp, 3145 __in uint8_t *buffer, 3146 __in uint32_t buffer_length, 3147 __in uint32_t current_offset, 3148 __out uint16_t *lengthp, 3149 __out uint32_t *next_offsetp, 3150 __out uint32_t *timestamp); 3151 #endif 3152 3153 LIBEFX_API 3154 extern __checkReturn efx_rc_t 3155 efx_rx_qflush( 3156 __in efx_rxq_t *erp); 3157 3158 LIBEFX_API 3159 extern void 3160 efx_rx_qenable( 3161 __in efx_rxq_t *erp); 3162 3163 LIBEFX_API 3164 extern void 3165 efx_rx_qdestroy( 3166 __in efx_rxq_t *erp); 3167 3168 /* TX */ 3169 3170 typedef struct efx_txq_s efx_txq_t; 3171 3172 #if EFSYS_OPT_QSTATS 3173 3174 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 3175 typedef enum efx_tx_qstat_e { 3176 TX_POST, 3177 TX_POST_PIO, 3178 TX_NQSTATS 3179 } efx_tx_qstat_t; 3180 3181 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 3182 3183 #endif /* EFSYS_OPT_QSTATS */ 3184 3185 LIBEFX_API 3186 extern __checkReturn efx_rc_t 3187 efx_tx_init( 3188 __in efx_nic_t *enp); 3189 3190 LIBEFX_API 3191 extern void 3192 efx_tx_fini( 3193 __in efx_nic_t *enp); 3194 3195 LIBEFX_API 3196 extern __checkReturn size_t 3197 efx_txq_size( 3198 __in const efx_nic_t *enp, 3199 __in unsigned int ndescs); 3200 3201 LIBEFX_API 3202 extern __checkReturn unsigned int 3203 efx_txq_nbufs( 3204 __in const efx_nic_t *enp, 3205 __in unsigned int ndescs); 3206 3207 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 3208 3209 #define EFX_TXQ_CKSUM_IPV4 0x0001 3210 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 3211 #define EFX_TXQ_FATSOV2 0x0004 3212 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 3213 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 3214 3215 LIBEFX_API 3216 extern __checkReturn efx_rc_t 3217 efx_tx_qcreate( 3218 __in efx_nic_t *enp, 3219 __in unsigned int index, 3220 __in unsigned int label, 3221 __in efsys_mem_t *esmp, 3222 __in size_t n, 3223 __in uint32_t id, 3224 __in uint16_t flags, 3225 __in efx_evq_t *eep, 3226 __deref_out efx_txq_t **etpp, 3227 __out unsigned int *addedp); 3228 3229 LIBEFX_API 3230 extern __checkReturn efx_rc_t 3231 efx_tx_qpost( 3232 __in efx_txq_t *etp, 3233 __in_ecount(ndescs) efx_buffer_t *eb, 3234 __in unsigned int ndescs, 3235 __in unsigned int completed, 3236 __inout unsigned int *addedp); 3237 3238 LIBEFX_API 3239 extern __checkReturn efx_rc_t 3240 efx_tx_qpace( 3241 __in efx_txq_t *etp, 3242 __in unsigned int ns); 3243 3244 LIBEFX_API 3245 extern void 3246 efx_tx_qpush( 3247 __in efx_txq_t *etp, 3248 __in unsigned int added, 3249 __in unsigned int pushed); 3250 3251 LIBEFX_API 3252 extern __checkReturn efx_rc_t 3253 efx_tx_qflush( 3254 __in efx_txq_t *etp); 3255 3256 LIBEFX_API 3257 extern void 3258 efx_tx_qenable( 3259 __in efx_txq_t *etp); 3260 3261 LIBEFX_API 3262 extern __checkReturn efx_rc_t 3263 efx_tx_qpio_enable( 3264 __in efx_txq_t *etp); 3265 3266 LIBEFX_API 3267 extern void 3268 efx_tx_qpio_disable( 3269 __in efx_txq_t *etp); 3270 3271 LIBEFX_API 3272 extern __checkReturn efx_rc_t 3273 efx_tx_qpio_write( 3274 __in efx_txq_t *etp, 3275 __in_ecount(buf_length) uint8_t *buffer, 3276 __in size_t buf_length, 3277 __in size_t pio_buf_offset); 3278 3279 LIBEFX_API 3280 extern __checkReturn efx_rc_t 3281 efx_tx_qpio_post( 3282 __in efx_txq_t *etp, 3283 __in size_t pkt_length, 3284 __in unsigned int completed, 3285 __inout unsigned int *addedp); 3286 3287 LIBEFX_API 3288 extern __checkReturn efx_rc_t 3289 efx_tx_qdesc_post( 3290 __in efx_txq_t *etp, 3291 __in_ecount(n) efx_desc_t *ed, 3292 __in unsigned int n, 3293 __in unsigned int completed, 3294 __inout unsigned int *addedp); 3295 3296 LIBEFX_API 3297 extern void 3298 efx_tx_qdesc_dma_create( 3299 __in efx_txq_t *etp, 3300 __in efsys_dma_addr_t addr, 3301 __in size_t size, 3302 __in boolean_t eop, 3303 __out efx_desc_t *edp); 3304 3305 LIBEFX_API 3306 extern void 3307 efx_tx_qdesc_tso_create( 3308 __in efx_txq_t *etp, 3309 __in uint16_t ipv4_id, 3310 __in uint32_t tcp_seq, 3311 __in uint8_t tcp_flags, 3312 __out efx_desc_t *edp); 3313 3314 /* Number of FATSOv2 option descriptors */ 3315 #define EFX_TX_FATSOV2_OPT_NDESCS 2 3316 3317 /* Maximum number of DMA segments per TSO packet (not superframe) */ 3318 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 3319 3320 LIBEFX_API 3321 extern void 3322 efx_tx_qdesc_tso2_create( 3323 __in efx_txq_t *etp, 3324 __in uint16_t ipv4_id, 3325 __in uint16_t outer_ipv4_id, 3326 __in uint32_t tcp_seq, 3327 __in uint16_t tcp_mss, 3328 __out_ecount(count) efx_desc_t *edp, 3329 __in int count); 3330 3331 LIBEFX_API 3332 extern void 3333 efx_tx_qdesc_vlantci_create( 3334 __in efx_txq_t *etp, 3335 __in uint16_t tci, 3336 __out efx_desc_t *edp); 3337 3338 LIBEFX_API 3339 extern void 3340 efx_tx_qdesc_checksum_create( 3341 __in efx_txq_t *etp, 3342 __in uint16_t flags, 3343 __out efx_desc_t *edp); 3344 3345 #if EFSYS_OPT_QSTATS 3346 3347 #if EFSYS_OPT_NAMES 3348 3349 LIBEFX_API 3350 extern const char * 3351 efx_tx_qstat_name( 3352 __in efx_nic_t *etp, 3353 __in unsigned int id); 3354 3355 #endif /* EFSYS_OPT_NAMES */ 3356 3357 LIBEFX_API 3358 extern void 3359 efx_tx_qstats_update( 3360 __in efx_txq_t *etp, 3361 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 3362 3363 #endif /* EFSYS_OPT_QSTATS */ 3364 3365 LIBEFX_API 3366 extern void 3367 efx_tx_qdestroy( 3368 __in efx_txq_t *etp); 3369 3370 3371 /* FILTER */ 3372 3373 #if EFSYS_OPT_FILTER 3374 3375 #define EFX_ETHER_TYPE_IPV4 0x0800 3376 #define EFX_ETHER_TYPE_IPV6 0x86DD 3377 3378 #define EFX_IPPROTO_TCP 6 3379 #define EFX_IPPROTO_UDP 17 3380 #define EFX_IPPROTO_GRE 47 3381 3382 /* Use RSS to spread across multiple queues */ 3383 #define EFX_FILTER_FLAG_RX_RSS 0x01 3384 /* Enable RX scatter */ 3385 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 3386 /* 3387 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 3388 * May only be set by the filter implementation for each type. 3389 * A removal request will restore the automatic filter in its place. 3390 */ 3391 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 3392 /* Filter is for RX */ 3393 #define EFX_FILTER_FLAG_RX 0x08 3394 /* Filter is for TX */ 3395 #define EFX_FILTER_FLAG_TX 0x10 3396 /* Set match flag on the received packet */ 3397 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 3398 /* Set match mark on the received packet */ 3399 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 3400 3401 typedef uint8_t efx_filter_flags_t; 3402 3403 /* 3404 * Flags which specify the fields to match on. The values are the same as in the 3405 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 3406 */ 3407 3408 /* Match by remote IP host address */ 3409 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 3410 /* Match by local IP host address */ 3411 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 3412 /* Match by remote MAC address */ 3413 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 3414 /* Match by remote TCP/UDP port */ 3415 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 3416 /* Match by remote TCP/UDP port */ 3417 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 3418 /* Match by local TCP/UDP port */ 3419 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 3420 /* Match by Ether-type */ 3421 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 3422 /* Match by inner VLAN ID */ 3423 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 3424 /* Match by outer VLAN ID */ 3425 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 3426 /* Match by IP transport protocol */ 3427 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 3428 /* Match by ingress MPORT */ 3429 #define EFX_FILTER_MATCH_MPORT 0x00000400 3430 /* Match by VNI or VSID */ 3431 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 3432 /* For encapsulated packets, match by inner frame local MAC address */ 3433 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 3434 /* For encapsulated packets, match all multicast inner frames */ 3435 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 3436 /* For encapsulated packets, match all unicast inner frames */ 3437 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 3438 /* 3439 * Match by encap type, this flag does not correspond to 3440 * the MCDI match flags and any unoccupied value may be used 3441 */ 3442 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 3443 /* Match otherwise-unmatched multicast and broadcast packets */ 3444 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 3445 /* Match otherwise-unmatched unicast packets */ 3446 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 3447 3448 typedef uint32_t efx_filter_match_flags_t; 3449 3450 /* Filter priority from lowest to highest */ 3451 typedef enum efx_filter_priority_s { 3452 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device 3453 * address list or hardware 3454 * requirements. This may only be used 3455 * by the filter implementation for 3456 * each NIC type. */ 3457 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 3458 EFX_FILTER_NPRI, 3459 } efx_filter_priority_t; 3460 3461 /* 3462 * FIXME: All these fields are assumed to be in little-endian byte order. 3463 * It may be better for some to be big-endian. See bug42804. 3464 */ 3465 3466 typedef struct efx_filter_spec_s { 3467 efx_filter_match_flags_t efs_match_flags; 3468 uint8_t efs_priority; 3469 efx_filter_flags_t efs_flags; 3470 uint16_t efs_dmaq_id; 3471 uint32_t efs_rss_context; 3472 uint32_t efs_mark; 3473 /* 3474 * Saved lower-priority filter. If it is set, it is restored on 3475 * filter delete operation. 3476 */ 3477 struct efx_filter_spec_s *efs_overridden_spec; 3478 /* Fields below here are hashed for software filter lookup */ 3479 uint16_t efs_outer_vid; 3480 uint16_t efs_inner_vid; 3481 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 3482 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 3483 uint16_t efs_ether_type; 3484 uint8_t efs_ip_proto; 3485 efx_tunnel_protocol_t efs_encap_type; 3486 uint16_t efs_loc_port; 3487 uint16_t efs_rem_port; 3488 efx_oword_t efs_rem_host; 3489 efx_oword_t efs_loc_host; 3490 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 3491 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 3492 uint32_t efs_ingress_mport; 3493 } efx_filter_spec_t; 3494 3495 3496 /* Default values for use in filter specifications */ 3497 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 3498 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 3499 3500 LIBEFX_API 3501 extern __checkReturn efx_rc_t 3502 efx_filter_init( 3503 __in efx_nic_t *enp); 3504 3505 LIBEFX_API 3506 extern void 3507 efx_filter_fini( 3508 __in efx_nic_t *enp); 3509 3510 LIBEFX_API 3511 extern __checkReturn efx_rc_t 3512 efx_filter_insert( 3513 __in efx_nic_t *enp, 3514 __inout efx_filter_spec_t *spec); 3515 3516 LIBEFX_API 3517 extern __checkReturn efx_rc_t 3518 efx_filter_remove( 3519 __in efx_nic_t *enp, 3520 __inout efx_filter_spec_t *spec); 3521 3522 LIBEFX_API 3523 extern __checkReturn efx_rc_t 3524 efx_filter_restore( 3525 __in efx_nic_t *enp); 3526 3527 LIBEFX_API 3528 extern __checkReturn efx_rc_t 3529 efx_filter_supported_filters( 3530 __in efx_nic_t *enp, 3531 __out_ecount(buffer_length) uint32_t *buffer, 3532 __in size_t buffer_length, 3533 __out size_t *list_lengthp); 3534 3535 LIBEFX_API 3536 extern void 3537 efx_filter_spec_init_rx( 3538 __out efx_filter_spec_t *spec, 3539 __in efx_filter_priority_t priority, 3540 __in efx_filter_flags_t flags, 3541 __in efx_rxq_t *erp); 3542 3543 LIBEFX_API 3544 extern void 3545 efx_filter_spec_init_tx( 3546 __out efx_filter_spec_t *spec, 3547 __in efx_txq_t *etp); 3548 3549 LIBEFX_API 3550 extern __checkReturn efx_rc_t 3551 efx_filter_spec_set_ipv4_local( 3552 __inout efx_filter_spec_t *spec, 3553 __in uint8_t proto, 3554 __in uint32_t host, 3555 __in uint16_t port); 3556 3557 LIBEFX_API 3558 extern __checkReturn efx_rc_t 3559 efx_filter_spec_set_ipv4_full( 3560 __inout efx_filter_spec_t *spec, 3561 __in uint8_t proto, 3562 __in uint32_t lhost, 3563 __in uint16_t lport, 3564 __in uint32_t rhost, 3565 __in uint16_t rport); 3566 3567 LIBEFX_API 3568 extern __checkReturn efx_rc_t 3569 efx_filter_spec_set_eth_local( 3570 __inout efx_filter_spec_t *spec, 3571 __in uint16_t vid, 3572 __in const uint8_t *addr); 3573 3574 LIBEFX_API 3575 extern void 3576 efx_filter_spec_set_ether_type( 3577 __inout efx_filter_spec_t *spec, 3578 __in uint16_t ether_type); 3579 3580 LIBEFX_API 3581 extern __checkReturn efx_rc_t 3582 efx_filter_spec_set_uc_def( 3583 __inout efx_filter_spec_t *spec); 3584 3585 LIBEFX_API 3586 extern __checkReturn efx_rc_t 3587 efx_filter_spec_set_mc_def( 3588 __inout efx_filter_spec_t *spec); 3589 3590 typedef enum efx_filter_inner_frame_match_e { 3591 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3592 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3593 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3594 } efx_filter_inner_frame_match_t; 3595 3596 LIBEFX_API 3597 extern __checkReturn efx_rc_t 3598 efx_filter_spec_set_encap_type( 3599 __inout efx_filter_spec_t *spec, 3600 __in efx_tunnel_protocol_t encap_type, 3601 __in efx_filter_inner_frame_match_t inner_frame_match); 3602 3603 LIBEFX_API 3604 extern __checkReturn efx_rc_t 3605 efx_filter_spec_set_vxlan( 3606 __inout efx_filter_spec_t *spec, 3607 __in const uint8_t *vni, 3608 __in const uint8_t *inner_addr, 3609 __in const uint8_t *outer_addr); 3610 3611 LIBEFX_API 3612 extern __checkReturn efx_rc_t 3613 efx_filter_spec_set_geneve( 3614 __inout efx_filter_spec_t *spec, 3615 __in const uint8_t *vni, 3616 __in const uint8_t *inner_addr, 3617 __in const uint8_t *outer_addr); 3618 3619 LIBEFX_API 3620 extern __checkReturn efx_rc_t 3621 efx_filter_spec_set_nvgre( 3622 __inout efx_filter_spec_t *spec, 3623 __in const uint8_t *vsid, 3624 __in const uint8_t *inner_addr, 3625 __in const uint8_t *outer_addr); 3626 3627 #if EFSYS_OPT_RX_SCALE 3628 LIBEFX_API 3629 extern __checkReturn efx_rc_t 3630 efx_filter_spec_set_rss_context( 3631 __inout efx_filter_spec_t *spec, 3632 __in uint32_t rss_context); 3633 #endif 3634 #endif /* EFSYS_OPT_FILTER */ 3635 3636 /* HASH */ 3637 3638 LIBEFX_API 3639 extern __checkReturn uint32_t 3640 efx_hash_dwords( 3641 __in_ecount(count) uint32_t const *input, 3642 __in size_t count, 3643 __in uint32_t init); 3644 3645 LIBEFX_API 3646 extern __checkReturn uint32_t 3647 efx_hash_bytes( 3648 __in_ecount(length) uint8_t const *input, 3649 __in size_t length, 3650 __in uint32_t init); 3651 3652 #if EFSYS_OPT_LICENSING 3653 3654 /* LICENSING */ 3655 3656 typedef struct efx_key_stats_s { 3657 uint32_t eks_valid; 3658 uint32_t eks_invalid; 3659 uint32_t eks_blacklisted; 3660 uint32_t eks_unverifiable; 3661 uint32_t eks_wrong_node; 3662 uint32_t eks_licensed_apps_lo; 3663 uint32_t eks_licensed_apps_hi; 3664 uint32_t eks_licensed_features_lo; 3665 uint32_t eks_licensed_features_hi; 3666 } efx_key_stats_t; 3667 3668 LIBEFX_API 3669 extern __checkReturn efx_rc_t 3670 efx_lic_init( 3671 __in efx_nic_t *enp); 3672 3673 LIBEFX_API 3674 extern void 3675 efx_lic_fini( 3676 __in efx_nic_t *enp); 3677 3678 LIBEFX_API 3679 extern __checkReturn boolean_t 3680 efx_lic_check_support( 3681 __in efx_nic_t *enp); 3682 3683 LIBEFX_API 3684 extern __checkReturn efx_rc_t 3685 efx_lic_update_licenses( 3686 __in efx_nic_t *enp); 3687 3688 LIBEFX_API 3689 extern __checkReturn efx_rc_t 3690 efx_lic_get_key_stats( 3691 __in efx_nic_t *enp, 3692 __out efx_key_stats_t *ksp); 3693 3694 LIBEFX_API 3695 extern __checkReturn efx_rc_t 3696 efx_lic_app_state( 3697 __in efx_nic_t *enp, 3698 __in uint64_t app_id, 3699 __out boolean_t *licensedp); 3700 3701 LIBEFX_API 3702 extern __checkReturn efx_rc_t 3703 efx_lic_get_id( 3704 __in efx_nic_t *enp, 3705 __in size_t buffer_size, 3706 __out uint32_t *typep, 3707 __out size_t *lengthp, 3708 __out_opt uint8_t *bufferp); 3709 3710 3711 LIBEFX_API 3712 extern __checkReturn efx_rc_t 3713 efx_lic_find_start( 3714 __in efx_nic_t *enp, 3715 __in_bcount(buffer_size) 3716 caddr_t bufferp, 3717 __in size_t buffer_size, 3718 __out uint32_t *startp); 3719 3720 LIBEFX_API 3721 extern __checkReturn efx_rc_t 3722 efx_lic_find_end( 3723 __in efx_nic_t *enp, 3724 __in_bcount(buffer_size) 3725 caddr_t bufferp, 3726 __in size_t buffer_size, 3727 __in uint32_t offset, 3728 __out uint32_t *endp); 3729 3730 LIBEFX_API 3731 extern __checkReturn __success(return != B_FALSE) boolean_t 3732 efx_lic_find_key( 3733 __in efx_nic_t *enp, 3734 __in_bcount(buffer_size) 3735 caddr_t bufferp, 3736 __in size_t buffer_size, 3737 __in uint32_t offset, 3738 __out uint32_t *startp, 3739 __out uint32_t *lengthp); 3740 3741 LIBEFX_API 3742 extern __checkReturn __success(return != B_FALSE) boolean_t 3743 efx_lic_validate_key( 3744 __in efx_nic_t *enp, 3745 __in_bcount(length) caddr_t keyp, 3746 __in uint32_t length); 3747 3748 LIBEFX_API 3749 extern __checkReturn efx_rc_t 3750 efx_lic_read_key( 3751 __in efx_nic_t *enp, 3752 __in_bcount(buffer_size) 3753 caddr_t bufferp, 3754 __in size_t buffer_size, 3755 __in uint32_t offset, 3756 __in uint32_t length, 3757 __out_bcount_part(key_max_size, *lengthp) 3758 caddr_t keyp, 3759 __in size_t key_max_size, 3760 __out uint32_t *lengthp); 3761 3762 LIBEFX_API 3763 extern __checkReturn efx_rc_t 3764 efx_lic_write_key( 3765 __in efx_nic_t *enp, 3766 __in_bcount(buffer_size) 3767 caddr_t bufferp, 3768 __in size_t buffer_size, 3769 __in uint32_t offset, 3770 __in_bcount(length) caddr_t keyp, 3771 __in uint32_t length, 3772 __out uint32_t *lengthp); 3773 3774 LIBEFX_API 3775 extern __checkReturn efx_rc_t 3776 efx_lic_delete_key( 3777 __in efx_nic_t *enp, 3778 __in_bcount(buffer_size) 3779 caddr_t bufferp, 3780 __in size_t buffer_size, 3781 __in uint32_t offset, 3782 __in uint32_t length, 3783 __in uint32_t end, 3784 __out uint32_t *deltap); 3785 3786 LIBEFX_API 3787 extern __checkReturn efx_rc_t 3788 efx_lic_create_partition( 3789 __in efx_nic_t *enp, 3790 __in_bcount(buffer_size) 3791 caddr_t bufferp, 3792 __in size_t buffer_size); 3793 3794 extern __checkReturn efx_rc_t 3795 efx_lic_finish_partition( 3796 __in efx_nic_t *enp, 3797 __in_bcount(buffer_size) 3798 caddr_t bufferp, 3799 __in size_t buffer_size); 3800 3801 #endif /* EFSYS_OPT_LICENSING */ 3802 3803 /* TUNNEL */ 3804 3805 #if EFSYS_OPT_TUNNEL 3806 3807 LIBEFX_API 3808 extern __checkReturn efx_rc_t 3809 efx_tunnel_init( 3810 __in efx_nic_t *enp); 3811 3812 LIBEFX_API 3813 extern void 3814 efx_tunnel_fini( 3815 __in efx_nic_t *enp); 3816 3817 /* 3818 * For overlay network encapsulation using UDP, the firmware needs to know 3819 * the configured UDP port for the overlay so it can decode encapsulated 3820 * frames correctly. 3821 * The UDP port/protocol list is global. 3822 */ 3823 3824 LIBEFX_API 3825 extern __checkReturn efx_rc_t 3826 efx_tunnel_config_udp_add( 3827 __in efx_nic_t *enp, 3828 __in uint16_t port /* host/cpu-endian */, 3829 __in efx_tunnel_protocol_t protocol); 3830 3831 /* 3832 * Returns EBUSY if reconfiguration of the port is in progress in other thread. 3833 */ 3834 LIBEFX_API 3835 extern __checkReturn efx_rc_t 3836 efx_tunnel_config_udp_remove( 3837 __in efx_nic_t *enp, 3838 __in uint16_t port /* host/cpu-endian */, 3839 __in efx_tunnel_protocol_t protocol); 3840 3841 /* 3842 * Returns EBUSY if reconfiguration of any of the tunnel entries 3843 * is in progress in other thread. 3844 */ 3845 LIBEFX_API 3846 extern __checkReturn efx_rc_t 3847 efx_tunnel_config_clear( 3848 __in efx_nic_t *enp); 3849 3850 /** 3851 * Apply tunnel UDP ports configuration to hardware. 3852 * 3853 * EAGAIN is returned if hardware will be reset (datapath and managment CPU 3854 * reboot). 3855 */ 3856 LIBEFX_API 3857 extern __checkReturn efx_rc_t 3858 efx_tunnel_reconfigure( 3859 __in efx_nic_t *enp); 3860 3861 #endif /* EFSYS_OPT_TUNNEL */ 3862 3863 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3864 3865 /** 3866 * Firmware subvariant choice options. 3867 * 3868 * It may be switched to no Tx checksum if attached drivers are either 3869 * preboot or firmware subvariant aware and no VIS are allocated. 3870 * If may be always switched to default explicitly using set request or 3871 * implicitly if unaware driver is attaching. If switching is done when 3872 * a driver is attached, it gets MC_REBOOT event and should recreate its 3873 * datapath. 3874 * 3875 * See SF-119419-TC DPDK Firmware Driver Interface and 3876 * SF-109306-TC EF10 for Driver Writers for details. 3877 */ 3878 typedef enum efx_nic_fw_subvariant_e { 3879 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3880 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3881 EFX_NIC_FW_SUBVARIANT_NTYPES 3882 } efx_nic_fw_subvariant_t; 3883 3884 LIBEFX_API 3885 extern __checkReturn efx_rc_t 3886 efx_nic_get_fw_subvariant( 3887 __in efx_nic_t *enp, 3888 __out efx_nic_fw_subvariant_t *subvariantp); 3889 3890 LIBEFX_API 3891 extern __checkReturn efx_rc_t 3892 efx_nic_set_fw_subvariant( 3893 __in efx_nic_t *enp, 3894 __in efx_nic_fw_subvariant_t subvariant); 3895 3896 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3897 3898 typedef enum efx_phy_fec_type_e { 3899 EFX_PHY_FEC_NONE = 0, 3900 EFX_PHY_FEC_BASER, 3901 EFX_PHY_FEC_RS 3902 } efx_phy_fec_type_t; 3903 3904 LIBEFX_API 3905 extern __checkReturn efx_rc_t 3906 efx_phy_fec_type_get( 3907 __in efx_nic_t *enp, 3908 __out efx_phy_fec_type_t *typep); 3909 3910 typedef struct efx_phy_link_state_s { 3911 uint32_t epls_adv_cap_mask; 3912 uint32_t epls_lp_cap_mask; 3913 uint32_t epls_ld_cap_mask; 3914 unsigned int epls_fcntl; 3915 efx_phy_fec_type_t epls_fec; 3916 efx_link_mode_t epls_link_mode; 3917 } efx_phy_link_state_t; 3918 3919 LIBEFX_API 3920 extern __checkReturn efx_rc_t 3921 efx_phy_link_state_get( 3922 __in efx_nic_t *enp, 3923 __out efx_phy_link_state_t *eplsp); 3924 3925 3926 #if EFSYS_OPT_EVB 3927 3928 typedef uint32_t efx_vswitch_id_t; 3929 typedef uint32_t efx_vport_id_t; 3930 3931 typedef enum efx_vswitch_type_e { 3932 EFX_VSWITCH_TYPE_VLAN = 1, 3933 EFX_VSWITCH_TYPE_VEB, 3934 /* VSWITCH_TYPE_VEPA: obsolete */ 3935 EFX_VSWITCH_TYPE_MUX = 4, 3936 } efx_vswitch_type_t; 3937 3938 typedef enum efx_vport_type_e { 3939 EFX_VPORT_TYPE_NORMAL = 4, 3940 EFX_VPORT_TYPE_EXPANSION, 3941 EFX_VPORT_TYPE_TEST, 3942 } efx_vport_type_t; 3943 3944 /* Unspecified VLAN ID to support disabling of VLAN filtering */ 3945 #define EFX_FILTER_VID_UNSPEC 0xffff 3946 #define EFX_DEFAULT_VSWITCH_ID 1 3947 3948 /* Default VF VLAN ID on creation */ 3949 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC 3950 #define EFX_VPORT_ID_INVALID 0 3951 3952 typedef struct efx_vport_config_s { 3953 /* Either VF index or EFX_PCI_VF_INVALID for PF */ 3954 uint16_t evc_function; 3955 /* VLAN ID of the associated function */ 3956 uint16_t evc_vid; 3957 /* vport id shared with client driver */ 3958 efx_vport_id_t evc_vport_id; 3959 /* MAC address of the associated function */ 3960 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; 3961 /* 3962 * vports created with this flag set may only transfer traffic on the 3963 * VLANs permitted by the vport. Also, an attempt to install filter with 3964 * VLAN will be refused unless requesting function has VLAN privilege. 3965 */ 3966 boolean_t evc_vlan_restrict; 3967 /* Whether this function is assigned or not */ 3968 boolean_t evc_vport_assigned; 3969 } efx_vport_config_t; 3970 3971 typedef struct efx_vswitch_s efx_vswitch_t; 3972 3973 LIBEFX_API 3974 extern __checkReturn efx_rc_t 3975 efx_evb_init( 3976 __in efx_nic_t *enp); 3977 3978 LIBEFX_API 3979 extern void 3980 efx_evb_fini( 3981 __in efx_nic_t *enp); 3982 3983 LIBEFX_API 3984 extern __checkReturn efx_rc_t 3985 efx_evb_vswitch_create( 3986 __in efx_nic_t *enp, 3987 __in uint32_t num_vports, 3988 __inout_ecount(num_vports) efx_vport_config_t *vport_configp, 3989 __deref_out efx_vswitch_t **evpp); 3990 3991 LIBEFX_API 3992 extern __checkReturn efx_rc_t 3993 efx_evb_vswitch_destroy( 3994 __in efx_nic_t *enp, 3995 __in efx_vswitch_t *evp); 3996 3997 LIBEFX_API 3998 extern __checkReturn efx_rc_t 3999 efx_evb_vport_mac_set( 4000 __in efx_nic_t *enp, 4001 __in efx_vswitch_t *evp, 4002 __in efx_vport_id_t vport_id, 4003 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); 4004 4005 LIBEFX_API 4006 extern __checkReturn efx_rc_t 4007 efx_evb_vport_vlan_set( 4008 __in efx_nic_t *enp, 4009 __in efx_vswitch_t *evp, 4010 __in efx_vport_id_t vport_id, 4011 __in uint16_t vid); 4012 4013 LIBEFX_API 4014 extern __checkReturn efx_rc_t 4015 efx_evb_vport_reset( 4016 __in efx_nic_t *enp, 4017 __in efx_vswitch_t *evp, 4018 __in efx_vport_id_t vport_id, 4019 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, 4020 __in uint16_t vid, 4021 __out boolean_t *is_fn_resetp); 4022 4023 LIBEFX_API 4024 extern __checkReturn efx_rc_t 4025 efx_evb_vport_stats( 4026 __in efx_nic_t *enp, 4027 __in efx_vswitch_t *evp, 4028 __in efx_vport_id_t vport_id, 4029 __out efsys_mem_t *stats_bufferp); 4030 4031 #endif /* EFSYS_OPT_EVB */ 4032 4033 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 4034 4035 typedef struct efx_proxy_auth_config_s { 4036 efsys_mem_t *request_bufferp; 4037 efsys_mem_t *response_bufferp; 4038 efsys_mem_t *status_bufferp; 4039 uint32_t block_cnt; 4040 uint32_t *op_listp; 4041 size_t op_count; 4042 uint32_t handled_privileges; 4043 } efx_proxy_auth_config_t; 4044 4045 typedef struct efx_proxy_cmd_params_s { 4046 uint32_t pf_index; 4047 uint32_t vf_index; 4048 uint8_t *request_bufferp; 4049 size_t request_size; 4050 uint8_t *response_bufferp; 4051 size_t response_size; 4052 size_t *response_size_actualp; 4053 } efx_proxy_cmd_params_t; 4054 4055 LIBEFX_API 4056 extern __checkReturn efx_rc_t 4057 efx_proxy_auth_init( 4058 __in efx_nic_t *enp); 4059 4060 LIBEFX_API 4061 extern void 4062 efx_proxy_auth_fini( 4063 __in efx_nic_t *enp); 4064 4065 LIBEFX_API 4066 extern __checkReturn efx_rc_t 4067 efx_proxy_auth_configure( 4068 __in efx_nic_t *enp, 4069 __in efx_proxy_auth_config_t *configp); 4070 4071 LIBEFX_API 4072 extern __checkReturn efx_rc_t 4073 efx_proxy_auth_destroy( 4074 __in efx_nic_t *enp, 4075 __in uint32_t handled_privileges); 4076 4077 LIBEFX_API 4078 extern __checkReturn efx_rc_t 4079 efx_proxy_auth_complete_request( 4080 __in efx_nic_t *enp, 4081 __in uint32_t fn_index, 4082 __in uint32_t proxy_result, 4083 __in uint32_t handle); 4084 4085 LIBEFX_API 4086 extern __checkReturn efx_rc_t 4087 efx_proxy_auth_exec_cmd( 4088 __in efx_nic_t *enp, 4089 __inout efx_proxy_cmd_params_t *paramsp); 4090 4091 LIBEFX_API 4092 extern __checkReturn efx_rc_t 4093 efx_proxy_auth_set_privilege_mask( 4094 __in efx_nic_t *enp, 4095 __in uint32_t vf_index, 4096 __in uint32_t mask, 4097 __in uint32_t value); 4098 4099 LIBEFX_API 4100 extern __checkReturn efx_rc_t 4101 efx_proxy_auth_privilege_mask_get( 4102 __in efx_nic_t *enp, 4103 __in uint32_t pf_index, 4104 __in uint32_t vf_index, 4105 __out uint32_t *maskp); 4106 4107 LIBEFX_API 4108 extern __checkReturn efx_rc_t 4109 efx_proxy_auth_privilege_modify( 4110 __in efx_nic_t *enp, 4111 __in uint32_t pf_index, 4112 __in uint32_t vf_index, 4113 __in uint32_t add_privileges_mask, 4114 __in uint32_t remove_privileges_mask); 4115 4116 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 4117 4118 #if EFSYS_OPT_MAE 4119 4120 LIBEFX_API 4121 extern __checkReturn efx_rc_t 4122 efx_mae_init( 4123 __in efx_nic_t *enp); 4124 4125 LIBEFX_API 4126 extern void 4127 efx_mae_fini( 4128 __in efx_nic_t *enp); 4129 4130 typedef struct efx_mae_limits_s { 4131 uint32_t eml_max_n_action_prios; 4132 uint32_t eml_max_n_outer_prios; 4133 uint32_t eml_encap_types_supported; 4134 uint32_t eml_encap_header_size_limit; 4135 uint32_t eml_max_n_counters; 4136 } efx_mae_limits_t; 4137 4138 LIBEFX_API 4139 extern __checkReturn efx_rc_t 4140 efx_mae_get_limits( 4141 __in efx_nic_t *enp, 4142 __out efx_mae_limits_t *emlp); 4143 4144 typedef enum efx_mae_rule_type_e { 4145 EFX_MAE_RULE_ACTION = 0, 4146 EFX_MAE_RULE_OUTER, 4147 4148 EFX_MAE_RULE_NTYPES 4149 } efx_mae_rule_type_t; 4150 4151 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t; 4152 4153 LIBEFX_API 4154 extern __checkReturn efx_rc_t 4155 efx_mae_match_spec_init( 4156 __in efx_nic_t *enp, 4157 __in efx_mae_rule_type_t type, 4158 __in uint32_t prio, 4159 __out efx_mae_match_spec_t **specp); 4160 4161 LIBEFX_API 4162 extern void 4163 efx_mae_match_spec_fini( 4164 __in efx_nic_t *enp, 4165 __in efx_mae_match_spec_t *spec); 4166 4167 typedef enum efx_mae_field_id_e { 4168 /* 4169 * Fields which can be set by efx_mae_match_spec_field_set() 4170 * or by using dedicated field-specific helper APIs. 4171 */ 4172 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0, 4173 EFX_MAE_FIELD_ETHER_TYPE_BE, 4174 EFX_MAE_FIELD_ETH_SADDR_BE, 4175 EFX_MAE_FIELD_ETH_DADDR_BE, 4176 EFX_MAE_FIELD_VLAN0_TCI_BE, 4177 EFX_MAE_FIELD_VLAN0_PROTO_BE, 4178 EFX_MAE_FIELD_VLAN1_TCI_BE, 4179 EFX_MAE_FIELD_VLAN1_PROTO_BE, 4180 EFX_MAE_FIELD_SRC_IP4_BE, 4181 EFX_MAE_FIELD_DST_IP4_BE, 4182 EFX_MAE_FIELD_IP_PROTO, 4183 EFX_MAE_FIELD_IP_TOS, 4184 EFX_MAE_FIELD_IP_TTL, 4185 EFX_MAE_FIELD_SRC_IP6_BE, 4186 EFX_MAE_FIELD_DST_IP6_BE, 4187 EFX_MAE_FIELD_L4_SPORT_BE, 4188 EFX_MAE_FIELD_L4_DPORT_BE, 4189 EFX_MAE_FIELD_TCP_FLAGS_BE, 4190 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE, 4191 EFX_MAE_FIELD_ENC_ETH_SADDR_BE, 4192 EFX_MAE_FIELD_ENC_ETH_DADDR_BE, 4193 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE, 4194 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE, 4195 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE, 4196 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE, 4197 EFX_MAE_FIELD_ENC_SRC_IP4_BE, 4198 EFX_MAE_FIELD_ENC_DST_IP4_BE, 4199 EFX_MAE_FIELD_ENC_IP_PROTO, 4200 EFX_MAE_FIELD_ENC_IP_TOS, 4201 EFX_MAE_FIELD_ENC_IP_TTL, 4202 EFX_MAE_FIELD_ENC_SRC_IP6_BE, 4203 EFX_MAE_FIELD_ENC_DST_IP6_BE, 4204 EFX_MAE_FIELD_ENC_L4_SPORT_BE, 4205 EFX_MAE_FIELD_ENC_L4_DPORT_BE, 4206 EFX_MAE_FIELD_ENC_VNET_ID_BE, 4207 EFX_MAE_FIELD_OUTER_RULE_ID, 4208 4209 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */ 4210 EFX_MAE_FIELD_HAS_OVLAN, 4211 EFX_MAE_FIELD_HAS_IVLAN, 4212 EFX_MAE_FIELD_ENC_HAS_OVLAN, 4213 EFX_MAE_FIELD_ENC_HAS_IVLAN, 4214 4215 /* 4216 * Fields which can be set by efx_mae_match_spec_field_set() 4217 * or by using dedicated field-specific helper APIs. 4218 */ 4219 EFX_MAE_FIELD_RECIRC_ID, 4220 EFX_MAE_FIELD_NIDS 4221 } efx_mae_field_id_t; 4222 4223 /* MPORT selector. Used to refer to MPORTs in match/action rules. */ 4224 typedef struct efx_mport_sel_s { 4225 uint32_t sel; 4226 } efx_mport_sel_t; 4227 4228 /* 4229 * MPORT ID. Used to refer dynamically to a specific MPORT. 4230 * The difference between MPORT selector and MPORT ID is that 4231 * selector can specify an exact MPORT ID or it can specify a 4232 * pattern by which an exact MPORT ID can be selected. For example, 4233 * static MPORT selector can specify MPORT of a current PF, which 4234 * will be translated to the dynamic MPORT ID based on which PF is 4235 * using that MPORT selector. 4236 */ 4237 typedef struct efx_mport_id_s { 4238 uint32_t id; 4239 } efx_mport_id_t; 4240 4241 typedef enum efx_mport_type_e { 4242 EFX_MPORT_TYPE_NET_PORT = 0, 4243 EFX_MPORT_TYPE_ALIAS, 4244 EFX_MPORT_TYPE_VNIC, 4245 } efx_mport_type_t; 4246 4247 typedef enum efx_mport_vnic_client_type_e { 4248 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1, 4249 EFX_MPORT_VNIC_CLIENT_PLUGIN, 4250 } efx_mport_vnic_client_type_t; 4251 4252 typedef struct efx_mport_desc_s { 4253 efx_mport_id_t emd_id; 4254 boolean_t emd_can_receive_on; 4255 boolean_t emd_can_deliver_to; 4256 boolean_t emd_can_delete; 4257 boolean_t emd_zombie; 4258 efx_mport_type_t emd_type; 4259 union { 4260 struct { 4261 uint32_t ep_index; 4262 } emd_net_port; 4263 struct { 4264 efx_mport_id_t ea_target_mport_id; 4265 } emd_alias; 4266 struct { 4267 efx_mport_vnic_client_type_t ev_client_type; 4268 efx_pcie_interface_t ev_intf; 4269 uint16_t ev_pf; 4270 uint16_t ev_vf; 4271 /* MCDI client handle for this VNIC. */ 4272 uint32_t ev_handle; 4273 } emd_vnic; 4274 }; 4275 } efx_mport_desc_t; 4276 4277 #define EFX_MPORT_NULL (0U) 4278 4279 /* 4280 * Generate an invalid MPORT selector. 4281 * 4282 * The resulting MPORT selector is opaque to the caller. Requests 4283 * that attempt to use it will be rejected. 4284 */ 4285 LIBEFX_API 4286 extern __checkReturn efx_rc_t 4287 efx_mae_mport_invalid( 4288 __out efx_mport_sel_t *mportp); 4289 4290 /* 4291 * Get MPORT selector of a physical port. 4292 * 4293 * The resulting MPORT selector is opaque to the caller and can be 4294 * passed as an argument to efx_mae_match_spec_mport_set() 4295 * and efx_mae_action_set_populate_deliver(). 4296 */ 4297 LIBEFX_API 4298 extern __checkReturn efx_rc_t 4299 efx_mae_mport_by_phy_port( 4300 __in uint32_t phy_port, 4301 __out efx_mport_sel_t *mportp); 4302 4303 /* 4304 * Get MPORT selector of a PCIe function. 4305 * 4306 * The resulting MPORT selector is opaque to the caller and can be 4307 * passed as an argument to efx_mae_match_spec_mport_set() 4308 * and efx_mae_action_set_populate_deliver(). 4309 */ 4310 LIBEFX_API 4311 extern __checkReturn efx_rc_t 4312 efx_mae_mport_by_pcie_function( 4313 __in uint32_t pf, 4314 __in uint32_t vf, 4315 __out efx_mport_sel_t *mportp); 4316 4317 /* 4318 * Get MPORT selector of a multi-host PCIe function. 4319 * 4320 * The resulting MPORT selector is opaque to the caller and can be 4321 * passed as an argument to efx_mae_match_spec_mport_set() 4322 * and efx_mae_action_set_populate_deliver(). 4323 */ 4324 LIBEFX_API 4325 extern __checkReturn efx_rc_t 4326 efx_mae_mport_by_pcie_mh_function( 4327 __in efx_pcie_interface_t intf, 4328 __in uint32_t pf, 4329 __in uint32_t vf, 4330 __out efx_mport_sel_t *mportp); 4331 4332 /* 4333 * Get MPORT selector by an MPORT ID 4334 * 4335 * The resulting MPORT selector is opaque to the caller and can be 4336 * passed as an argument to efx_mae_match_spec_mport_set() 4337 * and efx_mae_action_set_populate_deliver(). 4338 */ 4339 LIBEFX_API 4340 extern __checkReturn efx_rc_t 4341 efx_mae_mport_by_id( 4342 __in const efx_mport_id_t *mport_idp, 4343 __out efx_mport_sel_t *mportp); 4344 4345 /* Get MPORT ID by an MPORT selector */ 4346 LIBEFX_API 4347 extern __checkReturn efx_rc_t 4348 efx_mae_mport_id_by_selector( 4349 __in efx_nic_t *enp, 4350 __in const efx_mport_sel_t *mport_selectorp, 4351 __out efx_mport_id_t *mport_idp); 4352 4353 /* 4354 * Fields which have BE postfix in their named constants are expected 4355 * to be passed by callers in big-endian byte order. They will appear 4356 * in the MCDI buffer, which is a part of the match specification, in 4357 * the very same byte order, that is, no conversion will be performed. 4358 * 4359 * Fields which don't have BE postfix in their named constants are in 4360 * host byte order. MCDI expects them to be little-endian, so the API 4361 * will take care to carry out conversion to little-endian byte order. 4362 * At the moment, the only field in host byte order is MPORT selector. 4363 */ 4364 LIBEFX_API 4365 extern __checkReturn efx_rc_t 4366 efx_mae_match_spec_field_set( 4367 __in efx_mae_match_spec_t *spec, 4368 __in efx_mae_field_id_t field_id, 4369 __in size_t value_size, 4370 __in_bcount(value_size) const uint8_t *value, 4371 __in size_t mask_size, 4372 __in_bcount(mask_size) const uint8_t *mask); 4373 4374 /* The corresponding mask will be set to B_TRUE. */ 4375 LIBEFX_API 4376 extern __checkReturn efx_rc_t 4377 efx_mae_match_spec_bit_set( 4378 __in efx_mae_match_spec_t *spec, 4379 __in efx_mae_field_id_t field_id, 4380 __in boolean_t value); 4381 4382 /* If the mask argument is NULL, the API will use full mask by default. */ 4383 LIBEFX_API 4384 extern __checkReturn efx_rc_t 4385 efx_mae_match_spec_mport_set( 4386 __in efx_mae_match_spec_t *spec, 4387 __in const efx_mport_sel_t *valuep, 4388 __in_opt const efx_mport_sel_t *maskp); 4389 4390 LIBEFX_API 4391 extern __checkReturn efx_rc_t 4392 efx_mae_match_spec_recirc_id_set( 4393 __in efx_mae_match_spec_t *spec, 4394 __in uint8_t recirc_id); 4395 4396 LIBEFX_API 4397 extern __checkReturn boolean_t 4398 efx_mae_match_specs_equal( 4399 __in const efx_mae_match_spec_t *left, 4400 __in const efx_mae_match_spec_t *right); 4401 4402 /* 4403 * Make sure that match fields known by EFX have proper masks set 4404 * in the match specification as per requirements of SF-122526-TC. 4405 * 4406 * In the case efx_mae_field_id_t lacks named identifiers for any 4407 * fields which the FW maintains with support status MATCH_ALWAYS, 4408 * the validation result may not be accurate. 4409 */ 4410 LIBEFX_API 4411 extern __checkReturn boolean_t 4412 efx_mae_match_spec_is_valid( 4413 __in efx_nic_t *enp, 4414 __in const efx_mae_match_spec_t *spec); 4415 4416 typedef struct efx_mae_actions_s efx_mae_actions_t; 4417 4418 LIBEFX_API 4419 extern __checkReturn efx_rc_t 4420 efx_mae_action_set_spec_init( 4421 __in efx_nic_t *enp, 4422 __out efx_mae_actions_t **specp); 4423 4424 LIBEFX_API 4425 extern void 4426 efx_mae_action_set_spec_fini( 4427 __in efx_nic_t *enp, 4428 __in efx_mae_actions_t *spec); 4429 4430 LIBEFX_API 4431 extern __checkReturn efx_rc_t 4432 efx_mae_action_set_populate_decap( 4433 __in efx_mae_actions_t *spec); 4434 4435 LIBEFX_API 4436 extern __checkReturn efx_rc_t 4437 efx_mae_action_set_populate_vlan_pop( 4438 __in efx_mae_actions_t *spec); 4439 4440 /* 4441 * This always amends the outermost header. This way, for a tunnel 4442 * packet, if action DECAP is not requested, this will affect the 4443 * outer header; otherwise, the inner header will be updated. 4444 * 4445 * This will also take care to update IPv4 checksum accordingly. 4446 */ 4447 LIBEFX_API 4448 extern __checkReturn efx_rc_t 4449 efx_mae_action_set_populate_decr_ip_ttl( 4450 __in efx_mae_actions_t *spec); 4451 4452 LIBEFX_API 4453 extern __checkReturn efx_rc_t 4454 efx_mae_action_set_populate_vlan_push( 4455 __in efx_mae_actions_t *spec, 4456 __in uint16_t tpid_be, 4457 __in uint16_t tci_be); 4458 4459 /* 4460 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated 4461 * encap. header in the specification prior to action set allocation. 4462 */ 4463 LIBEFX_API 4464 extern __checkReturn efx_rc_t 4465 efx_mae_action_set_populate_encap( 4466 __in efx_mae_actions_t *spec); 4467 4468 /* 4469 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter 4470 * in the specification prior to action set allocation. 4471 * 4472 * NOTICE: the HW will conduct action COUNT after actions DECAP, 4473 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet, 4474 * but, as a workaround, this order is not validated by the API. 4475 * 4476 * The workaround helps to unblock DPDK + Open vSwitch use case. 4477 * In Open vSwitch, this action is always the first to be added, 4478 * in particular, it's known to be inserted before action DECAP, 4479 * so enforcing the right order here would cause runtime errors. 4480 * The existing behaviour in Open vSwitch is unlikely to change 4481 * any time soon, and the workaround is a good solution because 4482 * in fact the real COUNT order is a don't care to Open vSwitch. 4483 */ 4484 LIBEFX_API 4485 extern __checkReturn efx_rc_t 4486 efx_mae_action_set_populate_count( 4487 __in efx_mae_actions_t *spec); 4488 4489 LIBEFX_API 4490 extern __checkReturn efx_rc_t 4491 efx_mae_action_set_populate_flag( 4492 __in efx_mae_actions_t *spec); 4493 4494 LIBEFX_API 4495 extern __checkReturn efx_rc_t 4496 efx_mae_action_set_populate_mark( 4497 __in efx_mae_actions_t *spec, 4498 __in uint32_t mark_value); 4499 4500 LIBEFX_API 4501 extern __checkReturn efx_rc_t 4502 efx_mae_action_set_populate_deliver( 4503 __in efx_mae_actions_t *spec, 4504 __in const efx_mport_sel_t *mportp); 4505 4506 LIBEFX_API 4507 extern __checkReturn efx_rc_t 4508 efx_mae_action_set_populate_drop( 4509 __in efx_mae_actions_t *spec); 4510 4511 LIBEFX_API 4512 extern __checkReturn boolean_t 4513 efx_mae_action_set_specs_equal( 4514 __in const efx_mae_actions_t *left, 4515 __in const efx_mae_actions_t *right); 4516 4517 /* 4518 * Conduct a comparison to check whether two match specifications 4519 * of equal rule type (action / outer) and priority would map to 4520 * the very same rule class from the firmware's standpoint. 4521 * 4522 * For match specification fields that are not supported by firmware, 4523 * the rule class only matches if the mask/value pairs for that field 4524 * are equal. Clients should use efx_mae_match_spec_is_valid() before 4525 * calling this API to detect usage of unsupported fields. 4526 */ 4527 LIBEFX_API 4528 extern __checkReturn efx_rc_t 4529 efx_mae_match_specs_class_cmp( 4530 __in efx_nic_t *enp, 4531 __in const efx_mae_match_spec_t *left, 4532 __in const efx_mae_match_spec_t *right, 4533 __out boolean_t *have_same_classp); 4534 4535 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX 4536 4537 /* Rule ID */ 4538 typedef struct efx_mae_rule_id_s { 4539 uint32_t id; 4540 } efx_mae_rule_id_t; 4541 4542 /* 4543 * Set the initial recirculation ID. It goes to action rule (AR) lookup. 4544 * 4545 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set(). 4546 */ 4547 LIBEFX_API 4548 extern __checkReturn efx_rc_t 4549 efx_mae_outer_rule_recirc_id_set( 4550 __in efx_mae_match_spec_t *spec, 4551 __in uint8_t recirc_id); 4552 4553 LIBEFX_API 4554 extern __checkReturn efx_rc_t 4555 efx_mae_outer_rule_insert( 4556 __in efx_nic_t *enp, 4557 __in const efx_mae_match_spec_t *spec, 4558 __in efx_tunnel_protocol_t encap_type, 4559 __out efx_mae_rule_id_t *or_idp); 4560 4561 LIBEFX_API 4562 extern __checkReturn efx_rc_t 4563 efx_mae_outer_rule_remove( 4564 __in efx_nic_t *enp, 4565 __in const efx_mae_rule_id_t *or_idp); 4566 4567 LIBEFX_API 4568 extern __checkReturn efx_rc_t 4569 efx_mae_match_spec_outer_rule_id_set( 4570 __in efx_mae_match_spec_t *spec, 4571 __in const efx_mae_rule_id_t *or_idp); 4572 4573 /* Encap. header ID */ 4574 typedef struct efx_mae_eh_id_s { 4575 uint32_t id; 4576 } efx_mae_eh_id_t; 4577 4578 LIBEFX_API 4579 extern __checkReturn efx_rc_t 4580 efx_mae_encap_header_alloc( 4581 __in efx_nic_t *enp, 4582 __in efx_tunnel_protocol_t encap_type, 4583 __in_bcount(header_size) uint8_t *header_data, 4584 __in size_t header_size, 4585 __out efx_mae_eh_id_t *eh_idp); 4586 4587 LIBEFX_API 4588 extern __checkReturn efx_rc_t 4589 efx_mae_encap_header_free( 4590 __in efx_nic_t *enp, 4591 __in const efx_mae_eh_id_t *eh_idp); 4592 4593 /* See description before efx_mae_action_set_populate_encap(). */ 4594 LIBEFX_API 4595 extern __checkReturn efx_rc_t 4596 efx_mae_action_set_fill_in_eh_id( 4597 __in efx_mae_actions_t *spec, 4598 __in const efx_mae_eh_id_t *eh_idp); 4599 4600 typedef struct efx_counter_s { 4601 uint32_t id; 4602 } efx_counter_t; 4603 4604 LIBEFX_API 4605 extern __checkReturn unsigned int 4606 efx_mae_action_set_get_nb_count( 4607 __in const efx_mae_actions_t *spec); 4608 4609 /* See description before efx_mae_action_set_populate_count(). */ 4610 LIBEFX_API 4611 extern __checkReturn efx_rc_t 4612 efx_mae_action_set_fill_in_counter_id( 4613 __in efx_mae_actions_t *spec, 4614 __in const efx_counter_t *counter_idp); 4615 4616 /* Action set ID */ 4617 typedef struct efx_mae_aset_id_s { 4618 uint32_t id; 4619 } efx_mae_aset_id_t; 4620 4621 LIBEFX_API 4622 extern __checkReturn efx_rc_t 4623 efx_mae_action_set_alloc( 4624 __in efx_nic_t *enp, 4625 __in const efx_mae_actions_t *spec, 4626 __out efx_mae_aset_id_t *aset_idp); 4627 4628 /* 4629 * Generation count has two purposes: 4630 * 4631 * 1) Distinguish between counter packets that belong to freed counter 4632 * and the packets that belong to reallocated counter (with the same ID); 4633 * 2) Make sure that all packets are received for a counter that was freed; 4634 * 4635 * API users should provide generation count out parameter in allocation 4636 * function if counters can be reallocated and consistent counter values are 4637 * required. 4638 * 4639 * API users that need consistent final counter values after counter 4640 * deallocation or counter stream stop should provide the parameter in 4641 * functions that free the counters and stop the counter stream. 4642 */ 4643 LIBEFX_API 4644 extern __checkReturn efx_rc_t 4645 efx_mae_counters_alloc( 4646 __in efx_nic_t *enp, 4647 __in uint32_t n_counters, 4648 __out uint32_t *n_allocatedp, 4649 __out_ecount(n_counters) efx_counter_t *countersp, 4650 __out_opt uint32_t *gen_countp); 4651 4652 LIBEFX_API 4653 extern __checkReturn efx_rc_t 4654 efx_mae_counters_free( 4655 __in efx_nic_t *enp, 4656 __in uint32_t n_counters, 4657 __out uint32_t *n_freedp, 4658 __in_ecount(n_counters) const efx_counter_t *countersp, 4659 __out_opt uint32_t *gen_countp); 4660 4661 /* When set, include counters with a value of zero */ 4662 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0) 4663 4664 /* 4665 * Set if credit-based flow control is used. In this case the driver 4666 * must call efx_mae_counters_stream_give_credits() to notify the 4667 * packetiser of descriptors written. 4668 */ 4669 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0) 4670 4671 LIBEFX_API 4672 extern __checkReturn efx_rc_t 4673 efx_mae_counters_stream_start( 4674 __in efx_nic_t *enp, 4675 __in uint16_t rxq_id, 4676 __in uint16_t packet_size, 4677 __in uint32_t flags_in, 4678 __out uint32_t *flags_out); 4679 4680 LIBEFX_API 4681 extern __checkReturn efx_rc_t 4682 efx_mae_counters_stream_stop( 4683 __in efx_nic_t *enp, 4684 __in uint16_t rxq_id, 4685 __out_opt uint32_t *gen_countp); 4686 4687 LIBEFX_API 4688 extern __checkReturn efx_rc_t 4689 efx_mae_counters_stream_give_credits( 4690 __in efx_nic_t *enp, 4691 __in uint32_t n_credits); 4692 4693 LIBEFX_API 4694 extern __checkReturn efx_rc_t 4695 efx_mae_action_set_free( 4696 __in efx_nic_t *enp, 4697 __in const efx_mae_aset_id_t *aset_idp); 4698 4699 /* Action set list ID */ 4700 typedef struct efx_mae_aset_list_id_s { 4701 uint32_t id; 4702 } efx_mae_aset_list_id_t; 4703 4704 /* 4705 * Either action set list ID or action set ID must be passed to this API, 4706 * but not both. 4707 */ 4708 LIBEFX_API 4709 extern __checkReturn efx_rc_t 4710 efx_mae_action_rule_insert( 4711 __in efx_nic_t *enp, 4712 __in const efx_mae_match_spec_t *spec, 4713 __in const efx_mae_aset_list_id_t *asl_idp, 4714 __in const efx_mae_aset_id_t *as_idp, 4715 __out efx_mae_rule_id_t *ar_idp); 4716 4717 LIBEFX_API 4718 extern __checkReturn efx_rc_t 4719 efx_mae_action_rule_remove( 4720 __in efx_nic_t *enp, 4721 __in const efx_mae_rule_id_t *ar_idp); 4722 4723 LIBEFX_API 4724 extern __checkReturn efx_rc_t 4725 efx_mcdi_mport_alloc_alias( 4726 __in efx_nic_t *enp, 4727 __out efx_mport_id_t *mportp, 4728 __out_opt uint32_t *labelp); 4729 4730 LIBEFX_API 4731 extern __checkReturn efx_rc_t 4732 efx_mae_mport_free( 4733 __in efx_nic_t *enp, 4734 __in const efx_mport_id_t *mportp); 4735 4736 typedef __checkReturn efx_rc_t 4737 (efx_mae_read_mport_journal_cb)( 4738 __in void *cb_datap, 4739 __in efx_mport_desc_t *mportp, 4740 __in size_t mport_len); 4741 4742 /* 4743 * Read mport descriptions from the MAE journal (which describes added and 4744 * removed mports) and pass them to a user-supplied callback. The user gets 4745 * only one chance to process the data it's given. Once the callback function 4746 * finishes, that particular mport description will be gone. 4747 * The journal will be fully repopulated on PCI reset (efx_nic_reset function). 4748 */ 4749 LIBEFX_API 4750 extern __checkReturn efx_rc_t 4751 efx_mae_read_mport_journal( 4752 __in efx_nic_t *enp, 4753 __in efx_mae_read_mport_journal_cb *cbp, 4754 __in void *cb_datap); 4755 4756 #endif /* EFSYS_OPT_MAE */ 4757 4758 #if EFSYS_OPT_VIRTIO 4759 4760 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues 4761 * while virtio block device has a single virtqueue, 4762 * for further details refer section of 4.2.3 of SF-120734 4763 */ 4764 typedef enum efx_virtio_vq_type_e { 4765 EFX_VIRTIO_VQ_TYPE_NET_RXQ, 4766 EFX_VIRTIO_VQ_TYPE_NET_TXQ, 4767 EFX_VIRTIO_VQ_TYPE_BLOCK, 4768 EFX_VIRTIO_VQ_NTYPES 4769 } efx_virtio_vq_type_t; 4770 4771 typedef struct efx_virtio_vq_dyncfg_s { 4772 /* 4773 * If queue is being created to be migrated then this 4774 * should be the FINAL_PIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 4775 * of the queue being migrated from. Otherwise, it should be zero. 4776 */ 4777 uint32_t evvd_vq_pidx; 4778 /* 4779 * If this queue is being created to be migrated then this 4780 * should be the FINAL_CIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 4781 * of the queue being migrated from. Otherwise, it should be zero. 4782 */ 4783 uint32_t evvd_vq_cidx; 4784 } efx_virtio_vq_dyncfg_t; 4785 4786 /* 4787 * Virtqueue size must be a power of 2, maximum size is 32768 4788 * (see VIRTIO v1.1 section 2.6) 4789 */ 4790 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000 4791 4792 typedef struct efx_virtio_vq_cfg_s { 4793 unsigned int evvc_vq_num; 4794 efx_virtio_vq_type_t evvc_type; 4795 /* 4796 * vDPA as VF : It is target VF number if queue is being created on VF. 4797 * vDPA as PF : If queue to be created on PF then it should be 4798 * EFX_PCI_VF_INVALID. 4799 */ 4800 uint16_t evvc_target_vf; 4801 /* 4802 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and 4803 * virtqueue size 0 means the queue is unavailable. 4804 */ 4805 uint32_t evvc_vq_size; 4806 efsys_dma_addr_t evvc_desc_tbl_addr; 4807 efsys_dma_addr_t evvc_avail_ring_addr; 4808 efsys_dma_addr_t evvc_used_ring_addr; 4809 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */ 4810 uint16_t evvc_msix_vector; 4811 /* 4812 * evvc_pas_id contains a PCIe address space identifier if the queue 4813 * uses PASID. 4814 */ 4815 boolean_t evvc_use_pasid; 4816 uint32_t evvc_pas_id; 4817 /* Negotiated virtio features to be applied to this virtqueue */ 4818 uint64_t evcc_features; 4819 } efx_virtio_vq_cfg_t; 4820 4821 typedef struct efx_virtio_vq_s efx_virtio_vq_t; 4822 4823 typedef enum efx_virtio_device_type_e { 4824 EFX_VIRTIO_DEVICE_TYPE_RESERVED, 4825 EFX_VIRTIO_DEVICE_TYPE_NET, 4826 EFX_VIRTIO_DEVICE_TYPE_BLOCK, 4827 EFX_VIRTIO_DEVICE_NTYPES 4828 } efx_virtio_device_type_t; 4829 4830 LIBEFX_API 4831 extern __checkReturn efx_rc_t 4832 efx_virtio_init( 4833 __in efx_nic_t *enp); 4834 4835 LIBEFX_API 4836 extern void 4837 efx_virtio_fini( 4838 __in efx_nic_t *enp); 4839 4840 /* 4841 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit, 4842 * hypervisor starts configuring all the virtqueues in the device. When the 4843 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues, 4844 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would 4845 * be invoked from dev_conf callback to create the virtqueues, For further 4846 * details refer SF-122427. 4847 */ 4848 LIBEFX_API 4849 extern __checkReturn efx_rc_t 4850 efx_virtio_qcreate( 4851 __in efx_nic_t *enp, 4852 __deref_out efx_virtio_vq_t **evvpp); 4853 4854 LIBEFX_API 4855 extern __checkReturn efx_rc_t 4856 efx_virtio_qstart( 4857 __in efx_virtio_vq_t *evvp, 4858 __in efx_virtio_vq_cfg_t *evvcp, 4859 __in_opt efx_virtio_vq_dyncfg_t *evvdp); 4860 4861 LIBEFX_API 4862 extern __checkReturn efx_rc_t 4863 efx_virtio_qstop( 4864 __in efx_virtio_vq_t *evvp, 4865 __out_opt efx_virtio_vq_dyncfg_t *evvdp); 4866 4867 LIBEFX_API 4868 extern void 4869 efx_virtio_qdestroy( 4870 __in efx_virtio_vq_t *evvp); 4871 4872 /* 4873 * Get the offset in the BAR of the doorbells for a VI. 4874 * net device : doorbell offset of RX & TX queues 4875 * block device : request doorbell offset in the BAR. 4876 * For further details refer section of 4 of SF-119689 4877 */ 4878 LIBEFX_API 4879 extern __checkReturn efx_rc_t 4880 efx_virtio_get_doorbell_offset( 4881 __in efx_virtio_vq_t *evvp, 4882 __out uint32_t *offsetp); 4883 4884 LIBEFX_API 4885 extern __checkReturn efx_rc_t 4886 efx_virtio_get_features( 4887 __in efx_nic_t *enp, 4888 __in efx_virtio_device_type_t type, 4889 __out uint64_t *featuresp); 4890 4891 LIBEFX_API 4892 extern __checkReturn efx_rc_t 4893 efx_virtio_verify_features( 4894 __in efx_nic_t *enp, 4895 __in efx_virtio_device_type_t type, 4896 __in uint64_t features); 4897 4898 #endif /* EFSYS_OPT_VIRTIO */ 4899 4900 #ifdef __cplusplus 4901 } 4902 #endif 4903 4904 #endif /* _SYS_EFX_H */ 4905