1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2012-2019 Solarflare Communications Inc. 5 */ 6 7 #include "efx.h" 8 #include "efx_impl.h" 9 #if EFSYS_OPT_MON_MCDI 10 #include "mcdi_mon.h" 11 #endif 12 13 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 14 15 #include "ef10_tlv_layout.h" 16 17 __checkReturn efx_rc_t 18 efx_mcdi_get_port_assignment( 19 __in efx_nic_t *enp, 20 __out uint32_t *portp) 21 { 22 efx_mcdi_req_t req; 23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN, 24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN); 25 efx_rc_t rc; 26 27 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 28 29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT; 30 req.emr_in_buf = payload; 31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN; 32 req.emr_out_buf = payload; 33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN; 34 35 efx_mcdi_execute(enp, &req); 36 37 if (req.emr_rc != 0) { 38 rc = req.emr_rc; 39 goto fail1; 40 } 41 42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) { 43 rc = EMSGSIZE; 44 goto fail2; 45 } 46 47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT); 48 49 return (0); 50 51 fail2: 52 EFSYS_PROBE(fail2); 53 fail1: 54 EFSYS_PROBE1(fail1, efx_rc_t, rc); 55 56 return (rc); 57 } 58 59 __checkReturn efx_rc_t 60 efx_mcdi_get_port_modes( 61 __in efx_nic_t *enp, 62 __out uint32_t *modesp, 63 __out_opt uint32_t *current_modep, 64 __out_opt uint32_t *default_modep) 65 { 66 efx_mcdi_req_t req; 67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN, 68 MC_CMD_GET_PORT_MODES_OUT_LEN); 69 efx_rc_t rc; 70 71 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 72 73 req.emr_cmd = MC_CMD_GET_PORT_MODES; 74 req.emr_in_buf = payload; 75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN; 76 req.emr_out_buf = payload; 77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN; 78 79 efx_mcdi_execute(enp, &req); 80 81 if (req.emr_rc != 0) { 82 rc = req.emr_rc; 83 goto fail1; 84 } 85 86 /* 87 * Require only Modes and DefaultMode fields, unless the current mode 88 * was requested (CurrentMode field was added for Medford). 89 */ 90 if (req.emr_out_length_used < 91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) { 92 rc = EMSGSIZE; 93 goto fail2; 94 } 95 if ((current_modep != NULL) && (req.emr_out_length_used < 96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) { 97 rc = EMSGSIZE; 98 goto fail3; 99 } 100 101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES); 102 103 if (current_modep != NULL) { 104 *current_modep = MCDI_OUT_DWORD(req, 105 GET_PORT_MODES_OUT_CURRENT_MODE); 106 } 107 108 if (default_modep != NULL) { 109 *default_modep = MCDI_OUT_DWORD(req, 110 GET_PORT_MODES_OUT_DEFAULT_MODE); 111 } 112 113 return (0); 114 115 fail3: 116 EFSYS_PROBE(fail3); 117 fail2: 118 EFSYS_PROBE(fail2); 119 fail1: 120 EFSYS_PROBE1(fail1, efx_rc_t, rc); 121 122 return (rc); 123 } 124 125 __checkReturn efx_rc_t 126 ef10_nic_get_port_mode_bandwidth( 127 __in efx_nic_t *enp, 128 __out uint32_t *bandwidth_mbpsp) 129 { 130 uint32_t port_modes; 131 uint32_t current_mode; 132 efx_port_t *epp = &(enp->en_port); 133 134 uint32_t single_lane; 135 uint32_t dual_lane; 136 uint32_t quad_lane; 137 uint32_t bandwidth; 138 efx_rc_t rc; 139 140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, 141 ¤t_mode, NULL)) != 0) { 142 /* No port mode info available. */ 143 goto fail1; 144 } 145 146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX)) 147 single_lane = 25000; 148 else 149 single_lane = 10000; 150 151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX)) 152 dual_lane = 50000; 153 else 154 dual_lane = 20000; 155 156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX)) 157 quad_lane = 100000; 158 else 159 quad_lane = 40000; 160 161 switch (current_mode) { 162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */ 163 bandwidth = single_lane; 164 break; 165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */ 166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */ 167 bandwidth = dual_lane; 168 break; 169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */ 170 bandwidth = single_lane + single_lane; 171 break; 172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */ 173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */ 174 bandwidth = 4 * single_lane; 175 break; 176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */ 177 bandwidth = (2 * single_lane) + (2 * single_lane); 178 break; 179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */ 180 bandwidth = dual_lane + dual_lane; 181 break; 182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */ 183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */ 184 bandwidth = dual_lane + (2 * single_lane); 185 break; 186 /* Legacy Medford-only mode. Do not use (see bug63270) */ 187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */ 188 bandwidth = 4 * single_lane; 189 break; 190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */ 191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */ 192 bandwidth = quad_lane; 193 break; 194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */ 195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */ 196 bandwidth = 2 * dual_lane; 197 break; 198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */ 199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */ 200 bandwidth = quad_lane + (2 * single_lane); 201 break; 202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */ 203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */ 204 bandwidth = quad_lane + dual_lane; 205 break; 206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */ 207 bandwidth = quad_lane + quad_lane; 208 break; 209 default: 210 rc = EINVAL; 211 goto fail2; 212 } 213 214 *bandwidth_mbpsp = bandwidth; 215 216 return (0); 217 218 fail2: 219 EFSYS_PROBE(fail2); 220 fail1: 221 EFSYS_PROBE1(fail1, efx_rc_t, rc); 222 223 return (rc); 224 } 225 226 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 227 228 #if EFX_OPTS_EF10() 229 230 __checkReturn efx_rc_t 231 efx_mcdi_vadaptor_alloc( 232 __in efx_nic_t *enp, 233 __in uint32_t port_id) 234 { 235 efx_mcdi_req_t req; 236 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN, 237 MC_CMD_VADAPTOR_ALLOC_OUT_LEN); 238 efx_rc_t rc; 239 240 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC; 241 req.emr_in_buf = payload; 242 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN; 243 req.emr_out_buf = payload; 244 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN; 245 246 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 247 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS, 248 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED, 249 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0); 250 251 efx_mcdi_execute(enp, &req); 252 253 if (req.emr_rc != 0) { 254 rc = req.emr_rc; 255 goto fail1; 256 } 257 258 return (0); 259 260 fail1: 261 EFSYS_PROBE1(fail1, efx_rc_t, rc); 262 263 return (rc); 264 } 265 266 __checkReturn efx_rc_t 267 efx_mcdi_vadaptor_free( 268 __in efx_nic_t *enp, 269 __in uint32_t port_id) 270 { 271 efx_mcdi_req_t req; 272 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN, 273 MC_CMD_VADAPTOR_FREE_OUT_LEN); 274 efx_rc_t rc; 275 276 req.emr_cmd = MC_CMD_VADAPTOR_FREE; 277 req.emr_in_buf = payload; 278 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN; 279 req.emr_out_buf = payload; 280 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN; 281 282 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 283 284 efx_mcdi_execute(enp, &req); 285 286 if (req.emr_rc != 0) { 287 rc = req.emr_rc; 288 goto fail1; 289 } 290 291 return (0); 292 293 fail1: 294 EFSYS_PROBE1(fail1, efx_rc_t, rc); 295 296 return (rc); 297 } 298 299 #endif /* EFX_OPTS_EF10() */ 300 301 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 302 303 __checkReturn efx_rc_t 304 efx_mcdi_get_mac_address_pf( 305 __in efx_nic_t *enp, 306 __out_ecount_opt(6) uint8_t mac_addrp[6]) 307 { 308 efx_mcdi_req_t req; 309 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN, 310 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 311 efx_rc_t rc; 312 313 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 314 315 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES; 316 req.emr_in_buf = payload; 317 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN; 318 req.emr_out_buf = payload; 319 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN; 320 321 efx_mcdi_execute(enp, &req); 322 323 if (req.emr_rc != 0) { 324 rc = req.emr_rc; 325 goto fail1; 326 } 327 328 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) { 329 rc = EMSGSIZE; 330 goto fail2; 331 } 332 333 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) { 334 rc = ENOENT; 335 goto fail3; 336 } 337 338 if (mac_addrp != NULL) { 339 uint8_t *addrp; 340 341 addrp = MCDI_OUT2(req, uint8_t, 342 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE); 343 344 EFX_MAC_ADDR_COPY(mac_addrp, addrp); 345 } 346 347 return (0); 348 349 fail3: 350 EFSYS_PROBE(fail3); 351 fail2: 352 EFSYS_PROBE(fail2); 353 fail1: 354 EFSYS_PROBE1(fail1, efx_rc_t, rc); 355 356 return (rc); 357 } 358 359 __checkReturn efx_rc_t 360 efx_mcdi_get_mac_address_vf( 361 __in efx_nic_t *enp, 362 __out_ecount_opt(6) uint8_t mac_addrp[6]) 363 { 364 efx_mcdi_req_t req; 365 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN, 366 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 367 efx_rc_t rc; 368 369 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 370 371 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES; 372 req.emr_in_buf = payload; 373 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN; 374 req.emr_out_buf = payload; 375 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX; 376 377 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 378 EVB_PORT_ID_ASSIGNED); 379 380 efx_mcdi_execute(enp, &req); 381 382 if (req.emr_rc != 0) { 383 rc = req.emr_rc; 384 goto fail1; 385 } 386 387 if (req.emr_out_length_used < 388 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) { 389 rc = EMSGSIZE; 390 goto fail2; 391 } 392 393 if (MCDI_OUT_DWORD(req, 394 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) { 395 rc = ENOENT; 396 goto fail3; 397 } 398 399 if (mac_addrp != NULL) { 400 uint8_t *addrp; 401 402 addrp = MCDI_OUT2(req, uint8_t, 403 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR); 404 405 EFX_MAC_ADDR_COPY(mac_addrp, addrp); 406 } 407 408 return (0); 409 410 fail3: 411 EFSYS_PROBE(fail3); 412 fail2: 413 EFSYS_PROBE(fail2); 414 fail1: 415 EFSYS_PROBE1(fail1, efx_rc_t, rc); 416 417 return (rc); 418 } 419 420 __checkReturn efx_rc_t 421 efx_mcdi_get_clock( 422 __in efx_nic_t *enp, 423 __out uint32_t *sys_freqp, 424 __out uint32_t *dpcpu_freqp) 425 { 426 efx_mcdi_req_t req; 427 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN, 428 MC_CMD_GET_CLOCK_OUT_LEN); 429 efx_rc_t rc; 430 431 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp)); 432 433 req.emr_cmd = MC_CMD_GET_CLOCK; 434 req.emr_in_buf = payload; 435 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN; 436 req.emr_out_buf = payload; 437 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN; 438 439 efx_mcdi_execute(enp, &req); 440 441 if (req.emr_rc != 0) { 442 rc = req.emr_rc; 443 goto fail1; 444 } 445 446 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) { 447 rc = EMSGSIZE; 448 goto fail2; 449 } 450 451 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ); 452 if (*sys_freqp == 0) { 453 rc = EINVAL; 454 goto fail3; 455 } 456 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ); 457 if (*dpcpu_freqp == 0) { 458 rc = EINVAL; 459 goto fail4; 460 } 461 462 return (0); 463 464 fail4: 465 EFSYS_PROBE(fail4); 466 fail3: 467 EFSYS_PROBE(fail3); 468 fail2: 469 EFSYS_PROBE(fail2); 470 fail1: 471 EFSYS_PROBE1(fail1, efx_rc_t, rc); 472 473 return (rc); 474 } 475 476 __checkReturn efx_rc_t 477 efx_mcdi_get_rxdp_config( 478 __in efx_nic_t *enp, 479 __out uint32_t *end_paddingp) 480 { 481 efx_mcdi_req_t req; 482 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN, 483 MC_CMD_GET_RXDP_CONFIG_OUT_LEN); 484 uint32_t end_padding; 485 efx_rc_t rc; 486 487 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG; 488 req.emr_in_buf = payload; 489 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN; 490 req.emr_out_buf = payload; 491 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; 492 493 efx_mcdi_execute(enp, &req); 494 495 if (req.emr_rc != 0) { 496 rc = req.emr_rc; 497 goto fail1; 498 } 499 500 if (req.emr_out_length_used < MC_CMD_GET_RXDP_CONFIG_OUT_LEN) { 501 rc = EMSGSIZE; 502 goto fail2; 503 } 504 505 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 506 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { 507 /* RX DMA end padding is disabled */ 508 end_padding = 0; 509 } else { 510 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 511 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) { 512 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64: 513 end_padding = 64; 514 break; 515 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128: 516 end_padding = 128; 517 break; 518 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256: 519 end_padding = 256; 520 break; 521 default: 522 rc = ENOTSUP; 523 goto fail3; 524 } 525 } 526 527 *end_paddingp = end_padding; 528 529 return (0); 530 531 fail3: 532 EFSYS_PROBE(fail3); 533 fail2: 534 EFSYS_PROBE(fail2); 535 fail1: 536 EFSYS_PROBE1(fail1, efx_rc_t, rc); 537 538 return (rc); 539 } 540 541 __checkReturn efx_rc_t 542 efx_mcdi_get_vector_cfg( 543 __in efx_nic_t *enp, 544 __out_opt uint32_t *vec_basep, 545 __out_opt uint32_t *pf_nvecp, 546 __out_opt uint32_t *vf_nvecp) 547 { 548 efx_mcdi_req_t req; 549 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN, 550 MC_CMD_GET_VECTOR_CFG_OUT_LEN); 551 efx_rc_t rc; 552 553 req.emr_cmd = MC_CMD_GET_VECTOR_CFG; 554 req.emr_in_buf = payload; 555 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN; 556 req.emr_out_buf = payload; 557 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN; 558 559 efx_mcdi_execute(enp, &req); 560 561 if (req.emr_rc != 0) { 562 rc = req.emr_rc; 563 goto fail1; 564 } 565 566 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) { 567 rc = EMSGSIZE; 568 goto fail2; 569 } 570 571 if (vec_basep != NULL) 572 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE); 573 if (pf_nvecp != NULL) 574 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF); 575 if (vf_nvecp != NULL) 576 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF); 577 578 return (0); 579 580 fail2: 581 EFSYS_PROBE(fail2); 582 fail1: 583 EFSYS_PROBE1(fail1, efx_rc_t, rc); 584 585 return (rc); 586 } 587 588 __checkReturn efx_rc_t 589 efx_mcdi_alloc_vis( 590 __in efx_nic_t *enp, 591 __in uint32_t min_vi_count, 592 __in uint32_t max_vi_count, 593 __out uint32_t *vi_basep, 594 __out uint32_t *vi_countp, 595 __out uint32_t *vi_shiftp) 596 { 597 efx_mcdi_req_t req; 598 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN, 599 MC_CMD_ALLOC_VIS_EXT_OUT_LEN); 600 efx_rc_t rc; 601 602 if (vi_countp == NULL) { 603 rc = EINVAL; 604 goto fail1; 605 } 606 607 req.emr_cmd = MC_CMD_ALLOC_VIS; 608 req.emr_in_buf = payload; 609 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN; 610 req.emr_out_buf = payload; 611 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN; 612 613 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count); 614 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count); 615 616 efx_mcdi_execute(enp, &req); 617 618 if (req.emr_rc != 0) { 619 rc = req.emr_rc; 620 goto fail2; 621 } 622 623 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) { 624 rc = EMSGSIZE; 625 goto fail3; 626 } 627 628 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE); 629 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT); 630 631 /* Report VI_SHIFT if available (always zero for Huntington) */ 632 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN) 633 *vi_shiftp = 0; 634 else 635 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT); 636 637 return (0); 638 639 fail3: 640 EFSYS_PROBE(fail3); 641 fail2: 642 EFSYS_PROBE(fail2); 643 fail1: 644 EFSYS_PROBE1(fail1, efx_rc_t, rc); 645 646 return (rc); 647 } 648 649 650 __checkReturn efx_rc_t 651 efx_mcdi_free_vis( 652 __in efx_nic_t *enp) 653 { 654 efx_mcdi_req_t req; 655 efx_rc_t rc; 656 657 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0); 658 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0); 659 660 req.emr_cmd = MC_CMD_FREE_VIS; 661 req.emr_in_buf = NULL; 662 req.emr_in_length = 0; 663 req.emr_out_buf = NULL; 664 req.emr_out_length = 0; 665 666 efx_mcdi_execute_quiet(enp, &req); 667 668 /* Ignore ELREADY (no allocated VIs, so nothing to free) */ 669 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) { 670 rc = req.emr_rc; 671 goto fail1; 672 } 673 674 return (0); 675 676 fail1: 677 EFSYS_PROBE1(fail1, efx_rc_t, rc); 678 679 return (rc); 680 } 681 682 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 683 684 #if EFX_OPTS_EF10() 685 686 static __checkReturn efx_rc_t 687 efx_mcdi_alloc_piobuf( 688 __in efx_nic_t *enp, 689 __out efx_piobuf_handle_t *handlep) 690 { 691 efx_mcdi_req_t req; 692 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN, 693 MC_CMD_ALLOC_PIOBUF_OUT_LEN); 694 efx_rc_t rc; 695 696 if (handlep == NULL) { 697 rc = EINVAL; 698 goto fail1; 699 } 700 701 req.emr_cmd = MC_CMD_ALLOC_PIOBUF; 702 req.emr_in_buf = payload; 703 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN; 704 req.emr_out_buf = payload; 705 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN; 706 707 efx_mcdi_execute_quiet(enp, &req); 708 709 if (req.emr_rc != 0) { 710 rc = req.emr_rc; 711 goto fail2; 712 } 713 714 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 715 rc = EMSGSIZE; 716 goto fail3; 717 } 718 719 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 720 721 return (0); 722 723 fail3: 724 EFSYS_PROBE(fail3); 725 fail2: 726 EFSYS_PROBE(fail2); 727 fail1: 728 EFSYS_PROBE1(fail1, efx_rc_t, rc); 729 730 return (rc); 731 } 732 733 static __checkReturn efx_rc_t 734 efx_mcdi_free_piobuf( 735 __in efx_nic_t *enp, 736 __in efx_piobuf_handle_t handle) 737 { 738 efx_mcdi_req_t req; 739 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN, 740 MC_CMD_FREE_PIOBUF_OUT_LEN); 741 efx_rc_t rc; 742 743 req.emr_cmd = MC_CMD_FREE_PIOBUF; 744 req.emr_in_buf = payload; 745 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN; 746 req.emr_out_buf = payload; 747 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN; 748 749 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle); 750 751 efx_mcdi_execute_quiet(enp, &req); 752 753 if (req.emr_rc != 0) { 754 rc = req.emr_rc; 755 goto fail1; 756 } 757 758 return (0); 759 760 fail1: 761 EFSYS_PROBE1(fail1, efx_rc_t, rc); 762 763 return (rc); 764 } 765 766 static __checkReturn efx_rc_t 767 efx_mcdi_link_piobuf( 768 __in efx_nic_t *enp, 769 __in uint32_t vi_index, 770 __in efx_piobuf_handle_t handle) 771 { 772 efx_mcdi_req_t req; 773 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN, 774 MC_CMD_LINK_PIOBUF_OUT_LEN); 775 efx_rc_t rc; 776 777 req.emr_cmd = MC_CMD_LINK_PIOBUF; 778 req.emr_in_buf = payload; 779 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN; 780 req.emr_out_buf = payload; 781 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN; 782 783 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle); 784 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index); 785 786 efx_mcdi_execute(enp, &req); 787 788 if (req.emr_rc != 0) { 789 rc = req.emr_rc; 790 goto fail1; 791 } 792 793 return (0); 794 795 fail1: 796 EFSYS_PROBE1(fail1, efx_rc_t, rc); 797 798 return (rc); 799 } 800 801 static __checkReturn efx_rc_t 802 efx_mcdi_unlink_piobuf( 803 __in efx_nic_t *enp, 804 __in uint32_t vi_index) 805 { 806 efx_mcdi_req_t req; 807 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN, 808 MC_CMD_UNLINK_PIOBUF_OUT_LEN); 809 efx_rc_t rc; 810 811 req.emr_cmd = MC_CMD_UNLINK_PIOBUF; 812 req.emr_in_buf = payload; 813 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN; 814 req.emr_out_buf = payload; 815 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN; 816 817 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index); 818 819 efx_mcdi_execute_quiet(enp, &req); 820 821 if (req.emr_rc != 0) { 822 rc = req.emr_rc; 823 goto fail1; 824 } 825 826 return (0); 827 828 fail1: 829 EFSYS_PROBE1(fail1, efx_rc_t, rc); 830 831 return (rc); 832 } 833 834 static void 835 ef10_nic_alloc_piobufs( 836 __in efx_nic_t *enp, 837 __in uint32_t max_piobuf_count) 838 { 839 efx_piobuf_handle_t *handlep; 840 unsigned int i; 841 842 EFSYS_ASSERT3U(max_piobuf_count, <=, 843 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle)); 844 845 enp->en_arch.ef10.ena_piobuf_count = 0; 846 847 for (i = 0; i < max_piobuf_count; i++) { 848 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; 849 850 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0) 851 goto fail1; 852 853 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0; 854 enp->en_arch.ef10.ena_piobuf_count++; 855 } 856 857 return; 858 859 fail1: 860 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 861 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; 862 863 (void) efx_mcdi_free_piobuf(enp, *handlep); 864 *handlep = EFX_PIOBUF_HANDLE_INVALID; 865 } 866 enp->en_arch.ef10.ena_piobuf_count = 0; 867 } 868 869 870 static void 871 ef10_nic_free_piobufs( 872 __in efx_nic_t *enp) 873 { 874 efx_piobuf_handle_t *handlep; 875 unsigned int i; 876 877 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 878 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; 879 880 (void) efx_mcdi_free_piobuf(enp, *handlep); 881 *handlep = EFX_PIOBUF_HANDLE_INVALID; 882 } 883 enp->en_arch.ef10.ena_piobuf_count = 0; 884 } 885 886 /* Sub-allocate a block from a piobuf */ 887 __checkReturn efx_rc_t 888 ef10_nic_pio_alloc( 889 __inout efx_nic_t *enp, 890 __out uint32_t *bufnump, 891 __out efx_piobuf_handle_t *handlep, 892 __out uint32_t *blknump, 893 __out uint32_t *offsetp, 894 __out size_t *sizep) 895 { 896 efx_nic_cfg_t *encp = &enp->en_nic_cfg; 897 efx_drv_cfg_t *edcp = &enp->en_drv_cfg; 898 uint32_t blk_per_buf; 899 uint32_t buf, blk; 900 efx_rc_t rc; 901 902 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 903 EFSYS_ASSERT(bufnump); 904 EFSYS_ASSERT(handlep); 905 EFSYS_ASSERT(blknump); 906 EFSYS_ASSERT(offsetp); 907 EFSYS_ASSERT(sizep); 908 909 if ((edcp->edc_pio_alloc_size == 0) || 910 (enp->en_arch.ef10.ena_piobuf_count == 0)) { 911 rc = ENOMEM; 912 goto fail1; 913 } 914 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size; 915 916 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) { 917 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf]; 918 919 if (~(*map) == 0) 920 continue; 921 922 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map))); 923 for (blk = 0; blk < blk_per_buf; blk++) { 924 if ((*map & (1u << blk)) == 0) { 925 *map |= (1u << blk); 926 goto done; 927 } 928 } 929 } 930 rc = ENOMEM; 931 goto fail2; 932 933 done: 934 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf]; 935 *bufnump = buf; 936 *blknump = blk; 937 *sizep = edcp->edc_pio_alloc_size; 938 *offsetp = blk * (*sizep); 939 940 return (0); 941 942 fail2: 943 EFSYS_PROBE(fail2); 944 fail1: 945 EFSYS_PROBE1(fail1, efx_rc_t, rc); 946 947 return (rc); 948 } 949 950 /* Free a piobuf sub-allocated block */ 951 __checkReturn efx_rc_t 952 ef10_nic_pio_free( 953 __inout efx_nic_t *enp, 954 __in uint32_t bufnum, 955 __in uint32_t blknum) 956 { 957 uint32_t *map; 958 efx_rc_t rc; 959 960 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) || 961 (blknum >= (8 * sizeof (*map)))) { 962 rc = EINVAL; 963 goto fail1; 964 } 965 966 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum]; 967 if ((*map & (1u << blknum)) == 0) { 968 rc = ENOENT; 969 goto fail2; 970 } 971 *map &= ~(1u << blknum); 972 973 return (0); 974 975 fail2: 976 EFSYS_PROBE(fail2); 977 fail1: 978 EFSYS_PROBE1(fail1, efx_rc_t, rc); 979 980 return (rc); 981 } 982 983 __checkReturn efx_rc_t 984 ef10_nic_pio_link( 985 __inout efx_nic_t *enp, 986 __in uint32_t vi_index, 987 __in efx_piobuf_handle_t handle) 988 { 989 return (efx_mcdi_link_piobuf(enp, vi_index, handle)); 990 } 991 992 __checkReturn efx_rc_t 993 ef10_nic_pio_unlink( 994 __inout efx_nic_t *enp, 995 __in uint32_t vi_index) 996 { 997 return (efx_mcdi_unlink_piobuf(enp, vi_index)); 998 } 999 1000 #endif /* EFX_OPTS_EF10() */ 1001 1002 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1003 1004 static __checkReturn efx_rc_t 1005 ef10_mcdi_get_pf_count( 1006 __in efx_nic_t *enp, 1007 __out uint32_t *pf_countp) 1008 { 1009 efx_mcdi_req_t req; 1010 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN, 1011 MC_CMD_GET_PF_COUNT_OUT_LEN); 1012 efx_rc_t rc; 1013 1014 req.emr_cmd = MC_CMD_GET_PF_COUNT; 1015 req.emr_in_buf = payload; 1016 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN; 1017 req.emr_out_buf = payload; 1018 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN; 1019 1020 efx_mcdi_execute(enp, &req); 1021 1022 if (req.emr_rc != 0) { 1023 rc = req.emr_rc; 1024 goto fail1; 1025 } 1026 1027 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) { 1028 rc = EMSGSIZE; 1029 goto fail2; 1030 } 1031 1032 *pf_countp = *MCDI_OUT(req, uint8_t, 1033 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST); 1034 1035 EFSYS_ASSERT(*pf_countp != 0); 1036 1037 return (0); 1038 1039 fail2: 1040 EFSYS_PROBE(fail2); 1041 fail1: 1042 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1043 1044 return (rc); 1045 } 1046 1047 static __checkReturn efx_rc_t 1048 ef10_get_datapath_caps( 1049 __in efx_nic_t *enp) 1050 { 1051 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1052 efx_mcdi_req_t req; 1053 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN, 1054 MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); 1055 efx_rc_t rc; 1056 1057 req.emr_cmd = MC_CMD_GET_CAPABILITIES; 1058 req.emr_in_buf = payload; 1059 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; 1060 req.emr_out_buf = payload; 1061 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V7_OUT_LEN; 1062 1063 efx_mcdi_execute_quiet(enp, &req); 1064 1065 if (req.emr_rc != 0) { 1066 rc = req.emr_rc; 1067 goto fail1; 1068 } 1069 1070 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 1071 rc = EMSGSIZE; 1072 goto fail2; 1073 } 1074 1075 #define CAP_FLAGS1(_req, _flag) \ 1076 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \ 1077 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))) 1078 1079 #define CAP_FLAGS2(_req, _flag) \ 1080 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \ 1081 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \ 1082 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))) 1083 1084 #define CAP_FLAGS3(_req, _flag) \ 1085 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) && \ 1086 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V7_OUT_FLAGS3) & \ 1087 (1u << (MC_CMD_GET_CAPABILITIES_V7_OUT_ ## _flag ## _LBN)))) 1088 1089 /* Check if RXDP firmware inserts 14 byte prefix */ 1090 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14)) 1091 encp->enc_rx_prefix_size = 14; 1092 else 1093 encp->enc_rx_prefix_size = 0; 1094 1095 #if EFSYS_OPT_RX_SCALE 1096 /* Check if the firmware supports additional RSS modes */ 1097 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES)) 1098 encp->enc_rx_scale_additional_modes_supported = B_TRUE; 1099 else 1100 encp->enc_rx_scale_additional_modes_supported = B_FALSE; 1101 #endif /* EFSYS_OPT_RX_SCALE */ 1102 1103 /* Check if the firmware supports TSO */ 1104 if (CAP_FLAGS1(req, TX_TSO)) 1105 encp->enc_fw_assisted_tso_enabled = B_TRUE; 1106 else 1107 encp->enc_fw_assisted_tso_enabled = B_FALSE; 1108 1109 /* Check if the firmware supports FATSOv2 */ 1110 if (CAP_FLAGS2(req, TX_TSO_V2)) { 1111 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE; 1112 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req, 1113 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS); 1114 } else { 1115 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE; 1116 encp->enc_fw_assisted_tso_v2_n_contexts = 0; 1117 } 1118 1119 /* Check if the firmware supports FATSOv2 encap */ 1120 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP)) 1121 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE; 1122 else 1123 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE; 1124 1125 /* Check if TSOv3 is supported */ 1126 if (CAP_FLAGS2(req, TX_TSO_V3)) 1127 encp->enc_tso_v3_enabled = B_TRUE; 1128 else 1129 encp->enc_tso_v3_enabled = B_FALSE; 1130 1131 /* Check if the firmware has vadapter/vport/vswitch support */ 1132 if (CAP_FLAGS1(req, EVB)) 1133 encp->enc_datapath_cap_evb = B_TRUE; 1134 else 1135 encp->enc_datapath_cap_evb = B_FALSE; 1136 1137 /* Check if the firmware supports vport reconfiguration */ 1138 if (CAP_FLAGS1(req, VPORT_RECONFIGURE)) 1139 encp->enc_vport_reconfigure_supported = B_TRUE; 1140 else 1141 encp->enc_vport_reconfigure_supported = B_FALSE; 1142 1143 /* Check if the firmware supports VLAN insertion */ 1144 if (CAP_FLAGS1(req, TX_VLAN_INSERTION)) 1145 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE; 1146 else 1147 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; 1148 1149 /* Check if the firmware supports RX event batching */ 1150 if (CAP_FLAGS1(req, RX_BATCHING)) 1151 encp->enc_rx_batching_enabled = B_TRUE; 1152 else 1153 encp->enc_rx_batching_enabled = B_FALSE; 1154 1155 /* 1156 * Even if batching isn't reported as supported, we may still get 1157 * batched events (see bug61153). 1158 */ 1159 encp->enc_rx_batch_max = 16; 1160 1161 /* Check if the firmware supports disabling scatter on RXQs */ 1162 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER)) 1163 encp->enc_rx_disable_scatter_supported = B_TRUE; 1164 else 1165 encp->enc_rx_disable_scatter_supported = B_FALSE; 1166 1167 /* No limit on maximum number of Rx scatter elements per packet. */ 1168 encp->enc_rx_scatter_max = -1; 1169 1170 /* Check if the firmware supports packed stream mode */ 1171 if (CAP_FLAGS1(req, RX_PACKED_STREAM)) 1172 encp->enc_rx_packed_stream_supported = B_TRUE; 1173 else 1174 encp->enc_rx_packed_stream_supported = B_FALSE; 1175 1176 /* 1177 * Check if the firmware supports configurable buffer sizes 1178 * for packed stream mode (otherwise buffer size is 1Mbyte) 1179 */ 1180 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS)) 1181 encp->enc_rx_var_packed_stream_supported = B_TRUE; 1182 else 1183 encp->enc_rx_var_packed_stream_supported = B_FALSE; 1184 1185 /* Check if the firmware supports equal stride super-buffer mode */ 1186 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER)) 1187 encp->enc_rx_es_super_buffer_supported = B_TRUE; 1188 else 1189 encp->enc_rx_es_super_buffer_supported = B_FALSE; 1190 1191 /* Check if the firmware supports FW subvariant w/o Tx checksumming */ 1192 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM)) 1193 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE; 1194 else 1195 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE; 1196 1197 /* Check if the firmware supports set mac with running filters */ 1198 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED)) 1199 encp->enc_allow_set_mac_with_installed_filters = B_TRUE; 1200 else 1201 encp->enc_allow_set_mac_with_installed_filters = B_FALSE; 1202 1203 /* 1204 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows 1205 * specifying which parameters to configure. 1206 */ 1207 if (CAP_FLAGS1(req, SET_MAC_ENHANCED)) 1208 encp->enc_enhanced_set_mac_supported = B_TRUE; 1209 else 1210 encp->enc_enhanced_set_mac_supported = B_FALSE; 1211 1212 /* 1213 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows 1214 * us to let the firmware choose the settings to use on an EVQ. 1215 */ 1216 if (CAP_FLAGS2(req, INIT_EVQ_V2)) 1217 encp->enc_init_evq_v2_supported = B_TRUE; 1218 else 1219 encp->enc_init_evq_v2_supported = B_FALSE; 1220 1221 /* 1222 * Check if firmware supports extended width event queues, which have 1223 * a different event descriptor layout. 1224 */ 1225 if (CAP_FLAGS3(req, EXTENDED_WIDTH_EVQS_SUPPORTED)) 1226 encp->enc_init_evq_extended_width_supported = B_TRUE; 1227 else 1228 encp->enc_init_evq_extended_width_supported = B_FALSE; 1229 1230 /* 1231 * Check if the NO_CONT_EV mode for RX events is supported. 1232 */ 1233 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV)) 1234 encp->enc_no_cont_ev_mode_supported = B_TRUE; 1235 else 1236 encp->enc_no_cont_ev_mode_supported = B_FALSE; 1237 1238 /* 1239 * Check if buffer size may and must be specified on INIT_RXQ. 1240 * It may be always specified to efx_rx_qcreate(), but will be 1241 * just kept libefx internal if MCDI does not support it. 1242 */ 1243 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE)) 1244 encp->enc_init_rxq_with_buffer_size = B_TRUE; 1245 else 1246 encp->enc_init_rxq_with_buffer_size = B_FALSE; 1247 1248 /* 1249 * Check if firmware-verified NVRAM updates must be used. 1250 * 1251 * The firmware trusted installer requires all NVRAM updates to use 1252 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update) 1253 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated 1254 * partition and report the result). 1255 */ 1256 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT)) 1257 encp->enc_nvram_update_verify_result_supported = B_TRUE; 1258 else 1259 encp->enc_nvram_update_verify_result_supported = B_FALSE; 1260 1261 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT)) 1262 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE; 1263 else 1264 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE; 1265 1266 /* 1267 * Check if firmware update via the BUNDLE partition is supported 1268 */ 1269 if (CAP_FLAGS2(req, BUNDLE_UPDATE)) 1270 encp->enc_nvram_bundle_update_supported = B_TRUE; 1271 else 1272 encp->enc_nvram_bundle_update_supported = B_FALSE; 1273 1274 /* 1275 * Check if firmware provides packet memory and Rx datapath 1276 * counters. 1277 */ 1278 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS)) 1279 encp->enc_pm_and_rxdp_counters = B_TRUE; 1280 else 1281 encp->enc_pm_and_rxdp_counters = B_FALSE; 1282 1283 /* 1284 * Check if the 40G MAC hardware is capable of reporting 1285 * statistics for Tx size bins. 1286 */ 1287 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS)) 1288 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE; 1289 else 1290 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE; 1291 1292 /* 1293 * Check if firmware supports VXLAN and NVGRE tunnels. 1294 * The capability indicates Geneve protocol support as well. 1295 */ 1296 if (CAP_FLAGS1(req, VXLAN_NVGRE)) { 1297 encp->enc_tunnel_encapsulations_supported = 1298 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) | 1299 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) | 1300 (1u << EFX_TUNNEL_PROTOCOL_NVGRE); 1301 1302 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES == 1303 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 1304 encp->enc_tunnel_config_udp_entries_max = 1305 EFX_TUNNEL_MAXNENTRIES; 1306 } else { 1307 encp->enc_tunnel_config_udp_entries_max = 0; 1308 } 1309 1310 /* 1311 * Check if firmware reports the VI window mode. 1312 * Medford2 has a variable VI window size (8K, 16K or 64K). 1313 * Medford and Huntington have a fixed 8K VI window size. 1314 */ 1315 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 1316 uint8_t mode = 1317 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 1318 1319 switch (mode) { 1320 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K: 1321 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; 1322 break; 1323 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K: 1324 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K; 1325 break; 1326 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K: 1327 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K; 1328 break; 1329 default: 1330 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; 1331 break; 1332 } 1333 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) || 1334 (enp->en_family == EFX_FAMILY_MEDFORD)) { 1335 /* Huntington and Medford have fixed 8K window size */ 1336 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; 1337 } else { 1338 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; 1339 } 1340 1341 /* Check if firmware supports extended MAC stats. */ 1342 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 1343 /* Extended stats buffer supported */ 1344 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req, 1345 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 1346 } else { 1347 /* Use Siena-compatible legacy MAC stats */ 1348 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS; 1349 } 1350 1351 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2) 1352 encp->enc_fec_counters = B_TRUE; 1353 else 1354 encp->enc_fec_counters = B_FALSE; 1355 1356 /* Check if the firmware provides head-of-line blocking counters */ 1357 if (CAP_FLAGS2(req, RXDP_HLB_IDLE)) 1358 encp->enc_hlb_counters = B_TRUE; 1359 else 1360 encp->enc_hlb_counters = B_FALSE; 1361 1362 #if EFSYS_OPT_RX_SCALE 1363 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) { 1364 /* Only one exclusive RSS context is available per port. */ 1365 encp->enc_rx_scale_max_exclusive_contexts = 1; 1366 1367 switch (enp->en_family) { 1368 case EFX_FAMILY_MEDFORD2: 1369 encp->enc_rx_scale_hash_alg_mask = 1370 (1U << EFX_RX_HASHALG_TOEPLITZ); 1371 break; 1372 1373 case EFX_FAMILY_MEDFORD: 1374 case EFX_FAMILY_HUNTINGTON: 1375 /* 1376 * Packed stream firmware variant maintains a 1377 * non-standard algorithm for hash computation. 1378 * It implies explicit XORing together 1379 * source + destination IP addresses (or last 1380 * four bytes in the case of IPv6) and using the 1381 * resulting value as the input to a Toeplitz hash. 1382 */ 1383 encp->enc_rx_scale_hash_alg_mask = 1384 (1U << EFX_RX_HASHALG_PACKED_STREAM); 1385 break; 1386 1387 default: 1388 rc = EINVAL; 1389 goto fail3; 1390 } 1391 1392 /* Port numbers cannot contribute to the hash value */ 1393 encp->enc_rx_scale_l4_hash_supported = B_FALSE; 1394 } else { 1395 /* 1396 * Maximum number of exclusive RSS contexts. 1397 * EF10 hardware supports 64 in total, but 6 are reserved 1398 * for shared contexts. They are a global resource so 1399 * not all may be available. 1400 */ 1401 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6; 1402 1403 encp->enc_rx_scale_hash_alg_mask = 1404 (1U << EFX_RX_HASHALG_TOEPLITZ); 1405 1406 /* 1407 * It is possible to use port numbers as 1408 * the input data for hash computation. 1409 */ 1410 encp->enc_rx_scale_l4_hash_supported = B_TRUE; 1411 } 1412 #endif /* EFSYS_OPT_RX_SCALE */ 1413 1414 /* Check if the firmware supports "FLAG" and "MARK" filter actions */ 1415 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG)) 1416 encp->enc_filter_action_flag_supported = B_TRUE; 1417 else 1418 encp->enc_filter_action_flag_supported = B_FALSE; 1419 1420 if (CAP_FLAGS2(req, FILTER_ACTION_MARK)) 1421 encp->enc_filter_action_mark_supported = B_TRUE; 1422 else 1423 encp->enc_filter_action_mark_supported = B_FALSE; 1424 1425 /* Get maximum supported value for "MARK" filter action */ 1426 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN) 1427 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req, 1428 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX); 1429 else 1430 encp->enc_filter_action_mark_max = 0; 1431 1432 #if EFSYS_OPT_MAE 1433 /* 1434 * Check support for EF100 Match Action Engine (MAE). 1435 * MAE hardware is present on Riverhead boards (from R2), 1436 * and on Keystone, and requires support in firmware. 1437 * 1438 * MAE control operations require MAE control privilege, 1439 * which is not available for VFs. 1440 * 1441 * Privileges can change dynamically at runtime: we assume 1442 * MAE support requires the privilege is granted initially, 1443 * and ignore later dynamic changes. 1444 */ 1445 if (CAP_FLAGS3(req, MAE_SUPPORTED)) { 1446 encp->enc_mae_supported = B_TRUE; 1447 if (EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE)) 1448 encp->enc_mae_admin = B_TRUE; 1449 else 1450 encp->enc_mae_admin = B_FALSE; 1451 } else { 1452 encp->enc_mae_supported = B_FALSE; 1453 encp->enc_mae_admin = B_FALSE; 1454 } 1455 1456 /* 1457 * Check support for MAE action set v2 features. 1458 * These provide support for packet edits. 1459 */ 1460 if (CAP_FLAGS3(req, MAE_ACTION_SET_ALLOC_V2_SUPPORTED)) 1461 encp->enc_mae_aset_v2_supported = B_TRUE; 1462 else 1463 encp->enc_mae_aset_v2_supported = B_FALSE; 1464 #else 1465 encp->enc_mae_supported = B_FALSE; 1466 encp->enc_mae_admin = B_FALSE; 1467 #endif /* EFSYS_OPT_MAE */ 1468 1469 #undef CAP_FLAGS1 1470 #undef CAP_FLAGS2 1471 #undef CAP_FLAGS3 1472 1473 return (0); 1474 1475 #if EFSYS_OPT_RX_SCALE 1476 fail3: 1477 EFSYS_PROBE(fail3); 1478 #endif /* EFSYS_OPT_RX_SCALE */ 1479 fail2: 1480 EFSYS_PROBE(fail2); 1481 fail1: 1482 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1483 1484 return (rc); 1485 } 1486 1487 1488 #define EF10_LEGACY_PF_PRIVILEGE_MASK \ 1489 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ 1490 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \ 1491 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \ 1492 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \ 1493 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \ 1494 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \ 1495 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \ 1496 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \ 1497 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \ 1498 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \ 1499 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS) 1500 1501 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0 1502 1503 1504 __checkReturn efx_rc_t 1505 ef10_get_privilege_mask( 1506 __in efx_nic_t *enp, 1507 __out uint32_t *maskp) 1508 { 1509 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1510 uint32_t mask; 1511 efx_rc_t rc; 1512 1513 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf, 1514 &mask)) != 0) { 1515 if (rc != ENOTSUP) 1516 goto fail1; 1517 1518 /* Fallback for old firmware without privilege mask support */ 1519 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 1520 /* Assume PF has admin privilege */ 1521 mask = EF10_LEGACY_PF_PRIVILEGE_MASK; 1522 } else { 1523 /* VF is always unprivileged by default */ 1524 mask = EF10_LEGACY_VF_PRIVILEGE_MASK; 1525 } 1526 } 1527 1528 *maskp = mask; 1529 1530 return (0); 1531 1532 fail1: 1533 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1534 1535 return (rc); 1536 } 1537 1538 1539 #define EFX_EXT_PORT_MAX 4 1540 #define EFX_EXT_PORT_NA 0xFF 1541 1542 /* 1543 * Table of mapping schemes from port number to external number. 1544 * 1545 * Each port number ultimately corresponds to a connector: either as part of 1546 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on 1547 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T 1548 * "Salina"). In general: 1549 * 1550 * Port number (0-based) 1551 * | 1552 * port mapping (n:1) 1553 * | 1554 * v 1555 * External port number (1-based) 1556 * | 1557 * fixed (1:1) or cable assembly (1:m) 1558 * | 1559 * v 1560 * Connector 1561 * 1562 * The external numbering refers to the cages or magjacks on the board, 1563 * as visibly annotated on the board or back panel. This table describes 1564 * how to determine which external cage/magjack corresponds to the port 1565 * numbers used by the driver. 1566 * 1567 * The count of consecutive port numbers that map to each external number, 1568 * is determined by the chip family and the current port mode. 1569 * 1570 * For the Huntington family, the current port mode cannot be discovered, 1571 * but a single mapping is used by all modes for a given chip variant, 1572 * so the mapping used is instead the last match in the table to the full 1573 * set of port modes to which the NIC can be configured. Therefore the 1574 * ordering of entries in the mapping table is significant. 1575 */ 1576 static struct ef10_external_port_map_s { 1577 efx_family_t family; 1578 uint32_t modes_mask; 1579 uint8_t base_port[EFX_EXT_PORT_MAX]; 1580 } __ef10_external_port_mappings[] = { 1581 /* 1582 * Modes used by Huntington family controllers where each port 1583 * number maps to a separate cage. 1584 * SFN7x22F (Torino): 1585 * port 0 -> cage 1 1586 * port 1 -> cage 2 1587 * SFN7xx4F (Pavia): 1588 * port 0 -> cage 1 1589 * port 1 -> cage 2 1590 * port 2 -> cage 3 1591 * port 3 -> cage 4 1592 */ 1593 { 1594 EFX_FAMILY_HUNTINGTON, 1595 (1U << TLV_PORT_MODE_10G) | /* mode 0 */ 1596 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */ 1597 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */ 1598 { 0, 1, 2, 3 } 1599 }, 1600 /* 1601 * Modes which for Huntington identify a chip variant where 2 1602 * adjacent port numbers map to each cage. 1603 * SFN7x42Q (Monza): 1604 * port 0 -> cage 1 1605 * port 1 -> cage 1 1606 * port 2 -> cage 2 1607 * port 3 -> cage 2 1608 */ 1609 { 1610 EFX_FAMILY_HUNTINGTON, 1611 (1U << TLV_PORT_MODE_40G) | /* mode 1 */ 1612 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */ 1613 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */ 1614 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */ 1615 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1616 }, 1617 /* 1618 * Modes that on Medford allocate each port number to a separate 1619 * cage. 1620 * port 0 -> cage 1 1621 * port 1 -> cage 2 1622 * port 2 -> cage 3 1623 * port 3 -> cage 4 1624 */ 1625 { 1626 EFX_FAMILY_MEDFORD, 1627 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ 1628 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ 1629 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */ 1630 { 0, 1, 2, 3 } 1631 }, 1632 /* 1633 * Modes that on Medford allocate 2 adjacent port numbers to each 1634 * cage. 1635 * port 0 -> cage 1 1636 * port 1 -> cage 1 1637 * port 2 -> cage 2 1638 * port 3 -> cage 2 1639 */ 1640 { 1641 EFX_FAMILY_MEDFORD, 1642 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */ 1643 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */ 1644 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */ 1645 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */ 1646 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */ 1647 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */ 1648 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1649 }, 1650 /* 1651 * Modes that on Medford allocate 4 adjacent port numbers to 1652 * cage 1. 1653 * port 0 -> cage 1 1654 * port 1 -> cage 1 1655 * port 2 -> cage 1 1656 * port 3 -> cage 1 1657 */ 1658 { 1659 EFX_FAMILY_MEDFORD, 1660 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */ 1661 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */ 1662 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1663 }, 1664 /* 1665 * Modes that on Medford allocate 4 adjacent port numbers to 1666 * cage 2. 1667 * port 0 -> cage 2 1668 * port 1 -> cage 2 1669 * port 2 -> cage 2 1670 * port 3 -> cage 2 1671 */ 1672 { 1673 EFX_FAMILY_MEDFORD, 1674 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */ 1675 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1676 }, 1677 /* 1678 * Modes that on Medford2 allocate each port number to a separate 1679 * cage. 1680 * port 0 -> cage 1 1681 * port 1 -> cage 2 1682 * port 2 -> cage 3 1683 * port 3 -> cage 4 1684 */ 1685 { 1686 EFX_FAMILY_MEDFORD2, 1687 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ 1688 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ 1689 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */ 1690 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */ 1691 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */ 1692 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */ 1693 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */ 1694 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */ 1695 { 0, 1, 2, 3 } 1696 }, 1697 /* 1698 * Modes that on Medford2 allocate 1 port to cage 1 and the rest 1699 * to cage 2. 1700 * port 0 -> cage 1 1701 * port 1 -> cage 2 1702 * port 2 -> cage 2 1703 */ 1704 { 1705 EFX_FAMILY_MEDFORD2, 1706 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */ 1707 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */ 1708 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1709 }, 1710 /* 1711 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1 1712 * and the rest to cage 2. 1713 * port 0 -> cage 1 1714 * port 1 -> cage 1 1715 * port 2 -> cage 2 1716 * port 3 -> cage 2 1717 */ 1718 { 1719 EFX_FAMILY_MEDFORD2, 1720 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */ 1721 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */ 1722 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */ 1723 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */ 1724 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1725 }, 1726 /* 1727 * Modes that on Medford2 allocate up to 4 adjacent port numbers 1728 * to cage 1. 1729 * port 0 -> cage 1 1730 * port 1 -> cage 1 1731 * port 2 -> cage 1 1732 * port 3 -> cage 1 1733 */ 1734 { 1735 EFX_FAMILY_MEDFORD2, 1736 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */ 1737 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1738 }, 1739 /* 1740 * Modes that on Medford2 allocate up to 4 adjacent port numbers 1741 * to cage 2. 1742 * port 0 -> cage 2 1743 * port 1 -> cage 2 1744 * port 2 -> cage 2 1745 * port 3 -> cage 2 1746 */ 1747 { 1748 EFX_FAMILY_MEDFORD2, 1749 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */ 1750 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */ 1751 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */ 1752 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1753 }, 1754 /* 1755 * Modes that on Riverhead allocate each port number to a separate 1756 * cage. 1757 * port 0 -> cage 1 1758 * port 1 -> cage 2 1759 */ 1760 { 1761 EFX_FAMILY_RIVERHEAD, 1762 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ 1763 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ 1764 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */ 1765 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA } 1766 }, 1767 }; 1768 1769 static __checkReturn efx_rc_t 1770 ef10_external_port_mapping( 1771 __in efx_nic_t *enp, 1772 __in uint32_t port, 1773 __out uint8_t *external_portp) 1774 { 1775 efx_rc_t rc; 1776 int i; 1777 uint32_t port_modes; 1778 uint32_t matches; 1779 uint32_t current; 1780 struct ef10_external_port_map_s *mapp = NULL; 1781 int ext_index = port; /* Default 1-1 mapping */ 1782 1783 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t, 1784 NULL)) != 0) { 1785 /* 1786 * No current port mode information (i.e. Huntington) 1787 * - infer mapping from available modes 1788 */ 1789 if ((rc = efx_mcdi_get_port_modes(enp, 1790 &port_modes, NULL, NULL)) != 0) { 1791 /* 1792 * No port mode information available 1793 * - use default mapping 1794 */ 1795 goto out; 1796 } 1797 } else { 1798 /* Only need to scan the current mode */ 1799 port_modes = 1 << current; 1800 } 1801 1802 /* 1803 * Infer the internal port -> external number mapping from 1804 * the possible port modes for this NIC. 1805 */ 1806 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) { 1807 struct ef10_external_port_map_s *eepmp = 1808 &__ef10_external_port_mappings[i]; 1809 if (eepmp->family != enp->en_family) 1810 continue; 1811 matches = (eepmp->modes_mask & port_modes); 1812 if (matches != 0) { 1813 /* 1814 * Some modes match. For some Huntington boards 1815 * there will be multiple matches. The mapping on the 1816 * last match is used. 1817 */ 1818 mapp = eepmp; 1819 port_modes &= ~matches; 1820 } 1821 } 1822 1823 if (port_modes != 0) { 1824 /* Some advertised modes are not supported */ 1825 rc = ENOTSUP; 1826 goto fail1; 1827 } 1828 1829 out: 1830 if (mapp != NULL) { 1831 /* 1832 * External ports are assigned a sequence of consecutive 1833 * port numbers, so find the one with the closest base_port. 1834 */ 1835 uint32_t delta = EFX_EXT_PORT_NA; 1836 1837 for (i = 0; i < EFX_EXT_PORT_MAX; i++) { 1838 uint32_t base = mapp->base_port[i]; 1839 if ((base != EFX_EXT_PORT_NA) && (base <= port)) { 1840 if ((port - base) < delta) { 1841 delta = (port - base); 1842 ext_index = i; 1843 } 1844 } 1845 } 1846 } 1847 *external_portp = (uint8_t)(ext_index + 1); 1848 1849 return (0); 1850 1851 fail1: 1852 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1853 1854 return (rc); 1855 } 1856 1857 __checkReturn efx_rc_t 1858 efx_mcdi_nic_board_cfg( 1859 __in efx_nic_t *enp) 1860 { 1861 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 1862 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1863 ef10_link_state_t els; 1864 efx_port_t *epp = &(enp->en_port); 1865 efx_pcie_interface_t intf; 1866 uint32_t board_type = 0; 1867 uint32_t base, nvec; 1868 uint32_t port; 1869 uint32_t mask; 1870 uint32_t pf; 1871 uint32_t vf; 1872 uint8_t mac_addr[6] = { 0 }; 1873 efx_rc_t rc; 1874 1875 /* Get the (zero-based) MCDI port number */ 1876 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 1877 goto fail1; 1878 1879 /* EFX MCDI interface uses one-based port numbers */ 1880 emip->emi_port = port + 1; 1881 1882 encp->enc_assigned_port = port; 1883 1884 if ((rc = ef10_external_port_mapping(enp, port, 1885 &encp->enc_external_port)) != 0) 1886 goto fail2; 1887 1888 /* 1889 * Get PCIe function number from firmware (used for 1890 * per-function privilege and dynamic config info). 1891 * - PCIe PF: pf = PF number, vf = 0xffff. 1892 * - PCIe VF: pf = parent PF, vf = VF number. 1893 */ 1894 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf, &intf)) != 0) 1895 goto fail3; 1896 1897 encp->enc_pf = pf; 1898 encp->enc_vf = vf; 1899 encp->enc_intf = intf; 1900 1901 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0) 1902 goto fail4; 1903 1904 /* MAC address for this function */ 1905 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 1906 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 1907 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 1908 /* 1909 * Disable static config checking, ONLY for manufacturing test 1910 * and setup at the factory, to allow the static config to be 1911 * installed. 1912 */ 1913 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 1914 if ((rc == 0) && (mac_addr[0] & 0x02)) { 1915 /* 1916 * If the static config does not include a global MAC 1917 * address pool then the board may return a locally 1918 * administered MAC address (this should only happen on 1919 * incorrectly programmed boards). 1920 */ 1921 rc = EINVAL; 1922 } 1923 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 1924 } else { 1925 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 1926 } 1927 if (rc != 0) 1928 goto fail5; 1929 1930 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 1931 1932 /* 1933 * Get the current privilege mask. Note that this may be modified 1934 * dynamically, so for most cases the value is informational only. 1935 * If the privilege being discovered can't be granted dynamically, 1936 * it's fine to rely on the value. In all other cases, DO NOT use 1937 * the privilege mask to check for sufficient privileges, as that 1938 * can result in time-of-check/time-of-use bugs. 1939 */ 1940 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 1941 goto fail6; 1942 encp->enc_privilege_mask = mask; 1943 1944 /* Board configuration (legacy) */ 1945 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 1946 if (rc != 0) { 1947 /* Unprivileged functions may not be able to read board cfg */ 1948 if (rc == EACCES) 1949 board_type = 0; 1950 else 1951 goto fail7; 1952 } 1953 1954 encp->enc_board_type = board_type; 1955 1956 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 1957 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 1958 goto fail8; 1959 1960 /* 1961 * Firmware with support for *_FEC capability bits does not 1962 * report that the corresponding *_FEC_REQUESTED bits are supported. 1963 * Add them here so that drivers understand that they are supported. 1964 */ 1965 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC)) 1966 epp->ep_phy_cap_mask |= 1967 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED); 1968 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC)) 1969 epp->ep_phy_cap_mask |= 1970 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED); 1971 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC)) 1972 epp->ep_phy_cap_mask |= 1973 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED); 1974 1975 /* Obtain the default PHY advertised capabilities */ 1976 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 1977 goto fail9; 1978 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask; 1979 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; 1980 1981 /* Check capabilities of running datapath firmware */ 1982 if ((rc = ef10_get_datapath_caps(enp)) != 0) 1983 goto fail10; 1984 1985 /* Get interrupt vector limits */ 1986 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 1987 if (EFX_PCI_FUNCTION_IS_PF(encp)) 1988 goto fail11; 1989 1990 /* Ignore error (cannot query vector limits from a VF). */ 1991 base = 0; 1992 nvec = 1024; 1993 } 1994 encp->enc_intr_vec_base = base; 1995 encp->enc_intr_limit = nvec; 1996 1997 return (0); 1998 1999 fail11: 2000 EFSYS_PROBE(fail11); 2001 fail10: 2002 EFSYS_PROBE(fail10); 2003 fail9: 2004 EFSYS_PROBE(fail9); 2005 fail8: 2006 EFSYS_PROBE(fail8); 2007 fail7: 2008 EFSYS_PROBE(fail7); 2009 fail6: 2010 EFSYS_PROBE(fail6); 2011 fail5: 2012 EFSYS_PROBE(fail5); 2013 fail4: 2014 EFSYS_PROBE(fail4); 2015 fail3: 2016 EFSYS_PROBE(fail3); 2017 fail2: 2018 EFSYS_PROBE(fail2); 2019 fail1: 2020 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2021 2022 return (rc); 2023 } 2024 2025 __checkReturn efx_rc_t 2026 efx_mcdi_entity_reset( 2027 __in efx_nic_t *enp) 2028 { 2029 efx_mcdi_req_t req; 2030 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN, 2031 MC_CMD_ENTITY_RESET_OUT_LEN); 2032 efx_rc_t rc; 2033 2034 req.emr_cmd = MC_CMD_ENTITY_RESET; 2035 req.emr_in_buf = payload; 2036 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN; 2037 req.emr_out_buf = payload; 2038 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN; 2039 2040 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG, 2041 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1); 2042 2043 efx_mcdi_execute(enp, &req); 2044 2045 if (req.emr_rc != 0) { 2046 rc = req.emr_rc; 2047 goto fail1; 2048 } 2049 2050 return (0); 2051 2052 fail1: 2053 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2054 2055 return (rc); 2056 } 2057 2058 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 2059 2060 #if EFX_OPTS_EF10() 2061 2062 static __checkReturn efx_rc_t 2063 ef10_set_workaround_bug26807( 2064 __in efx_nic_t *enp) 2065 { 2066 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2067 uint32_t flags; 2068 efx_rc_t rc; 2069 2070 /* 2071 * If the bug26807 workaround is enabled, then firmware has enabled 2072 * support for chained multicast filters. Firmware will reset (FLR) 2073 * functions which have filters in the hardware filter table when the 2074 * workaround is enabled/disabled. 2075 * 2076 * We must recheck if the workaround is enabled after inserting the 2077 * first hardware filter, in case it has been changed since this check. 2078 */ 2079 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, 2080 B_TRUE, &flags); 2081 if (rc == 0) { 2082 encp->enc_bug26807_workaround = B_TRUE; 2083 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { 2084 /* 2085 * Other functions had installed filters before the 2086 * workaround was enabled, and they have been reset 2087 * by firmware. 2088 */ 2089 EFSYS_PROBE(bug26807_workaround_flr_done); 2090 /* FIXME: bump MC warm boot count ? */ 2091 } 2092 } else if (rc == EACCES) { 2093 /* 2094 * Unprivileged functions cannot enable the workaround in older 2095 * firmware. 2096 */ 2097 encp->enc_bug26807_workaround = B_FALSE; 2098 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 2099 encp->enc_bug26807_workaround = B_FALSE; 2100 } else { 2101 goto fail1; 2102 } 2103 2104 return (0); 2105 2106 fail1: 2107 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2108 2109 return (rc); 2110 } 2111 2112 static __checkReturn efx_rc_t 2113 ef10_nic_board_cfg( 2114 __in efx_nic_t *enp) 2115 { 2116 const efx_nic_ops_t *enop = enp->en_enop; 2117 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2118 efx_rc_t rc; 2119 2120 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0) 2121 goto fail1; 2122 2123 /* 2124 * Huntington RXDP firmware inserts a 0 or 14 byte prefix. 2125 * We only support the 14 byte prefix here. 2126 */ 2127 if (encp->enc_rx_prefix_size != 14) { 2128 rc = ENOTSUP; 2129 goto fail2; 2130 } 2131 2132 encp->enc_clk_mult = 1; /* not used for EF10 */ 2133 2134 /* Alignment for WPTR updates */ 2135 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 2136 2137 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); 2138 /* No boundary crossing limits */ 2139 encp->enc_tx_dma_desc_boundary = 0; 2140 2141 /* 2142 * Maximum number of bytes into the frame the TCP header can start for 2143 * firmware assisted TSO to work. 2144 */ 2145 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 2146 2147 /* EF10 TSO engine demands that packet header be contiguous. */ 2148 encp->enc_tx_tso_max_header_ndescs = 1; 2149 2150 /* The overall TSO header length is not limited. */ 2151 encp->enc_tx_tso_max_header_length = UINT32_MAX; 2152 2153 /* 2154 * There are no specific limitations on the number of 2155 * TSO payload descriptors. 2156 */ 2157 encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX; 2158 2159 /* TSO superframe payload length is not limited. */ 2160 encp->enc_tx_tso_max_payload_length = UINT32_MAX; 2161 2162 /* 2163 * Limitation on the maximum number of outgoing packets per 2164 * TSO transaction described in SF-108452-SW. 2165 */ 2166 encp->enc_tx_tso_max_nframes = 32767; 2167 2168 /* 2169 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 2170 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 2171 * resources (allocated to this PCIe function), which is zero until 2172 * after we have allocated VIs. 2173 */ 2174 encp->enc_evq_limit = 1024; 2175 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 2176 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 2177 2178 encp->enc_buftbl_limit = UINT32_MAX; 2179 2180 if ((rc = ef10_set_workaround_bug26807(enp)) != 0) 2181 goto fail3; 2182 2183 /* Get remaining controller-specific board config */ 2184 if ((rc = enop->eno_board_cfg(enp)) != 0) 2185 if (rc != EACCES) 2186 goto fail4; 2187 2188 return (0); 2189 2190 fail4: 2191 EFSYS_PROBE(fail4); 2192 fail3: 2193 EFSYS_PROBE(fail3); 2194 fail2: 2195 EFSYS_PROBE(fail2); 2196 fail1: 2197 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2198 2199 return (rc); 2200 } 2201 2202 __checkReturn efx_rc_t 2203 ef10_nic_probe( 2204 __in efx_nic_t *enp) 2205 { 2206 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2207 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); 2208 efx_rc_t rc; 2209 2210 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2211 2212 /* Read and clear any assertion state */ 2213 if ((rc = efx_mcdi_read_assertion(enp)) != 0) 2214 goto fail1; 2215 2216 /* Exit the assertion handler */ 2217 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) 2218 if (rc != EACCES) 2219 goto fail2; 2220 2221 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0) 2222 goto fail3; 2223 2224 if ((rc = ef10_nic_board_cfg(enp)) != 0) 2225 goto fail4; 2226 2227 /* 2228 * Set default driver config limits (based on board config). 2229 * 2230 * FIXME: For now allocate a fixed number of VIs which is likely to be 2231 * sufficient and small enough to allow multiple functions on the same 2232 * port. 2233 */ 2234 edcp->edc_min_vi_count = edcp->edc_max_vi_count = 2235 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit)); 2236 2237 /* The client driver must configure and enable PIO buffer support */ 2238 edcp->edc_max_piobuf_count = 0; 2239 edcp->edc_pio_alloc_size = 0; 2240 2241 #if EFSYS_OPT_MAC_STATS 2242 /* Wipe the MAC statistics */ 2243 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0) 2244 goto fail5; 2245 #endif 2246 2247 #if EFSYS_OPT_LOOPBACK 2248 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0) 2249 goto fail6; 2250 #endif 2251 2252 #if EFSYS_OPT_MON_STATS 2253 if ((rc = mcdi_mon_cfg_build(enp)) != 0) { 2254 /* Unprivileged functions do not have access to sensors */ 2255 if (rc != EACCES) 2256 goto fail7; 2257 } 2258 #endif 2259 2260 return (0); 2261 2262 #if EFSYS_OPT_MON_STATS 2263 fail7: 2264 EFSYS_PROBE(fail7); 2265 #endif 2266 #if EFSYS_OPT_LOOPBACK 2267 fail6: 2268 EFSYS_PROBE(fail6); 2269 #endif 2270 #if EFSYS_OPT_MAC_STATS 2271 fail5: 2272 EFSYS_PROBE(fail5); 2273 #endif 2274 fail4: 2275 EFSYS_PROBE(fail4); 2276 fail3: 2277 EFSYS_PROBE(fail3); 2278 fail2: 2279 EFSYS_PROBE(fail2); 2280 fail1: 2281 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2282 2283 return (rc); 2284 } 2285 2286 __checkReturn efx_rc_t 2287 ef10_nic_set_drv_limits( 2288 __inout efx_nic_t *enp, 2289 __in efx_drv_limits_t *edlp) 2290 { 2291 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 2292 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); 2293 uint32_t min_evq_count, max_evq_count; 2294 uint32_t min_rxq_count, max_rxq_count; 2295 uint32_t min_txq_count, max_txq_count; 2296 efx_rc_t rc; 2297 2298 if (edlp == NULL) { 2299 rc = EINVAL; 2300 goto fail1; 2301 } 2302 2303 /* Get minimum required and maximum usable VI limits */ 2304 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit); 2305 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit); 2306 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit); 2307 2308 edcp->edc_min_vi_count = 2309 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count)); 2310 2311 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit); 2312 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit); 2313 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit); 2314 2315 edcp->edc_max_vi_count = 2316 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count)); 2317 2318 /* 2319 * Check limits for sub-allocated piobuf blocks. 2320 * PIO is optional, so don't fail if the limits are incorrect. 2321 */ 2322 if ((encp->enc_piobuf_size == 0) || 2323 (encp->enc_piobuf_limit == 0) || 2324 (edlp->edl_min_pio_alloc_size == 0) || 2325 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) { 2326 /* Disable PIO */ 2327 edcp->edc_max_piobuf_count = 0; 2328 edcp->edc_pio_alloc_size = 0; 2329 } else { 2330 uint32_t blk_size, blk_count, blks_per_piobuf; 2331 2332 blk_size = 2333 MAX(edlp->edl_min_pio_alloc_size, 2334 encp->enc_piobuf_min_alloc_size); 2335 2336 blks_per_piobuf = encp->enc_piobuf_size / blk_size; 2337 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32); 2338 2339 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf); 2340 2341 /* A zero max pio alloc count means unlimited */ 2342 if ((edlp->edl_max_pio_alloc_count > 0) && 2343 (edlp->edl_max_pio_alloc_count < blk_count)) { 2344 blk_count = edlp->edl_max_pio_alloc_count; 2345 } 2346 2347 edcp->edc_pio_alloc_size = blk_size; 2348 edcp->edc_max_piobuf_count = 2349 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf; 2350 } 2351 2352 return (0); 2353 2354 fail1: 2355 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2356 2357 return (rc); 2358 } 2359 2360 2361 __checkReturn efx_rc_t 2362 ef10_nic_reset( 2363 __in efx_nic_t *enp) 2364 { 2365 efx_rc_t rc; 2366 2367 /* ef10_nic_reset() is called to recover from BADASSERT failures. */ 2368 if ((rc = efx_mcdi_read_assertion(enp)) != 0) 2369 goto fail1; 2370 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) 2371 goto fail2; 2372 2373 if ((rc = efx_mcdi_entity_reset(enp)) != 0) 2374 goto fail3; 2375 2376 /* Clear RX/TX DMA queue errors */ 2377 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR); 2378 2379 return (0); 2380 2381 fail3: 2382 EFSYS_PROBE(fail3); 2383 fail2: 2384 EFSYS_PROBE(fail2); 2385 fail1: 2386 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2387 2388 return (rc); 2389 } 2390 2391 #endif /* EFX_OPTS_EF10() */ 2392 2393 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 2394 2395 __checkReturn efx_rc_t 2396 ef10_upstream_port_vadaptor_alloc( 2397 __in efx_nic_t *enp) 2398 { 2399 uint32_t retry; 2400 uint32_t delay_us; 2401 efx_rc_t rc; 2402 2403 /* 2404 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF 2405 * driver has yet to bring up the EVB port. See bug 56147. In this case, 2406 * retry the request several times after waiting a while. The wait time 2407 * between retries starts small (10ms) and exponentially increases. 2408 * Total wait time is a little over two seconds. Retry logic in the 2409 * client driver may mean this whole loop is repeated if it continues to 2410 * fail. 2411 */ 2412 retry = 0; 2413 delay_us = 10000; 2414 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) { 2415 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) || 2416 (rc != ENOENT)) { 2417 /* 2418 * Do not retry alloc for PF, or for other errors on 2419 * a VF. 2420 */ 2421 goto fail1; 2422 } 2423 2424 /* VF startup before PF is ready. Retry allocation. */ 2425 if (retry > 5) { 2426 /* Too many attempts */ 2427 rc = EINVAL; 2428 goto fail2; 2429 } 2430 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry); 2431 EFSYS_SLEEP(delay_us); 2432 retry++; 2433 if (delay_us < 500000) 2434 delay_us <<= 2; 2435 } 2436 2437 return (0); 2438 2439 fail2: 2440 EFSYS_PROBE(fail2); 2441 fail1: 2442 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2443 2444 return (rc); 2445 } 2446 2447 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 2448 2449 #if EFX_OPTS_EF10() 2450 2451 __checkReturn efx_rc_t 2452 ef10_nic_init( 2453 __in efx_nic_t *enp) 2454 { 2455 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); 2456 uint32_t min_vi_count, max_vi_count; 2457 uint32_t vi_count, vi_base, vi_shift; 2458 uint32_t i; 2459 uint32_t vi_window_size; 2460 efx_rc_t rc; 2461 boolean_t alloc_vadaptor = B_TRUE; 2462 2463 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2464 2465 /* Enable reporting of some events (e.g. link change) */ 2466 if ((rc = efx_mcdi_log_ctrl(enp)) != 0) 2467 goto fail1; 2468 2469 /* Allocate (optional) on-chip PIO buffers */ 2470 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count); 2471 2472 /* 2473 * For best performance, PIO writes should use a write-combined 2474 * (WC) memory mapping. Using a separate WC mapping for the PIO 2475 * aperture of each VI would be a burden to drivers (and not 2476 * possible if the host page size is >4Kbyte). 2477 * 2478 * To avoid this we use a single uncached (UC) mapping for VI 2479 * register access, and a single WC mapping for extra VIs used 2480 * for PIO writes. 2481 * 2482 * Each piobuf must be linked to a VI in the WC mapping, and to 2483 * each VI that is using a sub-allocated block from the piobuf. 2484 */ 2485 min_vi_count = edcp->edc_min_vi_count; 2486 max_vi_count = 2487 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count; 2488 2489 /* Ensure that the previously attached driver's VIs are freed */ 2490 if ((rc = efx_mcdi_free_vis(enp)) != 0) 2491 goto fail2; 2492 2493 /* 2494 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this 2495 * fails then retrying the request for fewer VI resources may succeed. 2496 */ 2497 vi_count = 0; 2498 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count, 2499 &vi_base, &vi_count, &vi_shift)) != 0) 2500 goto fail3; 2501 2502 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count); 2503 2504 if (vi_count < min_vi_count) { 2505 rc = ENOMEM; 2506 goto fail4; 2507 } 2508 2509 enp->en_arch.ef10.ena_vi_base = vi_base; 2510 enp->en_arch.ef10.ena_vi_count = vi_count; 2511 enp->en_arch.ef10.ena_vi_shift = vi_shift; 2512 2513 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) { 2514 /* Not enough extra VIs to map piobufs */ 2515 ef10_nic_free_piobufs(enp); 2516 } 2517 2518 enp->en_arch.ef10.ena_pio_write_vi_base = 2519 vi_count - enp->en_arch.ef10.ena_piobuf_count; 2520 2521 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=, 2522 EFX_VI_WINDOW_SHIFT_INVALID); 2523 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=, 2524 EFX_VI_WINDOW_SHIFT_64K); 2525 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift; 2526 2527 /* Save UC memory mapping details */ 2528 enp->en_arch.ef10.ena_uc_mem_map_offset = 0; 2529 if (enp->en_arch.ef10.ena_piobuf_count > 0) { 2530 enp->en_arch.ef10.ena_uc_mem_map_size = 2531 (vi_window_size * 2532 enp->en_arch.ef10.ena_pio_write_vi_base); 2533 } else { 2534 enp->en_arch.ef10.ena_uc_mem_map_size = 2535 (vi_window_size * 2536 enp->en_arch.ef10.ena_vi_count); 2537 } 2538 2539 /* Save WC memory mapping details */ 2540 enp->en_arch.ef10.ena_wc_mem_map_offset = 2541 enp->en_arch.ef10.ena_uc_mem_map_offset + 2542 enp->en_arch.ef10.ena_uc_mem_map_size; 2543 2544 enp->en_arch.ef10.ena_wc_mem_map_size = 2545 (vi_window_size * 2546 enp->en_arch.ef10.ena_piobuf_count); 2547 2548 /* Link piobufs to extra VIs in WC mapping */ 2549 if (enp->en_arch.ef10.ena_piobuf_count > 0) { 2550 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 2551 rc = efx_mcdi_link_piobuf(enp, 2552 enp->en_arch.ef10.ena_pio_write_vi_base + i, 2553 enp->en_arch.ef10.ena_piobuf_handle[i]); 2554 if (rc != 0) 2555 break; 2556 } 2557 } 2558 2559 /* 2560 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs 2561 * during NIC initialization when vSwitch is created and vports are 2562 * allocated. Hence, skip vAdaptor allocation for EVB and update vport 2563 * id in NIC structure with the one allocated for PF. 2564 */ 2565 2566 enp->en_vport_id = EVB_PORT_ID_ASSIGNED; 2567 #if EFSYS_OPT_EVB 2568 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) { 2569 /* For EVB use vport allocated on vswitch */ 2570 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id; 2571 alloc_vadaptor = B_FALSE; 2572 } 2573 #endif 2574 if (alloc_vadaptor != B_FALSE) { 2575 /* Allocate a vAdaptor attached to our upstream vPort/pPort */ 2576 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0) 2577 goto fail5; 2578 } 2579 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2; 2580 2581 return (0); 2582 2583 fail5: 2584 EFSYS_PROBE(fail5); 2585 fail4: 2586 EFSYS_PROBE(fail4); 2587 fail3: 2588 EFSYS_PROBE(fail3); 2589 fail2: 2590 EFSYS_PROBE(fail2); 2591 2592 ef10_nic_free_piobufs(enp); 2593 2594 fail1: 2595 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2596 2597 return (rc); 2598 } 2599 2600 __checkReturn efx_rc_t 2601 ef10_nic_get_vi_pool( 2602 __in efx_nic_t *enp, 2603 __out uint32_t *vi_countp) 2604 { 2605 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2606 2607 /* 2608 * Report VIs that the client driver can use. 2609 * Do not include VIs used for PIO buffer writes. 2610 */ 2611 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base; 2612 2613 return (0); 2614 } 2615 2616 __checkReturn efx_rc_t 2617 ef10_nic_get_bar_region( 2618 __in efx_nic_t *enp, 2619 __in efx_nic_region_t region, 2620 __out uint32_t *offsetp, 2621 __out size_t *sizep) 2622 { 2623 efx_rc_t rc; 2624 2625 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp)); 2626 2627 /* 2628 * TODO: Specify host memory mapping alignment and granularity 2629 * in efx_drv_limits_t so that they can be taken into account 2630 * when allocating extra VIs for PIO writes. 2631 */ 2632 switch (region) { 2633 case EFX_REGION_VI: 2634 /* UC mapped memory BAR region for VI registers */ 2635 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset; 2636 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size; 2637 break; 2638 2639 case EFX_REGION_PIO_WRITE_VI: 2640 /* WC mapped memory BAR region for piobuf writes */ 2641 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset; 2642 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size; 2643 break; 2644 2645 default: 2646 rc = EINVAL; 2647 goto fail1; 2648 } 2649 2650 return (0); 2651 2652 fail1: 2653 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2654 2655 return (rc); 2656 } 2657 2658 __checkReturn boolean_t 2659 ef10_nic_hw_unavailable( 2660 __in efx_nic_t *enp) 2661 { 2662 efx_dword_t dword; 2663 2664 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL) 2665 return (B_TRUE); 2666 2667 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE); 2668 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff) 2669 goto unavail; 2670 2671 return (B_FALSE); 2672 2673 unavail: 2674 ef10_nic_set_hw_unavailable(enp); 2675 2676 return (B_TRUE); 2677 } 2678 2679 void 2680 ef10_nic_set_hw_unavailable( 2681 __in efx_nic_t *enp) 2682 { 2683 EFSYS_PROBE(hw_unavail); 2684 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL; 2685 } 2686 2687 2688 void 2689 ef10_nic_fini( 2690 __in efx_nic_t *enp) 2691 { 2692 uint32_t i; 2693 efx_rc_t rc; 2694 boolean_t do_vadaptor_free = B_TRUE; 2695 2696 #if EFSYS_OPT_EVB 2697 if (enp->en_vswitchp != NULL) { 2698 /* 2699 * For SR-IOV the vAdaptor is freed with the vswitch, 2700 * so do not free it here. 2701 */ 2702 do_vadaptor_free = B_FALSE; 2703 } 2704 #endif 2705 if (do_vadaptor_free != B_FALSE) { 2706 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id); 2707 enp->en_vport_id = EVB_PORT_ID_NULL; 2708 } 2709 2710 /* Unlink piobufs from extra VIs in WC mapping */ 2711 if (enp->en_arch.ef10.ena_piobuf_count > 0) { 2712 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { 2713 rc = efx_mcdi_unlink_piobuf(enp, 2714 enp->en_arch.ef10.ena_pio_write_vi_base + i); 2715 if (rc != 0) 2716 break; 2717 } 2718 } 2719 2720 ef10_nic_free_piobufs(enp); 2721 2722 (void) efx_mcdi_free_vis(enp); 2723 enp->en_arch.ef10.ena_vi_count = 0; 2724 } 2725 2726 void 2727 ef10_nic_unprobe( 2728 __in efx_nic_t *enp) 2729 { 2730 #if EFSYS_OPT_MON_STATS 2731 mcdi_mon_cfg_free(enp); 2732 #endif /* EFSYS_OPT_MON_STATS */ 2733 (void) efx_mcdi_drv_attach(enp, B_FALSE); 2734 } 2735 2736 #if EFSYS_OPT_DIAG 2737 2738 __checkReturn efx_rc_t 2739 ef10_nic_register_test( 2740 __in efx_nic_t *enp) 2741 { 2742 efx_rc_t rc; 2743 2744 /* FIXME */ 2745 _NOTE(ARGUNUSED(enp)) 2746 _NOTE(CONSTANTCONDITION) 2747 if (B_FALSE) { 2748 rc = ENOTSUP; 2749 goto fail1; 2750 } 2751 /* FIXME */ 2752 2753 return (0); 2754 2755 fail1: 2756 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2757 2758 return (rc); 2759 } 2760 2761 #endif /* EFSYS_OPT_DIAG */ 2762 2763 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 2764 2765 __checkReturn efx_rc_t 2766 efx_mcdi_get_nic_global( 2767 __in efx_nic_t *enp, 2768 __in uint32_t key, 2769 __out uint32_t *valuep) 2770 { 2771 efx_mcdi_req_t req; 2772 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN, 2773 MC_CMD_GET_NIC_GLOBAL_OUT_LEN); 2774 efx_rc_t rc; 2775 2776 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL; 2777 req.emr_in_buf = payload; 2778 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN; 2779 req.emr_out_buf = payload; 2780 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN; 2781 2782 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key); 2783 2784 efx_mcdi_execute(enp, &req); 2785 2786 if (req.emr_rc != 0) { 2787 rc = req.emr_rc; 2788 goto fail1; 2789 } 2790 2791 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) { 2792 rc = EMSGSIZE; 2793 goto fail2; 2794 } 2795 2796 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE); 2797 2798 return (0); 2799 2800 fail2: 2801 EFSYS_PROBE(fail2); 2802 fail1: 2803 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2804 2805 return (rc); 2806 } 2807 2808 __checkReturn efx_rc_t 2809 efx_mcdi_set_nic_global( 2810 __in efx_nic_t *enp, 2811 __in uint32_t key, 2812 __in uint32_t value) 2813 { 2814 efx_mcdi_req_t req; 2815 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0); 2816 efx_rc_t rc; 2817 2818 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL; 2819 req.emr_in_buf = payload; 2820 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN; 2821 req.emr_out_buf = NULL; 2822 req.emr_out_length = 0; 2823 2824 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key); 2825 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value); 2826 2827 efx_mcdi_execute(enp, &req); 2828 2829 if (req.emr_rc != 0) { 2830 rc = req.emr_rc; 2831 goto fail1; 2832 } 2833 2834 return (0); 2835 2836 fail1: 2837 EFSYS_PROBE1(fail1, efx_rc_t, rc); 2838 2839 return (rc); 2840 } 2841 2842 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 2843 2844 #endif /* EFX_OPTS_EF10() */ 2845