1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE solicited event. */ 30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 31 32 /* Invalidate a CQE. */ 33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 34 35 /* Hardware index widths. */ 36 #define MLX5_CQ_INDEX_WIDTH 24 37 #define MLX5_WQ_INDEX_WIDTH 16 38 39 /* WQE Segment sizes in bytes. */ 40 #define MLX5_WSEG_SIZE 16u 41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 44 45 /* WQE/WQEBB size in bytes. */ 46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 47 48 /* 49 * Max size of a WQE session. 50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 51 * the WQE size field in Control Segment is 6 bits wide. 52 */ 53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 54 55 /* 56 * Default minimum number of Tx queues for inlining packets. 57 * If there are less queues as specified we assume we have 58 * no enough CPU resources (cycles) to perform inlining, 59 * the PCIe throughput is not supposed as bottleneck and 60 * inlining is disabled. 61 */ 62 #define MLX5_INLINE_MAX_TXQS 8u 63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 64 65 /* 66 * Default packet length threshold to be inlined with 67 * enhanced MPW. If packet length exceeds the threshold 68 * the data are not inlined. Should be aligned in WQEBB 69 * boundary with accounting the title Control and Ethernet 70 * segments. 71 */ 72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 73 MLX5_DSEG_MIN_INLINE_SIZE) 74 /* 75 * Maximal inline data length sent with enhanced MPW. 76 * Is based on maximal WQE size. 77 */ 78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 79 MLX5_WQE_CSEG_SIZE - \ 80 MLX5_WQE_ESEG_SIZE - \ 81 MLX5_WQE_DSEG_SIZE + \ 82 MLX5_DSEG_MIN_INLINE_SIZE) 83 /* 84 * Minimal amount of packets to be sent with EMPW. 85 * This limits the minimal required size of sent EMPW. 86 * If there are no enough resources to built minimal 87 * EMPW the sending loop exits. 88 */ 89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 90 /* 91 * Maximal amount of packets to be sent with EMPW. 92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 94 * without CQE generation request, being multiplied by 95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 96 * in tx burst routine at the moment of freeing multiple mbufs. 97 */ 98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 99 #define MLX5_MPW_MAX_PACKETS 6 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6 101 102 /* 103 * Default packet length threshold to be inlined with 104 * ordinary SEND. Inlining saves the MR key search 105 * and extra PCIe data fetch transaction, but eats the 106 * CPU cycles. 107 */ 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 109 MLX5_ESEG_MIN_INLINE_SIZE - \ 110 MLX5_WQE_CSEG_SIZE - \ 111 MLX5_WQE_ESEG_SIZE - \ 112 MLX5_WQE_DSEG_SIZE) 113 /* 114 * Maximal inline data length sent with ordinary SEND. 115 * Is based on maximal WQE size. 116 */ 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 118 MLX5_WQE_CSEG_SIZE - \ 119 MLX5_WQE_ESEG_SIZE - \ 120 MLX5_WQE_DSEG_SIZE + \ 121 MLX5_ESEG_MIN_INLINE_SIZE) 122 123 /* Missed in mlx5dv.h, should define here. */ 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 126 #endif 127 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN 129 #define MLX5_OPCODE_SEND_EN 0x17u 130 #endif 131 132 #ifndef HAVE_MLX5_OPCODE_WAIT 133 #define MLX5_OPCODE_WAIT 0x0fu 134 #endif 135 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du 138 #endif 139 140 /* CQE value to inform that VLAN is stripped. */ 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 142 143 /* IPv4 options. */ 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 145 146 /* IPv6 packet. */ 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 148 149 /* IPv4 packet. */ 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 151 152 /* TCP packet. */ 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 154 155 /* UDP packet. */ 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 157 158 /* IP is fragmented. */ 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 160 161 /* L2 header is valid. */ 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 163 164 /* L3 header is valid. */ 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 166 167 /* L4 header is valid. */ 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 169 170 /* Outer packet, 0 IPv4, 1 IPv6. */ 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 172 173 /* Tunnel packet bit in the CQE. */ 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 175 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40 178 179 /* Mask for L4 type in the CQE hdr_type_etc field. */ 180 #define MLX5_CQE_L4_TYPE_MASK 0x70 181 182 /* The bit index of L4 type in CQE hdr_type_etc field. */ 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 184 185 /* L4 type to indicate TCP packet without acknowledgment. */ 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 187 188 /* L4 type to indicate TCP packet with acknowledgment. */ 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 190 191 /* Inner L3 checksum offload (Tunneled packets only). */ 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 193 194 /* Inner L4 checksum offload (Tunneled packets only). */ 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 196 197 /* Outer L4 type is TCP. */ 198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 199 200 /* Outer L4 type is UDP. */ 201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 202 203 /* Outer L3 type is IPV4. */ 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 205 206 /* Outer L3 type is IPV6. */ 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 208 209 /* Inner L4 type is TCP. */ 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 211 212 /* Inner L4 type is UDP. */ 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 214 215 /* Inner L3 type is IPV4. */ 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 217 218 /* Inner L3 type is IPV6. */ 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 220 221 /* VLAN insertion flag. */ 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 223 224 /* Data inline segment flag. */ 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 226 227 /* Is flow mark valid. */ 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 230 #else 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 232 #endif 233 234 /* INVALID is used by packets matching no flow rules. */ 235 #define MLX5_FLOW_MARK_INVALID 0 236 237 /* Maximum allowed value to mark a packet. */ 238 #define MLX5_FLOW_MARK_MAX 0xfffff0 239 240 /* Default mark value used when none is provided. */ 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 242 243 /* Default mark mask for metadata legacy mode. */ 244 #define MLX5_FLOW_MARK_MASK 0xffffff 245 246 /* Byte length mask when mark is enable in miniCQE */ 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 248 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 250 #define MLX5_DSEG_MAX 63 251 252 /* The completion mode offset in the WQE control segment line 2. */ 253 #define MLX5_COMP_MODE_OFFSET 2 254 255 /* Amount of data bytes in minimal inline data segment. */ 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 257 258 /* Amount of data bytes in minimal inline eth segment. */ 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 260 261 /* Amount of data bytes after eth data segment. */ 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 263 264 /* The maximum log value of segments per RQ WQE. */ 265 #define MLX5_MAX_LOG_RQ_SEGS 5u 266 267 /* The alignment needed for WQ buffer. */ 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 269 270 /* The alignment needed for CQ buffer. */ 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 272 273 /* Completion mode. */ 274 enum mlx5_completion_mode { 275 MLX5_COMP_ONLY_ERR = 0x0, 276 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 277 MLX5_COMP_ALWAYS = 0x2, 278 MLX5_COMP_CQE_AND_EQE = 0x3, 279 }; 280 281 /* MPW mode. */ 282 enum mlx5_mpw_mode { 283 MLX5_MPW_DISABLED, 284 MLX5_MPW, 285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 286 }; 287 288 /* WQE Control segment. */ 289 struct mlx5_wqe_cseg { 290 uint32_t opcode; 291 uint32_t sq_ds; 292 uint32_t flags; 293 uint32_t misc; 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 295 296 /* 297 * WQE CSEG opcode field size is 32 bits, divided: 298 * Bits 31:24 OPC_MOD 299 * Bits 23:8 wqe_index 300 * Bits 7:0 OPCODE 301 */ 302 #define WQE_CSEG_OPC_MOD_OFFSET 24 303 #define WQE_CSEG_WQE_INDEX_OFFSET 8 304 305 /* Header of data segment. Minimal size Data Segment */ 306 struct mlx5_wqe_dseg { 307 uint32_t bcount; 308 union { 309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 310 struct { 311 uint32_t lkey; 312 uint64_t pbuf; 313 } __rte_packed; 314 }; 315 } __rte_packed; 316 317 /* Subset of struct WQE Ethernet Segment. */ 318 struct mlx5_wqe_eseg { 319 union { 320 struct { 321 uint32_t swp_offs; 322 uint8_t cs_flags; 323 uint8_t swp_flags; 324 uint16_t mss; 325 uint32_t metadata; 326 uint16_t inline_hdr_sz; 327 union { 328 uint16_t inline_data; 329 uint16_t vlan_tag; 330 }; 331 } __rte_packed; 332 struct { 333 uint32_t offsets; 334 uint32_t flags; 335 uint32_t flow_metadata; 336 uint32_t inline_hdr; 337 } __rte_packed; 338 }; 339 } __rte_packed; 340 341 struct mlx5_wqe_qseg { 342 uint32_t reserved0; 343 uint32_t reserved1; 344 uint32_t max_index; 345 uint32_t qpn_cqn; 346 } __rte_packed; 347 348 /* The title WQEBB, header of WQE. */ 349 struct mlx5_wqe { 350 union { 351 struct mlx5_wqe_cseg cseg; 352 uint32_t ctrl[4]; 353 }; 354 struct mlx5_wqe_eseg eseg; 355 union { 356 struct mlx5_wqe_dseg dseg[2]; 357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 358 }; 359 } __rte_packed; 360 361 /* WQE for Multi-Packet RQ. */ 362 struct mlx5_wqe_mprq { 363 struct mlx5_wqe_srq_next_seg next_seg; 364 struct mlx5_wqe_data_seg dseg; 365 }; 366 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff 368 #define MLX5_MPRQ_LEN_SHIFT 0 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000 372 #define MLX5_MPRQ_FILLER_SHIFT 31 373 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 375 376 /* CQ element structure - should be equal to the cache line size */ 377 struct mlx5_cqe { 378 #if (RTE_CACHE_LINE_SIZE == 128) 379 uint8_t padding[64]; 380 #endif 381 uint8_t pkt_info; 382 uint8_t rsvd0; 383 uint16_t wqe_id; 384 uint8_t lro_tcppsh_abort_dupack; 385 uint8_t lro_min_ttl; 386 uint16_t lro_tcp_win; 387 uint32_t lro_ack_seq_num; 388 uint32_t rx_hash_res; 389 uint8_t rx_hash_type; 390 uint8_t rsvd1[3]; 391 uint16_t csum; 392 uint8_t rsvd2[6]; 393 uint16_t hdr_type_etc; 394 uint16_t vlan_info; 395 uint8_t lro_num_seg; 396 uint8_t rsvd3[3]; 397 uint32_t flow_table_metadata; 398 uint8_t rsvd4[4]; 399 uint32_t byte_cnt; 400 uint64_t timestamp; 401 uint32_t sop_drop_qpn; 402 uint16_t wqe_counter; 403 uint8_t rsvd5; 404 uint8_t op_own; 405 }; 406 407 struct mlx5_cqe_ts { 408 uint64_t timestamp; 409 uint32_t sop_drop_qpn; 410 uint16_t wqe_counter; 411 uint8_t rsvd5; 412 uint8_t op_own; 413 }; 414 415 /* GGA */ 416 /* MMO metadata segment */ 417 418 #define MLX5_OPCODE_MMO 0x2fu 419 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 420 #define MLX5_OPC_MOD_MMO_COMP 0x2u 421 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 422 #define MLX5_OPC_MOD_MMO_DMA 0x1u 423 424 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 425 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 426 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 427 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 428 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 429 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 430 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 431 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 432 433 struct mlx5_wqe_metadata_seg { 434 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 435 uint32_t lkey; 436 uint64_t addr; 437 }; 438 439 struct mlx5_gga_wqe { 440 uint32_t opcode; 441 uint32_t sq_ds; 442 uint32_t flags; 443 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ 444 uint32_t gga_ctrl2; 445 uint32_t opaque_lkey; 446 uint64_t opaque_vaddr; 447 struct mlx5_wqe_dseg gather; 448 struct mlx5_wqe_dseg scatter; 449 } __rte_packed; 450 451 struct mlx5_gga_compress_opaque { 452 uint32_t syndrom; 453 uint32_t reserved0; 454 uint32_t scattered_length; 455 uint32_t gathered_length; 456 uint64_t scatter_crc; 457 uint64_t gather_crc; 458 uint32_t crc32; 459 uint32_t adler32; 460 uint8_t reserved1[216]; 461 } __rte_packed; 462 463 struct mlx5_ifc_regexp_mmo_control_bits { 464 uint8_t reserved_at_31[0x2]; 465 uint8_t le[0x1]; 466 uint8_t reserved_at_28[0x1]; 467 uint8_t subset_id_0[0xc]; 468 uint8_t reserved_at_16[0x4]; 469 uint8_t subset_id_1[0xc]; 470 uint8_t ctrl[0x4]; 471 uint8_t subset_id_2[0xc]; 472 uint8_t reserved_at_16_1[0x4]; 473 uint8_t subset_id_3[0xc]; 474 }; 475 476 struct mlx5_ifc_regexp_metadata_bits { 477 uint8_t rof_version[0x10]; 478 uint8_t latency_count[0x10]; 479 uint8_t instruction_count[0x10]; 480 uint8_t primary_thread_count[0x10]; 481 uint8_t match_count[0x8]; 482 uint8_t detected_match_count[0x8]; 483 uint8_t status[0x10]; 484 uint8_t job_id[0x20]; 485 uint8_t reserved[0x80]; 486 }; 487 488 struct mlx5_ifc_regexp_match_tuple_bits { 489 uint8_t length[0x10]; 490 uint8_t start_ptr[0x10]; 491 uint8_t rule_id[0x20]; 492 }; 493 494 /* Adding direct verbs to data-path. */ 495 496 /* CQ sequence number mask. */ 497 #define MLX5_CQ_SQN_MASK 0x3 498 499 /* CQ sequence number index. */ 500 #define MLX5_CQ_SQN_OFFSET 28 501 502 /* CQ doorbell index mask. */ 503 #define MLX5_CI_MASK 0xffffff 504 505 /* CQ doorbell offset. */ 506 #define MLX5_CQ_ARM_DB 1 507 508 /* CQ doorbell offset*/ 509 #define MLX5_CQ_DOORBELL 0x20 510 511 /* CQE format value. */ 512 #define MLX5_COMPRESSED 0x3 513 514 /* CQ doorbell cmd types. */ 515 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 516 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 517 518 /* Action type of header modification. */ 519 enum { 520 MLX5_MODIFICATION_TYPE_SET = 0x1, 521 MLX5_MODIFICATION_TYPE_ADD = 0x2, 522 MLX5_MODIFICATION_TYPE_COPY = 0x3, 523 }; 524 525 /* The field of packet to be modified. */ 526 enum mlx5_modification_field { 527 MLX5_MODI_OUT_NONE = -1, 528 MLX5_MODI_OUT_SMAC_47_16 = 1, 529 MLX5_MODI_OUT_SMAC_15_0, 530 MLX5_MODI_OUT_ETHERTYPE, 531 MLX5_MODI_OUT_DMAC_47_16, 532 MLX5_MODI_OUT_DMAC_15_0, 533 MLX5_MODI_OUT_IP_DSCP, 534 MLX5_MODI_OUT_TCP_FLAGS, 535 MLX5_MODI_OUT_TCP_SPORT, 536 MLX5_MODI_OUT_TCP_DPORT, 537 MLX5_MODI_OUT_IPV4_TTL, 538 MLX5_MODI_OUT_UDP_SPORT, 539 MLX5_MODI_OUT_UDP_DPORT, 540 MLX5_MODI_OUT_SIPV6_127_96, 541 MLX5_MODI_OUT_SIPV6_95_64, 542 MLX5_MODI_OUT_SIPV6_63_32, 543 MLX5_MODI_OUT_SIPV6_31_0, 544 MLX5_MODI_OUT_DIPV6_127_96, 545 MLX5_MODI_OUT_DIPV6_95_64, 546 MLX5_MODI_OUT_DIPV6_63_32, 547 MLX5_MODI_OUT_DIPV6_31_0, 548 MLX5_MODI_OUT_SIPV4, 549 MLX5_MODI_OUT_DIPV4, 550 MLX5_MODI_OUT_FIRST_VID, 551 MLX5_MODI_IN_SMAC_47_16 = 0x31, 552 MLX5_MODI_IN_SMAC_15_0, 553 MLX5_MODI_IN_ETHERTYPE, 554 MLX5_MODI_IN_DMAC_47_16, 555 MLX5_MODI_IN_DMAC_15_0, 556 MLX5_MODI_IN_IP_DSCP, 557 MLX5_MODI_IN_TCP_FLAGS, 558 MLX5_MODI_IN_TCP_SPORT, 559 MLX5_MODI_IN_TCP_DPORT, 560 MLX5_MODI_IN_IPV4_TTL, 561 MLX5_MODI_IN_UDP_SPORT, 562 MLX5_MODI_IN_UDP_DPORT, 563 MLX5_MODI_IN_SIPV6_127_96, 564 MLX5_MODI_IN_SIPV6_95_64, 565 MLX5_MODI_IN_SIPV6_63_32, 566 MLX5_MODI_IN_SIPV6_31_0, 567 MLX5_MODI_IN_DIPV6_127_96, 568 MLX5_MODI_IN_DIPV6_95_64, 569 MLX5_MODI_IN_DIPV6_63_32, 570 MLX5_MODI_IN_DIPV6_31_0, 571 MLX5_MODI_IN_SIPV4, 572 MLX5_MODI_IN_DIPV4, 573 MLX5_MODI_OUT_IPV6_HOPLIMIT, 574 MLX5_MODI_IN_IPV6_HOPLIMIT, 575 MLX5_MODI_META_DATA_REG_A, 576 MLX5_MODI_META_DATA_REG_B = 0x50, 577 MLX5_MODI_META_REG_C_0, 578 MLX5_MODI_META_REG_C_1, 579 MLX5_MODI_META_REG_C_2, 580 MLX5_MODI_META_REG_C_3, 581 MLX5_MODI_META_REG_C_4, 582 MLX5_MODI_META_REG_C_5, 583 MLX5_MODI_META_REG_C_6, 584 MLX5_MODI_META_REG_C_7, 585 MLX5_MODI_OUT_TCP_SEQ_NUM, 586 MLX5_MODI_IN_TCP_SEQ_NUM, 587 MLX5_MODI_OUT_TCP_ACK_NUM, 588 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 589 MLX5_MODI_GTP_TEID = 0x6E, 590 }; 591 592 /* Total number of metadata reg_c's. */ 593 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 594 595 enum modify_reg { 596 REG_NON = 0, 597 REG_A, 598 REG_B, 599 REG_C_0, 600 REG_C_1, 601 REG_C_2, 602 REG_C_3, 603 REG_C_4, 604 REG_C_5, 605 REG_C_6, 606 REG_C_7, 607 }; 608 609 /* Modification sub command. */ 610 struct mlx5_modification_cmd { 611 union { 612 uint32_t data0; 613 struct { 614 unsigned int length:5; 615 unsigned int rsvd0:3; 616 unsigned int offset:5; 617 unsigned int rsvd1:3; 618 unsigned int field:12; 619 unsigned int action_type:4; 620 }; 621 }; 622 union { 623 uint32_t data1; 624 uint8_t data[4]; 625 struct { 626 unsigned int rsvd2:8; 627 unsigned int dst_offset:5; 628 unsigned int rsvd3:3; 629 unsigned int dst_field:12; 630 unsigned int rsvd4:4; 631 }; 632 }; 633 }; 634 635 typedef uint64_t u64; 636 typedef uint32_t u32; 637 typedef uint16_t u16; 638 typedef uint8_t u8; 639 640 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 641 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 642 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 643 (&(__mlx5_nullp(typ)->fld))) 644 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 645 (__mlx5_bit_off(typ, fld) & 0x1f)) 646 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 647 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 648 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 649 __mlx5_dw_bit_off(typ, fld)) 650 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 651 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 652 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 653 (__mlx5_bit_off(typ, fld) & 0xf)) 654 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 655 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 656 __mlx5_16_bit_off(typ, fld)) 657 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 658 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 659 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 660 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 661 662 /* insert a value to a struct */ 663 #define MLX5_SET(typ, p, fld, v) \ 664 do { \ 665 u32 _v = v; \ 666 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 667 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 668 __mlx5_dw_off(typ, fld))) & \ 669 (~__mlx5_dw_mask(typ, fld))) | \ 670 (((_v) & __mlx5_mask(typ, fld)) << \ 671 __mlx5_dw_bit_off(typ, fld))); \ 672 } while (0) 673 674 #define MLX5_SET64(typ, p, fld, v) \ 675 do { \ 676 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 677 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 678 rte_cpu_to_be_64(v); \ 679 } while (0) 680 681 #define MLX5_SET16(typ, p, fld, v) \ 682 do { \ 683 u16 _v = v; \ 684 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 685 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 686 __mlx5_16_off(typ, fld))) & \ 687 (~__mlx5_16_mask(typ, fld))) | \ 688 (((_v) & __mlx5_mask16(typ, fld)) << \ 689 __mlx5_16_bit_off(typ, fld))); \ 690 } while (0) 691 692 #define MLX5_GET_VOLATILE(typ, p, fld) \ 693 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 694 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 695 __mlx5_mask(typ, fld)) 696 #define MLX5_GET(typ, p, fld) \ 697 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 698 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 699 __mlx5_mask(typ, fld)) 700 #define MLX5_GET16(typ, p, fld) \ 701 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 702 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 703 __mlx5_mask16(typ, fld)) 704 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 705 __mlx5_64_off(typ, fld))) 706 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 707 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 708 709 struct mlx5_ifc_fte_match_set_misc_bits { 710 u8 gre_c_present[0x1]; 711 u8 reserved_at_1[0x1]; 712 u8 gre_k_present[0x1]; 713 u8 gre_s_present[0x1]; 714 u8 source_vhci_port[0x4]; 715 u8 source_sqn[0x18]; 716 u8 reserved_at_20[0x10]; 717 u8 source_port[0x10]; 718 u8 outer_second_prio[0x3]; 719 u8 outer_second_cfi[0x1]; 720 u8 outer_second_vid[0xc]; 721 u8 inner_second_prio[0x3]; 722 u8 inner_second_cfi[0x1]; 723 u8 inner_second_vid[0xc]; 724 u8 outer_second_cvlan_tag[0x1]; 725 u8 inner_second_cvlan_tag[0x1]; 726 u8 outer_second_svlan_tag[0x1]; 727 u8 inner_second_svlan_tag[0x1]; 728 u8 reserved_at_64[0xc]; 729 u8 gre_protocol[0x10]; 730 u8 gre_key_h[0x18]; 731 u8 gre_key_l[0x8]; 732 u8 vxlan_vni[0x18]; 733 u8 reserved_at_b8[0x8]; 734 u8 geneve_vni[0x18]; 735 u8 reserved_at_e4[0x7]; 736 u8 geneve_oam[0x1]; 737 u8 reserved_at_e0[0xc]; 738 u8 outer_ipv6_flow_label[0x14]; 739 u8 reserved_at_100[0xc]; 740 u8 inner_ipv6_flow_label[0x14]; 741 u8 reserved_at_120[0xa]; 742 u8 geneve_opt_len[0x6]; 743 u8 geneve_protocol_type[0x10]; 744 u8 reserved_at_140[0xc0]; 745 }; 746 747 struct mlx5_ifc_ipv4_layout_bits { 748 u8 reserved_at_0[0x60]; 749 u8 ipv4[0x20]; 750 }; 751 752 struct mlx5_ifc_ipv6_layout_bits { 753 u8 ipv6[16][0x8]; 754 }; 755 756 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 757 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 758 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 759 u8 reserved_at_0[0x80]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 763 u8 smac_47_16[0x20]; 764 u8 smac_15_0[0x10]; 765 u8 ethertype[0x10]; 766 u8 dmac_47_16[0x20]; 767 u8 dmac_15_0[0x10]; 768 u8 first_prio[0x3]; 769 u8 first_cfi[0x1]; 770 u8 first_vid[0xc]; 771 u8 ip_protocol[0x8]; 772 u8 ip_dscp[0x6]; 773 u8 ip_ecn[0x2]; 774 u8 cvlan_tag[0x1]; 775 u8 svlan_tag[0x1]; 776 u8 frag[0x1]; 777 u8 ip_version[0x4]; 778 u8 tcp_flags[0x9]; 779 u8 tcp_sport[0x10]; 780 u8 tcp_dport[0x10]; 781 u8 reserved_at_c0[0x18]; 782 u8 ip_ttl_hoplimit[0x8]; 783 u8 udp_sport[0x10]; 784 u8 udp_dport[0x10]; 785 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 786 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 787 }; 788 789 struct mlx5_ifc_fte_match_mpls_bits { 790 u8 mpls_label[0x14]; 791 u8 mpls_exp[0x3]; 792 u8 mpls_s_bos[0x1]; 793 u8 mpls_ttl[0x8]; 794 }; 795 796 struct mlx5_ifc_fte_match_set_misc2_bits { 797 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 798 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 799 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 800 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 801 u8 metadata_reg_c_7[0x20]; 802 u8 metadata_reg_c_6[0x20]; 803 u8 metadata_reg_c_5[0x20]; 804 u8 metadata_reg_c_4[0x20]; 805 u8 metadata_reg_c_3[0x20]; 806 u8 metadata_reg_c_2[0x20]; 807 u8 metadata_reg_c_1[0x20]; 808 u8 metadata_reg_c_0[0x20]; 809 u8 metadata_reg_a[0x20]; 810 u8 metadata_reg_b[0x20]; 811 u8 reserved_at_1c0[0x40]; 812 }; 813 814 struct mlx5_ifc_fte_match_set_misc3_bits { 815 u8 inner_tcp_seq_num[0x20]; 816 u8 outer_tcp_seq_num[0x20]; 817 u8 inner_tcp_ack_num[0x20]; 818 u8 outer_tcp_ack_num[0x20]; 819 u8 reserved_at_auto1[0x8]; 820 u8 outer_vxlan_gpe_vni[0x18]; 821 u8 outer_vxlan_gpe_next_protocol[0x8]; 822 u8 outer_vxlan_gpe_flags[0x8]; 823 u8 reserved_at_a8[0x10]; 824 u8 icmp_header_data[0x20]; 825 u8 icmpv6_header_data[0x20]; 826 u8 icmp_type[0x8]; 827 u8 icmp_code[0x8]; 828 u8 icmpv6_type[0x8]; 829 u8 icmpv6_code[0x8]; 830 u8 geneve_tlv_option_0_data[0x20]; 831 u8 gtpu_teid[0x20]; 832 u8 gtpu_msg_type[0x08]; 833 u8 gtpu_msg_flags[0x08]; 834 u8 reserved_at_170[0x10]; 835 u8 gtpu_dw_2[0x20]; 836 u8 gtpu_first_ext_dw_0[0x20]; 837 u8 gtpu_dw_0[0x20]; 838 u8 reserved_at_240[0x20]; 839 840 }; 841 842 struct mlx5_ifc_fte_match_set_misc4_bits { 843 u8 prog_sample_field_value_0[0x20]; 844 u8 prog_sample_field_id_0[0x20]; 845 u8 prog_sample_field_value_1[0x20]; 846 u8 prog_sample_field_id_1[0x20]; 847 u8 prog_sample_field_value_2[0x20]; 848 u8 prog_sample_field_id_2[0x20]; 849 u8 prog_sample_field_value_3[0x20]; 850 u8 prog_sample_field_id_3[0x20]; 851 u8 reserved_at_100[0x100]; 852 }; 853 854 /* Flow matcher. */ 855 struct mlx5_ifc_fte_match_param_bits { 856 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 857 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 858 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 859 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 860 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 861 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 862 /* 863 * Add reserved bit to match the struct size with the size defined in PRM. 864 * This extension is not required in Linux. 865 */ 866 #ifndef HAVE_INFINIBAND_VERBS_H 867 u8 reserved_0[0x400]; 868 #endif 869 }; 870 871 struct mlx5_ifc_dest_format_struct_bits { 872 u8 destination_type[0x8]; 873 u8 destination_id[0x18]; 874 u8 reserved_0[0x20]; 875 }; 876 877 enum { 878 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 879 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 880 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 881 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 882 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 883 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 884 }; 885 886 enum { 887 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 888 MLX5_CMD_OP_CREATE_MKEY = 0x200, 889 MLX5_CMD_OP_CREATE_CQ = 0x400, 890 MLX5_CMD_OP_CREATE_QP = 0x500, 891 MLX5_CMD_OP_RST2INIT_QP = 0x502, 892 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 893 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 894 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 895 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 896 MLX5_CMD_OP_QP_2ERR = 0x507, 897 MLX5_CMD_OP_QP_2RST = 0x50A, 898 MLX5_CMD_OP_QUERY_QP = 0x50B, 899 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 900 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 901 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 902 MLX5_CMD_OP_RESUME_QP = 0x510, 903 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 904 MLX5_CMD_OP_ALLOC_PD = 0x800, 905 MLX5_CMD_OP_DEALLOC_PD = 0x801, 906 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 907 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 908 MLX5_CMD_OP_CREATE_TIR = 0x900, 909 MLX5_CMD_OP_MODIFY_TIR = 0x901, 910 MLX5_CMD_OP_CREATE_SQ = 0X904, 911 MLX5_CMD_OP_MODIFY_SQ = 0X905, 912 MLX5_CMD_OP_CREATE_RQ = 0x908, 913 MLX5_CMD_OP_MODIFY_RQ = 0x909, 914 MLX5_CMD_OP_CREATE_TIS = 0x912, 915 MLX5_CMD_OP_QUERY_TIS = 0x915, 916 MLX5_CMD_OP_CREATE_RQT = 0x916, 917 MLX5_CMD_OP_MODIFY_RQT = 0x917, 918 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 919 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 920 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 921 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 922 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 923 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 924 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 925 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 926 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 927 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 928 }; 929 930 enum { 931 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 932 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 933 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 934 }; 935 936 #define MLX5_ADAPTER_PAGE_SHIFT 12 937 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 938 /** 939 * The batch counter dcs id starts from 0x800000 and none batch counter 940 * starts from 0. As currently, the counter is changed to be indexed by 941 * pool index and the offset of the counter in the pool counters_raw array. 942 * It means now the counter index is same for batch and none batch counter. 943 * Add the 0x800000 batch counter offset to the batch counter index helps 944 * indicate the counter index is from batch or none batch container pool. 945 */ 946 #define MLX5_CNT_BATCH_OFFSET 0x800000 947 948 /* The counter batch query requires ID align with 4. */ 949 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 950 951 /* Flow counters. */ 952 struct mlx5_ifc_alloc_flow_counter_out_bits { 953 u8 status[0x8]; 954 u8 reserved_at_8[0x18]; 955 u8 syndrome[0x20]; 956 u8 flow_counter_id[0x20]; 957 u8 reserved_at_60[0x20]; 958 }; 959 960 struct mlx5_ifc_alloc_flow_counter_in_bits { 961 u8 opcode[0x10]; 962 u8 reserved_at_10[0x10]; 963 u8 reserved_at_20[0x10]; 964 u8 op_mod[0x10]; 965 u8 flow_counter_id[0x20]; 966 u8 reserved_at_40[0x18]; 967 u8 flow_counter_bulk[0x8]; 968 }; 969 970 struct mlx5_ifc_dealloc_flow_counter_out_bits { 971 u8 status[0x8]; 972 u8 reserved_at_8[0x18]; 973 u8 syndrome[0x20]; 974 u8 reserved_at_40[0x40]; 975 }; 976 977 struct mlx5_ifc_dealloc_flow_counter_in_bits { 978 u8 opcode[0x10]; 979 u8 reserved_at_10[0x10]; 980 u8 reserved_at_20[0x10]; 981 u8 op_mod[0x10]; 982 u8 flow_counter_id[0x20]; 983 u8 reserved_at_60[0x20]; 984 }; 985 986 struct mlx5_ifc_traffic_counter_bits { 987 u8 packets[0x40]; 988 u8 octets[0x40]; 989 }; 990 991 struct mlx5_ifc_query_flow_counter_out_bits { 992 u8 status[0x8]; 993 u8 reserved_at_8[0x18]; 994 u8 syndrome[0x20]; 995 u8 reserved_at_40[0x40]; 996 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 997 }; 998 999 struct mlx5_ifc_query_flow_counter_in_bits { 1000 u8 opcode[0x10]; 1001 u8 reserved_at_10[0x10]; 1002 u8 reserved_at_20[0x10]; 1003 u8 op_mod[0x10]; 1004 u8 reserved_at_40[0x20]; 1005 u8 mkey[0x20]; 1006 u8 address[0x40]; 1007 u8 clear[0x1]; 1008 u8 dump_to_memory[0x1]; 1009 u8 num_of_counters[0x1e]; 1010 u8 flow_counter_id[0x20]; 1011 }; 1012 1013 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1014 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1015 1016 1017 struct mlx5_ifc_klm_bits { 1018 u8 byte_count[0x20]; 1019 u8 mkey[0x20]; 1020 u8 address[0x40]; 1021 }; 1022 1023 struct mlx5_ifc_mkc_bits { 1024 u8 reserved_at_0[0x1]; 1025 u8 free[0x1]; 1026 u8 reserved_at_2[0x1]; 1027 u8 access_mode_4_2[0x3]; 1028 u8 reserved_at_6[0x7]; 1029 u8 relaxed_ordering_write[0x1]; 1030 u8 reserved_at_e[0x1]; 1031 u8 small_fence_on_rdma_read_response[0x1]; 1032 u8 umr_en[0x1]; 1033 u8 a[0x1]; 1034 u8 rw[0x1]; 1035 u8 rr[0x1]; 1036 u8 lw[0x1]; 1037 u8 lr[0x1]; 1038 u8 access_mode_1_0[0x2]; 1039 u8 reserved_at_18[0x8]; 1040 1041 u8 qpn[0x18]; 1042 u8 mkey_7_0[0x8]; 1043 1044 u8 reserved_at_40[0x20]; 1045 1046 u8 length64[0x1]; 1047 u8 bsf_en[0x1]; 1048 u8 sync_umr[0x1]; 1049 u8 reserved_at_63[0x2]; 1050 u8 expected_sigerr_count[0x1]; 1051 u8 reserved_at_66[0x1]; 1052 u8 en_rinval[0x1]; 1053 u8 pd[0x18]; 1054 1055 u8 start_addr[0x40]; 1056 1057 u8 len[0x40]; 1058 1059 u8 bsf_octword_size[0x20]; 1060 1061 u8 reserved_at_120[0x80]; 1062 1063 u8 translations_octword_size[0x20]; 1064 1065 u8 reserved_at_1c0[0x19]; 1066 u8 relaxed_ordering_read[0x1]; 1067 u8 reserved_at_1da[0x1]; 1068 u8 log_page_size[0x5]; 1069 1070 u8 reserved_at_1e0[0x20]; 1071 }; 1072 1073 struct mlx5_ifc_create_mkey_out_bits { 1074 u8 status[0x8]; 1075 u8 reserved_at_8[0x18]; 1076 1077 u8 syndrome[0x20]; 1078 1079 u8 reserved_at_40[0x8]; 1080 u8 mkey_index[0x18]; 1081 1082 u8 reserved_at_60[0x20]; 1083 }; 1084 1085 struct mlx5_ifc_create_mkey_in_bits { 1086 u8 opcode[0x10]; 1087 u8 reserved_at_10[0x10]; 1088 1089 u8 reserved_at_20[0x10]; 1090 u8 op_mod[0x10]; 1091 1092 u8 reserved_at_40[0x20]; 1093 1094 u8 pg_access[0x1]; 1095 u8 reserved_at_61[0x1f]; 1096 1097 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1098 1099 u8 reserved_at_280[0x80]; 1100 1101 u8 translations_octword_actual_size[0x20]; 1102 1103 u8 mkey_umem_id[0x20]; 1104 1105 u8 mkey_umem_offset[0x40]; 1106 1107 u8 reserved_at_380[0x500]; 1108 1109 u8 klm_pas_mtt[][0x20]; 1110 }; 1111 1112 enum { 1113 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1114 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1115 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1116 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1117 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1118 }; 1119 1120 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1121 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1122 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1123 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1124 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1125 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1126 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1127 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1128 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1129 (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT) 1130 1131 enum { 1132 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1133 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1134 }; 1135 1136 enum { 1137 MLX5_CAP_INLINE_MODE_L2, 1138 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1139 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1140 }; 1141 1142 enum { 1143 MLX5_INLINE_MODE_NONE, 1144 MLX5_INLINE_MODE_L2, 1145 MLX5_INLINE_MODE_IP, 1146 MLX5_INLINE_MODE_TCP_UDP, 1147 MLX5_INLINE_MODE_RESERVED4, 1148 MLX5_INLINE_MODE_INNER_L2, 1149 MLX5_INLINE_MODE_INNER_IP, 1150 MLX5_INLINE_MODE_INNER_TCP_UDP, 1151 }; 1152 1153 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1154 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1155 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1156 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1157 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1158 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1159 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1160 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1161 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1162 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1163 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1164 1165 struct mlx5_ifc_cmd_hca_cap_bits { 1166 u8 reserved_at_0[0x30]; 1167 u8 vhca_id[0x10]; 1168 u8 reserved_at_40[0x20]; 1169 u8 reserved_at_60[0x3]; 1170 u8 log_regexp_scatter_gather_size[0x5]; 1171 u8 reserved_at_68[0x3]; 1172 u8 log_dma_mmo_size[0x5]; 1173 u8 reserved_at_70[0x3]; 1174 u8 log_compress_mmo_size[0x5]; 1175 u8 reserved_at_78[0x3]; 1176 u8 log_decompress_mmo_size[0x5]; 1177 u8 log_max_srq_sz[0x8]; 1178 u8 log_max_qp_sz[0x8]; 1179 u8 reserved_at_90[0x9]; 1180 u8 wqe_index_ignore_cap[0x1]; 1181 u8 dynamic_qp_allocation[0x1]; 1182 u8 log_max_qp[0x5]; 1183 u8 regexp[0x1]; 1184 u8 reserved_at_a1[0x3]; 1185 u8 regexp_num_of_engines[0x4]; 1186 u8 reserved_at_a8[0x1]; 1187 u8 reg_c_preserve[0x1]; 1188 u8 reserved_at_aa[0x1]; 1189 u8 log_max_srq[0x5]; 1190 u8 reserved_at_b0[0x3]; 1191 u8 regexp_log_crspace_size[0x5]; 1192 u8 reserved_at_b8[0x3]; 1193 u8 scatter_fcs_w_decap_disable[0x1]; 1194 u8 reserved_at_bc[0x4]; 1195 u8 reserved_at_c0[0x8]; 1196 u8 log_max_cq_sz[0x8]; 1197 u8 reserved_at_d0[0xb]; 1198 u8 log_max_cq[0x5]; 1199 u8 log_max_eq_sz[0x8]; 1200 u8 relaxed_ordering_write[0x1]; 1201 u8 relaxed_ordering_read[0x1]; 1202 u8 access_register_user[0x1]; 1203 u8 log_max_mkey[0x5]; 1204 u8 reserved_at_f0[0x8]; 1205 u8 dump_fill_mkey[0x1]; 1206 u8 reserved_at_f9[0x3]; 1207 u8 log_max_eq[0x4]; 1208 u8 max_indirection[0x8]; 1209 u8 fixed_buffer_size[0x1]; 1210 u8 log_max_mrw_sz[0x7]; 1211 u8 force_teardown[0x1]; 1212 u8 reserved_at_111[0x1]; 1213 u8 log_max_bsf_list_size[0x6]; 1214 u8 umr_extended_translation_offset[0x1]; 1215 u8 null_mkey[0x1]; 1216 u8 log_max_klm_list_size[0x6]; 1217 u8 non_wire_sq[0x1]; 1218 u8 reserved_at_121[0x9]; 1219 u8 log_max_ra_req_dc[0x6]; 1220 u8 reserved_at_130[0x3]; 1221 u8 log_max_static_sq_wq[0x5]; 1222 u8 reserved_at_138[0x2]; 1223 u8 log_max_ra_res_dc[0x6]; 1224 u8 reserved_at_140[0xa]; 1225 u8 log_max_ra_req_qp[0x6]; 1226 u8 rtr2rts_qp_counters_set_id[0x1]; 1227 u8 rts2rts_udp_sport[0x1]; 1228 u8 rts2rts_lag_tx_port_affinity[0x1]; 1229 u8 dma_mmo[0x1]; 1230 u8 compress_min_block_size[0x4]; 1231 u8 compress[0x1]; 1232 u8 decompress[0x1]; 1233 u8 log_max_ra_res_qp[0x6]; 1234 u8 end_pad[0x1]; 1235 u8 cc_query_allowed[0x1]; 1236 u8 cc_modify_allowed[0x1]; 1237 u8 start_pad[0x1]; 1238 u8 cache_line_128byte[0x1]; 1239 u8 reserved_at_165[0xa]; 1240 u8 qcam_reg[0x1]; 1241 u8 gid_table_size[0x10]; 1242 u8 out_of_seq_cnt[0x1]; 1243 u8 vport_counters[0x1]; 1244 u8 retransmission_q_counters[0x1]; 1245 u8 debug[0x1]; 1246 u8 modify_rq_counter_set_id[0x1]; 1247 u8 rq_delay_drop[0x1]; 1248 u8 max_qp_cnt[0xa]; 1249 u8 pkey_table_size[0x10]; 1250 u8 vport_group_manager[0x1]; 1251 u8 vhca_group_manager[0x1]; 1252 u8 ib_virt[0x1]; 1253 u8 eth_virt[0x1]; 1254 u8 vnic_env_queue_counters[0x1]; 1255 u8 ets[0x1]; 1256 u8 nic_flow_table[0x1]; 1257 u8 eswitch_manager[0x1]; 1258 u8 device_memory[0x1]; 1259 u8 mcam_reg[0x1]; 1260 u8 pcam_reg[0x1]; 1261 u8 local_ca_ack_delay[0x5]; 1262 u8 port_module_event[0x1]; 1263 u8 enhanced_error_q_counters[0x1]; 1264 u8 ports_check[0x1]; 1265 u8 reserved_at_1b3[0x1]; 1266 u8 disable_link_up[0x1]; 1267 u8 beacon_led[0x1]; 1268 u8 port_type[0x2]; 1269 u8 num_ports[0x8]; 1270 u8 reserved_at_1c0[0x1]; 1271 u8 pps[0x1]; 1272 u8 pps_modify[0x1]; 1273 u8 log_max_msg[0x5]; 1274 u8 reserved_at_1c8[0x4]; 1275 u8 max_tc[0x4]; 1276 u8 temp_warn_event[0x1]; 1277 u8 dcbx[0x1]; 1278 u8 general_notification_event[0x1]; 1279 u8 reserved_at_1d3[0x2]; 1280 u8 fpga[0x1]; 1281 u8 rol_s[0x1]; 1282 u8 rol_g[0x1]; 1283 u8 reserved_at_1d8[0x1]; 1284 u8 wol_s[0x1]; 1285 u8 wol_g[0x1]; 1286 u8 wol_a[0x1]; 1287 u8 wol_b[0x1]; 1288 u8 wol_m[0x1]; 1289 u8 wol_u[0x1]; 1290 u8 wol_p[0x1]; 1291 u8 stat_rate_support[0x10]; 1292 u8 reserved_at_1f0[0xc]; 1293 u8 cqe_version[0x4]; 1294 u8 compact_address_vector[0x1]; 1295 u8 striding_rq[0x1]; 1296 u8 reserved_at_202[0x1]; 1297 u8 ipoib_enhanced_offloads[0x1]; 1298 u8 ipoib_basic_offloads[0x1]; 1299 u8 reserved_at_205[0x1]; 1300 u8 repeated_block_disabled[0x1]; 1301 u8 umr_modify_entity_size_disabled[0x1]; 1302 u8 umr_modify_atomic_disabled[0x1]; 1303 u8 umr_indirect_mkey_disabled[0x1]; 1304 u8 umr_fence[0x2]; 1305 u8 reserved_at_20c[0x3]; 1306 u8 drain_sigerr[0x1]; 1307 u8 cmdif_checksum[0x2]; 1308 u8 sigerr_cqe[0x1]; 1309 u8 reserved_at_213[0x1]; 1310 u8 wq_signature[0x1]; 1311 u8 sctr_data_cqe[0x1]; 1312 u8 reserved_at_216[0x1]; 1313 u8 sho[0x1]; 1314 u8 tph[0x1]; 1315 u8 rf[0x1]; 1316 u8 dct[0x1]; 1317 u8 qos[0x1]; 1318 u8 eth_net_offloads[0x1]; 1319 u8 roce[0x1]; 1320 u8 atomic[0x1]; 1321 u8 reserved_at_21f[0x1]; 1322 u8 cq_oi[0x1]; 1323 u8 cq_resize[0x1]; 1324 u8 cq_moderation[0x1]; 1325 u8 reserved_at_223[0x3]; 1326 u8 cq_eq_remap[0x1]; 1327 u8 pg[0x1]; 1328 u8 block_lb_mc[0x1]; 1329 u8 reserved_at_229[0x1]; 1330 u8 scqe_break_moderation[0x1]; 1331 u8 cq_period_start_from_cqe[0x1]; 1332 u8 cd[0x1]; 1333 u8 reserved_at_22d[0x1]; 1334 u8 apm[0x1]; 1335 u8 vector_calc[0x1]; 1336 u8 umr_ptr_rlky[0x1]; 1337 u8 imaicl[0x1]; 1338 u8 reserved_at_232[0x4]; 1339 u8 qkv[0x1]; 1340 u8 pkv[0x1]; 1341 u8 set_deth_sqpn[0x1]; 1342 u8 reserved_at_239[0x3]; 1343 u8 xrc[0x1]; 1344 u8 ud[0x1]; 1345 u8 uc[0x1]; 1346 u8 rc[0x1]; 1347 u8 uar_4k[0x1]; 1348 u8 reserved_at_241[0x9]; 1349 u8 uar_sz[0x6]; 1350 u8 reserved_at_250[0x8]; 1351 u8 log_pg_sz[0x8]; 1352 u8 bf[0x1]; 1353 u8 driver_version[0x1]; 1354 u8 pad_tx_eth_packet[0x1]; 1355 u8 reserved_at_263[0x8]; 1356 u8 log_bf_reg_size[0x5]; 1357 u8 reserved_at_270[0xb]; 1358 u8 lag_master[0x1]; 1359 u8 num_lag_ports[0x4]; 1360 u8 reserved_at_280[0x10]; 1361 u8 max_wqe_sz_sq[0x10]; 1362 u8 reserved_at_2a0[0x10]; 1363 u8 max_wqe_sz_rq[0x10]; 1364 u8 max_flow_counter_31_16[0x10]; 1365 u8 max_wqe_sz_sq_dc[0x10]; 1366 u8 reserved_at_2e0[0x7]; 1367 u8 max_qp_mcg[0x19]; 1368 u8 reserved_at_300[0x10]; 1369 u8 flow_counter_bulk_alloc[0x08]; 1370 u8 log_max_mcg[0x8]; 1371 u8 reserved_at_320[0x3]; 1372 u8 log_max_transport_domain[0x5]; 1373 u8 reserved_at_328[0x3]; 1374 u8 log_max_pd[0x5]; 1375 u8 reserved_at_330[0xb]; 1376 u8 log_max_xrcd[0x5]; 1377 u8 nic_receive_steering_discard[0x1]; 1378 u8 receive_discard_vport_down[0x1]; 1379 u8 transmit_discard_vport_down[0x1]; 1380 u8 reserved_at_343[0x5]; 1381 u8 log_max_flow_counter_bulk[0x8]; 1382 u8 max_flow_counter_15_0[0x10]; 1383 u8 modify_tis[0x1]; 1384 u8 flow_counters_dump[0x1]; 1385 u8 reserved_at_360[0x1]; 1386 u8 log_max_rq[0x5]; 1387 u8 reserved_at_368[0x3]; 1388 u8 log_max_sq[0x5]; 1389 u8 reserved_at_370[0x3]; 1390 u8 log_max_tir[0x5]; 1391 u8 reserved_at_378[0x3]; 1392 u8 log_max_tis[0x5]; 1393 u8 basic_cyclic_rcv_wqe[0x1]; 1394 u8 reserved_at_381[0x2]; 1395 u8 log_max_rmp[0x5]; 1396 u8 reserved_at_388[0x3]; 1397 u8 log_max_rqt[0x5]; 1398 u8 reserved_at_390[0x3]; 1399 u8 log_max_rqt_size[0x5]; 1400 u8 reserved_at_398[0x3]; 1401 u8 log_max_tis_per_sq[0x5]; 1402 u8 ext_stride_num_range[0x1]; 1403 u8 reserved_at_3a1[0x2]; 1404 u8 log_max_stride_sz_rq[0x5]; 1405 u8 reserved_at_3a8[0x3]; 1406 u8 log_min_stride_sz_rq[0x5]; 1407 u8 reserved_at_3b0[0x3]; 1408 u8 log_max_stride_sz_sq[0x5]; 1409 u8 reserved_at_3b8[0x3]; 1410 u8 log_min_stride_sz_sq[0x5]; 1411 u8 hairpin[0x1]; 1412 u8 reserved_at_3c1[0x2]; 1413 u8 log_max_hairpin_queues[0x5]; 1414 u8 reserved_at_3c8[0x3]; 1415 u8 log_max_hairpin_wq_data_sz[0x5]; 1416 u8 reserved_at_3d0[0x3]; 1417 u8 log_max_hairpin_num_packets[0x5]; 1418 u8 reserved_at_3d8[0x3]; 1419 u8 log_max_wq_sz[0x5]; 1420 u8 nic_vport_change_event[0x1]; 1421 u8 disable_local_lb_uc[0x1]; 1422 u8 disable_local_lb_mc[0x1]; 1423 u8 log_min_hairpin_wq_data_sz[0x5]; 1424 u8 reserved_at_3e8[0x3]; 1425 u8 log_max_vlan_list[0x5]; 1426 u8 reserved_at_3f0[0x3]; 1427 u8 log_max_current_mc_list[0x5]; 1428 u8 reserved_at_3f8[0x3]; 1429 u8 log_max_current_uc_list[0x5]; 1430 u8 general_obj_types[0x40]; 1431 u8 reserved_at_440[0x20]; 1432 u8 reserved_at_460[0x10]; 1433 u8 max_num_eqs[0x10]; 1434 u8 reserved_at_480[0x3]; 1435 u8 log_max_l2_table[0x5]; 1436 u8 reserved_at_488[0x8]; 1437 u8 log_uar_page_sz[0x10]; 1438 u8 reserved_at_4a0[0x20]; 1439 u8 device_frequency_mhz[0x20]; 1440 u8 device_frequency_khz[0x20]; 1441 u8 reserved_at_500[0x20]; 1442 u8 num_of_uars_per_page[0x20]; 1443 u8 flex_parser_protocols[0x20]; 1444 u8 max_geneve_tlv_options[0x8]; 1445 u8 reserved_at_568[0x3]; 1446 u8 max_geneve_tlv_option_data_len[0x5]; 1447 u8 reserved_at_570[0x4c]; 1448 u8 mini_cqe_resp_stride_index[0x1]; 1449 u8 cqe_128_always[0x1]; 1450 u8 cqe_compression_128[0x1]; 1451 u8 cqe_compression[0x1]; 1452 u8 cqe_compression_timeout[0x10]; 1453 u8 cqe_compression_max_num[0x10]; 1454 u8 reserved_at_5e0[0x10]; 1455 u8 tag_matching[0x1]; 1456 u8 rndv_offload_rc[0x1]; 1457 u8 rndv_offload_dc[0x1]; 1458 u8 log_tag_matching_list_sz[0x5]; 1459 u8 reserved_at_5f8[0x3]; 1460 u8 log_max_xrq[0x5]; 1461 u8 affiliate_nic_vport_criteria[0x8]; 1462 u8 native_port_num[0x8]; 1463 u8 num_vhca_ports[0x8]; 1464 u8 reserved_at_618[0x6]; 1465 u8 sw_owner_id[0x1]; 1466 u8 reserved_at_61f[0x1e1]; 1467 }; 1468 1469 struct mlx5_ifc_qos_cap_bits { 1470 u8 packet_pacing[0x1]; 1471 u8 esw_scheduling[0x1]; 1472 u8 esw_bw_share[0x1]; 1473 u8 esw_rate_limit[0x1]; 1474 u8 reserved_at_4[0x1]; 1475 u8 packet_pacing_burst_bound[0x1]; 1476 u8 packet_pacing_typical_size[0x1]; 1477 u8 flow_meter_srtcm[0x1]; 1478 u8 reserved_at_8[0x8]; 1479 u8 log_max_flow_meter[0x8]; 1480 u8 flow_meter_reg_id[0x8]; 1481 u8 wqe_rate_pp[0x1]; 1482 u8 reserved_at_25[0x7]; 1483 u8 flow_meter_reg_share[0x1]; 1484 u8 reserved_at_2e[0x17]; 1485 u8 packet_pacing_max_rate[0x20]; 1486 u8 packet_pacing_min_rate[0x20]; 1487 u8 reserved_at_80[0x10]; 1488 u8 packet_pacing_rate_table_size[0x10]; 1489 u8 esw_element_type[0x10]; 1490 u8 esw_tsar_type[0x10]; 1491 u8 reserved_at_c0[0x10]; 1492 u8 max_qos_para_vport[0x10]; 1493 u8 max_tsar_bw_share[0x20]; 1494 u8 reserved_at_100[0x6e8]; 1495 }; 1496 1497 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1498 u8 csum_cap[0x1]; 1499 u8 vlan_cap[0x1]; 1500 u8 lro_cap[0x1]; 1501 u8 lro_psh_flag[0x1]; 1502 u8 lro_time_stamp[0x1]; 1503 u8 lro_max_msg_sz_mode[0x2]; 1504 u8 wqe_vlan_insert[0x1]; 1505 u8 self_lb_en_modifiable[0x1]; 1506 u8 self_lb_mc[0x1]; 1507 u8 self_lb_uc[0x1]; 1508 u8 max_lso_cap[0x5]; 1509 u8 multi_pkt_send_wqe[0x2]; 1510 u8 wqe_inline_mode[0x2]; 1511 u8 rss_ind_tbl_cap[0x4]; 1512 u8 reg_umr_sq[0x1]; 1513 u8 scatter_fcs[0x1]; 1514 u8 enhanced_multi_pkt_send_wqe[0x1]; 1515 u8 tunnel_lso_const_out_ip_id[0x1]; 1516 u8 tunnel_lro_gre[0x1]; 1517 u8 tunnel_lro_vxlan[0x1]; 1518 u8 tunnel_stateless_gre[0x1]; 1519 u8 tunnel_stateless_vxlan[0x1]; 1520 u8 swp[0x1]; 1521 u8 swp_csum[0x1]; 1522 u8 swp_lso[0x1]; 1523 u8 reserved_at_23[0x8]; 1524 u8 tunnel_stateless_gtp[0x1]; 1525 u8 reserved_at_25[0x4]; 1526 u8 max_vxlan_udp_ports[0x8]; 1527 u8 reserved_at_38[0x6]; 1528 u8 max_geneve_opt_len[0x1]; 1529 u8 tunnel_stateless_geneve_rx[0x1]; 1530 u8 reserved_at_40[0x10]; 1531 u8 lro_min_mss_size[0x10]; 1532 u8 reserved_at_60[0x120]; 1533 u8 lro_timer_supported_periods[4][0x20]; 1534 u8 reserved_at_200[0x600]; 1535 }; 1536 1537 enum { 1538 MLX5_VIRTQ_TYPE_SPLIT = 0, 1539 MLX5_VIRTQ_TYPE_PACKED = 1, 1540 }; 1541 1542 enum { 1543 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 1544 MLX5_VIRTQ_EVENT_MODE_QP = 1, 1545 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 1546 }; 1547 1548 struct mlx5_ifc_virtio_emulation_cap_bits { 1549 u8 desc_tunnel_offload_type[0x1]; 1550 u8 eth_frame_offload_type[0x1]; 1551 u8 virtio_version_1_0[0x1]; 1552 u8 tso_ipv4[0x1]; 1553 u8 tso_ipv6[0x1]; 1554 u8 tx_csum[0x1]; 1555 u8 rx_csum[0x1]; 1556 u8 reserved_at_7[0x1][0x9]; 1557 u8 event_mode[0x8]; 1558 u8 virtio_queue_type[0x8]; 1559 u8 reserved_at_20[0x13]; 1560 u8 log_doorbell_stride[0x5]; 1561 u8 reserved_at_3b[0x3]; 1562 u8 log_doorbell_bar_size[0x5]; 1563 u8 doorbell_bar_offset[0x40]; 1564 u8 reserved_at_80[0x8]; 1565 u8 max_num_virtio_queues[0x18]; 1566 u8 reserved_at_a0[0x60]; 1567 u8 umem_1_buffer_param_a[0x20]; 1568 u8 umem_1_buffer_param_b[0x20]; 1569 u8 umem_2_buffer_param_a[0x20]; 1570 u8 umem_2_buffer_param_b[0x20]; 1571 u8 umem_3_buffer_param_a[0x20]; 1572 u8 umem_3_buffer_param_b[0x20]; 1573 u8 reserved_at_1c0[0x620]; 1574 }; 1575 1576 struct mlx5_ifc_flow_table_prop_layout_bits { 1577 u8 ft_support[0x1]; 1578 u8 flow_tag[0x1]; 1579 u8 flow_counter[0x1]; 1580 u8 flow_modify_en[0x1]; 1581 u8 modify_root[0x1]; 1582 u8 identified_miss_table[0x1]; 1583 u8 flow_table_modify[0x1]; 1584 u8 reformat[0x1]; 1585 u8 decap[0x1]; 1586 u8 reset_root_to_default[0x1]; 1587 u8 pop_vlan[0x1]; 1588 u8 push_vlan[0x1]; 1589 u8 fpga_vendor_acceleration[0x1]; 1590 u8 pop_vlan_2[0x1]; 1591 u8 push_vlan_2[0x1]; 1592 u8 reformat_and_vlan_action[0x1]; 1593 u8 modify_and_vlan_action[0x1]; 1594 u8 sw_owner[0x1]; 1595 u8 reformat_l3_tunnel_to_l2[0x1]; 1596 u8 reformat_l2_to_l3_tunnel[0x1]; 1597 u8 reformat_and_modify_action[0x1]; 1598 u8 reserved_at_15[0x9]; 1599 u8 sw_owner_v2[0x1]; 1600 u8 reserved_at_1f[0x1]; 1601 u8 reserved_at_20[0x2]; 1602 u8 log_max_ft_size[0x6]; 1603 u8 log_max_modify_header_context[0x8]; 1604 u8 max_modify_header_actions[0x8]; 1605 u8 max_ft_level[0x8]; 1606 u8 reserved_at_40[0x8]; 1607 u8 log_max_ft_sampler_num[8]; 1608 u8 metadata_reg_b_width[0x8]; 1609 u8 metadata_reg_a_width[0x8]; 1610 u8 reserved_at_60[0x18]; 1611 u8 log_max_ft_num[0x8]; 1612 u8 reserved_at_80[0x10]; 1613 u8 log_max_flow_counter[0x8]; 1614 u8 log_max_destination[0x8]; 1615 u8 reserved_at_a0[0x18]; 1616 u8 log_max_flow[0x8]; 1617 u8 reserved_at_c0[0x140]; 1618 }; 1619 1620 struct mlx5_ifc_flow_table_nic_cap_bits { 1621 u8 reserved_at_0[0x200]; 1622 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties; 1623 }; 1624 1625 union mlx5_ifc_hca_cap_union_bits { 1626 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1627 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 1628 per_protocol_networking_offload_caps; 1629 struct mlx5_ifc_qos_cap_bits qos_cap; 1630 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 1631 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1632 u8 reserved_at_0[0x8000]; 1633 }; 1634 1635 struct mlx5_ifc_set_action_in_bits { 1636 u8 action_type[0x4]; 1637 u8 field[0xc]; 1638 u8 reserved_at_10[0x3]; 1639 u8 offset[0x5]; 1640 u8 reserved_at_18[0x3]; 1641 u8 length[0x5]; 1642 u8 data[0x20]; 1643 }; 1644 1645 struct mlx5_ifc_query_hca_cap_out_bits { 1646 u8 status[0x8]; 1647 u8 reserved_at_8[0x18]; 1648 u8 syndrome[0x20]; 1649 u8 reserved_at_40[0x40]; 1650 union mlx5_ifc_hca_cap_union_bits capability; 1651 }; 1652 1653 struct mlx5_ifc_query_hca_cap_in_bits { 1654 u8 opcode[0x10]; 1655 u8 reserved_at_10[0x10]; 1656 u8 reserved_at_20[0x10]; 1657 u8 op_mod[0x10]; 1658 u8 reserved_at_40[0x40]; 1659 }; 1660 1661 struct mlx5_ifc_mac_address_layout_bits { 1662 u8 reserved_at_0[0x10]; 1663 u8 mac_addr_47_32[0x10]; 1664 u8 mac_addr_31_0[0x20]; 1665 }; 1666 1667 struct mlx5_ifc_nic_vport_context_bits { 1668 u8 reserved_at_0[0x5]; 1669 u8 min_wqe_inline_mode[0x3]; 1670 u8 reserved_at_8[0x15]; 1671 u8 disable_mc_local_lb[0x1]; 1672 u8 disable_uc_local_lb[0x1]; 1673 u8 roce_en[0x1]; 1674 u8 arm_change_event[0x1]; 1675 u8 reserved_at_21[0x1a]; 1676 u8 event_on_mtu[0x1]; 1677 u8 event_on_promisc_change[0x1]; 1678 u8 event_on_vlan_change[0x1]; 1679 u8 event_on_mc_address_change[0x1]; 1680 u8 event_on_uc_address_change[0x1]; 1681 u8 reserved_at_40[0xc]; 1682 u8 affiliation_criteria[0x4]; 1683 u8 affiliated_vhca_id[0x10]; 1684 u8 reserved_at_60[0xd0]; 1685 u8 mtu[0x10]; 1686 u8 system_image_guid[0x40]; 1687 u8 port_guid[0x40]; 1688 u8 node_guid[0x40]; 1689 u8 reserved_at_200[0x140]; 1690 u8 qkey_violation_counter[0x10]; 1691 u8 reserved_at_350[0x430]; 1692 u8 promisc_uc[0x1]; 1693 u8 promisc_mc[0x1]; 1694 u8 promisc_all[0x1]; 1695 u8 reserved_at_783[0x2]; 1696 u8 allowed_list_type[0x3]; 1697 u8 reserved_at_788[0xc]; 1698 u8 allowed_list_size[0xc]; 1699 struct mlx5_ifc_mac_address_layout_bits permanent_address; 1700 u8 reserved_at_7e0[0x20]; 1701 }; 1702 1703 struct mlx5_ifc_query_nic_vport_context_out_bits { 1704 u8 status[0x8]; 1705 u8 reserved_at_8[0x18]; 1706 u8 syndrome[0x20]; 1707 u8 reserved_at_40[0x40]; 1708 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 1709 }; 1710 1711 struct mlx5_ifc_query_nic_vport_context_in_bits { 1712 u8 opcode[0x10]; 1713 u8 reserved_at_10[0x10]; 1714 u8 reserved_at_20[0x10]; 1715 u8 op_mod[0x10]; 1716 u8 other_vport[0x1]; 1717 u8 reserved_at_41[0xf]; 1718 u8 vport_number[0x10]; 1719 u8 reserved_at_60[0x5]; 1720 u8 allowed_list_type[0x3]; 1721 u8 reserved_at_68[0x18]; 1722 }; 1723 1724 struct mlx5_ifc_tisc_bits { 1725 u8 strict_lag_tx_port_affinity[0x1]; 1726 u8 reserved_at_1[0x3]; 1727 u8 lag_tx_port_affinity[0x04]; 1728 u8 reserved_at_8[0x4]; 1729 u8 prio[0x4]; 1730 u8 reserved_at_10[0x10]; 1731 u8 reserved_at_20[0x100]; 1732 u8 reserved_at_120[0x8]; 1733 u8 transport_domain[0x18]; 1734 u8 reserved_at_140[0x8]; 1735 u8 underlay_qpn[0x18]; 1736 u8 reserved_at_160[0x3a0]; 1737 }; 1738 1739 struct mlx5_ifc_query_tis_out_bits { 1740 u8 status[0x8]; 1741 u8 reserved_at_8[0x18]; 1742 u8 syndrome[0x20]; 1743 u8 reserved_at_40[0x40]; 1744 struct mlx5_ifc_tisc_bits tis_context; 1745 }; 1746 1747 struct mlx5_ifc_query_tis_in_bits { 1748 u8 opcode[0x10]; 1749 u8 reserved_at_10[0x10]; 1750 u8 reserved_at_20[0x10]; 1751 u8 op_mod[0x10]; 1752 u8 reserved_at_40[0x8]; 1753 u8 tisn[0x18]; 1754 u8 reserved_at_60[0x20]; 1755 }; 1756 1757 struct mlx5_ifc_alloc_transport_domain_out_bits { 1758 u8 status[0x8]; 1759 u8 reserved_at_8[0x18]; 1760 u8 syndrome[0x20]; 1761 u8 reserved_at_40[0x8]; 1762 u8 transport_domain[0x18]; 1763 u8 reserved_at_60[0x20]; 1764 }; 1765 1766 struct mlx5_ifc_alloc_transport_domain_in_bits { 1767 u8 opcode[0x10]; 1768 u8 reserved_at_10[0x10]; 1769 u8 reserved_at_20[0x10]; 1770 u8 op_mod[0x10]; 1771 u8 reserved_at_40[0x40]; 1772 }; 1773 1774 enum { 1775 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1776 MLX5_WQ_TYPE_CYCLIC = 0x1, 1777 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1778 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1779 }; 1780 1781 enum { 1782 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1783 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1784 }; 1785 1786 struct mlx5_ifc_wq_bits { 1787 u8 wq_type[0x4]; 1788 u8 wq_signature[0x1]; 1789 u8 end_padding_mode[0x2]; 1790 u8 cd_slave[0x1]; 1791 u8 reserved_at_8[0x18]; 1792 u8 hds_skip_first_sge[0x1]; 1793 u8 log2_hds_buf_size[0x3]; 1794 u8 reserved_at_24[0x7]; 1795 u8 page_offset[0x5]; 1796 u8 lwm[0x10]; 1797 u8 reserved_at_40[0x8]; 1798 u8 pd[0x18]; 1799 u8 reserved_at_60[0x8]; 1800 u8 uar_page[0x18]; 1801 u8 dbr_addr[0x40]; 1802 u8 hw_counter[0x20]; 1803 u8 sw_counter[0x20]; 1804 u8 reserved_at_100[0xc]; 1805 u8 log_wq_stride[0x4]; 1806 u8 reserved_at_110[0x3]; 1807 u8 log_wq_pg_sz[0x5]; 1808 u8 reserved_at_118[0x3]; 1809 u8 log_wq_sz[0x5]; 1810 u8 dbr_umem_valid[0x1]; 1811 u8 wq_umem_valid[0x1]; 1812 u8 reserved_at_122[0x1]; 1813 u8 log_hairpin_num_packets[0x5]; 1814 u8 reserved_at_128[0x3]; 1815 u8 log_hairpin_data_sz[0x5]; 1816 u8 reserved_at_130[0x4]; 1817 u8 single_wqe_log_num_of_strides[0x4]; 1818 u8 two_byte_shift_en[0x1]; 1819 u8 reserved_at_139[0x4]; 1820 u8 single_stride_log_num_of_bytes[0x3]; 1821 u8 dbr_umem_id[0x20]; 1822 u8 wq_umem_id[0x20]; 1823 u8 wq_umem_offset[0x40]; 1824 u8 reserved_at_1c0[0x440]; 1825 }; 1826 1827 enum { 1828 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1829 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 1830 }; 1831 1832 enum { 1833 MLX5_RQC_STATE_RST = 0x0, 1834 MLX5_RQC_STATE_RDY = 0x1, 1835 MLX5_RQC_STATE_ERR = 0x3, 1836 }; 1837 1838 struct mlx5_ifc_rqc_bits { 1839 u8 rlky[0x1]; 1840 u8 delay_drop_en[0x1]; 1841 u8 scatter_fcs[0x1]; 1842 u8 vsd[0x1]; 1843 u8 mem_rq_type[0x4]; 1844 u8 state[0x4]; 1845 u8 reserved_at_c[0x1]; 1846 u8 flush_in_error_en[0x1]; 1847 u8 hairpin[0x1]; 1848 u8 reserved_at_f[0x11]; 1849 u8 reserved_at_20[0x8]; 1850 u8 user_index[0x18]; 1851 u8 reserved_at_40[0x8]; 1852 u8 cqn[0x18]; 1853 u8 counter_set_id[0x8]; 1854 u8 reserved_at_68[0x18]; 1855 u8 reserved_at_80[0x8]; 1856 u8 rmpn[0x18]; 1857 u8 reserved_at_a0[0x8]; 1858 u8 hairpin_peer_sq[0x18]; 1859 u8 reserved_at_c0[0x10]; 1860 u8 hairpin_peer_vhca[0x10]; 1861 u8 reserved_at_e0[0xa0]; 1862 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 1863 }; 1864 1865 struct mlx5_ifc_create_rq_out_bits { 1866 u8 status[0x8]; 1867 u8 reserved_at_8[0x18]; 1868 u8 syndrome[0x20]; 1869 u8 reserved_at_40[0x8]; 1870 u8 rqn[0x18]; 1871 u8 reserved_at_60[0x20]; 1872 }; 1873 1874 struct mlx5_ifc_create_rq_in_bits { 1875 u8 opcode[0x10]; 1876 u8 uid[0x10]; 1877 u8 reserved_at_20[0x10]; 1878 u8 op_mod[0x10]; 1879 u8 reserved_at_40[0xc0]; 1880 struct mlx5_ifc_rqc_bits ctx; 1881 }; 1882 1883 struct mlx5_ifc_modify_rq_out_bits { 1884 u8 status[0x8]; 1885 u8 reserved_at_8[0x18]; 1886 u8 syndrome[0x20]; 1887 u8 reserved_at_40[0x40]; 1888 }; 1889 1890 struct mlx5_ifc_create_tis_out_bits { 1891 u8 status[0x8]; 1892 u8 reserved_at_8[0x18]; 1893 u8 syndrome[0x20]; 1894 u8 reserved_at_40[0x8]; 1895 u8 tisn[0x18]; 1896 u8 reserved_at_60[0x20]; 1897 }; 1898 1899 struct mlx5_ifc_create_tis_in_bits { 1900 u8 opcode[0x10]; 1901 u8 uid[0x10]; 1902 u8 reserved_at_20[0x10]; 1903 u8 op_mod[0x10]; 1904 u8 reserved_at_40[0xc0]; 1905 struct mlx5_ifc_tisc_bits ctx; 1906 }; 1907 1908 enum { 1909 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 1910 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 1911 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 1912 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 1913 }; 1914 1915 struct mlx5_ifc_modify_rq_in_bits { 1916 u8 opcode[0x10]; 1917 u8 uid[0x10]; 1918 u8 reserved_at_20[0x10]; 1919 u8 op_mod[0x10]; 1920 u8 rq_state[0x4]; 1921 u8 reserved_at_44[0x4]; 1922 u8 rqn[0x18]; 1923 u8 reserved_at_60[0x20]; 1924 u8 modify_bitmask[0x40]; 1925 u8 reserved_at_c0[0x40]; 1926 struct mlx5_ifc_rqc_bits ctx; 1927 }; 1928 1929 enum { 1930 MLX5_L3_PROT_TYPE_IPV4 = 0, 1931 MLX5_L3_PROT_TYPE_IPV6 = 1, 1932 }; 1933 1934 enum { 1935 MLX5_L4_PROT_TYPE_TCP = 0, 1936 MLX5_L4_PROT_TYPE_UDP = 1, 1937 }; 1938 1939 enum { 1940 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1941 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1942 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1943 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1944 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1945 }; 1946 1947 struct mlx5_ifc_rx_hash_field_select_bits { 1948 u8 l3_prot_type[0x1]; 1949 u8 l4_prot_type[0x1]; 1950 u8 selected_fields[0x1e]; 1951 }; 1952 1953 enum { 1954 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 1955 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 1956 }; 1957 1958 enum { 1959 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 1960 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 1961 }; 1962 1963 enum { 1964 MLX5_RX_HASH_FN_NONE = 0x0, 1965 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 1966 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 1967 }; 1968 1969 enum { 1970 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 1971 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 1972 }; 1973 1974 enum { 1975 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 1976 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 1977 }; 1978 1979 struct mlx5_ifc_tirc_bits { 1980 u8 reserved_at_0[0x20]; 1981 u8 disp_type[0x4]; 1982 u8 reserved_at_24[0x1c]; 1983 u8 reserved_at_40[0x40]; 1984 u8 reserved_at_80[0x4]; 1985 u8 lro_timeout_period_usecs[0x10]; 1986 u8 lro_enable_mask[0x4]; 1987 u8 lro_max_msg_sz[0x8]; 1988 u8 reserved_at_a0[0x40]; 1989 u8 reserved_at_e0[0x8]; 1990 u8 inline_rqn[0x18]; 1991 u8 rx_hash_symmetric[0x1]; 1992 u8 reserved_at_101[0x1]; 1993 u8 tunneled_offload_en[0x1]; 1994 u8 reserved_at_103[0x5]; 1995 u8 indirect_table[0x18]; 1996 u8 rx_hash_fn[0x4]; 1997 u8 reserved_at_124[0x2]; 1998 u8 self_lb_block[0x2]; 1999 u8 transport_domain[0x18]; 2000 u8 rx_hash_toeplitz_key[10][0x20]; 2001 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2002 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2003 u8 reserved_at_2c0[0x4c0]; 2004 }; 2005 2006 struct mlx5_ifc_create_tir_out_bits { 2007 u8 status[0x8]; 2008 u8 reserved_at_8[0x18]; 2009 u8 syndrome[0x20]; 2010 u8 reserved_at_40[0x8]; 2011 u8 tirn[0x18]; 2012 u8 reserved_at_60[0x20]; 2013 }; 2014 2015 struct mlx5_ifc_create_tir_in_bits { 2016 u8 opcode[0x10]; 2017 u8 uid[0x10]; 2018 u8 reserved_at_20[0x10]; 2019 u8 op_mod[0x10]; 2020 u8 reserved_at_40[0xc0]; 2021 struct mlx5_ifc_tirc_bits ctx; 2022 }; 2023 2024 enum { 2025 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2026 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2027 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2028 /* bit 3 - tunneled_offload_en modify not supported. */ 2029 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 2030 }; 2031 2032 struct mlx5_ifc_modify_tir_out_bits { 2033 u8 status[0x8]; 2034 u8 reserved_at_8[0x18]; 2035 u8 syndrome[0x20]; 2036 u8 reserved_at_40[0x40]; 2037 }; 2038 2039 struct mlx5_ifc_modify_tir_in_bits { 2040 u8 opcode[0x10]; 2041 u8 uid[0x10]; 2042 u8 reserved_at_20[0x10]; 2043 u8 op_mod[0x10]; 2044 u8 reserved_at_40[0x8]; 2045 u8 tirn[0x18]; 2046 u8 reserved_at_60[0x20]; 2047 u8 modify_bitmask[0x40]; 2048 u8 reserved_at_c0[0x40]; 2049 struct mlx5_ifc_tirc_bits ctx; 2050 }; 2051 2052 enum { 2053 MLX5_INLINE_Q_TYPE_RQ = 0x0, 2054 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 2055 }; 2056 2057 struct mlx5_ifc_rq_num_bits { 2058 u8 reserved_at_0[0x8]; 2059 u8 rq_num[0x18]; 2060 }; 2061 2062 struct mlx5_ifc_rqtc_bits { 2063 u8 reserved_at_0[0xa5]; 2064 u8 list_q_type[0x3]; 2065 u8 reserved_at_a8[0x8]; 2066 u8 rqt_max_size[0x10]; 2067 u8 reserved_at_c0[0x10]; 2068 u8 rqt_actual_size[0x10]; 2069 u8 reserved_at_e0[0x6a0]; 2070 struct mlx5_ifc_rq_num_bits rq_num[]; 2071 }; 2072 2073 struct mlx5_ifc_create_rqt_out_bits { 2074 u8 status[0x8]; 2075 u8 reserved_at_8[0x18]; 2076 u8 syndrome[0x20]; 2077 u8 reserved_at_40[0x8]; 2078 u8 rqtn[0x18]; 2079 u8 reserved_at_60[0x20]; 2080 }; 2081 2082 #ifdef PEDANTIC 2083 #pragma GCC diagnostic ignored "-Wpedantic" 2084 #endif 2085 struct mlx5_ifc_create_rqt_in_bits { 2086 u8 opcode[0x10]; 2087 u8 uid[0x10]; 2088 u8 reserved_at_20[0x10]; 2089 u8 op_mod[0x10]; 2090 u8 reserved_at_40[0xc0]; 2091 struct mlx5_ifc_rqtc_bits rqt_context; 2092 }; 2093 2094 struct mlx5_ifc_modify_rqt_in_bits { 2095 u8 opcode[0x10]; 2096 u8 uid[0x10]; 2097 u8 reserved_at_20[0x10]; 2098 u8 op_mod[0x10]; 2099 u8 reserved_at_40[0x8]; 2100 u8 rqtn[0x18]; 2101 u8 reserved_at_60[0x20]; 2102 u8 modify_bitmask[0x40]; 2103 u8 reserved_at_c0[0x40]; 2104 struct mlx5_ifc_rqtc_bits rqt_context; 2105 }; 2106 #ifdef PEDANTIC 2107 #pragma GCC diagnostic error "-Wpedantic" 2108 #endif 2109 2110 struct mlx5_ifc_modify_rqt_out_bits { 2111 u8 status[0x8]; 2112 u8 reserved_at_8[0x18]; 2113 u8 syndrome[0x20]; 2114 u8 reserved_at_40[0x40]; 2115 }; 2116 2117 enum { 2118 MLX5_SQC_STATE_RST = 0x0, 2119 MLX5_SQC_STATE_RDY = 0x1, 2120 MLX5_SQC_STATE_ERR = 0x3, 2121 }; 2122 2123 struct mlx5_ifc_sqc_bits { 2124 u8 rlky[0x1]; 2125 u8 cd_master[0x1]; 2126 u8 fre[0x1]; 2127 u8 flush_in_error_en[0x1]; 2128 u8 allow_multi_pkt_send_wqe[0x1]; 2129 u8 min_wqe_inline_mode[0x3]; 2130 u8 state[0x4]; 2131 u8 reg_umr[0x1]; 2132 u8 allow_swp[0x1]; 2133 u8 hairpin[0x1]; 2134 u8 non_wire[0x1]; 2135 u8 static_sq_wq[0x1]; 2136 u8 reserved_at_11[0xf]; 2137 u8 reserved_at_20[0x8]; 2138 u8 user_index[0x18]; 2139 u8 reserved_at_40[0x8]; 2140 u8 cqn[0x18]; 2141 u8 reserved_at_60[0x8]; 2142 u8 hairpin_peer_rq[0x18]; 2143 u8 reserved_at_80[0x10]; 2144 u8 hairpin_peer_vhca[0x10]; 2145 u8 reserved_at_a0[0x50]; 2146 u8 packet_pacing_rate_limit_index[0x10]; 2147 u8 tis_lst_sz[0x10]; 2148 u8 reserved_at_110[0x10]; 2149 u8 reserved_at_120[0x40]; 2150 u8 reserved_at_160[0x8]; 2151 u8 tis_num_0[0x18]; 2152 struct mlx5_ifc_wq_bits wq; 2153 }; 2154 2155 struct mlx5_ifc_query_sq_in_bits { 2156 u8 opcode[0x10]; 2157 u8 reserved_at_10[0x10]; 2158 u8 reserved_at_20[0x10]; 2159 u8 op_mod[0x10]; 2160 u8 reserved_at_40[0x8]; 2161 u8 sqn[0x18]; 2162 u8 reserved_at_60[0x20]; 2163 }; 2164 2165 struct mlx5_ifc_modify_sq_out_bits { 2166 u8 status[0x8]; 2167 u8 reserved_at_8[0x18]; 2168 u8 syndrome[0x20]; 2169 u8 reserved_at_40[0x40]; 2170 }; 2171 2172 struct mlx5_ifc_modify_sq_in_bits { 2173 u8 opcode[0x10]; 2174 u8 uid[0x10]; 2175 u8 reserved_at_20[0x10]; 2176 u8 op_mod[0x10]; 2177 u8 sq_state[0x4]; 2178 u8 reserved_at_44[0x4]; 2179 u8 sqn[0x18]; 2180 u8 reserved_at_60[0x20]; 2181 u8 modify_bitmask[0x40]; 2182 u8 reserved_at_c0[0x40]; 2183 struct mlx5_ifc_sqc_bits ctx; 2184 }; 2185 2186 struct mlx5_ifc_create_sq_out_bits { 2187 u8 status[0x8]; 2188 u8 reserved_at_8[0x18]; 2189 u8 syndrome[0x20]; 2190 u8 reserved_at_40[0x8]; 2191 u8 sqn[0x18]; 2192 u8 reserved_at_60[0x20]; 2193 }; 2194 2195 struct mlx5_ifc_create_sq_in_bits { 2196 u8 opcode[0x10]; 2197 u8 uid[0x10]; 2198 u8 reserved_at_20[0x10]; 2199 u8 op_mod[0x10]; 2200 u8 reserved_at_40[0xc0]; 2201 struct mlx5_ifc_sqc_bits ctx; 2202 }; 2203 2204 enum { 2205 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 2206 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 2207 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 2208 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 2209 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 2210 }; 2211 2212 struct mlx5_ifc_flow_meter_parameters_bits { 2213 u8 valid[0x1]; // 00h 2214 u8 bucket_overflow[0x1]; 2215 u8 start_color[0x2]; 2216 u8 both_buckets_on_green[0x1]; 2217 u8 meter_mode[0x2]; 2218 u8 reserved_at_1[0x19]; 2219 u8 reserved_at_2[0x20]; //04h 2220 u8 reserved_at_3[0x3]; 2221 u8 cbs_exponent[0x5]; // 08h 2222 u8 cbs_mantissa[0x8]; 2223 u8 reserved_at_4[0x3]; 2224 u8 cir_exponent[0x5]; 2225 u8 cir_mantissa[0x8]; 2226 u8 reserved_at_5[0x20]; // 0Ch 2227 u8 reserved_at_6[0x3]; 2228 u8 ebs_exponent[0x5]; // 10h 2229 u8 ebs_mantissa[0x8]; 2230 u8 reserved_at_7[0x3]; 2231 u8 eir_exponent[0x5]; 2232 u8 eir_mantissa[0x8]; 2233 u8 reserved_at_8[0x60]; // 14h-1Ch 2234 }; 2235 2236 enum { 2237 MLX5_CQE_SIZE_64B = 0x0, 2238 MLX5_CQE_SIZE_128B = 0x1, 2239 }; 2240 2241 struct mlx5_ifc_cqc_bits { 2242 u8 status[0x4]; 2243 u8 as_notify[0x1]; 2244 u8 initiator_src_dct[0x1]; 2245 u8 dbr_umem_valid[0x1]; 2246 u8 reserved_at_7[0x1]; 2247 u8 cqe_sz[0x3]; 2248 u8 cc[0x1]; 2249 u8 reserved_at_c[0x1]; 2250 u8 scqe_break_moderation_en[0x1]; 2251 u8 oi[0x1]; 2252 u8 cq_period_mode[0x2]; 2253 u8 cqe_comp_en[0x1]; 2254 u8 mini_cqe_res_format[0x2]; 2255 u8 st[0x4]; 2256 u8 reserved_at_18[0x1]; 2257 u8 cqe_comp_layout[0x7]; 2258 u8 dbr_umem_id[0x20]; 2259 u8 reserved_at_40[0x14]; 2260 u8 page_offset[0x6]; 2261 u8 reserved_at_5a[0x2]; 2262 u8 mini_cqe_res_format_ext[0x2]; 2263 u8 cq_timestamp_format[0x2]; 2264 u8 reserved_at_60[0x3]; 2265 u8 log_cq_size[0x5]; 2266 u8 uar_page[0x18]; 2267 u8 reserved_at_80[0x4]; 2268 u8 cq_period[0xc]; 2269 u8 cq_max_count[0x10]; 2270 u8 reserved_at_a0[0x18]; 2271 u8 c_eqn[0x8]; 2272 u8 reserved_at_c0[0x3]; 2273 u8 log_page_size[0x5]; 2274 u8 reserved_at_c8[0x18]; 2275 u8 reserved_at_e0[0x20]; 2276 u8 reserved_at_100[0x8]; 2277 u8 last_notified_index[0x18]; 2278 u8 reserved_at_120[0x8]; 2279 u8 last_solicit_index[0x18]; 2280 u8 reserved_at_140[0x8]; 2281 u8 consumer_counter[0x18]; 2282 u8 reserved_at_160[0x8]; 2283 u8 producer_counter[0x18]; 2284 u8 local_partition_id[0xc]; 2285 u8 process_id[0x14]; 2286 u8 reserved_at_1A0[0x20]; 2287 u8 dbr_addr[0x40]; 2288 }; 2289 2290 struct mlx5_ifc_health_buffer_bits { 2291 u8 reserved_0[0x100]; 2292 u8 assert_existptr[0x20]; 2293 u8 assert_callra[0x20]; 2294 u8 reserved_1[0x40]; 2295 u8 fw_version[0x20]; 2296 u8 hw_id[0x20]; 2297 u8 reserved_2[0x20]; 2298 u8 irisc_index[0x8]; 2299 u8 synd[0x8]; 2300 u8 ext_synd[0x10]; 2301 }; 2302 2303 struct mlx5_ifc_initial_seg_bits { 2304 u8 fw_rev_minor[0x10]; 2305 u8 fw_rev_major[0x10]; 2306 u8 cmd_interface_rev[0x10]; 2307 u8 fw_rev_subminor[0x10]; 2308 u8 reserved_0[0x40]; 2309 u8 cmdq_phy_addr_63_32[0x20]; 2310 u8 cmdq_phy_addr_31_12[0x14]; 2311 u8 reserved_1[0x2]; 2312 u8 nic_interface[0x2]; 2313 u8 log_cmdq_size[0x4]; 2314 u8 log_cmdq_stride[0x4]; 2315 u8 command_doorbell_vector[0x20]; 2316 u8 reserved_2[0xf00]; 2317 u8 initializing[0x1]; 2318 u8 nic_interface_supported[0x7]; 2319 u8 reserved_4[0x18]; 2320 struct mlx5_ifc_health_buffer_bits health_buffer; 2321 u8 no_dram_nic_offset[0x20]; 2322 u8 reserved_5[0x6de0]; 2323 u8 internal_timer_h[0x20]; 2324 u8 internal_timer_l[0x20]; 2325 u8 reserved_6[0x20]; 2326 u8 reserved_7[0x1f]; 2327 u8 clear_int[0x1]; 2328 u8 health_syndrome[0x8]; 2329 u8 health_counter[0x18]; 2330 u8 reserved_8[0x17fc0]; 2331 }; 2332 2333 struct mlx5_ifc_create_cq_out_bits { 2334 u8 status[0x8]; 2335 u8 reserved_at_8[0x18]; 2336 u8 syndrome[0x20]; 2337 u8 reserved_at_40[0x8]; 2338 u8 cqn[0x18]; 2339 u8 reserved_at_60[0x20]; 2340 }; 2341 2342 struct mlx5_ifc_create_cq_in_bits { 2343 u8 opcode[0x10]; 2344 u8 uid[0x10]; 2345 u8 reserved_at_20[0x10]; 2346 u8 op_mod[0x10]; 2347 u8 reserved_at_40[0x40]; 2348 struct mlx5_ifc_cqc_bits cq_context; 2349 u8 cq_umem_offset[0x40]; 2350 u8 cq_umem_id[0x20]; 2351 u8 cq_umem_valid[0x1]; 2352 u8 reserved_at_2e1[0x1f]; 2353 u8 reserved_at_300[0x580]; 2354 u8 pas[]; 2355 }; 2356 2357 enum { 2358 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 2359 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 2360 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 2361 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 2362 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 2363 }; 2364 2365 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 2366 u8 opcode[0x10]; 2367 u8 reserved_at_10[0x20]; 2368 u8 obj_type[0x10]; 2369 u8 obj_id[0x20]; 2370 u8 reserved_at_60[0x20]; 2371 }; 2372 2373 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 2374 u8 status[0x8]; 2375 u8 reserved_at_8[0x18]; 2376 u8 syndrome[0x20]; 2377 u8 obj_id[0x20]; 2378 u8 reserved_at_60[0x20]; 2379 }; 2380 2381 struct mlx5_ifc_virtio_q_counters_bits { 2382 u8 modify_field_select[0x40]; 2383 u8 reserved_at_40[0x40]; 2384 u8 received_desc[0x40]; 2385 u8 completed_desc[0x40]; 2386 u8 error_cqes[0x20]; 2387 u8 bad_desc_errors[0x20]; 2388 u8 exceed_max_chain[0x20]; 2389 u8 invalid_buffer[0x20]; 2390 u8 reserved_at_180[0x50]; 2391 }; 2392 2393 struct mlx5_ifc_geneve_tlv_option_bits { 2394 u8 modify_field_select[0x40]; 2395 u8 reserved_at_40[0x18]; 2396 u8 geneve_option_fte_index[0x8]; 2397 u8 option_class[0x10]; 2398 u8 option_type[0x8]; 2399 u8 reserved_at_78[0x3]; 2400 u8 option_data_length[0x5]; 2401 u8 reserved_at_80[0x180]; 2402 }; 2403 2404 struct mlx5_ifc_create_virtio_q_counters_in_bits { 2405 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2406 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2407 }; 2408 2409 struct mlx5_ifc_query_virtio_q_counters_out_bits { 2410 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2411 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2412 }; 2413 2414 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 2415 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2416 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 2417 }; 2418 2419 enum { 2420 MLX5_VIRTQ_STATE_INIT = 0, 2421 MLX5_VIRTQ_STATE_RDY = 1, 2422 MLX5_VIRTQ_STATE_SUSPEND = 2, 2423 MLX5_VIRTQ_STATE_ERROR = 3, 2424 }; 2425 2426 enum { 2427 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 2428 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 2429 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 2430 }; 2431 2432 struct mlx5_ifc_virtio_q_bits { 2433 u8 virtio_q_type[0x8]; 2434 u8 reserved_at_8[0x5]; 2435 u8 event_mode[0x3]; 2436 u8 queue_index[0x10]; 2437 u8 full_emulation[0x1]; 2438 u8 virtio_version_1_0[0x1]; 2439 u8 reserved_at_22[0x2]; 2440 u8 offload_type[0x4]; 2441 u8 event_qpn_or_msix[0x18]; 2442 u8 doorbell_stride_idx[0x10]; 2443 u8 queue_size[0x10]; 2444 u8 device_emulation_id[0x20]; 2445 u8 desc_addr[0x40]; 2446 u8 used_addr[0x40]; 2447 u8 available_addr[0x40]; 2448 u8 virtio_q_mkey[0x20]; 2449 u8 reserved_at_160[0x18]; 2450 u8 error_type[0x8]; 2451 u8 umem_1_id[0x20]; 2452 u8 umem_1_size[0x20]; 2453 u8 umem_1_offset[0x40]; 2454 u8 umem_2_id[0x20]; 2455 u8 umem_2_size[0x20]; 2456 u8 umem_2_offset[0x40]; 2457 u8 umem_3_id[0x20]; 2458 u8 umem_3_size[0x20]; 2459 u8 umem_3_offset[0x40]; 2460 u8 counter_set_id[0x20]; 2461 u8 reserved_at_320[0x8]; 2462 u8 pd[0x18]; 2463 u8 reserved_at_340[0x2]; 2464 u8 queue_period_mode[0x2]; 2465 u8 queue_period_us[0xc]; 2466 u8 queue_max_count[0x10]; 2467 u8 reserved_at_360[0xa0]; 2468 }; 2469 2470 struct mlx5_ifc_virtio_net_q_bits { 2471 u8 modify_field_select[0x40]; 2472 u8 reserved_at_40[0x40]; 2473 u8 tso_ipv4[0x1]; 2474 u8 tso_ipv6[0x1]; 2475 u8 tx_csum[0x1]; 2476 u8 rx_csum[0x1]; 2477 u8 reserved_at_84[0x6]; 2478 u8 dirty_bitmap_dump_enable[0x1]; 2479 u8 vhost_log_page[0x5]; 2480 u8 reserved_at_90[0xc]; 2481 u8 state[0x4]; 2482 u8 reserved_at_a0[0x8]; 2483 u8 tisn_or_qpn[0x18]; 2484 u8 dirty_bitmap_mkey[0x20]; 2485 u8 dirty_bitmap_size[0x20]; 2486 u8 dirty_bitmap_addr[0x40]; 2487 u8 hw_available_index[0x10]; 2488 u8 hw_used_index[0x10]; 2489 u8 reserved_at_160[0xa0]; 2490 struct mlx5_ifc_virtio_q_bits virtio_q_context; 2491 }; 2492 2493 struct mlx5_ifc_create_virtq_in_bits { 2494 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2495 struct mlx5_ifc_virtio_net_q_bits virtq; 2496 }; 2497 2498 struct mlx5_ifc_query_virtq_out_bits { 2499 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2500 struct mlx5_ifc_virtio_net_q_bits virtq; 2501 }; 2502 2503 struct mlx5_ifc_flow_hit_aso_bits { 2504 u8 modify_field_select[0x40]; 2505 u8 reserved_at_40[0x48]; 2506 u8 access_pd[0x18]; 2507 u8 reserved_at_a0[0x160]; 2508 u8 flag[0x200]; 2509 }; 2510 2511 struct mlx5_ifc_create_flow_hit_aso_in_bits { 2512 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2513 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 2514 }; 2515 2516 enum mlx5_access_aso_opc_mod { 2517 ASO_OPC_MOD_IPSEC = 0x0, 2518 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 2519 ASO_OPC_MOD_POLICER = 0x2, 2520 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 2521 ASO_OPC_MOD_FLOW_HIT = 0x4, 2522 }; 2523 2524 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 2525 2526 enum mlx5_aso_data_mask_mode { 2527 BITWISE_64BIT = 0x0, 2528 BYTEWISE_64BYTE = 0x1, 2529 CALCULATED_64BYTE = 0x2, 2530 }; 2531 2532 #define ASO_CSEG_COND_0_OPER_OFFSET 20 2533 #define ASO_CSEG_COND_1_OPER_OFFSET 16 2534 2535 enum mlx5_aso_pre_cond_op { 2536 ASO_OP_ALWAYS_FALSE = 0x0, 2537 ASO_OP_ALWAYS_TRUE = 0x1, 2538 ASO_OP_EQUAL = 0x2, 2539 ASO_OP_NOT_EQUAL = 0x3, 2540 ASO_OP_GREATER_OR_EQUAL = 0x4, 2541 ASO_OP_LESSER_OR_EQUAL = 0x5, 2542 ASO_OP_LESSER = 0x6, 2543 ASO_OP_GREATER = 0x7, 2544 ASO_OP_CYCLIC_GREATER = 0x8, 2545 ASO_OP_CYCLIC_LESSER = 0x9, 2546 }; 2547 2548 #define ASO_CSEG_COND_OPER_OFFSET 6 2549 2550 enum mlx5_aso_op { 2551 ASO_OPER_LOGICAL_AND = 0x0, 2552 ASO_OPER_LOGICAL_OR = 0x1, 2553 }; 2554 2555 /* ASO WQE CTRL segment. */ 2556 struct mlx5_aso_cseg { 2557 uint32_t va_h; 2558 uint32_t va_l_r; 2559 uint32_t lkey; 2560 uint32_t operand_masks; 2561 uint32_t condition_0_data; 2562 uint32_t condition_0_mask; 2563 uint32_t condition_1_data; 2564 uint32_t condition_1_mask; 2565 uint64_t bitwise_data; 2566 uint64_t data_mask; 2567 } __rte_packed; 2568 2569 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 2570 2571 /* ASO WQE Data segment. */ 2572 struct mlx5_aso_dseg { 2573 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 2574 } __rte_packed; 2575 2576 /* ASO WQE. */ 2577 struct mlx5_aso_wqe { 2578 struct mlx5_wqe_cseg general_cseg; 2579 struct mlx5_aso_cseg aso_cseg; 2580 struct mlx5_aso_dseg aso_dseg; 2581 } __rte_packed; 2582 2583 enum { 2584 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 2585 }; 2586 2587 enum { 2588 MLX5_QP_ST_RC = 0x0, 2589 }; 2590 2591 enum { 2592 MLX5_QP_PM_MIGRATED = 0x3, 2593 }; 2594 2595 enum { 2596 MLX5_NON_ZERO_RQ = 0x0, 2597 MLX5_SRQ_RQ = 0x1, 2598 MLX5_CRQ_RQ = 0x2, 2599 MLX5_ZERO_LEN_RQ = 0x3, 2600 }; 2601 2602 struct mlx5_ifc_ads_bits { 2603 u8 fl[0x1]; 2604 u8 free_ar[0x1]; 2605 u8 reserved_at_2[0xe]; 2606 u8 pkey_index[0x10]; 2607 u8 reserved_at_20[0x8]; 2608 u8 grh[0x1]; 2609 u8 mlid[0x7]; 2610 u8 rlid[0x10]; 2611 u8 ack_timeout[0x5]; 2612 u8 reserved_at_45[0x3]; 2613 u8 src_addr_index[0x8]; 2614 u8 reserved_at_50[0x4]; 2615 u8 stat_rate[0x4]; 2616 u8 hop_limit[0x8]; 2617 u8 reserved_at_60[0x4]; 2618 u8 tclass[0x8]; 2619 u8 flow_label[0x14]; 2620 u8 rgid_rip[16][0x8]; 2621 u8 reserved_at_100[0x4]; 2622 u8 f_dscp[0x1]; 2623 u8 f_ecn[0x1]; 2624 u8 reserved_at_106[0x1]; 2625 u8 f_eth_prio[0x1]; 2626 u8 ecn[0x2]; 2627 u8 dscp[0x6]; 2628 u8 udp_sport[0x10]; 2629 u8 dei_cfi[0x1]; 2630 u8 eth_prio[0x3]; 2631 u8 sl[0x4]; 2632 u8 vhca_port_num[0x8]; 2633 u8 rmac_47_32[0x10]; 2634 u8 rmac_31_0[0x20]; 2635 }; 2636 2637 struct mlx5_ifc_qpc_bits { 2638 u8 state[0x4]; 2639 u8 lag_tx_port_affinity[0x4]; 2640 u8 st[0x8]; 2641 u8 reserved_at_10[0x3]; 2642 u8 pm_state[0x2]; 2643 u8 reserved_at_15[0x1]; 2644 u8 req_e2e_credit_mode[0x2]; 2645 u8 offload_type[0x4]; 2646 u8 end_padding_mode[0x2]; 2647 u8 reserved_at_1e[0x2]; 2648 u8 wq_signature[0x1]; 2649 u8 block_lb_mc[0x1]; 2650 u8 atomic_like_write_en[0x1]; 2651 u8 latency_sensitive[0x1]; 2652 u8 reserved_at_24[0x1]; 2653 u8 drain_sigerr[0x1]; 2654 u8 reserved_at_26[0x2]; 2655 u8 pd[0x18]; 2656 u8 mtu[0x3]; 2657 u8 log_msg_max[0x5]; 2658 u8 reserved_at_48[0x1]; 2659 u8 log_rq_size[0x4]; 2660 u8 log_rq_stride[0x3]; 2661 u8 no_sq[0x1]; 2662 u8 log_sq_size[0x4]; 2663 u8 reserved_at_55[0x6]; 2664 u8 rlky[0x1]; 2665 u8 ulp_stateless_offload_mode[0x4]; 2666 u8 counter_set_id[0x8]; 2667 u8 uar_page[0x18]; 2668 u8 reserved_at_80[0x8]; 2669 u8 user_index[0x18]; 2670 u8 reserved_at_a0[0x3]; 2671 u8 log_page_size[0x5]; 2672 u8 remote_qpn[0x18]; 2673 struct mlx5_ifc_ads_bits primary_address_path; 2674 struct mlx5_ifc_ads_bits secondary_address_path; 2675 u8 log_ack_req_freq[0x4]; 2676 u8 reserved_at_384[0x4]; 2677 u8 log_sra_max[0x3]; 2678 u8 reserved_at_38b[0x2]; 2679 u8 retry_count[0x3]; 2680 u8 rnr_retry[0x3]; 2681 u8 reserved_at_393[0x1]; 2682 u8 fre[0x1]; 2683 u8 cur_rnr_retry[0x3]; 2684 u8 cur_retry_count[0x3]; 2685 u8 reserved_at_39b[0x5]; 2686 u8 reserved_at_3a0[0x20]; 2687 u8 reserved_at_3c0[0x8]; 2688 u8 next_send_psn[0x18]; 2689 u8 reserved_at_3e0[0x8]; 2690 u8 cqn_snd[0x18]; 2691 u8 reserved_at_400[0x8]; 2692 u8 deth_sqpn[0x18]; 2693 u8 reserved_at_420[0x20]; 2694 u8 reserved_at_440[0x8]; 2695 u8 last_acked_psn[0x18]; 2696 u8 reserved_at_460[0x8]; 2697 u8 ssn[0x18]; 2698 u8 reserved_at_480[0x8]; 2699 u8 log_rra_max[0x3]; 2700 u8 reserved_at_48b[0x1]; 2701 u8 atomic_mode[0x4]; 2702 u8 rre[0x1]; 2703 u8 rwe[0x1]; 2704 u8 rae[0x1]; 2705 u8 reserved_at_493[0x1]; 2706 u8 page_offset[0x6]; 2707 u8 reserved_at_49a[0x3]; 2708 u8 cd_slave_receive[0x1]; 2709 u8 cd_slave_send[0x1]; 2710 u8 cd_master[0x1]; 2711 u8 reserved_at_4a0[0x3]; 2712 u8 min_rnr_nak[0x5]; 2713 u8 next_rcv_psn[0x18]; 2714 u8 reserved_at_4c0[0x8]; 2715 u8 xrcd[0x18]; 2716 u8 reserved_at_4e0[0x8]; 2717 u8 cqn_rcv[0x18]; 2718 u8 dbr_addr[0x40]; 2719 u8 q_key[0x20]; 2720 u8 reserved_at_560[0x5]; 2721 u8 rq_type[0x3]; 2722 u8 srqn_rmpn_xrqn[0x18]; 2723 u8 reserved_at_580[0x8]; 2724 u8 rmsn[0x18]; 2725 u8 hw_sq_wqebb_counter[0x10]; 2726 u8 sw_sq_wqebb_counter[0x10]; 2727 u8 hw_rq_counter[0x20]; 2728 u8 sw_rq_counter[0x20]; 2729 u8 reserved_at_600[0x20]; 2730 u8 reserved_at_620[0xf]; 2731 u8 cgs[0x1]; 2732 u8 cs_req[0x8]; 2733 u8 cs_res[0x8]; 2734 u8 dc_access_key[0x40]; 2735 u8 reserved_at_680[0x3]; 2736 u8 dbr_umem_valid[0x1]; 2737 u8 reserved_at_684[0x9c]; 2738 u8 dbr_umem_id[0x20]; 2739 }; 2740 2741 struct mlx5_ifc_create_qp_out_bits { 2742 u8 status[0x8]; 2743 u8 reserved_at_8[0x18]; 2744 u8 syndrome[0x20]; 2745 u8 reserved_at_40[0x8]; 2746 u8 qpn[0x18]; 2747 u8 reserved_at_60[0x20]; 2748 }; 2749 2750 #ifdef PEDANTIC 2751 #pragma GCC diagnostic ignored "-Wpedantic" 2752 #endif 2753 struct mlx5_ifc_create_qp_in_bits { 2754 u8 opcode[0x10]; 2755 u8 uid[0x10]; 2756 u8 reserved_at_20[0x10]; 2757 u8 op_mod[0x10]; 2758 u8 reserved_at_40[0x40]; 2759 u8 opt_param_mask[0x20]; 2760 u8 reserved_at_a0[0x20]; 2761 struct mlx5_ifc_qpc_bits qpc; 2762 u8 wq_umem_offset[0x40]; 2763 u8 wq_umem_id[0x20]; 2764 u8 wq_umem_valid[0x1]; 2765 u8 reserved_at_861[0x1f]; 2766 u8 pas[0][0x40]; 2767 }; 2768 #ifdef PEDANTIC 2769 #pragma GCC diagnostic error "-Wpedantic" 2770 #endif 2771 2772 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2773 u8 status[0x8]; 2774 u8 reserved_at_8[0x18]; 2775 u8 syndrome[0x20]; 2776 u8 reserved_at_40[0x40]; 2777 }; 2778 2779 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2780 u8 opcode[0x10]; 2781 u8 uid[0x10]; 2782 u8 reserved_at_20[0x10]; 2783 u8 op_mod[0x10]; 2784 u8 reserved_at_40[0x8]; 2785 u8 qpn[0x18]; 2786 u8 reserved_at_60[0x20]; 2787 u8 opt_param_mask[0x20]; 2788 u8 reserved_at_a0[0x20]; 2789 struct mlx5_ifc_qpc_bits qpc; 2790 u8 reserved_at_800[0x80]; 2791 }; 2792 2793 struct mlx5_ifc_sqd2rts_qp_out_bits { 2794 u8 status[0x8]; 2795 u8 reserved_at_8[0x18]; 2796 u8 syndrome[0x20]; 2797 u8 reserved_at_40[0x40]; 2798 }; 2799 2800 struct mlx5_ifc_sqd2rts_qp_in_bits { 2801 u8 opcode[0x10]; 2802 u8 uid[0x10]; 2803 u8 reserved_at_20[0x10]; 2804 u8 op_mod[0x10]; 2805 u8 reserved_at_40[0x8]; 2806 u8 qpn[0x18]; 2807 u8 reserved_at_60[0x20]; 2808 u8 opt_param_mask[0x20]; 2809 u8 reserved_at_a0[0x20]; 2810 struct mlx5_ifc_qpc_bits qpc; 2811 u8 reserved_at_800[0x80]; 2812 }; 2813 2814 struct mlx5_ifc_rts2rts_qp_out_bits { 2815 u8 status[0x8]; 2816 u8 reserved_at_8[0x18]; 2817 u8 syndrome[0x20]; 2818 u8 reserved_at_40[0x40]; 2819 }; 2820 2821 struct mlx5_ifc_rts2rts_qp_in_bits { 2822 u8 opcode[0x10]; 2823 u8 uid[0x10]; 2824 u8 reserved_at_20[0x10]; 2825 u8 op_mod[0x10]; 2826 u8 reserved_at_40[0x8]; 2827 u8 qpn[0x18]; 2828 u8 reserved_at_60[0x20]; 2829 u8 opt_param_mask[0x20]; 2830 u8 reserved_at_a0[0x20]; 2831 struct mlx5_ifc_qpc_bits qpc; 2832 u8 reserved_at_800[0x80]; 2833 }; 2834 2835 struct mlx5_ifc_rtr2rts_qp_out_bits { 2836 u8 status[0x8]; 2837 u8 reserved_at_8[0x18]; 2838 u8 syndrome[0x20]; 2839 u8 reserved_at_40[0x40]; 2840 }; 2841 2842 struct mlx5_ifc_rtr2rts_qp_in_bits { 2843 u8 opcode[0x10]; 2844 u8 uid[0x10]; 2845 u8 reserved_at_20[0x10]; 2846 u8 op_mod[0x10]; 2847 u8 reserved_at_40[0x8]; 2848 u8 qpn[0x18]; 2849 u8 reserved_at_60[0x20]; 2850 u8 opt_param_mask[0x20]; 2851 u8 reserved_at_a0[0x20]; 2852 struct mlx5_ifc_qpc_bits qpc; 2853 u8 reserved_at_800[0x80]; 2854 }; 2855 2856 struct mlx5_ifc_rst2init_qp_out_bits { 2857 u8 status[0x8]; 2858 u8 reserved_at_8[0x18]; 2859 u8 syndrome[0x20]; 2860 u8 reserved_at_40[0x40]; 2861 }; 2862 2863 struct mlx5_ifc_rst2init_qp_in_bits { 2864 u8 opcode[0x10]; 2865 u8 uid[0x10]; 2866 u8 reserved_at_20[0x10]; 2867 u8 op_mod[0x10]; 2868 u8 reserved_at_40[0x8]; 2869 u8 qpn[0x18]; 2870 u8 reserved_at_60[0x20]; 2871 u8 opt_param_mask[0x20]; 2872 u8 reserved_at_a0[0x20]; 2873 struct mlx5_ifc_qpc_bits qpc; 2874 u8 reserved_at_800[0x80]; 2875 }; 2876 2877 struct mlx5_ifc_init2rtr_qp_out_bits { 2878 u8 status[0x8]; 2879 u8 reserved_at_8[0x18]; 2880 u8 syndrome[0x20]; 2881 u8 reserved_at_40[0x40]; 2882 }; 2883 2884 struct mlx5_ifc_init2rtr_qp_in_bits { 2885 u8 opcode[0x10]; 2886 u8 uid[0x10]; 2887 u8 reserved_at_20[0x10]; 2888 u8 op_mod[0x10]; 2889 u8 reserved_at_40[0x8]; 2890 u8 qpn[0x18]; 2891 u8 reserved_at_60[0x20]; 2892 u8 opt_param_mask[0x20]; 2893 u8 reserved_at_a0[0x20]; 2894 struct mlx5_ifc_qpc_bits qpc; 2895 u8 reserved_at_800[0x80]; 2896 }; 2897 2898 struct mlx5_ifc_init2init_qp_out_bits { 2899 u8 status[0x8]; 2900 u8 reserved_at_8[0x18]; 2901 u8 syndrome[0x20]; 2902 u8 reserved_at_40[0x40]; 2903 }; 2904 2905 struct mlx5_ifc_init2init_qp_in_bits { 2906 u8 opcode[0x10]; 2907 u8 uid[0x10]; 2908 u8 reserved_at_20[0x10]; 2909 u8 op_mod[0x10]; 2910 u8 reserved_at_40[0x8]; 2911 u8 qpn[0x18]; 2912 u8 reserved_at_60[0x20]; 2913 u8 opt_param_mask[0x20]; 2914 u8 reserved_at_a0[0x20]; 2915 struct mlx5_ifc_qpc_bits qpc; 2916 u8 reserved_at_800[0x80]; 2917 }; 2918 2919 struct mlx5_ifc_dealloc_pd_out_bits { 2920 u8 status[0x8]; 2921 u8 reserved_0[0x18]; 2922 u8 syndrome[0x20]; 2923 u8 reserved_1[0x40]; 2924 }; 2925 2926 struct mlx5_ifc_dealloc_pd_in_bits { 2927 u8 opcode[0x10]; 2928 u8 reserved_0[0x10]; 2929 u8 reserved_1[0x10]; 2930 u8 op_mod[0x10]; 2931 u8 reserved_2[0x8]; 2932 u8 pd[0x18]; 2933 u8 reserved_3[0x20]; 2934 }; 2935 2936 struct mlx5_ifc_alloc_pd_out_bits { 2937 u8 status[0x8]; 2938 u8 reserved_0[0x18]; 2939 u8 syndrome[0x20]; 2940 u8 reserved_1[0x8]; 2941 u8 pd[0x18]; 2942 u8 reserved_2[0x20]; 2943 }; 2944 2945 struct mlx5_ifc_alloc_pd_in_bits { 2946 u8 opcode[0x10]; 2947 u8 reserved_0[0x10]; 2948 u8 reserved_1[0x10]; 2949 u8 op_mod[0x10]; 2950 u8 reserved_2[0x40]; 2951 }; 2952 2953 #ifdef PEDANTIC 2954 #pragma GCC diagnostic ignored "-Wpedantic" 2955 #endif 2956 struct mlx5_ifc_query_qp_out_bits { 2957 u8 status[0x8]; 2958 u8 reserved_at_8[0x18]; 2959 u8 syndrome[0x20]; 2960 u8 reserved_at_40[0x40]; 2961 u8 opt_param_mask[0x20]; 2962 u8 reserved_at_a0[0x20]; 2963 struct mlx5_ifc_qpc_bits qpc; 2964 u8 reserved_at_800[0x80]; 2965 u8 pas[0][0x40]; 2966 }; 2967 #ifdef PEDANTIC 2968 #pragma GCC diagnostic error "-Wpedantic" 2969 #endif 2970 2971 struct mlx5_ifc_query_qp_in_bits { 2972 u8 opcode[0x10]; 2973 u8 reserved_at_10[0x10]; 2974 u8 reserved_at_20[0x10]; 2975 u8 op_mod[0x10]; 2976 u8 reserved_at_40[0x8]; 2977 u8 qpn[0x18]; 2978 u8 reserved_at_60[0x20]; 2979 }; 2980 2981 enum { 2982 MLX5_DATA_RATE = 0x0, 2983 MLX5_WQE_RATE = 0x1, 2984 }; 2985 2986 struct mlx5_ifc_set_pp_rate_limit_context_bits { 2987 u8 rate_limit[0x20]; 2988 u8 burst_upper_bound[0x20]; 2989 u8 reserved_at_40[0xC]; 2990 u8 rate_mode[0x4]; 2991 u8 typical_packet_size[0x10]; 2992 u8 reserved_at_60[0x120]; 2993 }; 2994 2995 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 2996 2997 #ifdef PEDANTIC 2998 #pragma GCC diagnostic ignored "-Wpedantic" 2999 #endif 3000 struct mlx5_ifc_access_register_out_bits { 3001 u8 status[0x8]; 3002 u8 reserved_at_8[0x18]; 3003 u8 syndrome[0x20]; 3004 u8 reserved_at_40[0x40]; 3005 u8 register_data[0][0x20]; 3006 }; 3007 3008 struct mlx5_ifc_access_register_in_bits { 3009 u8 opcode[0x10]; 3010 u8 reserved_at_10[0x10]; 3011 u8 reserved_at_20[0x10]; 3012 u8 op_mod[0x10]; 3013 u8 reserved_at_40[0x10]; 3014 u8 register_id[0x10]; 3015 u8 argument[0x20]; 3016 u8 register_data[0][0x20]; 3017 }; 3018 #ifdef PEDANTIC 3019 #pragma GCC diagnostic error "-Wpedantic" 3020 #endif 3021 3022 enum { 3023 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 3024 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 3025 }; 3026 3027 enum { 3028 MLX5_REGISTER_ID_MTUTC = 0x9055, 3029 }; 3030 3031 struct mlx5_ifc_register_mtutc_bits { 3032 u8 time_stamp_mode[0x2]; 3033 u8 time_stamp_state[0x2]; 3034 u8 reserved_at_4[0x18]; 3035 u8 operation[0x4]; 3036 u8 freq_adjustment[0x20]; 3037 u8 reserved_at_40[0x40]; 3038 u8 utc_sec[0x20]; 3039 u8 utc_nsec[0x20]; 3040 u8 time_adjustment[0x20]; 3041 }; 3042 3043 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 3044 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 3045 3046 struct mlx5_ifc_parse_graph_arc_bits { 3047 u8 start_inner_tunnel[0x1]; 3048 u8 reserved_at_1[0x7]; 3049 u8 arc_parse_graph_node[0x8]; 3050 u8 compare_condition_value[0x10]; 3051 u8 parse_graph_node_handle[0x20]; 3052 u8 reserved_at_40[0x40]; 3053 }; 3054 3055 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 3056 u8 flow_match_sample_en[0x1]; 3057 u8 reserved_at_1[0x3]; 3058 u8 flow_match_sample_offset_mode[0x4]; 3059 u8 reserved_at_5[0x8]; 3060 u8 flow_match_sample_field_offset[0x10]; 3061 u8 reserved_at_32[0x4]; 3062 u8 flow_match_sample_field_offset_shift[0x4]; 3063 u8 flow_match_sample_field_base_offset[0x8]; 3064 u8 reserved_at_48[0xd]; 3065 u8 flow_match_sample_tunnel_mode[0x3]; 3066 u8 flow_match_sample_field_offset_mask[0x20]; 3067 u8 flow_match_sample_field_id[0x20]; 3068 }; 3069 3070 struct mlx5_ifc_parse_graph_flex_bits { 3071 u8 modify_field_select[0x40]; 3072 u8 reserved_at_64[0x20]; 3073 u8 header_length_base_value[0x10]; 3074 u8 reserved_at_112[0x4]; 3075 u8 header_length_field_shift[0x4]; 3076 u8 reserved_at_120[0x4]; 3077 u8 header_length_mode[0x4]; 3078 u8 header_length_field_offset[0x10]; 3079 u8 next_header_field_offset[0x10]; 3080 u8 reserved_at_160[0x1b]; 3081 u8 next_header_field_size[0x5]; 3082 u8 header_length_field_mask[0x20]; 3083 u8 reserved_at_224[0x20]; 3084 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 3085 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 3086 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 3087 }; 3088 3089 struct mlx5_ifc_create_flex_parser_in_bits { 3090 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3091 struct mlx5_ifc_parse_graph_flex_bits flex; 3092 }; 3093 3094 struct mlx5_ifc_create_flex_parser_out_bits { 3095 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3096 struct mlx5_ifc_parse_graph_flex_bits flex; 3097 }; 3098 3099 struct mlx5_ifc_parse_graph_flex_out_bits { 3100 u8 status[0x8]; 3101 u8 reserved_at_8[0x18]; 3102 u8 syndrome[0x20]; 3103 u8 reserved_at_40[0x40]; 3104 struct mlx5_ifc_parse_graph_flex_bits capability; 3105 }; 3106 3107 struct regexp_params_field_select_bits { 3108 u8 reserved_at_0[0x1e]; 3109 u8 stop_engine[0x1]; 3110 u8 db_umem_id[0x1]; 3111 }; 3112 3113 struct mlx5_ifc_regexp_params_bits { 3114 u8 reserved_at_0[0x1f]; 3115 u8 stop_engine[0x1]; 3116 u8 db_umem_id[0x20]; 3117 u8 db_umem_offset[0x40]; 3118 u8 reserved_at_80[0x100]; 3119 }; 3120 3121 struct mlx5_ifc_set_regexp_params_in_bits { 3122 u8 opcode[0x10]; 3123 u8 uid[0x10]; 3124 u8 reserved_at_20[0x10]; 3125 u8 op_mod[0x10]; 3126 u8 reserved_at_40[0x18]; 3127 u8 engine_id[0x8]; 3128 struct regexp_params_field_select_bits field_select; 3129 struct mlx5_ifc_regexp_params_bits regexp_params; 3130 }; 3131 3132 struct mlx5_ifc_set_regexp_params_out_bits { 3133 u8 status[0x8]; 3134 u8 reserved_at_8[0x18]; 3135 u8 syndrome[0x20]; 3136 u8 reserved_at_18[0x40]; 3137 }; 3138 3139 struct mlx5_ifc_query_regexp_params_in_bits { 3140 u8 opcode[0x10]; 3141 u8 uid[0x10]; 3142 u8 reserved_at_20[0x10]; 3143 u8 op_mod[0x10]; 3144 u8 reserved_at_40[0x18]; 3145 u8 engine_id[0x8]; 3146 u8 reserved[0x20]; 3147 }; 3148 3149 struct mlx5_ifc_query_regexp_params_out_bits { 3150 u8 status[0x8]; 3151 u8 reserved_at_8[0x18]; 3152 u8 syndrome[0x20]; 3153 u8 reserved[0x40]; 3154 struct mlx5_ifc_regexp_params_bits regexp_params; 3155 }; 3156 3157 struct mlx5_ifc_set_regexp_register_in_bits { 3158 u8 opcode[0x10]; 3159 u8 uid[0x10]; 3160 u8 reserved_at_20[0x10]; 3161 u8 op_mod[0x10]; 3162 u8 reserved_at_40[0x18]; 3163 u8 engine_id[0x8]; 3164 u8 register_address[0x20]; 3165 u8 register_data[0x20]; 3166 u8 reserved[0x60]; 3167 }; 3168 3169 struct mlx5_ifc_set_regexp_register_out_bits { 3170 u8 status[0x8]; 3171 u8 reserved_at_8[0x18]; 3172 u8 syndrome[0x20]; 3173 u8 reserved[0x40]; 3174 }; 3175 3176 struct mlx5_ifc_query_regexp_register_in_bits { 3177 u8 opcode[0x10]; 3178 u8 uid[0x10]; 3179 u8 reserved_at_20[0x10]; 3180 u8 op_mod[0x10]; 3181 u8 reserved_at_40[0x18]; 3182 u8 engine_id[0x8]; 3183 u8 register_address[0x20]; 3184 }; 3185 3186 struct mlx5_ifc_query_regexp_register_out_bits { 3187 u8 status[0x8]; 3188 u8 reserved_at_8[0x18]; 3189 u8 syndrome[0x20]; 3190 u8 reserved[0x20]; 3191 u8 register_data[0x20]; 3192 }; 3193 3194 /* CQE format mask. */ 3195 #define MLX5E_CQE_FORMAT_MASK 0xc 3196 3197 /* MPW opcode. */ 3198 #define MLX5_OPC_MOD_MPW 0x01 3199 3200 /* Compressed Rx CQE structure. */ 3201 struct mlx5_mini_cqe8 { 3202 union { 3203 uint32_t rx_hash_result; 3204 struct { 3205 union { 3206 uint16_t checksum; 3207 uint16_t flow_tag_high; 3208 struct { 3209 uint8_t reserved; 3210 uint8_t hdr_type; 3211 }; 3212 }; 3213 uint16_t stride_idx; 3214 }; 3215 struct { 3216 uint16_t wqe_counter; 3217 uint8_t s_wqe_opcode; 3218 uint8_t reserved; 3219 } s_wqe_info; 3220 }; 3221 union { 3222 uint32_t byte_cnt_flow; 3223 uint32_t byte_cnt; 3224 }; 3225 }; 3226 3227 /* Mini CQE responder format. */ 3228 enum { 3229 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 3230 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 3231 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 3232 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 3233 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 3234 }; 3235 3236 /* srTCM PRM flow meter parameters. */ 3237 enum { 3238 MLX5_FLOW_COLOR_RED = 0, 3239 MLX5_FLOW_COLOR_YELLOW, 3240 MLX5_FLOW_COLOR_GREEN, 3241 MLX5_FLOW_COLOR_UNDEFINED, 3242 }; 3243 3244 /* Maximum value of srTCM metering parameters. */ 3245 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F)) 3246 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF) 3247 #define MLX5_SRTCM_EBS_MAX 0 3248 3249 /* The bits meter color use. */ 3250 #define MLX5_MTR_COLOR_BITS 8 3251 3252 /* Length mode of dynamic flex parser graph node. */ 3253 enum mlx5_parse_graph_node_len_mode { 3254 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 3255 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 3256 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 3257 }; 3258 3259 /* Offset mode of the samples of flex parser. */ 3260 enum mlx5_parse_graph_flow_match_sample_offset_mode { 3261 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 3262 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 3263 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 3264 }; 3265 3266 /* Node index for an input / output arc of the flex parser graph. */ 3267 enum mlx5_parse_graph_arc_node_index { 3268 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 3269 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 3270 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 3271 MLX5_GRAPH_ARC_NODE_IP = 0x3, 3272 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 3273 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 3274 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 3275 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 3276 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 3277 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 3278 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 3279 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 3280 }; 3281 3282 /** 3283 * Convert a user mark to flow mark. 3284 * 3285 * @param val 3286 * Mark value to convert. 3287 * 3288 * @return 3289 * Converted mark value. 3290 */ 3291 static inline uint32_t 3292 mlx5_flow_mark_set(uint32_t val) 3293 { 3294 uint32_t ret; 3295 3296 /* 3297 * Add one to the user value to differentiate un-marked flows from 3298 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 3299 * remains untouched. 3300 */ 3301 if (val != MLX5_FLOW_MARK_DEFAULT) 3302 ++val; 3303 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3304 /* 3305 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 3306 * word, byte-swapped by the kernel on little-endian systems. In this 3307 * case, left-shifting the resulting big-endian value ensures the 3308 * least significant 24 bits are retained when converting it back. 3309 */ 3310 ret = rte_cpu_to_be_32(val) >> 8; 3311 #else 3312 ret = val; 3313 #endif 3314 return ret; 3315 } 3316 3317 /** 3318 * Convert a mark to user mark. 3319 * 3320 * @param val 3321 * Mark value to convert. 3322 * 3323 * @return 3324 * Converted mark value. 3325 */ 3326 static inline uint32_t 3327 mlx5_flow_mark_get(uint32_t val) 3328 { 3329 /* 3330 * Subtract one from the retrieved value. It was added by 3331 * mlx5_flow_mark_set() to distinguish unmarked flows. 3332 */ 3333 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3334 return (val >> 8) - 1; 3335 #else 3336 return val - 1; 3337 #endif 3338 } 3339 3340 #endif /* RTE_PMD_MLX5_PRM_H_ */ 3341