1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 struct mlx5_hca_flow_attr { 93 uint32_t tunnel_header_0_1; 94 uint32_t tunnel_header_2_3; 95 }; 96 97 /* HCA supports this number of time periods for LRO. */ 98 #define MLX5_LRO_NUM_SUPP_PERIODS 4 99 100 /* HCA attributes. */ 101 struct mlx5_hca_attr { 102 uint32_t eswitch_manager:1; 103 uint32_t flow_counters_dump:1; 104 uint32_t log_max_rqt_size:5; 105 uint32_t parse_graph_flex_node:1; 106 uint8_t flow_counter_bulk_alloc_bitmap; 107 uint32_t eth_net_offloads:1; 108 uint32_t eth_virt:1; 109 uint32_t wqe_vlan_insert:1; 110 uint32_t csum_cap:1; 111 uint32_t wqe_inline_mode:2; 112 uint32_t vport_inline_mode:3; 113 uint32_t tunnel_stateless_geneve_rx:1; 114 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 115 uint32_t tunnel_stateless_gtp:1; 116 uint32_t lro_cap:1; 117 uint32_t tunnel_lro_gre:1; 118 uint32_t tunnel_lro_vxlan:1; 119 uint32_t lro_max_msg_sz_mode:2; 120 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 121 uint16_t lro_min_mss_size; 122 uint32_t flex_parser_protocols; 123 uint32_t max_geneve_tlv_options; 124 uint32_t max_geneve_tlv_option_data_len; 125 uint32_t hairpin:1; 126 uint32_t log_max_hairpin_queues:5; 127 uint32_t log_max_hairpin_wq_data_sz:5; 128 uint32_t log_max_hairpin_num_packets:5; 129 uint32_t vhca_id:16; 130 uint32_t relaxed_ordering_write:1; 131 uint32_t relaxed_ordering_read:1; 132 uint32_t access_register_user:1; 133 uint32_t wqe_index_ignore:1; 134 uint32_t cross_channel:1; 135 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 136 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 137 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 138 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 139 uint32_t scatter_fcs_w_decap_disable:1; 140 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 141 uint32_t roce:1; 142 uint32_t rq_ts_format:2; 143 uint32_t sq_ts_format:2; 144 uint32_t steering_format_version:4; 145 uint32_t qp_ts_format:2; 146 uint32_t regex:1; 147 uint32_t reg_c_preserve:1; 148 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 149 uint32_t crypto:1; /* Crypto engine is supported. */ 150 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 151 uint32_t dek:1; /* General obj type DEK is supported. */ 152 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 153 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 154 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 155 uint32_t regexp_num_of_engines; 156 uint32_t log_max_ft_sampler_num:8; 157 uint32_t inner_ipv4_ihl:1; 158 uint32_t outer_ipv4_ihl:1; 159 uint32_t geneve_tlv_opt; 160 uint32_t cqe_compression:1; 161 uint32_t mini_cqe_resp_flow_tag:1; 162 uint32_t mini_cqe_resp_l3_l4_tag:1; 163 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 164 struct mlx5_hca_qos_attr qos; 165 struct mlx5_hca_vdpa_attr vdpa; 166 struct mlx5_hca_flow_attr flow; 167 int log_max_qp_sz; 168 int log_max_cq_sz; 169 int log_max_qp; 170 int log_max_cq; 171 uint32_t log_max_pd; 172 uint32_t log_max_mrw_sz; 173 uint32_t log_max_srq; 174 uint32_t log_max_srq_sz; 175 uint32_t rss_ind_tbl_cap; 176 uint32_t mmo_dma_en:1; 177 uint32_t mmo_compress_en:1; 178 uint32_t mmo_decompress_en:1; 179 uint32_t compress_min_block_size:4; 180 uint32_t log_max_mmo_dma:5; 181 uint32_t log_max_mmo_compress:5; 182 uint32_t log_max_mmo_decompress:5; 183 uint32_t umr_modify_entity_size_disabled:1; 184 uint32_t umr_indirect_mkey_disabled:1; 185 }; 186 187 struct mlx5_devx_wq_attr { 188 uint32_t wq_type:4; 189 uint32_t wq_signature:1; 190 uint32_t end_padding_mode:2; 191 uint32_t cd_slave:1; 192 uint32_t hds_skip_first_sge:1; 193 uint32_t log2_hds_buf_size:3; 194 uint32_t page_offset:5; 195 uint32_t lwm:16; 196 uint32_t pd:24; 197 uint32_t uar_page:24; 198 uint64_t dbr_addr; 199 uint32_t hw_counter; 200 uint32_t sw_counter; 201 uint32_t log_wq_stride:4; 202 uint32_t log_wq_pg_sz:5; 203 uint32_t log_wq_sz:5; 204 uint32_t dbr_umem_valid:1; 205 uint32_t wq_umem_valid:1; 206 uint32_t log_hairpin_num_packets:5; 207 uint32_t log_hairpin_data_sz:5; 208 uint32_t single_wqe_log_num_of_strides:4; 209 uint32_t two_byte_shift_en:1; 210 uint32_t single_stride_log_num_of_bytes:3; 211 uint32_t dbr_umem_id; 212 uint32_t wq_umem_id; 213 uint64_t wq_umem_offset; 214 }; 215 216 /* Create RQ attributes structure, used by create RQ operation. */ 217 struct mlx5_devx_create_rq_attr { 218 uint32_t rlky:1; 219 uint32_t delay_drop_en:1; 220 uint32_t scatter_fcs:1; 221 uint32_t vsd:1; 222 uint32_t mem_rq_type:4; 223 uint32_t state:4; 224 uint32_t flush_in_error_en:1; 225 uint32_t hairpin:1; 226 uint32_t ts_format:2; 227 uint32_t user_index:24; 228 uint32_t cqn:24; 229 uint32_t counter_set_id:8; 230 uint32_t rmpn:24; 231 struct mlx5_devx_wq_attr wq_attr; 232 }; 233 234 /* Modify RQ attributes structure, used by modify RQ operation. */ 235 struct mlx5_devx_modify_rq_attr { 236 uint32_t rqn:24; 237 uint32_t rq_state:4; /* Current RQ state. */ 238 uint32_t state:4; /* Required RQ state. */ 239 uint32_t scatter_fcs:1; 240 uint32_t vsd:1; 241 uint32_t counter_set_id:8; 242 uint32_t hairpin_peer_sq:24; 243 uint32_t hairpin_peer_vhca:16; 244 uint64_t modify_bitmask; 245 uint32_t lwm:16; /* Contained WQ lwm. */ 246 }; 247 248 struct mlx5_rx_hash_field_select { 249 uint32_t l3_prot_type:1; 250 uint32_t l4_prot_type:1; 251 uint32_t selected_fields:30; 252 }; 253 254 /* TIR attributes structure, used by TIR operations. */ 255 struct mlx5_devx_tir_attr { 256 uint32_t disp_type:4; 257 uint32_t lro_timeout_period_usecs:16; 258 uint32_t lro_enable_mask:4; 259 uint32_t lro_max_msg_sz:8; 260 uint32_t inline_rqn:24; 261 uint32_t rx_hash_symmetric:1; 262 uint32_t tunneled_offload_en:1; 263 uint32_t indirect_table:24; 264 uint32_t rx_hash_fn:4; 265 uint32_t self_lb_block:2; 266 uint32_t transport_domain:24; 267 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 268 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 269 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 270 }; 271 272 /* TIR attributes structure, used by TIR modify. */ 273 struct mlx5_devx_modify_tir_attr { 274 uint32_t tirn:24; 275 uint64_t modify_bitmask; 276 struct mlx5_devx_tir_attr tir; 277 }; 278 279 /* RQT attributes structure, used by RQT operations. */ 280 struct mlx5_devx_rqt_attr { 281 uint8_t rq_type; 282 uint32_t rqt_max_size:16; 283 uint32_t rqt_actual_size:16; 284 uint32_t rq_list[]; 285 }; 286 287 /* TIS attributes structure. */ 288 struct mlx5_devx_tis_attr { 289 uint32_t strict_lag_tx_port_affinity:1; 290 uint32_t tls_en:1; 291 uint32_t lag_tx_port_affinity:4; 292 uint32_t prio:4; 293 uint32_t transport_domain:24; 294 }; 295 296 /* SQ attributes structure, used by SQ create operation. */ 297 struct mlx5_devx_create_sq_attr { 298 uint32_t rlky:1; 299 uint32_t cd_master:1; 300 uint32_t fre:1; 301 uint32_t flush_in_error_en:1; 302 uint32_t allow_multi_pkt_send_wqe:1; 303 uint32_t min_wqe_inline_mode:3; 304 uint32_t state:4; 305 uint32_t reg_umr:1; 306 uint32_t allow_swp:1; 307 uint32_t hairpin:1; 308 uint32_t non_wire:1; 309 uint32_t static_sq_wq:1; 310 uint32_t ts_format:2; 311 uint32_t user_index:24; 312 uint32_t cqn:24; 313 uint32_t packet_pacing_rate_limit_index:16; 314 uint32_t tis_lst_sz:16; 315 uint32_t tis_num:24; 316 struct mlx5_devx_wq_attr wq_attr; 317 }; 318 319 /* SQ attributes structure, used by SQ modify operation. */ 320 struct mlx5_devx_modify_sq_attr { 321 uint32_t sq_state:4; 322 uint32_t state:4; 323 uint32_t hairpin_peer_rq:24; 324 uint32_t hairpin_peer_vhca:16; 325 }; 326 327 328 /* CQ attributes structure, used by CQ operations. */ 329 struct mlx5_devx_cq_attr { 330 uint32_t q_umem_valid:1; 331 uint32_t db_umem_valid:1; 332 uint32_t use_first_only:1; 333 uint32_t overrun_ignore:1; 334 uint32_t cqe_comp_en:1; 335 uint32_t mini_cqe_res_format:2; 336 uint32_t mini_cqe_res_format_ext:2; 337 uint32_t log_cq_size:5; 338 uint32_t log_page_size:5; 339 uint32_t uar_page_id; 340 uint32_t q_umem_id; 341 uint64_t q_umem_offset; 342 uint32_t db_umem_id; 343 uint64_t db_umem_offset; 344 uint32_t eqn; 345 uint64_t db_addr; 346 }; 347 348 /* Virtq attributes structure, used by VIRTQ operations. */ 349 struct mlx5_devx_virtq_attr { 350 uint16_t hw_available_index; 351 uint16_t hw_used_index; 352 uint16_t q_size; 353 uint32_t pd:24; 354 uint32_t virtio_version_1_0:1; 355 uint32_t tso_ipv4:1; 356 uint32_t tso_ipv6:1; 357 uint32_t tx_csum:1; 358 uint32_t rx_csum:1; 359 uint32_t event_mode:3; 360 uint32_t state:4; 361 uint32_t hw_latency_mode:2; 362 uint32_t hw_max_latency_us:12; 363 uint32_t hw_max_pending_comp:16; 364 uint32_t dirty_bitmap_dump_enable:1; 365 uint32_t dirty_bitmap_mkey; 366 uint32_t dirty_bitmap_size; 367 uint32_t mkey; 368 uint32_t qp_id; 369 uint32_t queue_index; 370 uint32_t tis_id; 371 uint32_t counters_obj_id; 372 uint64_t dirty_bitmap_addr; 373 uint64_t type; 374 uint64_t desc_addr; 375 uint64_t used_addr; 376 uint64_t available_addr; 377 struct { 378 uint32_t id; 379 uint32_t size; 380 uint64_t offset; 381 } umems[3]; 382 uint8_t error_type; 383 }; 384 385 386 struct mlx5_devx_qp_attr { 387 uint32_t pd:24; 388 uint32_t uar_index:24; 389 uint32_t cqn:24; 390 uint32_t log_page_size:5; 391 uint32_t rq_size:17; /* Must be power of 2. */ 392 uint32_t log_rq_stride:3; 393 uint32_t sq_size:17; /* Must be power of 2. */ 394 uint32_t ts_format:2; 395 uint32_t dbr_umem_valid:1; 396 uint32_t dbr_umem_id; 397 uint64_t dbr_address; 398 uint32_t wq_umem_id; 399 uint64_t wq_umem_offset; 400 uint32_t user_index:24; 401 }; 402 403 struct mlx5_devx_virtio_q_couners_attr { 404 uint64_t received_desc; 405 uint64_t completed_desc; 406 uint32_t error_cqes; 407 uint32_t bad_desc_errors; 408 uint32_t exceed_max_chain; 409 uint32_t invalid_buffer; 410 }; 411 412 /* 413 * graph flow match sample attributes structure, 414 * used by flex parser operations. 415 */ 416 struct mlx5_devx_match_sample_attr { 417 uint32_t flow_match_sample_en:1; 418 uint32_t flow_match_sample_field_offset:16; 419 uint32_t flow_match_sample_offset_mode:4; 420 uint32_t flow_match_sample_field_offset_mask; 421 uint32_t flow_match_sample_field_offset_shift:4; 422 uint32_t flow_match_sample_field_base_offset:8; 423 uint32_t flow_match_sample_tunnel_mode:3; 424 uint32_t flow_match_sample_field_id; 425 }; 426 427 /* graph node arc attributes structure, used by flex parser operations. */ 428 struct mlx5_devx_graph_arc_attr { 429 uint32_t compare_condition_value:16; 430 uint32_t start_inner_tunnel:1; 431 uint32_t arc_parse_graph_node:8; 432 uint32_t parse_graph_node_handle; 433 }; 434 435 /* Maximal number of samples per graph node. */ 436 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 437 438 /* Maximal number of input/output arcs per graph node. */ 439 #define MLX5_GRAPH_NODE_ARC_NUM 8 440 441 /* parse graph node attributes structure, used by flex parser operations. */ 442 struct mlx5_devx_graph_node_attr { 443 uint32_t modify_field_select; 444 uint32_t header_length_mode:4; 445 uint32_t header_length_base_value:16; 446 uint32_t header_length_field_shift:4; 447 uint32_t header_length_field_offset:16; 448 uint32_t header_length_field_mask; 449 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 450 uint32_t next_header_field_offset:16; 451 uint32_t next_header_field_size:5; 452 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 453 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 454 }; 455 456 /* Encryption key size is up to 1024 bit, 128 bytes. */ 457 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 458 459 struct mlx5_devx_dek_attr { 460 uint32_t key_size:4; 461 uint32_t has_keytag:1; 462 uint32_t key_purpose:4; 463 uint32_t pd:24; 464 uint64_t opaque; 465 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 466 }; 467 468 struct mlx5_devx_import_kek_attr { 469 uint64_t modify_field_select; 470 uint32_t state:8; 471 uint32_t key_size:4; 472 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 473 }; 474 475 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 476 477 struct mlx5_devx_credential_attr { 478 uint64_t modify_field_select; 479 uint32_t state:8; 480 uint32_t credential_role:8; 481 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 482 }; 483 484 struct mlx5_devx_crypto_login_attr { 485 uint64_t modify_field_select; 486 uint32_t credential_pointer:24; 487 uint32_t session_import_kek_ptr:24; 488 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 489 }; 490 491 /* mlx5_devx_cmds.c */ 492 493 __rte_internal 494 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 495 uint32_t bulk_sz); 496 __rte_internal 497 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 498 __rte_internal 499 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 500 int clear, uint32_t n_counters, 501 uint64_t *pkts, uint64_t *bytes, 502 uint32_t mkey, void *addr, 503 void *cmd_comp, 504 uint64_t async_id); 505 __rte_internal 506 int mlx5_devx_cmd_query_hca_attr(void *ctx, 507 struct mlx5_hca_attr *attr); 508 __rte_internal 509 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 510 struct mlx5_devx_mkey_attr *attr); 511 __rte_internal 512 int mlx5_devx_get_out_command_status(void *out); 513 __rte_internal 514 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 515 uint32_t *tis_td); 516 __rte_internal 517 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 518 struct mlx5_devx_create_rq_attr *rq_attr, 519 int socket); 520 __rte_internal 521 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 522 struct mlx5_devx_modify_rq_attr *rq_attr); 523 __rte_internal 524 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 525 struct mlx5_devx_tir_attr *tir_attr); 526 __rte_internal 527 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 528 struct mlx5_devx_rqt_attr *rqt_attr); 529 __rte_internal 530 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 531 struct mlx5_devx_create_sq_attr *sq_attr); 532 __rte_internal 533 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 534 struct mlx5_devx_modify_sq_attr *sq_attr); 535 __rte_internal 536 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 537 struct mlx5_devx_tis_attr *tis_attr); 538 __rte_internal 539 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 540 __rte_internal 541 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 542 FILE *file); 543 __rte_internal 544 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 545 __rte_internal 546 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 547 struct mlx5_devx_cq_attr *attr); 548 __rte_internal 549 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 550 struct mlx5_devx_virtq_attr *attr); 551 __rte_internal 552 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 553 struct mlx5_devx_virtq_attr *attr); 554 __rte_internal 555 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 556 struct mlx5_devx_virtq_attr *attr); 557 __rte_internal 558 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 559 struct mlx5_devx_qp_attr *attr); 560 __rte_internal 561 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 562 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 563 __rte_internal 564 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 565 struct mlx5_devx_rqt_attr *rqt_attr); 566 __rte_internal 567 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 568 struct mlx5_devx_modify_tir_attr *tir_attr); 569 __rte_internal 570 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 571 uint32_t ids[], uint32_t num); 572 573 __rte_internal 574 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 575 struct mlx5_devx_graph_node_attr *data); 576 577 __rte_internal 578 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 579 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 580 581 __rte_internal 582 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 583 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 584 585 __rte_internal 586 struct mlx5_devx_obj * 587 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 588 uint16_t class, uint8_t type, uint8_t len); 589 590 /** 591 * Create virtio queue counters object DevX API. 592 * 593 * @param[in] ctx 594 * Device context. 595 596 * @return 597 * The DevX object created, NULL otherwise and rte_errno is set. 598 */ 599 __rte_internal 600 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 601 602 /** 603 * Query virtio queue counters object using DevX API. 604 * 605 * @param[in] couners_obj 606 * Pointer to virtq object structure. 607 * @param [in/out] attr 608 * Pointer to virtio queue counters attributes structure. 609 * 610 * @return 611 * 0 on success, a negative errno value otherwise and rte_errno is set. 612 */ 613 __rte_internal 614 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 615 struct mlx5_devx_virtio_q_couners_attr *attr); 616 __rte_internal 617 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 618 uint32_t pd); 619 __rte_internal 620 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 621 622 __rte_internal 623 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 624 625 __rte_internal 626 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 627 __rte_internal 628 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 629 uint32_t *out_of_buffers); 630 __rte_internal 631 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 632 uint32_t pd, uint32_t log_obj_size); 633 634 /** 635 * Create general object of type FLOW_METER_ASO using DevX API.. 636 * 637 * @param[in] ctx 638 * Device context. 639 * @param [in] pd 640 * PD value to associate the FLOW_METER_ASO object with. 641 * @param [in] log_obj_size 642 * log_obj_size define to allocate number of 2 * meters 643 * in one FLOW_METER_ASO object. 644 * 645 * @return 646 * The DevX object created, NULL otherwise and rte_errno is set. 647 */ 648 __rte_internal 649 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 650 uint32_t pd, uint32_t log_obj_size); 651 __rte_internal 652 struct mlx5_devx_obj * 653 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 654 655 __rte_internal 656 struct mlx5_devx_obj * 657 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 658 struct mlx5_devx_import_kek_attr *attr); 659 660 __rte_internal 661 struct mlx5_devx_obj * 662 mlx5_devx_cmd_create_credential_obj(void *ctx, 663 struct mlx5_devx_credential_attr *attr); 664 665 __rte_internal 666 struct mlx5_devx_obj * 667 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 668 struct mlx5_devx_crypto_login_attr *attr); 669 670 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 671