1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 struct mlx5_hca_flow_attr { 93 uint32_t tunnel_header_0_1; 94 uint32_t tunnel_header_2_3; 95 }; 96 97 /* HCA supports this number of time periods for LRO. */ 98 #define MLX5_LRO_NUM_SUPP_PERIODS 4 99 100 /* HCA attributes. */ 101 struct mlx5_hca_attr { 102 uint32_t eswitch_manager:1; 103 uint32_t flow_counters_dump:1; 104 uint32_t log_max_rqt_size:5; 105 uint32_t parse_graph_flex_node:1; 106 uint8_t flow_counter_bulk_alloc_bitmap; 107 uint32_t eth_net_offloads:1; 108 uint32_t eth_virt:1; 109 uint32_t wqe_vlan_insert:1; 110 uint32_t csum_cap:1; 111 uint32_t wqe_inline_mode:2; 112 uint32_t vport_inline_mode:3; 113 uint32_t tunnel_stateless_geneve_rx:1; 114 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 115 uint32_t tunnel_stateless_gtp:1; 116 uint32_t lro_cap:1; 117 uint32_t tunnel_lro_gre:1; 118 uint32_t tunnel_lro_vxlan:1; 119 uint32_t tunnel_stateless_gre:1; 120 uint32_t tunnel_stateless_vxlan:1; 121 uint32_t swp:1; 122 uint32_t swp_csum:1; 123 uint32_t swp_lso:1; 124 uint32_t lro_max_msg_sz_mode:2; 125 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 126 uint16_t lro_min_mss_size; 127 uint32_t flex_parser_protocols; 128 uint32_t max_geneve_tlv_options; 129 uint32_t max_geneve_tlv_option_data_len; 130 uint32_t hairpin:1; 131 uint32_t log_max_hairpin_queues:5; 132 uint32_t log_max_hairpin_wq_data_sz:5; 133 uint32_t log_max_hairpin_num_packets:5; 134 uint32_t vhca_id:16; 135 uint32_t relaxed_ordering_write:1; 136 uint32_t relaxed_ordering_read:1; 137 uint32_t access_register_user:1; 138 uint32_t wqe_index_ignore:1; 139 uint32_t cross_channel:1; 140 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 141 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 142 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 143 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 144 uint32_t scatter_fcs_w_decap_disable:1; 145 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 146 uint32_t roce:1; 147 uint32_t rq_ts_format:2; 148 uint32_t sq_ts_format:2; 149 uint32_t steering_format_version:4; 150 uint32_t qp_ts_format:2; 151 uint32_t regex:1; 152 uint32_t reg_c_preserve:1; 153 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 154 uint32_t crypto:1; /* Crypto engine is supported. */ 155 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 156 uint32_t dek:1; /* General obj type DEK is supported. */ 157 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 158 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 159 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 160 uint32_t regexp_num_of_engines; 161 uint32_t log_max_ft_sampler_num:8; 162 uint32_t inner_ipv4_ihl:1; 163 uint32_t outer_ipv4_ihl:1; 164 uint32_t geneve_tlv_opt; 165 uint32_t cqe_compression:1; 166 uint32_t mini_cqe_resp_flow_tag:1; 167 uint32_t mini_cqe_resp_l3_l4_tag:1; 168 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 169 struct mlx5_hca_qos_attr qos; 170 struct mlx5_hca_vdpa_attr vdpa; 171 struct mlx5_hca_flow_attr flow; 172 int log_max_qp_sz; 173 int log_max_cq_sz; 174 int log_max_qp; 175 int log_max_cq; 176 uint32_t log_max_pd; 177 uint32_t log_max_mrw_sz; 178 uint32_t log_max_srq; 179 uint32_t log_max_srq_sz; 180 uint32_t rss_ind_tbl_cap; 181 uint32_t mmo_dma_sq_en:1; 182 uint32_t mmo_compress_sq_en:1; 183 uint32_t mmo_decompress_sq_en:1; 184 uint32_t mmo_dma_qp_en:1; 185 uint32_t mmo_compress_qp_en:1; 186 uint32_t mmo_decompress_qp_en:1; 187 uint32_t mmo_regex_qp_en:1; 188 uint32_t mmo_regex_sq_en:1; 189 uint32_t compress_min_block_size:4; 190 uint32_t log_max_mmo_dma:5; 191 uint32_t log_max_mmo_compress:5; 192 uint32_t log_max_mmo_decompress:5; 193 uint32_t umr_modify_entity_size_disabled:1; 194 uint32_t umr_indirect_mkey_disabled:1; 195 }; 196 197 struct mlx5_devx_wq_attr { 198 uint32_t wq_type:4; 199 uint32_t wq_signature:1; 200 uint32_t end_padding_mode:2; 201 uint32_t cd_slave:1; 202 uint32_t hds_skip_first_sge:1; 203 uint32_t log2_hds_buf_size:3; 204 uint32_t page_offset:5; 205 uint32_t lwm:16; 206 uint32_t pd:24; 207 uint32_t uar_page:24; 208 uint64_t dbr_addr; 209 uint32_t hw_counter; 210 uint32_t sw_counter; 211 uint32_t log_wq_stride:4; 212 uint32_t log_wq_pg_sz:5; 213 uint32_t log_wq_sz:5; 214 uint32_t dbr_umem_valid:1; 215 uint32_t wq_umem_valid:1; 216 uint32_t log_hairpin_num_packets:5; 217 uint32_t log_hairpin_data_sz:5; 218 uint32_t single_wqe_log_num_of_strides:4; 219 uint32_t two_byte_shift_en:1; 220 uint32_t single_stride_log_num_of_bytes:3; 221 uint32_t dbr_umem_id; 222 uint32_t wq_umem_id; 223 uint64_t wq_umem_offset; 224 }; 225 226 /* Create RQ attributes structure, used by create RQ operation. */ 227 struct mlx5_devx_create_rq_attr { 228 uint32_t rlky:1; 229 uint32_t delay_drop_en:1; 230 uint32_t scatter_fcs:1; 231 uint32_t vsd:1; 232 uint32_t mem_rq_type:4; 233 uint32_t state:4; 234 uint32_t flush_in_error_en:1; 235 uint32_t hairpin:1; 236 uint32_t ts_format:2; 237 uint32_t user_index:24; 238 uint32_t cqn:24; 239 uint32_t counter_set_id:8; 240 uint32_t rmpn:24; 241 struct mlx5_devx_wq_attr wq_attr; 242 }; 243 244 /* Modify RQ attributes structure, used by modify RQ operation. */ 245 struct mlx5_devx_modify_rq_attr { 246 uint32_t rqn:24; 247 uint32_t rq_state:4; /* Current RQ state. */ 248 uint32_t state:4; /* Required RQ state. */ 249 uint32_t scatter_fcs:1; 250 uint32_t vsd:1; 251 uint32_t counter_set_id:8; 252 uint32_t hairpin_peer_sq:24; 253 uint32_t hairpin_peer_vhca:16; 254 uint64_t modify_bitmask; 255 uint32_t lwm:16; /* Contained WQ lwm. */ 256 }; 257 258 struct mlx5_rx_hash_field_select { 259 uint32_t l3_prot_type:1; 260 uint32_t l4_prot_type:1; 261 uint32_t selected_fields:30; 262 }; 263 264 /* TIR attributes structure, used by TIR operations. */ 265 struct mlx5_devx_tir_attr { 266 uint32_t disp_type:4; 267 uint32_t lro_timeout_period_usecs:16; 268 uint32_t lro_enable_mask:4; 269 uint32_t lro_max_msg_sz:8; 270 uint32_t inline_rqn:24; 271 uint32_t rx_hash_symmetric:1; 272 uint32_t tunneled_offload_en:1; 273 uint32_t indirect_table:24; 274 uint32_t rx_hash_fn:4; 275 uint32_t self_lb_block:2; 276 uint32_t transport_domain:24; 277 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 278 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 279 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 280 }; 281 282 /* TIR attributes structure, used by TIR modify. */ 283 struct mlx5_devx_modify_tir_attr { 284 uint32_t tirn:24; 285 uint64_t modify_bitmask; 286 struct mlx5_devx_tir_attr tir; 287 }; 288 289 /* RQT attributes structure, used by RQT operations. */ 290 struct mlx5_devx_rqt_attr { 291 uint8_t rq_type; 292 uint32_t rqt_max_size:16; 293 uint32_t rqt_actual_size:16; 294 uint32_t rq_list[]; 295 }; 296 297 /* TIS attributes structure. */ 298 struct mlx5_devx_tis_attr { 299 uint32_t strict_lag_tx_port_affinity:1; 300 uint32_t tls_en:1; 301 uint32_t lag_tx_port_affinity:4; 302 uint32_t prio:4; 303 uint32_t transport_domain:24; 304 }; 305 306 /* SQ attributes structure, used by SQ create operation. */ 307 struct mlx5_devx_create_sq_attr { 308 uint32_t rlky:1; 309 uint32_t cd_master:1; 310 uint32_t fre:1; 311 uint32_t flush_in_error_en:1; 312 uint32_t allow_multi_pkt_send_wqe:1; 313 uint32_t min_wqe_inline_mode:3; 314 uint32_t state:4; 315 uint32_t reg_umr:1; 316 uint32_t allow_swp:1; 317 uint32_t hairpin:1; 318 uint32_t non_wire:1; 319 uint32_t static_sq_wq:1; 320 uint32_t ts_format:2; 321 uint32_t user_index:24; 322 uint32_t cqn:24; 323 uint32_t packet_pacing_rate_limit_index:16; 324 uint32_t tis_lst_sz:16; 325 uint32_t tis_num:24; 326 struct mlx5_devx_wq_attr wq_attr; 327 }; 328 329 /* SQ attributes structure, used by SQ modify operation. */ 330 struct mlx5_devx_modify_sq_attr { 331 uint32_t sq_state:4; 332 uint32_t state:4; 333 uint32_t hairpin_peer_rq:24; 334 uint32_t hairpin_peer_vhca:16; 335 }; 336 337 338 /* CQ attributes structure, used by CQ operations. */ 339 struct mlx5_devx_cq_attr { 340 uint32_t q_umem_valid:1; 341 uint32_t db_umem_valid:1; 342 uint32_t use_first_only:1; 343 uint32_t overrun_ignore:1; 344 uint32_t cqe_comp_en:1; 345 uint32_t mini_cqe_res_format:2; 346 uint32_t mini_cqe_res_format_ext:2; 347 uint32_t log_cq_size:5; 348 uint32_t log_page_size:5; 349 uint32_t uar_page_id; 350 uint32_t q_umem_id; 351 uint64_t q_umem_offset; 352 uint32_t db_umem_id; 353 uint64_t db_umem_offset; 354 uint32_t eqn; 355 uint64_t db_addr; 356 }; 357 358 /* Virtq attributes structure, used by VIRTQ operations. */ 359 struct mlx5_devx_virtq_attr { 360 uint16_t hw_available_index; 361 uint16_t hw_used_index; 362 uint16_t q_size; 363 uint32_t pd:24; 364 uint32_t virtio_version_1_0:1; 365 uint32_t tso_ipv4:1; 366 uint32_t tso_ipv6:1; 367 uint32_t tx_csum:1; 368 uint32_t rx_csum:1; 369 uint32_t event_mode:3; 370 uint32_t state:4; 371 uint32_t hw_latency_mode:2; 372 uint32_t hw_max_latency_us:12; 373 uint32_t hw_max_pending_comp:16; 374 uint32_t dirty_bitmap_dump_enable:1; 375 uint32_t dirty_bitmap_mkey; 376 uint32_t dirty_bitmap_size; 377 uint32_t mkey; 378 uint32_t qp_id; 379 uint32_t queue_index; 380 uint32_t tis_id; 381 uint32_t counters_obj_id; 382 uint64_t dirty_bitmap_addr; 383 uint64_t type; 384 uint64_t desc_addr; 385 uint64_t used_addr; 386 uint64_t available_addr; 387 struct { 388 uint32_t id; 389 uint32_t size; 390 uint64_t offset; 391 } umems[3]; 392 uint8_t error_type; 393 }; 394 395 396 struct mlx5_devx_qp_attr { 397 uint32_t pd:24; 398 uint32_t uar_index:24; 399 uint32_t cqn:24; 400 uint32_t log_page_size:5; 401 uint32_t rq_size:17; /* Must be power of 2. */ 402 uint32_t log_rq_stride:3; 403 uint32_t sq_size:17; /* Must be power of 2. */ 404 uint32_t ts_format:2; 405 uint32_t dbr_umem_valid:1; 406 uint32_t dbr_umem_id; 407 uint64_t dbr_address; 408 uint32_t wq_umem_id; 409 uint64_t wq_umem_offset; 410 uint32_t user_index:24; 411 uint32_t mmo:1; 412 }; 413 414 struct mlx5_devx_virtio_q_couners_attr { 415 uint64_t received_desc; 416 uint64_t completed_desc; 417 uint32_t error_cqes; 418 uint32_t bad_desc_errors; 419 uint32_t exceed_max_chain; 420 uint32_t invalid_buffer; 421 }; 422 423 /* 424 * graph flow match sample attributes structure, 425 * used by flex parser operations. 426 */ 427 struct mlx5_devx_match_sample_attr { 428 uint32_t flow_match_sample_en:1; 429 uint32_t flow_match_sample_field_offset:16; 430 uint32_t flow_match_sample_offset_mode:4; 431 uint32_t flow_match_sample_field_offset_mask; 432 uint32_t flow_match_sample_field_offset_shift:4; 433 uint32_t flow_match_sample_field_base_offset:8; 434 uint32_t flow_match_sample_tunnel_mode:3; 435 uint32_t flow_match_sample_field_id; 436 }; 437 438 /* graph node arc attributes structure, used by flex parser operations. */ 439 struct mlx5_devx_graph_arc_attr { 440 uint32_t compare_condition_value:16; 441 uint32_t start_inner_tunnel:1; 442 uint32_t arc_parse_graph_node:8; 443 uint32_t parse_graph_node_handle; 444 }; 445 446 /* Maximal number of samples per graph node. */ 447 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 448 449 /* Maximal number of input/output arcs per graph node. */ 450 #define MLX5_GRAPH_NODE_ARC_NUM 8 451 452 /* parse graph node attributes structure, used by flex parser operations. */ 453 struct mlx5_devx_graph_node_attr { 454 uint32_t modify_field_select; 455 uint32_t header_length_mode:4; 456 uint32_t header_length_base_value:16; 457 uint32_t header_length_field_shift:4; 458 uint32_t header_length_field_offset:16; 459 uint32_t header_length_field_mask; 460 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 461 uint32_t next_header_field_offset:16; 462 uint32_t next_header_field_size:5; 463 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 464 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 465 }; 466 467 /* Encryption key size is up to 1024 bit, 128 bytes. */ 468 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 469 470 struct mlx5_devx_dek_attr { 471 uint32_t key_size:4; 472 uint32_t has_keytag:1; 473 uint32_t key_purpose:4; 474 uint32_t pd:24; 475 uint64_t opaque; 476 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 477 }; 478 479 struct mlx5_devx_import_kek_attr { 480 uint64_t modify_field_select; 481 uint32_t state:8; 482 uint32_t key_size:4; 483 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 484 }; 485 486 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 487 488 struct mlx5_devx_credential_attr { 489 uint64_t modify_field_select; 490 uint32_t state:8; 491 uint32_t credential_role:8; 492 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 493 }; 494 495 struct mlx5_devx_crypto_login_attr { 496 uint64_t modify_field_select; 497 uint32_t credential_pointer:24; 498 uint32_t session_import_kek_ptr:24; 499 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 500 }; 501 502 /* mlx5_devx_cmds.c */ 503 504 __rte_internal 505 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 506 uint32_t bulk_sz); 507 __rte_internal 508 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 509 __rte_internal 510 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 511 int clear, uint32_t n_counters, 512 uint64_t *pkts, uint64_t *bytes, 513 uint32_t mkey, void *addr, 514 void *cmd_comp, 515 uint64_t async_id); 516 __rte_internal 517 int mlx5_devx_cmd_query_hca_attr(void *ctx, 518 struct mlx5_hca_attr *attr); 519 __rte_internal 520 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 521 struct mlx5_devx_mkey_attr *attr); 522 __rte_internal 523 int mlx5_devx_get_out_command_status(void *out); 524 __rte_internal 525 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 526 uint32_t *tis_td); 527 __rte_internal 528 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 529 struct mlx5_devx_create_rq_attr *rq_attr, 530 int socket); 531 __rte_internal 532 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 533 struct mlx5_devx_modify_rq_attr *rq_attr); 534 __rte_internal 535 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 536 struct mlx5_devx_tir_attr *tir_attr); 537 __rte_internal 538 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 539 struct mlx5_devx_rqt_attr *rqt_attr); 540 __rte_internal 541 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 542 struct mlx5_devx_create_sq_attr *sq_attr); 543 __rte_internal 544 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 545 struct mlx5_devx_modify_sq_attr *sq_attr); 546 __rte_internal 547 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 548 struct mlx5_devx_tis_attr *tis_attr); 549 __rte_internal 550 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 551 __rte_internal 552 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 553 FILE *file); 554 __rte_internal 555 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 556 __rte_internal 557 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 558 struct mlx5_devx_cq_attr *attr); 559 __rte_internal 560 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 561 struct mlx5_devx_virtq_attr *attr); 562 __rte_internal 563 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 564 struct mlx5_devx_virtq_attr *attr); 565 __rte_internal 566 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 567 struct mlx5_devx_virtq_attr *attr); 568 __rte_internal 569 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 570 struct mlx5_devx_qp_attr *attr); 571 __rte_internal 572 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 573 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 574 __rte_internal 575 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 576 struct mlx5_devx_rqt_attr *rqt_attr); 577 __rte_internal 578 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 579 struct mlx5_devx_modify_tir_attr *tir_attr); 580 __rte_internal 581 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 582 uint32_t ids[], uint32_t num); 583 584 __rte_internal 585 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 586 struct mlx5_devx_graph_node_attr *data); 587 588 __rte_internal 589 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 590 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 591 592 __rte_internal 593 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 594 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 595 596 __rte_internal 597 struct mlx5_devx_obj * 598 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 599 uint16_t class, uint8_t type, uint8_t len); 600 601 /** 602 * Create virtio queue counters object DevX API. 603 * 604 * @param[in] ctx 605 * Device context. 606 607 * @return 608 * The DevX object created, NULL otherwise and rte_errno is set. 609 */ 610 __rte_internal 611 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 612 613 /** 614 * Query virtio queue counters object using DevX API. 615 * 616 * @param[in] couners_obj 617 * Pointer to virtq object structure. 618 * @param [in/out] attr 619 * Pointer to virtio queue counters attributes structure. 620 * 621 * @return 622 * 0 on success, a negative errno value otherwise and rte_errno is set. 623 */ 624 __rte_internal 625 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 626 struct mlx5_devx_virtio_q_couners_attr *attr); 627 __rte_internal 628 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 629 uint32_t pd); 630 __rte_internal 631 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 632 633 __rte_internal 634 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 635 636 __rte_internal 637 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 638 __rte_internal 639 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 640 uint32_t *out_of_buffers); 641 __rte_internal 642 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 643 uint32_t pd, uint32_t log_obj_size); 644 645 /** 646 * Create general object of type FLOW_METER_ASO using DevX API.. 647 * 648 * @param[in] ctx 649 * Device context. 650 * @param [in] pd 651 * PD value to associate the FLOW_METER_ASO object with. 652 * @param [in] log_obj_size 653 * log_obj_size define to allocate number of 2 * meters 654 * in one FLOW_METER_ASO object. 655 * 656 * @return 657 * The DevX object created, NULL otherwise and rte_errno is set. 658 */ 659 __rte_internal 660 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 661 uint32_t pd, uint32_t log_obj_size); 662 __rte_internal 663 struct mlx5_devx_obj * 664 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 665 666 __rte_internal 667 struct mlx5_devx_obj * 668 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 669 struct mlx5_devx_import_kek_attr *attr); 670 671 __rte_internal 672 struct mlx5_devx_obj * 673 mlx5_devx_cmd_create_credential_obj(void *ctx, 674 struct mlx5_devx_credential_attr *attr); 675 676 __rte_internal 677 struct mlx5_devx_obj * 678 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 679 struct mlx5_devx_crypto_login_attr *attr); 680 681 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 682