1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 /* HCA supports this number of time periods for LRO. */ 93 #define MLX5_LRO_NUM_SUPP_PERIODS 4 94 95 /* HCA attributes. */ 96 struct mlx5_hca_attr { 97 uint32_t eswitch_manager:1; 98 uint32_t flow_counters_dump:1; 99 uint32_t log_max_rqt_size:5; 100 uint32_t parse_graph_flex_node:1; 101 uint8_t flow_counter_bulk_alloc_bitmap; 102 uint32_t eth_net_offloads:1; 103 uint32_t eth_virt:1; 104 uint32_t wqe_vlan_insert:1; 105 uint32_t csum_cap:1; 106 uint32_t wqe_inline_mode:2; 107 uint32_t vport_inline_mode:3; 108 uint32_t tunnel_stateless_geneve_rx:1; 109 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 110 uint32_t tunnel_stateless_gtp:1; 111 uint32_t lro_cap:1; 112 uint32_t tunnel_lro_gre:1; 113 uint32_t tunnel_lro_vxlan:1; 114 uint32_t lro_max_msg_sz_mode:2; 115 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 116 uint16_t lro_min_mss_size; 117 uint32_t flex_parser_protocols; 118 uint32_t max_geneve_tlv_options; 119 uint32_t max_geneve_tlv_option_data_len; 120 uint32_t hairpin:1; 121 uint32_t log_max_hairpin_queues:5; 122 uint32_t log_max_hairpin_wq_data_sz:5; 123 uint32_t log_max_hairpin_num_packets:5; 124 uint32_t vhca_id:16; 125 uint32_t relaxed_ordering_write:1; 126 uint32_t relaxed_ordering_read:1; 127 uint32_t access_register_user:1; 128 uint32_t wqe_index_ignore:1; 129 uint32_t cross_channel:1; 130 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 131 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 132 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 133 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 134 uint32_t scatter_fcs_w_decap_disable:1; 135 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 136 uint32_t roce:1; 137 uint32_t rq_ts_format:2; 138 uint32_t sq_ts_format:2; 139 uint32_t qp_ts_format:2; 140 uint32_t regex:1; 141 uint32_t reg_c_preserve:1; 142 uint32_t crypto:1; /* Crypto engine is supported. */ 143 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 144 uint32_t dek:1; /* General obj type DEK is supported. */ 145 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 146 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 147 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 148 uint32_t regexp_num_of_engines; 149 uint32_t log_max_ft_sampler_num:8; 150 uint32_t geneve_tlv_opt; 151 uint32_t cqe_compression:1; 152 uint32_t mini_cqe_resp_flow_tag:1; 153 uint32_t mini_cqe_resp_l3_l4_tag:1; 154 struct mlx5_hca_qos_attr qos; 155 struct mlx5_hca_vdpa_attr vdpa; 156 int log_max_qp_sz; 157 int log_max_cq_sz; 158 int log_max_qp; 159 int log_max_cq; 160 uint32_t log_max_pd; 161 uint32_t log_max_mrw_sz; 162 uint32_t log_max_srq; 163 uint32_t log_max_srq_sz; 164 uint32_t rss_ind_tbl_cap; 165 uint32_t mmo_dma_en:1; 166 uint32_t mmo_compress_en:1; 167 uint32_t mmo_decompress_en:1; 168 uint32_t compress_min_block_size:4; 169 uint32_t log_max_mmo_dma:5; 170 uint32_t log_max_mmo_compress:5; 171 uint32_t log_max_mmo_decompress:5; 172 uint32_t umr_modify_entity_size_disabled:1; 173 uint32_t umr_indirect_mkey_disabled:1; 174 }; 175 176 struct mlx5_devx_wq_attr { 177 uint32_t wq_type:4; 178 uint32_t wq_signature:1; 179 uint32_t end_padding_mode:2; 180 uint32_t cd_slave:1; 181 uint32_t hds_skip_first_sge:1; 182 uint32_t log2_hds_buf_size:3; 183 uint32_t page_offset:5; 184 uint32_t lwm:16; 185 uint32_t pd:24; 186 uint32_t uar_page:24; 187 uint64_t dbr_addr; 188 uint32_t hw_counter; 189 uint32_t sw_counter; 190 uint32_t log_wq_stride:4; 191 uint32_t log_wq_pg_sz:5; 192 uint32_t log_wq_sz:5; 193 uint32_t dbr_umem_valid:1; 194 uint32_t wq_umem_valid:1; 195 uint32_t log_hairpin_num_packets:5; 196 uint32_t log_hairpin_data_sz:5; 197 uint32_t single_wqe_log_num_of_strides:4; 198 uint32_t two_byte_shift_en:1; 199 uint32_t single_stride_log_num_of_bytes:3; 200 uint32_t dbr_umem_id; 201 uint32_t wq_umem_id; 202 uint64_t wq_umem_offset; 203 }; 204 205 /* Create RQ attributes structure, used by create RQ operation. */ 206 struct mlx5_devx_create_rq_attr { 207 uint32_t rlky:1; 208 uint32_t delay_drop_en:1; 209 uint32_t scatter_fcs:1; 210 uint32_t vsd:1; 211 uint32_t mem_rq_type:4; 212 uint32_t state:4; 213 uint32_t flush_in_error_en:1; 214 uint32_t hairpin:1; 215 uint32_t ts_format:2; 216 uint32_t user_index:24; 217 uint32_t cqn:24; 218 uint32_t counter_set_id:8; 219 uint32_t rmpn:24; 220 struct mlx5_devx_wq_attr wq_attr; 221 }; 222 223 /* Modify RQ attributes structure, used by modify RQ operation. */ 224 struct mlx5_devx_modify_rq_attr { 225 uint32_t rqn:24; 226 uint32_t rq_state:4; /* Current RQ state. */ 227 uint32_t state:4; /* Required RQ state. */ 228 uint32_t scatter_fcs:1; 229 uint32_t vsd:1; 230 uint32_t counter_set_id:8; 231 uint32_t hairpin_peer_sq:24; 232 uint32_t hairpin_peer_vhca:16; 233 uint64_t modify_bitmask; 234 uint32_t lwm:16; /* Contained WQ lwm. */ 235 }; 236 237 struct mlx5_rx_hash_field_select { 238 uint32_t l3_prot_type:1; 239 uint32_t l4_prot_type:1; 240 uint32_t selected_fields:30; 241 }; 242 243 /* TIR attributes structure, used by TIR operations. */ 244 struct mlx5_devx_tir_attr { 245 uint32_t disp_type:4; 246 uint32_t lro_timeout_period_usecs:16; 247 uint32_t lro_enable_mask:4; 248 uint32_t lro_max_msg_sz:8; 249 uint32_t inline_rqn:24; 250 uint32_t rx_hash_symmetric:1; 251 uint32_t tunneled_offload_en:1; 252 uint32_t indirect_table:24; 253 uint32_t rx_hash_fn:4; 254 uint32_t self_lb_block:2; 255 uint32_t transport_domain:24; 256 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 257 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 258 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 259 }; 260 261 /* TIR attributes structure, used by TIR modify. */ 262 struct mlx5_devx_modify_tir_attr { 263 uint32_t tirn:24; 264 uint64_t modify_bitmask; 265 struct mlx5_devx_tir_attr tir; 266 }; 267 268 /* RQT attributes structure, used by RQT operations. */ 269 struct mlx5_devx_rqt_attr { 270 uint8_t rq_type; 271 uint32_t rqt_max_size:16; 272 uint32_t rqt_actual_size:16; 273 uint32_t rq_list[]; 274 }; 275 276 /* TIS attributes structure. */ 277 struct mlx5_devx_tis_attr { 278 uint32_t strict_lag_tx_port_affinity:1; 279 uint32_t tls_en:1; 280 uint32_t lag_tx_port_affinity:4; 281 uint32_t prio:4; 282 uint32_t transport_domain:24; 283 }; 284 285 /* SQ attributes structure, used by SQ create operation. */ 286 struct mlx5_devx_create_sq_attr { 287 uint32_t rlky:1; 288 uint32_t cd_master:1; 289 uint32_t fre:1; 290 uint32_t flush_in_error_en:1; 291 uint32_t allow_multi_pkt_send_wqe:1; 292 uint32_t min_wqe_inline_mode:3; 293 uint32_t state:4; 294 uint32_t reg_umr:1; 295 uint32_t allow_swp:1; 296 uint32_t hairpin:1; 297 uint32_t non_wire:1; 298 uint32_t static_sq_wq:1; 299 uint32_t ts_format:2; 300 uint32_t user_index:24; 301 uint32_t cqn:24; 302 uint32_t packet_pacing_rate_limit_index:16; 303 uint32_t tis_lst_sz:16; 304 uint32_t tis_num:24; 305 struct mlx5_devx_wq_attr wq_attr; 306 }; 307 308 /* SQ attributes structure, used by SQ modify operation. */ 309 struct mlx5_devx_modify_sq_attr { 310 uint32_t sq_state:4; 311 uint32_t state:4; 312 uint32_t hairpin_peer_rq:24; 313 uint32_t hairpin_peer_vhca:16; 314 }; 315 316 317 /* CQ attributes structure, used by CQ operations. */ 318 struct mlx5_devx_cq_attr { 319 uint32_t q_umem_valid:1; 320 uint32_t db_umem_valid:1; 321 uint32_t use_first_only:1; 322 uint32_t overrun_ignore:1; 323 uint32_t cqe_comp_en:1; 324 uint32_t mini_cqe_res_format:2; 325 uint32_t mini_cqe_res_format_ext:2; 326 uint32_t log_cq_size:5; 327 uint32_t log_page_size:5; 328 uint32_t uar_page_id; 329 uint32_t q_umem_id; 330 uint64_t q_umem_offset; 331 uint32_t db_umem_id; 332 uint64_t db_umem_offset; 333 uint32_t eqn; 334 uint64_t db_addr; 335 }; 336 337 /* Virtq attributes structure, used by VIRTQ operations. */ 338 struct mlx5_devx_virtq_attr { 339 uint16_t hw_available_index; 340 uint16_t hw_used_index; 341 uint16_t q_size; 342 uint32_t pd:24; 343 uint32_t virtio_version_1_0:1; 344 uint32_t tso_ipv4:1; 345 uint32_t tso_ipv6:1; 346 uint32_t tx_csum:1; 347 uint32_t rx_csum:1; 348 uint32_t event_mode:3; 349 uint32_t state:4; 350 uint32_t hw_latency_mode:2; 351 uint32_t hw_max_latency_us:12; 352 uint32_t hw_max_pending_comp:16; 353 uint32_t dirty_bitmap_dump_enable:1; 354 uint32_t dirty_bitmap_mkey; 355 uint32_t dirty_bitmap_size; 356 uint32_t mkey; 357 uint32_t qp_id; 358 uint32_t queue_index; 359 uint32_t tis_id; 360 uint32_t counters_obj_id; 361 uint64_t dirty_bitmap_addr; 362 uint64_t type; 363 uint64_t desc_addr; 364 uint64_t used_addr; 365 uint64_t available_addr; 366 struct { 367 uint32_t id; 368 uint32_t size; 369 uint64_t offset; 370 } umems[3]; 371 uint8_t error_type; 372 }; 373 374 375 struct mlx5_devx_qp_attr { 376 uint32_t pd:24; 377 uint32_t uar_index:24; 378 uint32_t cqn:24; 379 uint32_t log_page_size:5; 380 uint32_t rq_size:17; /* Must be power of 2. */ 381 uint32_t log_rq_stride:3; 382 uint32_t sq_size:17; /* Must be power of 2. */ 383 uint32_t ts_format:2; 384 uint32_t dbr_umem_valid:1; 385 uint32_t dbr_umem_id; 386 uint64_t dbr_address; 387 uint32_t wq_umem_id; 388 uint64_t wq_umem_offset; 389 }; 390 391 struct mlx5_devx_virtio_q_couners_attr { 392 uint64_t received_desc; 393 uint64_t completed_desc; 394 uint32_t error_cqes; 395 uint32_t bad_desc_errors; 396 uint32_t exceed_max_chain; 397 uint32_t invalid_buffer; 398 }; 399 400 /* 401 * graph flow match sample attributes structure, 402 * used by flex parser operations. 403 */ 404 struct mlx5_devx_match_sample_attr { 405 uint32_t flow_match_sample_en:1; 406 uint32_t flow_match_sample_field_offset:16; 407 uint32_t flow_match_sample_offset_mode:4; 408 uint32_t flow_match_sample_field_offset_mask; 409 uint32_t flow_match_sample_field_offset_shift:4; 410 uint32_t flow_match_sample_field_base_offset:8; 411 uint32_t flow_match_sample_tunnel_mode:3; 412 uint32_t flow_match_sample_field_id; 413 }; 414 415 /* graph node arc attributes structure, used by flex parser operations. */ 416 struct mlx5_devx_graph_arc_attr { 417 uint32_t compare_condition_value:16; 418 uint32_t start_inner_tunnel:1; 419 uint32_t arc_parse_graph_node:8; 420 uint32_t parse_graph_node_handle; 421 }; 422 423 /* Maximal number of samples per graph node. */ 424 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 425 426 /* Maximal number of input/output arcs per graph node. */ 427 #define MLX5_GRAPH_NODE_ARC_NUM 8 428 429 /* parse graph node attributes structure, used by flex parser operations. */ 430 struct mlx5_devx_graph_node_attr { 431 uint32_t modify_field_select; 432 uint32_t header_length_mode:4; 433 uint32_t header_length_base_value:16; 434 uint32_t header_length_field_shift:4; 435 uint32_t header_length_field_offset:16; 436 uint32_t header_length_field_mask; 437 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 438 uint32_t next_header_field_offset:16; 439 uint32_t next_header_field_size:5; 440 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 441 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 442 }; 443 444 /* Encryption key size is up to 1024 bit, 128 bytes. */ 445 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 446 447 struct mlx5_devx_dek_attr { 448 uint32_t key_size:4; 449 uint32_t has_keytag:1; 450 uint32_t key_purpose:4; 451 uint32_t pd:24; 452 uint64_t opaque; 453 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 454 }; 455 456 struct mlx5_devx_import_kek_attr { 457 uint64_t modify_field_select; 458 uint32_t state:8; 459 uint32_t key_size:4; 460 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 461 }; 462 463 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 464 465 struct mlx5_devx_credential_attr { 466 uint64_t modify_field_select; 467 uint32_t state:8; 468 uint32_t credential_role:8; 469 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 470 }; 471 472 struct mlx5_devx_crypto_login_attr { 473 uint64_t modify_field_select; 474 uint32_t credential_pointer:24; 475 uint32_t session_import_kek_ptr:24; 476 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 477 }; 478 479 /* mlx5_devx_cmds.c */ 480 481 __rte_internal 482 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 483 uint32_t bulk_sz); 484 __rte_internal 485 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 486 __rte_internal 487 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 488 int clear, uint32_t n_counters, 489 uint64_t *pkts, uint64_t *bytes, 490 uint32_t mkey, void *addr, 491 void *cmd_comp, 492 uint64_t async_id); 493 __rte_internal 494 int mlx5_devx_cmd_query_hca_attr(void *ctx, 495 struct mlx5_hca_attr *attr); 496 __rte_internal 497 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 498 struct mlx5_devx_mkey_attr *attr); 499 __rte_internal 500 int mlx5_devx_get_out_command_status(void *out); 501 __rte_internal 502 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 503 uint32_t *tis_td); 504 __rte_internal 505 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 506 struct mlx5_devx_create_rq_attr *rq_attr, 507 int socket); 508 __rte_internal 509 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 510 struct mlx5_devx_modify_rq_attr *rq_attr); 511 __rte_internal 512 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 513 struct mlx5_devx_tir_attr *tir_attr); 514 __rte_internal 515 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 516 struct mlx5_devx_rqt_attr *rqt_attr); 517 __rte_internal 518 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 519 struct mlx5_devx_create_sq_attr *sq_attr); 520 __rte_internal 521 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 522 struct mlx5_devx_modify_sq_attr *sq_attr); 523 __rte_internal 524 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 525 struct mlx5_devx_tis_attr *tis_attr); 526 __rte_internal 527 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 528 __rte_internal 529 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 530 FILE *file); 531 __rte_internal 532 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 533 __rte_internal 534 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 535 struct mlx5_devx_cq_attr *attr); 536 __rte_internal 537 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 538 struct mlx5_devx_virtq_attr *attr); 539 __rte_internal 540 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 541 struct mlx5_devx_virtq_attr *attr); 542 __rte_internal 543 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 544 struct mlx5_devx_virtq_attr *attr); 545 __rte_internal 546 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 547 struct mlx5_devx_qp_attr *attr); 548 __rte_internal 549 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 550 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 551 __rte_internal 552 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 553 struct mlx5_devx_rqt_attr *rqt_attr); 554 __rte_internal 555 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 556 struct mlx5_devx_modify_tir_attr *tir_attr); 557 __rte_internal 558 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 559 uint32_t ids[], uint32_t num); 560 561 __rte_internal 562 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 563 struct mlx5_devx_graph_node_attr *data); 564 565 __rte_internal 566 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 567 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 568 569 __rte_internal 570 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 571 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 572 573 __rte_internal 574 struct mlx5_devx_obj * 575 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 576 uint16_t class, uint8_t type, uint8_t len); 577 578 /** 579 * Create virtio queue counters object DevX API. 580 * 581 * @param[in] ctx 582 * Device context. 583 584 * @return 585 * The DevX object created, NULL otherwise and rte_errno is set. 586 */ 587 __rte_internal 588 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 589 590 /** 591 * Query virtio queue counters object using DevX API. 592 * 593 * @param[in] couners_obj 594 * Pointer to virtq object structure. 595 * @param [in/out] attr 596 * Pointer to virtio queue counters attributes structure. 597 * 598 * @return 599 * 0 on success, a negative errno value otherwise and rte_errno is set. 600 */ 601 __rte_internal 602 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 603 struct mlx5_devx_virtio_q_couners_attr *attr); 604 __rte_internal 605 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 606 uint32_t pd); 607 __rte_internal 608 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 609 610 __rte_internal 611 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 612 613 __rte_internal 614 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 615 __rte_internal 616 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 617 uint32_t *out_of_buffers); 618 /** 619 * Create general object of type FLOW_METER_ASO using DevX API.. 620 * 621 * @param[in] ctx 622 * Device context. 623 * @param [in] pd 624 * PD value to associate the FLOW_METER_ASO object with. 625 * @param [in] log_obj_size 626 * log_obj_size define to allocate number of 2 * meters 627 * in one FLOW_METER_ASO object. 628 * 629 * @return 630 * The DevX object created, NULL otherwise and rte_errno is set. 631 */ 632 __rte_internal 633 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 634 uint32_t pd, uint32_t log_obj_size); 635 __rte_internal 636 struct mlx5_devx_obj * 637 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 638 639 __rte_internal 640 struct mlx5_devx_obj * 641 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 642 struct mlx5_devx_import_kek_attr *attr); 643 644 __rte_internal 645 struct mlx5_devx_obj * 646 mlx5_devx_cmd_create_credential_obj(void *ctx, 647 struct mlx5_devx_credential_attr *attr); 648 649 __rte_internal 650 struct mlx5_devx_obj * 651 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 652 struct mlx5_devx_crypto_login_attr *attr); 653 654 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 655