1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_mkey_attr { 19 uint64_t addr; 20 uint64_t size; 21 uint32_t umem_id; 22 uint32_t pd; 23 uint32_t log_entity_size; 24 uint32_t pg_access:1; 25 uint32_t relaxed_ordering_write:1; 26 uint32_t relaxed_ordering_read:1; 27 uint32_t umr_en:1; 28 uint32_t crypto_en:2; 29 uint32_t set_remote_rw:1; 30 struct mlx5_klm *klm_array; 31 int klm_num; 32 }; 33 34 /* HCA qos attributes. */ 35 struct mlx5_hca_qos_attr { 36 uint32_t sup:1; /* Whether QOS is supported. */ 37 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 38 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 39 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 40 uint32_t flow_meter:1; 41 /* 42 * Flow meter is supported, updated version. 43 * When flow_meter is 1, it indicates that REG_C sharing is supported. 44 * If flow_meter is 1, flow_meter_old is also 1. 45 * Using older driver versions, flow_meter_old can be 1 46 * while flow_meter is 0. 47 */ 48 uint32_t flow_meter_aso_sup:1; 49 /* Whether FLOW_METER_ASO Object is supported. */ 50 uint8_t log_max_flow_meter; 51 /* Power of the maximum supported meters. */ 52 uint8_t flow_meter_reg_c_ids; 53 /* Bitmap of the reg_Cs available for flow meter to use. */ 54 uint32_t log_meter_aso_granularity:5; 55 /* Power of the minimum allocation granularity Object. */ 56 uint32_t log_meter_aso_max_alloc:5; 57 /* Power of the maximum allocation granularity Object. */ 58 uint32_t log_max_num_meter_aso:5; 59 /* Power of the maximum number of supported objects. */ 60 61 }; 62 63 struct mlx5_hca_vdpa_attr { 64 uint8_t virtio_queue_type; 65 uint32_t valid:1; 66 uint32_t desc_tunnel_offload_type:1; 67 uint32_t eth_frame_offload_type:1; 68 uint32_t virtio_version_1_0:1; 69 uint32_t tso_ipv4:1; 70 uint32_t tso_ipv6:1; 71 uint32_t tx_csum:1; 72 uint32_t rx_csum:1; 73 uint32_t event_mode:3; 74 uint32_t log_doorbell_stride:5; 75 uint32_t log_doorbell_bar_size:5; 76 uint32_t queue_counters_valid:1; 77 uint32_t max_num_virtio_queues; 78 struct { 79 uint32_t a; 80 uint32_t b; 81 } umems[3]; 82 uint64_t doorbell_bar_offset; 83 }; 84 85 struct mlx5_hca_flow_attr { 86 uint32_t tunnel_header_0_1; 87 uint32_t tunnel_header_2_3; 88 }; 89 90 /** 91 * Accumulate port PARSE_GRAPH_NODE capabilities from 92 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 93 */ 94 __extension__ 95 struct mlx5_hca_flex_attr { 96 uint32_t node_in; 97 uint32_t node_out; 98 uint16_t header_length_mode; 99 uint16_t sample_offset_mode; 100 uint8_t max_num_arc_in; 101 uint8_t max_num_arc_out; 102 uint8_t max_num_sample; 103 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 104 uint8_t sample_id_in_out:1; 105 uint16_t max_base_header_length; 106 uint8_t max_sample_base_offset; 107 uint16_t max_next_header_offset; 108 uint8_t header_length_mask_width; 109 }; 110 111 /* ISO C restricts enumerator values to range of 'int' */ 112 __extension__ 113 enum { 114 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 115 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 116 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 117 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 118 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 119 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 120 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 121 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 122 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 123 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 124 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 125 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 126 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 127 }; 128 129 enum { 130 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 131 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 132 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 133 }; 134 135 /* 136 * DWORD shift is the base for calculating header_length_field_mask 137 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 138 */ 139 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 140 141 static inline uint32_t 142 mlx5_hca_parse_graph_node_base_hdr_len_mask 143 (const struct mlx5_hca_flex_attr *attr) 144 { 145 return (1 << attr->header_length_mask_width) - 1; 146 } 147 148 /* HCA supports this number of time periods for LRO. */ 149 #define MLX5_LRO_NUM_SUPP_PERIODS 4 150 151 /* HCA attributes. */ 152 struct mlx5_hca_attr { 153 uint32_t eswitch_manager:1; 154 uint32_t flow_counters_dump:1; 155 uint32_t log_max_rqt_size:5; 156 uint32_t parse_graph_flex_node:1; 157 uint8_t flow_counter_bulk_alloc_bitmap; 158 uint32_t eth_net_offloads:1; 159 uint32_t eth_virt:1; 160 uint32_t wqe_vlan_insert:1; 161 uint32_t csum_cap:1; 162 uint32_t vlan_cap:1; 163 uint32_t wqe_inline_mode:2; 164 uint32_t vport_inline_mode:3; 165 uint32_t tunnel_stateless_geneve_rx:1; 166 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 167 uint32_t tunnel_stateless_gtp:1; 168 uint32_t max_lso_cap; 169 uint32_t scatter_fcs:1; 170 uint32_t lro_cap:1; 171 uint32_t tunnel_lro_gre:1; 172 uint32_t tunnel_lro_vxlan:1; 173 uint32_t tunnel_stateless_gre:1; 174 uint32_t tunnel_stateless_vxlan:1; 175 uint32_t swp:1; 176 uint32_t swp_csum:1; 177 uint32_t swp_lso:1; 178 uint32_t lro_max_msg_sz_mode:2; 179 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 180 uint16_t lro_min_mss_size; 181 uint32_t flex_parser_protocols; 182 uint32_t max_geneve_tlv_options; 183 uint32_t max_geneve_tlv_option_data_len; 184 uint32_t hairpin:1; 185 uint32_t log_max_hairpin_queues:5; 186 uint32_t log_max_hairpin_wq_data_sz:5; 187 uint32_t log_max_hairpin_num_packets:5; 188 uint32_t vhca_id:16; 189 uint32_t relaxed_ordering_write:1; 190 uint32_t relaxed_ordering_read:1; 191 uint32_t access_register_user:1; 192 uint32_t wqe_index_ignore:1; 193 uint32_t cross_channel:1; 194 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 195 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 196 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 197 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 198 uint32_t scatter_fcs_w_decap_disable:1; 199 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 200 uint32_t roce:1; 201 uint32_t rq_ts_format:2; 202 uint32_t sq_ts_format:2; 203 uint32_t steering_format_version:4; 204 uint32_t qp_ts_format:2; 205 uint32_t regexp_params:1; 206 uint32_t regexp_version:3; 207 uint32_t reg_c_preserve:1; 208 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 209 uint32_t crypto:1; /* Crypto engine is supported. */ 210 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 211 uint32_t dek:1; /* General obj type DEK is supported. */ 212 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 213 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 214 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 215 uint32_t regexp_num_of_engines; 216 uint32_t log_max_ft_sampler_num:8; 217 uint32_t inner_ipv4_ihl:1; 218 uint32_t outer_ipv4_ihl:1; 219 uint32_t geneve_tlv_opt; 220 uint32_t cqe_compression:1; 221 uint32_t mini_cqe_resp_flow_tag:1; 222 uint32_t mini_cqe_resp_l3_l4_tag:1; 223 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 224 struct mlx5_hca_qos_attr qos; 225 struct mlx5_hca_vdpa_attr vdpa; 226 struct mlx5_hca_flow_attr flow; 227 struct mlx5_hca_flex_attr flex; 228 int log_max_qp_sz; 229 int log_max_cq_sz; 230 int log_max_qp; 231 int log_max_cq; 232 uint32_t log_max_pd; 233 uint32_t log_max_mrw_sz; 234 uint32_t log_max_srq; 235 uint32_t log_max_srq_sz; 236 uint32_t rss_ind_tbl_cap; 237 uint32_t mmo_dma_sq_en:1; 238 uint32_t mmo_compress_sq_en:1; 239 uint32_t mmo_decompress_sq_en:1; 240 uint32_t mmo_dma_qp_en:1; 241 uint32_t mmo_compress_qp_en:1; 242 uint32_t mmo_decompress_qp_en:1; 243 uint32_t mmo_regex_qp_en:1; 244 uint32_t mmo_regex_sq_en:1; 245 uint32_t compress_min_block_size:4; 246 uint32_t log_max_mmo_dma:5; 247 uint32_t log_max_mmo_compress:5; 248 uint32_t log_max_mmo_decompress:5; 249 uint32_t umr_modify_entity_size_disabled:1; 250 uint32_t umr_indirect_mkey_disabled:1; 251 }; 252 253 /* LAG Context. */ 254 struct mlx5_devx_lag_context { 255 uint32_t fdb_selection_mode:1; 256 uint32_t port_select_mode:3; 257 uint32_t lag_state:3; 258 uint32_t tx_remap_affinity_1:4; 259 uint32_t tx_remap_affinity_2:4; 260 }; 261 262 struct mlx5_devx_wq_attr { 263 uint32_t wq_type:4; 264 uint32_t wq_signature:1; 265 uint32_t end_padding_mode:2; 266 uint32_t cd_slave:1; 267 uint32_t hds_skip_first_sge:1; 268 uint32_t log2_hds_buf_size:3; 269 uint32_t page_offset:5; 270 uint32_t lwm:16; 271 uint32_t pd:24; 272 uint32_t uar_page:24; 273 uint64_t dbr_addr; 274 uint32_t hw_counter; 275 uint32_t sw_counter; 276 uint32_t log_wq_stride:4; 277 uint32_t log_wq_pg_sz:5; 278 uint32_t log_wq_sz:5; 279 uint32_t dbr_umem_valid:1; 280 uint32_t wq_umem_valid:1; 281 uint32_t log_hairpin_num_packets:5; 282 uint32_t log_hairpin_data_sz:5; 283 uint32_t single_wqe_log_num_of_strides:4; 284 uint32_t two_byte_shift_en:1; 285 uint32_t single_stride_log_num_of_bytes:3; 286 uint32_t dbr_umem_id; 287 uint32_t wq_umem_id; 288 uint64_t wq_umem_offset; 289 }; 290 291 /* Create RQ attributes structure, used by create RQ operation. */ 292 struct mlx5_devx_create_rq_attr { 293 uint32_t rlky:1; 294 uint32_t delay_drop_en:1; 295 uint32_t scatter_fcs:1; 296 uint32_t vsd:1; 297 uint32_t mem_rq_type:4; 298 uint32_t state:4; 299 uint32_t flush_in_error_en:1; 300 uint32_t hairpin:1; 301 uint32_t ts_format:2; 302 uint32_t user_index:24; 303 uint32_t cqn:24; 304 uint32_t counter_set_id:8; 305 uint32_t rmpn:24; 306 struct mlx5_devx_wq_attr wq_attr; 307 }; 308 309 /* Modify RQ attributes structure, used by modify RQ operation. */ 310 struct mlx5_devx_modify_rq_attr { 311 uint32_t rqn:24; 312 uint32_t rq_state:4; /* Current RQ state. */ 313 uint32_t state:4; /* Required RQ state. */ 314 uint32_t scatter_fcs:1; 315 uint32_t vsd:1; 316 uint32_t counter_set_id:8; 317 uint32_t hairpin_peer_sq:24; 318 uint32_t hairpin_peer_vhca:16; 319 uint64_t modify_bitmask; 320 uint32_t lwm:16; /* Contained WQ lwm. */ 321 }; 322 323 struct mlx5_rx_hash_field_select { 324 uint32_t l3_prot_type:1; 325 uint32_t l4_prot_type:1; 326 uint32_t selected_fields:30; 327 }; 328 329 /* TIR attributes structure, used by TIR operations. */ 330 struct mlx5_devx_tir_attr { 331 uint32_t disp_type:4; 332 uint32_t lro_timeout_period_usecs:16; 333 uint32_t lro_enable_mask:4; 334 uint32_t lro_max_msg_sz:8; 335 uint32_t inline_rqn:24; 336 uint32_t rx_hash_symmetric:1; 337 uint32_t tunneled_offload_en:1; 338 uint32_t indirect_table:24; 339 uint32_t rx_hash_fn:4; 340 uint32_t self_lb_block:2; 341 uint32_t transport_domain:24; 342 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 343 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 344 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 345 }; 346 347 /* TIR attributes structure, used by TIR modify. */ 348 struct mlx5_devx_modify_tir_attr { 349 uint32_t tirn:24; 350 uint64_t modify_bitmask; 351 struct mlx5_devx_tir_attr tir; 352 }; 353 354 /* RQT attributes structure, used by RQT operations. */ 355 struct mlx5_devx_rqt_attr { 356 uint8_t rq_type; 357 uint32_t rqt_max_size:16; 358 uint32_t rqt_actual_size:16; 359 uint32_t rq_list[]; 360 }; 361 362 /* TIS attributes structure. */ 363 struct mlx5_devx_tis_attr { 364 uint32_t strict_lag_tx_port_affinity:1; 365 uint32_t tls_en:1; 366 uint32_t lag_tx_port_affinity:4; 367 uint32_t prio:4; 368 uint32_t transport_domain:24; 369 }; 370 371 /* SQ attributes structure, used by SQ create operation. */ 372 struct mlx5_devx_create_sq_attr { 373 uint32_t rlky:1; 374 uint32_t cd_master:1; 375 uint32_t fre:1; 376 uint32_t flush_in_error_en:1; 377 uint32_t allow_multi_pkt_send_wqe:1; 378 uint32_t min_wqe_inline_mode:3; 379 uint32_t state:4; 380 uint32_t reg_umr:1; 381 uint32_t allow_swp:1; 382 uint32_t hairpin:1; 383 uint32_t non_wire:1; 384 uint32_t static_sq_wq:1; 385 uint32_t ts_format:2; 386 uint32_t user_index:24; 387 uint32_t cqn:24; 388 uint32_t packet_pacing_rate_limit_index:16; 389 uint32_t tis_lst_sz:16; 390 uint32_t tis_num:24; 391 struct mlx5_devx_wq_attr wq_attr; 392 }; 393 394 /* SQ attributes structure, used by SQ modify operation. */ 395 struct mlx5_devx_modify_sq_attr { 396 uint32_t sq_state:4; 397 uint32_t state:4; 398 uint32_t hairpin_peer_rq:24; 399 uint32_t hairpin_peer_vhca:16; 400 }; 401 402 403 /* CQ attributes structure, used by CQ operations. */ 404 struct mlx5_devx_cq_attr { 405 uint32_t q_umem_valid:1; 406 uint32_t db_umem_valid:1; 407 uint32_t use_first_only:1; 408 uint32_t overrun_ignore:1; 409 uint32_t cqe_comp_en:1; 410 uint32_t mini_cqe_res_format:2; 411 uint32_t mini_cqe_res_format_ext:2; 412 uint32_t log_cq_size:5; 413 uint32_t log_page_size:5; 414 uint32_t uar_page_id; 415 uint32_t q_umem_id; 416 uint64_t q_umem_offset; 417 uint32_t db_umem_id; 418 uint64_t db_umem_offset; 419 uint32_t eqn; 420 uint64_t db_addr; 421 }; 422 423 /* Virtq attributes structure, used by VIRTQ operations. */ 424 struct mlx5_devx_virtq_attr { 425 uint16_t hw_available_index; 426 uint16_t hw_used_index; 427 uint16_t q_size; 428 uint32_t pd:24; 429 uint32_t virtio_version_1_0:1; 430 uint32_t tso_ipv4:1; 431 uint32_t tso_ipv6:1; 432 uint32_t tx_csum:1; 433 uint32_t rx_csum:1; 434 uint32_t event_mode:3; 435 uint32_t state:4; 436 uint32_t hw_latency_mode:2; 437 uint32_t hw_max_latency_us:12; 438 uint32_t hw_max_pending_comp:16; 439 uint32_t dirty_bitmap_dump_enable:1; 440 uint32_t dirty_bitmap_mkey; 441 uint32_t dirty_bitmap_size; 442 uint32_t mkey; 443 uint32_t qp_id; 444 uint32_t queue_index; 445 uint32_t tis_id; 446 uint32_t counters_obj_id; 447 uint64_t dirty_bitmap_addr; 448 uint64_t type; 449 uint64_t desc_addr; 450 uint64_t used_addr; 451 uint64_t available_addr; 452 struct { 453 uint32_t id; 454 uint32_t size; 455 uint64_t offset; 456 } umems[3]; 457 uint8_t error_type; 458 }; 459 460 461 struct mlx5_devx_qp_attr { 462 uint32_t pd:24; 463 uint32_t uar_index:24; 464 uint32_t cqn:24; 465 uint32_t log_page_size:5; 466 uint32_t rq_size:17; /* Must be power of 2. */ 467 uint32_t log_rq_stride:3; 468 uint32_t sq_size:17; /* Must be power of 2. */ 469 uint32_t ts_format:2; 470 uint32_t dbr_umem_valid:1; 471 uint32_t dbr_umem_id; 472 uint64_t dbr_address; 473 uint32_t wq_umem_id; 474 uint64_t wq_umem_offset; 475 uint32_t user_index:24; 476 uint32_t mmo:1; 477 }; 478 479 struct mlx5_devx_virtio_q_couners_attr { 480 uint64_t received_desc; 481 uint64_t completed_desc; 482 uint32_t error_cqes; 483 uint32_t bad_desc_errors; 484 uint32_t exceed_max_chain; 485 uint32_t invalid_buffer; 486 }; 487 488 /* 489 * graph flow match sample attributes structure, 490 * used by flex parser operations. 491 */ 492 struct mlx5_devx_match_sample_attr { 493 uint32_t flow_match_sample_en:1; 494 uint32_t flow_match_sample_field_offset:16; 495 uint32_t flow_match_sample_offset_mode:4; 496 uint32_t flow_match_sample_field_offset_mask; 497 uint32_t flow_match_sample_field_offset_shift:4; 498 uint32_t flow_match_sample_field_base_offset:8; 499 uint32_t flow_match_sample_tunnel_mode:3; 500 uint32_t flow_match_sample_field_id; 501 }; 502 503 /* graph node arc attributes structure, used by flex parser operations. */ 504 struct mlx5_devx_graph_arc_attr { 505 uint32_t compare_condition_value:16; 506 uint32_t start_inner_tunnel:1; 507 uint32_t arc_parse_graph_node:8; 508 uint32_t parse_graph_node_handle; 509 }; 510 511 /* Maximal number of samples per graph node. */ 512 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 513 514 /* Maximal number of input/output arcs per graph node. */ 515 #define MLX5_GRAPH_NODE_ARC_NUM 8 516 517 /* parse graph node attributes structure, used by flex parser operations. */ 518 struct mlx5_devx_graph_node_attr { 519 uint32_t modify_field_select; 520 uint32_t header_length_mode:4; 521 uint32_t header_length_base_value:16; 522 uint32_t header_length_field_shift:4; 523 uint32_t header_length_field_offset:16; 524 uint32_t header_length_field_mask; 525 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 526 uint32_t next_header_field_offset:16; 527 uint32_t next_header_field_size:5; 528 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 529 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 530 }; 531 532 /* Encryption key size is up to 1024 bit, 128 bytes. */ 533 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 534 535 struct mlx5_devx_dek_attr { 536 uint32_t key_size:4; 537 uint32_t has_keytag:1; 538 uint32_t key_purpose:4; 539 uint32_t pd:24; 540 uint64_t opaque; 541 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 542 }; 543 544 struct mlx5_devx_import_kek_attr { 545 uint64_t modify_field_select; 546 uint32_t state:8; 547 uint32_t key_size:4; 548 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 549 }; 550 551 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 552 553 struct mlx5_devx_credential_attr { 554 uint64_t modify_field_select; 555 uint32_t state:8; 556 uint32_t credential_role:8; 557 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 558 }; 559 560 struct mlx5_devx_crypto_login_attr { 561 uint64_t modify_field_select; 562 uint32_t credential_pointer:24; 563 uint32_t session_import_kek_ptr:24; 564 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 565 }; 566 567 /* mlx5_devx_cmds.c */ 568 569 __rte_internal 570 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 571 uint32_t bulk_sz); 572 __rte_internal 573 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 574 __rte_internal 575 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 576 int clear, uint32_t n_counters, 577 uint64_t *pkts, uint64_t *bytes, 578 uint32_t mkey, void *addr, 579 void *cmd_comp, 580 uint64_t async_id); 581 __rte_internal 582 int mlx5_devx_cmd_query_hca_attr(void *ctx, 583 struct mlx5_hca_attr *attr); 584 __rte_internal 585 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 586 struct mlx5_devx_mkey_attr *attr); 587 __rte_internal 588 int mlx5_devx_get_out_command_status(void *out); 589 __rte_internal 590 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 591 uint32_t *tis_td); 592 __rte_internal 593 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 594 struct mlx5_devx_create_rq_attr *rq_attr, 595 int socket); 596 __rte_internal 597 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 598 struct mlx5_devx_modify_rq_attr *rq_attr); 599 __rte_internal 600 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 601 struct mlx5_devx_tir_attr *tir_attr); 602 __rte_internal 603 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 604 struct mlx5_devx_rqt_attr *rqt_attr); 605 __rte_internal 606 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 607 struct mlx5_devx_create_sq_attr *sq_attr); 608 __rte_internal 609 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 610 struct mlx5_devx_modify_sq_attr *sq_attr); 611 __rte_internal 612 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 613 struct mlx5_devx_tis_attr *tis_attr); 614 __rte_internal 615 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 616 __rte_internal 617 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 618 FILE *file); 619 __rte_internal 620 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 621 __rte_internal 622 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 623 struct mlx5_devx_cq_attr *attr); 624 __rte_internal 625 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 626 struct mlx5_devx_virtq_attr *attr); 627 __rte_internal 628 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 629 struct mlx5_devx_virtq_attr *attr); 630 __rte_internal 631 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 632 struct mlx5_devx_virtq_attr *attr); 633 __rte_internal 634 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 635 struct mlx5_devx_qp_attr *attr); 636 __rte_internal 637 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 638 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 639 __rte_internal 640 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 641 struct mlx5_devx_rqt_attr *rqt_attr); 642 __rte_internal 643 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 644 struct mlx5_devx_modify_tir_attr *tir_attr); 645 __rte_internal 646 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 647 uint32_t ids[], uint32_t num); 648 649 __rte_internal 650 struct mlx5_devx_obj * 651 mlx5_devx_cmd_create_flex_parser(void *ctx, 652 struct mlx5_devx_graph_node_attr *data); 653 654 __rte_internal 655 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 656 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 657 658 __rte_internal 659 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 660 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 661 662 __rte_internal 663 struct mlx5_devx_obj * 664 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 665 uint16_t class, uint8_t type, uint8_t len); 666 667 /** 668 * Create virtio queue counters object DevX API. 669 * 670 * @param[in] ctx 671 * Device context. 672 673 * @return 674 * The DevX object created, NULL otherwise and rte_errno is set. 675 */ 676 __rte_internal 677 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 678 679 /** 680 * Query virtio queue counters object using DevX API. 681 * 682 * @param[in] couners_obj 683 * Pointer to virtq object structure. 684 * @param [in/out] attr 685 * Pointer to virtio queue counters attributes structure. 686 * 687 * @return 688 * 0 on success, a negative errno value otherwise and rte_errno is set. 689 */ 690 __rte_internal 691 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 692 struct mlx5_devx_virtio_q_couners_attr *attr); 693 __rte_internal 694 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 695 uint32_t pd); 696 __rte_internal 697 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 698 699 __rte_internal 700 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 701 702 __rte_internal 703 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 704 __rte_internal 705 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 706 uint32_t *out_of_buffers); 707 __rte_internal 708 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 709 uint32_t pd, uint32_t log_obj_size); 710 711 /** 712 * Create general object of type FLOW_METER_ASO using DevX API.. 713 * 714 * @param[in] ctx 715 * Device context. 716 * @param [in] pd 717 * PD value to associate the FLOW_METER_ASO object with. 718 * @param [in] log_obj_size 719 * log_obj_size define to allocate number of 2 * meters 720 * in one FLOW_METER_ASO object. 721 * 722 * @return 723 * The DevX object created, NULL otherwise and rte_errno is set. 724 */ 725 __rte_internal 726 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 727 uint32_t pd, uint32_t log_obj_size); 728 __rte_internal 729 struct mlx5_devx_obj * 730 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 731 732 __rte_internal 733 struct mlx5_devx_obj * 734 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 735 struct mlx5_devx_import_kek_attr *attr); 736 737 __rte_internal 738 struct mlx5_devx_obj * 739 mlx5_devx_cmd_create_credential_obj(void *ctx, 740 struct mlx5_devx_credential_attr *attr); 741 742 __rte_internal 743 struct mlx5_devx_obj * 744 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 745 struct mlx5_devx_crypto_login_attr *attr); 746 747 __rte_internal 748 int 749 mlx5_devx_cmd_query_lag(void *ctx, 750 struct mlx5_devx_lag_context *lag_ctx); 751 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 752