1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 struct mlx5_hca_flow_attr { 93 uint32_t tunnel_header_0_1; 94 uint32_t tunnel_header_2_3; 95 }; 96 97 /* HCA supports this number of time periods for LRO. */ 98 #define MLX5_LRO_NUM_SUPP_PERIODS 4 99 100 /* HCA attributes. */ 101 struct mlx5_hca_attr { 102 uint32_t eswitch_manager:1; 103 uint32_t flow_counters_dump:1; 104 uint32_t log_max_rqt_size:5; 105 uint32_t parse_graph_flex_node:1; 106 uint8_t flow_counter_bulk_alloc_bitmap; 107 uint32_t eth_net_offloads:1; 108 uint32_t eth_virt:1; 109 uint32_t wqe_vlan_insert:1; 110 uint32_t csum_cap:1; 111 uint32_t wqe_inline_mode:2; 112 uint32_t vport_inline_mode:3; 113 uint32_t tunnel_stateless_geneve_rx:1; 114 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 115 uint32_t tunnel_stateless_gtp:1; 116 uint32_t lro_cap:1; 117 uint32_t tunnel_lro_gre:1; 118 uint32_t tunnel_lro_vxlan:1; 119 uint32_t swp:1; 120 uint32_t swp_csum:1; 121 uint32_t swp_lso:1; 122 uint32_t lro_max_msg_sz_mode:2; 123 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 124 uint16_t lro_min_mss_size; 125 uint32_t flex_parser_protocols; 126 uint32_t max_geneve_tlv_options; 127 uint32_t max_geneve_tlv_option_data_len; 128 uint32_t hairpin:1; 129 uint32_t log_max_hairpin_queues:5; 130 uint32_t log_max_hairpin_wq_data_sz:5; 131 uint32_t log_max_hairpin_num_packets:5; 132 uint32_t vhca_id:16; 133 uint32_t relaxed_ordering_write:1; 134 uint32_t relaxed_ordering_read:1; 135 uint32_t access_register_user:1; 136 uint32_t wqe_index_ignore:1; 137 uint32_t cross_channel:1; 138 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 139 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 140 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 141 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 142 uint32_t scatter_fcs_w_decap_disable:1; 143 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 144 uint32_t roce:1; 145 uint32_t rq_ts_format:2; 146 uint32_t sq_ts_format:2; 147 uint32_t steering_format_version:4; 148 uint32_t qp_ts_format:2; 149 uint32_t regex:1; 150 uint32_t reg_c_preserve:1; 151 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 152 uint32_t crypto:1; /* Crypto engine is supported. */ 153 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 154 uint32_t dek:1; /* General obj type DEK is supported. */ 155 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 156 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 157 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 158 uint32_t regexp_num_of_engines; 159 uint32_t log_max_ft_sampler_num:8; 160 uint32_t inner_ipv4_ihl:1; 161 uint32_t outer_ipv4_ihl:1; 162 uint32_t geneve_tlv_opt; 163 uint32_t cqe_compression:1; 164 uint32_t mini_cqe_resp_flow_tag:1; 165 uint32_t mini_cqe_resp_l3_l4_tag:1; 166 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 167 struct mlx5_hca_qos_attr qos; 168 struct mlx5_hca_vdpa_attr vdpa; 169 struct mlx5_hca_flow_attr flow; 170 int log_max_qp_sz; 171 int log_max_cq_sz; 172 int log_max_qp; 173 int log_max_cq; 174 uint32_t log_max_pd; 175 uint32_t log_max_mrw_sz; 176 uint32_t log_max_srq; 177 uint32_t log_max_srq_sz; 178 uint32_t rss_ind_tbl_cap; 179 uint32_t mmo_dma_sq_en:1; 180 uint32_t mmo_compress_sq_en:1; 181 uint32_t mmo_decompress_sq_en:1; 182 uint32_t mmo_dma_qp_en:1; 183 uint32_t mmo_compress_qp_en:1; 184 uint32_t mmo_decompress_qp_en:1; 185 uint32_t mmo_regex_qp_en:1; 186 uint32_t mmo_regex_sq_en:1; 187 uint32_t compress_min_block_size:4; 188 uint32_t log_max_mmo_dma:5; 189 uint32_t log_max_mmo_compress:5; 190 uint32_t log_max_mmo_decompress:5; 191 uint32_t umr_modify_entity_size_disabled:1; 192 uint32_t umr_indirect_mkey_disabled:1; 193 }; 194 195 struct mlx5_devx_wq_attr { 196 uint32_t wq_type:4; 197 uint32_t wq_signature:1; 198 uint32_t end_padding_mode:2; 199 uint32_t cd_slave:1; 200 uint32_t hds_skip_first_sge:1; 201 uint32_t log2_hds_buf_size:3; 202 uint32_t page_offset:5; 203 uint32_t lwm:16; 204 uint32_t pd:24; 205 uint32_t uar_page:24; 206 uint64_t dbr_addr; 207 uint32_t hw_counter; 208 uint32_t sw_counter; 209 uint32_t log_wq_stride:4; 210 uint32_t log_wq_pg_sz:5; 211 uint32_t log_wq_sz:5; 212 uint32_t dbr_umem_valid:1; 213 uint32_t wq_umem_valid:1; 214 uint32_t log_hairpin_num_packets:5; 215 uint32_t log_hairpin_data_sz:5; 216 uint32_t single_wqe_log_num_of_strides:4; 217 uint32_t two_byte_shift_en:1; 218 uint32_t single_stride_log_num_of_bytes:3; 219 uint32_t dbr_umem_id; 220 uint32_t wq_umem_id; 221 uint64_t wq_umem_offset; 222 }; 223 224 /* Create RQ attributes structure, used by create RQ operation. */ 225 struct mlx5_devx_create_rq_attr { 226 uint32_t rlky:1; 227 uint32_t delay_drop_en:1; 228 uint32_t scatter_fcs:1; 229 uint32_t vsd:1; 230 uint32_t mem_rq_type:4; 231 uint32_t state:4; 232 uint32_t flush_in_error_en:1; 233 uint32_t hairpin:1; 234 uint32_t ts_format:2; 235 uint32_t user_index:24; 236 uint32_t cqn:24; 237 uint32_t counter_set_id:8; 238 uint32_t rmpn:24; 239 struct mlx5_devx_wq_attr wq_attr; 240 }; 241 242 /* Modify RQ attributes structure, used by modify RQ operation. */ 243 struct mlx5_devx_modify_rq_attr { 244 uint32_t rqn:24; 245 uint32_t rq_state:4; /* Current RQ state. */ 246 uint32_t state:4; /* Required RQ state. */ 247 uint32_t scatter_fcs:1; 248 uint32_t vsd:1; 249 uint32_t counter_set_id:8; 250 uint32_t hairpin_peer_sq:24; 251 uint32_t hairpin_peer_vhca:16; 252 uint64_t modify_bitmask; 253 uint32_t lwm:16; /* Contained WQ lwm. */ 254 }; 255 256 struct mlx5_rx_hash_field_select { 257 uint32_t l3_prot_type:1; 258 uint32_t l4_prot_type:1; 259 uint32_t selected_fields:30; 260 }; 261 262 /* TIR attributes structure, used by TIR operations. */ 263 struct mlx5_devx_tir_attr { 264 uint32_t disp_type:4; 265 uint32_t lro_timeout_period_usecs:16; 266 uint32_t lro_enable_mask:4; 267 uint32_t lro_max_msg_sz:8; 268 uint32_t inline_rqn:24; 269 uint32_t rx_hash_symmetric:1; 270 uint32_t tunneled_offload_en:1; 271 uint32_t indirect_table:24; 272 uint32_t rx_hash_fn:4; 273 uint32_t self_lb_block:2; 274 uint32_t transport_domain:24; 275 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 276 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 277 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 278 }; 279 280 /* TIR attributes structure, used by TIR modify. */ 281 struct mlx5_devx_modify_tir_attr { 282 uint32_t tirn:24; 283 uint64_t modify_bitmask; 284 struct mlx5_devx_tir_attr tir; 285 }; 286 287 /* RQT attributes structure, used by RQT operations. */ 288 struct mlx5_devx_rqt_attr { 289 uint8_t rq_type; 290 uint32_t rqt_max_size:16; 291 uint32_t rqt_actual_size:16; 292 uint32_t rq_list[]; 293 }; 294 295 /* TIS attributes structure. */ 296 struct mlx5_devx_tis_attr { 297 uint32_t strict_lag_tx_port_affinity:1; 298 uint32_t tls_en:1; 299 uint32_t lag_tx_port_affinity:4; 300 uint32_t prio:4; 301 uint32_t transport_domain:24; 302 }; 303 304 /* SQ attributes structure, used by SQ create operation. */ 305 struct mlx5_devx_create_sq_attr { 306 uint32_t rlky:1; 307 uint32_t cd_master:1; 308 uint32_t fre:1; 309 uint32_t flush_in_error_en:1; 310 uint32_t allow_multi_pkt_send_wqe:1; 311 uint32_t min_wqe_inline_mode:3; 312 uint32_t state:4; 313 uint32_t reg_umr:1; 314 uint32_t allow_swp:1; 315 uint32_t hairpin:1; 316 uint32_t non_wire:1; 317 uint32_t static_sq_wq:1; 318 uint32_t ts_format:2; 319 uint32_t user_index:24; 320 uint32_t cqn:24; 321 uint32_t packet_pacing_rate_limit_index:16; 322 uint32_t tis_lst_sz:16; 323 uint32_t tis_num:24; 324 struct mlx5_devx_wq_attr wq_attr; 325 }; 326 327 /* SQ attributes structure, used by SQ modify operation. */ 328 struct mlx5_devx_modify_sq_attr { 329 uint32_t sq_state:4; 330 uint32_t state:4; 331 uint32_t hairpin_peer_rq:24; 332 uint32_t hairpin_peer_vhca:16; 333 }; 334 335 336 /* CQ attributes structure, used by CQ operations. */ 337 struct mlx5_devx_cq_attr { 338 uint32_t q_umem_valid:1; 339 uint32_t db_umem_valid:1; 340 uint32_t use_first_only:1; 341 uint32_t overrun_ignore:1; 342 uint32_t cqe_comp_en:1; 343 uint32_t mini_cqe_res_format:2; 344 uint32_t mini_cqe_res_format_ext:2; 345 uint32_t log_cq_size:5; 346 uint32_t log_page_size:5; 347 uint32_t uar_page_id; 348 uint32_t q_umem_id; 349 uint64_t q_umem_offset; 350 uint32_t db_umem_id; 351 uint64_t db_umem_offset; 352 uint32_t eqn; 353 uint64_t db_addr; 354 }; 355 356 /* Virtq attributes structure, used by VIRTQ operations. */ 357 struct mlx5_devx_virtq_attr { 358 uint16_t hw_available_index; 359 uint16_t hw_used_index; 360 uint16_t q_size; 361 uint32_t pd:24; 362 uint32_t virtio_version_1_0:1; 363 uint32_t tso_ipv4:1; 364 uint32_t tso_ipv6:1; 365 uint32_t tx_csum:1; 366 uint32_t rx_csum:1; 367 uint32_t event_mode:3; 368 uint32_t state:4; 369 uint32_t hw_latency_mode:2; 370 uint32_t hw_max_latency_us:12; 371 uint32_t hw_max_pending_comp:16; 372 uint32_t dirty_bitmap_dump_enable:1; 373 uint32_t dirty_bitmap_mkey; 374 uint32_t dirty_bitmap_size; 375 uint32_t mkey; 376 uint32_t qp_id; 377 uint32_t queue_index; 378 uint32_t tis_id; 379 uint32_t counters_obj_id; 380 uint64_t dirty_bitmap_addr; 381 uint64_t type; 382 uint64_t desc_addr; 383 uint64_t used_addr; 384 uint64_t available_addr; 385 struct { 386 uint32_t id; 387 uint32_t size; 388 uint64_t offset; 389 } umems[3]; 390 uint8_t error_type; 391 }; 392 393 394 struct mlx5_devx_qp_attr { 395 uint32_t pd:24; 396 uint32_t uar_index:24; 397 uint32_t cqn:24; 398 uint32_t log_page_size:5; 399 uint32_t rq_size:17; /* Must be power of 2. */ 400 uint32_t log_rq_stride:3; 401 uint32_t sq_size:17; /* Must be power of 2. */ 402 uint32_t ts_format:2; 403 uint32_t dbr_umem_valid:1; 404 uint32_t dbr_umem_id; 405 uint64_t dbr_address; 406 uint32_t wq_umem_id; 407 uint64_t wq_umem_offset; 408 uint32_t user_index:24; 409 uint32_t mmo:1; 410 }; 411 412 struct mlx5_devx_virtio_q_couners_attr { 413 uint64_t received_desc; 414 uint64_t completed_desc; 415 uint32_t error_cqes; 416 uint32_t bad_desc_errors; 417 uint32_t exceed_max_chain; 418 uint32_t invalid_buffer; 419 }; 420 421 /* 422 * graph flow match sample attributes structure, 423 * used by flex parser operations. 424 */ 425 struct mlx5_devx_match_sample_attr { 426 uint32_t flow_match_sample_en:1; 427 uint32_t flow_match_sample_field_offset:16; 428 uint32_t flow_match_sample_offset_mode:4; 429 uint32_t flow_match_sample_field_offset_mask; 430 uint32_t flow_match_sample_field_offset_shift:4; 431 uint32_t flow_match_sample_field_base_offset:8; 432 uint32_t flow_match_sample_tunnel_mode:3; 433 uint32_t flow_match_sample_field_id; 434 }; 435 436 /* graph node arc attributes structure, used by flex parser operations. */ 437 struct mlx5_devx_graph_arc_attr { 438 uint32_t compare_condition_value:16; 439 uint32_t start_inner_tunnel:1; 440 uint32_t arc_parse_graph_node:8; 441 uint32_t parse_graph_node_handle; 442 }; 443 444 /* Maximal number of samples per graph node. */ 445 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 446 447 /* Maximal number of input/output arcs per graph node. */ 448 #define MLX5_GRAPH_NODE_ARC_NUM 8 449 450 /* parse graph node attributes structure, used by flex parser operations. */ 451 struct mlx5_devx_graph_node_attr { 452 uint32_t modify_field_select; 453 uint32_t header_length_mode:4; 454 uint32_t header_length_base_value:16; 455 uint32_t header_length_field_shift:4; 456 uint32_t header_length_field_offset:16; 457 uint32_t header_length_field_mask; 458 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 459 uint32_t next_header_field_offset:16; 460 uint32_t next_header_field_size:5; 461 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 462 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 463 }; 464 465 /* Encryption key size is up to 1024 bit, 128 bytes. */ 466 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 467 468 struct mlx5_devx_dek_attr { 469 uint32_t key_size:4; 470 uint32_t has_keytag:1; 471 uint32_t key_purpose:4; 472 uint32_t pd:24; 473 uint64_t opaque; 474 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 475 }; 476 477 struct mlx5_devx_import_kek_attr { 478 uint64_t modify_field_select; 479 uint32_t state:8; 480 uint32_t key_size:4; 481 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 482 }; 483 484 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 485 486 struct mlx5_devx_credential_attr { 487 uint64_t modify_field_select; 488 uint32_t state:8; 489 uint32_t credential_role:8; 490 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 491 }; 492 493 struct mlx5_devx_crypto_login_attr { 494 uint64_t modify_field_select; 495 uint32_t credential_pointer:24; 496 uint32_t session_import_kek_ptr:24; 497 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 498 }; 499 500 /* mlx5_devx_cmds.c */ 501 502 __rte_internal 503 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 504 uint32_t bulk_sz); 505 __rte_internal 506 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 507 __rte_internal 508 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 509 int clear, uint32_t n_counters, 510 uint64_t *pkts, uint64_t *bytes, 511 uint32_t mkey, void *addr, 512 void *cmd_comp, 513 uint64_t async_id); 514 __rte_internal 515 int mlx5_devx_cmd_query_hca_attr(void *ctx, 516 struct mlx5_hca_attr *attr); 517 __rte_internal 518 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 519 struct mlx5_devx_mkey_attr *attr); 520 __rte_internal 521 int mlx5_devx_get_out_command_status(void *out); 522 __rte_internal 523 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 524 uint32_t *tis_td); 525 __rte_internal 526 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 527 struct mlx5_devx_create_rq_attr *rq_attr, 528 int socket); 529 __rte_internal 530 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 531 struct mlx5_devx_modify_rq_attr *rq_attr); 532 __rte_internal 533 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 534 struct mlx5_devx_tir_attr *tir_attr); 535 __rte_internal 536 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 537 struct mlx5_devx_rqt_attr *rqt_attr); 538 __rte_internal 539 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 540 struct mlx5_devx_create_sq_attr *sq_attr); 541 __rte_internal 542 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 543 struct mlx5_devx_modify_sq_attr *sq_attr); 544 __rte_internal 545 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 546 struct mlx5_devx_tis_attr *tis_attr); 547 __rte_internal 548 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 549 __rte_internal 550 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 551 FILE *file); 552 __rte_internal 553 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 554 __rte_internal 555 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 556 struct mlx5_devx_cq_attr *attr); 557 __rte_internal 558 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 559 struct mlx5_devx_virtq_attr *attr); 560 __rte_internal 561 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 562 struct mlx5_devx_virtq_attr *attr); 563 __rte_internal 564 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 565 struct mlx5_devx_virtq_attr *attr); 566 __rte_internal 567 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 568 struct mlx5_devx_qp_attr *attr); 569 __rte_internal 570 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 571 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 572 __rte_internal 573 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 574 struct mlx5_devx_rqt_attr *rqt_attr); 575 __rte_internal 576 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 577 struct mlx5_devx_modify_tir_attr *tir_attr); 578 __rte_internal 579 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 580 uint32_t ids[], uint32_t num); 581 582 __rte_internal 583 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 584 struct mlx5_devx_graph_node_attr *data); 585 586 __rte_internal 587 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 588 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 589 590 __rte_internal 591 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 592 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 593 594 __rte_internal 595 struct mlx5_devx_obj * 596 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 597 uint16_t class, uint8_t type, uint8_t len); 598 599 /** 600 * Create virtio queue counters object DevX API. 601 * 602 * @param[in] ctx 603 * Device context. 604 605 * @return 606 * The DevX object created, NULL otherwise and rte_errno is set. 607 */ 608 __rte_internal 609 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 610 611 /** 612 * Query virtio queue counters object using DevX API. 613 * 614 * @param[in] couners_obj 615 * Pointer to virtq object structure. 616 * @param [in/out] attr 617 * Pointer to virtio queue counters attributes structure. 618 * 619 * @return 620 * 0 on success, a negative errno value otherwise and rte_errno is set. 621 */ 622 __rte_internal 623 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 624 struct mlx5_devx_virtio_q_couners_attr *attr); 625 __rte_internal 626 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 627 uint32_t pd); 628 __rte_internal 629 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 630 631 __rte_internal 632 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 633 634 __rte_internal 635 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 636 __rte_internal 637 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 638 uint32_t *out_of_buffers); 639 __rte_internal 640 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 641 uint32_t pd, uint32_t log_obj_size); 642 643 /** 644 * Create general object of type FLOW_METER_ASO using DevX API.. 645 * 646 * @param[in] ctx 647 * Device context. 648 * @param [in] pd 649 * PD value to associate the FLOW_METER_ASO object with. 650 * @param [in] log_obj_size 651 * log_obj_size define to allocate number of 2 * meters 652 * in one FLOW_METER_ASO object. 653 * 654 * @return 655 * The DevX object created, NULL otherwise and rte_errno is set. 656 */ 657 __rte_internal 658 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 659 uint32_t pd, uint32_t log_obj_size); 660 __rte_internal 661 struct mlx5_devx_obj * 662 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 663 664 __rte_internal 665 struct mlx5_devx_obj * 666 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 667 struct mlx5_devx_import_kek_attr *attr); 668 669 __rte_internal 670 struct mlx5_devx_obj * 671 mlx5_devx_cmd_create_credential_obj(void *ctx, 672 struct mlx5_devx_credential_attr *attr); 673 674 __rte_internal 675 struct mlx5_devx_obj * 676 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 677 struct mlx5_devx_crypto_login_attr *attr); 678 679 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 680