1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 struct mlx5_hca_flow_attr { 93 uint32_t tunnel_header_0_1; 94 uint32_t tunnel_header_2_3; 95 }; 96 97 /* HCA supports this number of time periods for LRO. */ 98 #define MLX5_LRO_NUM_SUPP_PERIODS 4 99 100 /* HCA attributes. */ 101 struct mlx5_hca_attr { 102 uint32_t eswitch_manager:1; 103 uint32_t flow_counters_dump:1; 104 uint32_t log_max_rqt_size:5; 105 uint32_t parse_graph_flex_node:1; 106 uint8_t flow_counter_bulk_alloc_bitmap; 107 uint32_t eth_net_offloads:1; 108 uint32_t eth_virt:1; 109 uint32_t wqe_vlan_insert:1; 110 uint32_t csum_cap:1; 111 uint32_t vlan_cap:1; 112 uint32_t wqe_inline_mode:2; 113 uint32_t vport_inline_mode:3; 114 uint32_t tunnel_stateless_geneve_rx:1; 115 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 116 uint32_t tunnel_stateless_gtp:1; 117 uint32_t max_lso_cap; 118 uint32_t lro_cap:1; 119 uint32_t tunnel_lro_gre:1; 120 uint32_t tunnel_lro_vxlan:1; 121 uint32_t tunnel_stateless_gre:1; 122 uint32_t tunnel_stateless_vxlan:1; 123 uint32_t swp:1; 124 uint32_t swp_csum:1; 125 uint32_t swp_lso:1; 126 uint32_t lro_max_msg_sz_mode:2; 127 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 128 uint16_t lro_min_mss_size; 129 uint32_t flex_parser_protocols; 130 uint32_t max_geneve_tlv_options; 131 uint32_t max_geneve_tlv_option_data_len; 132 uint32_t hairpin:1; 133 uint32_t log_max_hairpin_queues:5; 134 uint32_t log_max_hairpin_wq_data_sz:5; 135 uint32_t log_max_hairpin_num_packets:5; 136 uint32_t vhca_id:16; 137 uint32_t relaxed_ordering_write:1; 138 uint32_t relaxed_ordering_read:1; 139 uint32_t access_register_user:1; 140 uint32_t wqe_index_ignore:1; 141 uint32_t cross_channel:1; 142 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 143 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 144 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 145 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 146 uint32_t scatter_fcs_w_decap_disable:1; 147 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 148 uint32_t roce:1; 149 uint32_t rq_ts_format:2; 150 uint32_t sq_ts_format:2; 151 uint32_t steering_format_version:4; 152 uint32_t qp_ts_format:2; 153 uint32_t regex:1; 154 uint32_t reg_c_preserve:1; 155 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 156 uint32_t crypto:1; /* Crypto engine is supported. */ 157 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 158 uint32_t dek:1; /* General obj type DEK is supported. */ 159 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 160 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 161 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 162 uint32_t regexp_num_of_engines; 163 uint32_t log_max_ft_sampler_num:8; 164 uint32_t inner_ipv4_ihl:1; 165 uint32_t outer_ipv4_ihl:1; 166 uint32_t geneve_tlv_opt; 167 uint32_t cqe_compression:1; 168 uint32_t mini_cqe_resp_flow_tag:1; 169 uint32_t mini_cqe_resp_l3_l4_tag:1; 170 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 171 struct mlx5_hca_qos_attr qos; 172 struct mlx5_hca_vdpa_attr vdpa; 173 struct mlx5_hca_flow_attr flow; 174 int log_max_qp_sz; 175 int log_max_cq_sz; 176 int log_max_qp; 177 int log_max_cq; 178 uint32_t log_max_pd; 179 uint32_t log_max_mrw_sz; 180 uint32_t log_max_srq; 181 uint32_t log_max_srq_sz; 182 uint32_t rss_ind_tbl_cap; 183 uint32_t mmo_dma_sq_en:1; 184 uint32_t mmo_compress_sq_en:1; 185 uint32_t mmo_decompress_sq_en:1; 186 uint32_t mmo_dma_qp_en:1; 187 uint32_t mmo_compress_qp_en:1; 188 uint32_t mmo_decompress_qp_en:1; 189 uint32_t mmo_regex_qp_en:1; 190 uint32_t mmo_regex_sq_en:1; 191 uint32_t compress_min_block_size:4; 192 uint32_t log_max_mmo_dma:5; 193 uint32_t log_max_mmo_compress:5; 194 uint32_t log_max_mmo_decompress:5; 195 uint32_t umr_modify_entity_size_disabled:1; 196 uint32_t umr_indirect_mkey_disabled:1; 197 }; 198 199 struct mlx5_devx_wq_attr { 200 uint32_t wq_type:4; 201 uint32_t wq_signature:1; 202 uint32_t end_padding_mode:2; 203 uint32_t cd_slave:1; 204 uint32_t hds_skip_first_sge:1; 205 uint32_t log2_hds_buf_size:3; 206 uint32_t page_offset:5; 207 uint32_t lwm:16; 208 uint32_t pd:24; 209 uint32_t uar_page:24; 210 uint64_t dbr_addr; 211 uint32_t hw_counter; 212 uint32_t sw_counter; 213 uint32_t log_wq_stride:4; 214 uint32_t log_wq_pg_sz:5; 215 uint32_t log_wq_sz:5; 216 uint32_t dbr_umem_valid:1; 217 uint32_t wq_umem_valid:1; 218 uint32_t log_hairpin_num_packets:5; 219 uint32_t log_hairpin_data_sz:5; 220 uint32_t single_wqe_log_num_of_strides:4; 221 uint32_t two_byte_shift_en:1; 222 uint32_t single_stride_log_num_of_bytes:3; 223 uint32_t dbr_umem_id; 224 uint32_t wq_umem_id; 225 uint64_t wq_umem_offset; 226 }; 227 228 /* Create RQ attributes structure, used by create RQ operation. */ 229 struct mlx5_devx_create_rq_attr { 230 uint32_t rlky:1; 231 uint32_t delay_drop_en:1; 232 uint32_t scatter_fcs:1; 233 uint32_t vsd:1; 234 uint32_t mem_rq_type:4; 235 uint32_t state:4; 236 uint32_t flush_in_error_en:1; 237 uint32_t hairpin:1; 238 uint32_t ts_format:2; 239 uint32_t user_index:24; 240 uint32_t cqn:24; 241 uint32_t counter_set_id:8; 242 uint32_t rmpn:24; 243 struct mlx5_devx_wq_attr wq_attr; 244 }; 245 246 /* Modify RQ attributes structure, used by modify RQ operation. */ 247 struct mlx5_devx_modify_rq_attr { 248 uint32_t rqn:24; 249 uint32_t rq_state:4; /* Current RQ state. */ 250 uint32_t state:4; /* Required RQ state. */ 251 uint32_t scatter_fcs:1; 252 uint32_t vsd:1; 253 uint32_t counter_set_id:8; 254 uint32_t hairpin_peer_sq:24; 255 uint32_t hairpin_peer_vhca:16; 256 uint64_t modify_bitmask; 257 uint32_t lwm:16; /* Contained WQ lwm. */ 258 }; 259 260 struct mlx5_rx_hash_field_select { 261 uint32_t l3_prot_type:1; 262 uint32_t l4_prot_type:1; 263 uint32_t selected_fields:30; 264 }; 265 266 /* TIR attributes structure, used by TIR operations. */ 267 struct mlx5_devx_tir_attr { 268 uint32_t disp_type:4; 269 uint32_t lro_timeout_period_usecs:16; 270 uint32_t lro_enable_mask:4; 271 uint32_t lro_max_msg_sz:8; 272 uint32_t inline_rqn:24; 273 uint32_t rx_hash_symmetric:1; 274 uint32_t tunneled_offload_en:1; 275 uint32_t indirect_table:24; 276 uint32_t rx_hash_fn:4; 277 uint32_t self_lb_block:2; 278 uint32_t transport_domain:24; 279 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 280 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 281 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 282 }; 283 284 /* TIR attributes structure, used by TIR modify. */ 285 struct mlx5_devx_modify_tir_attr { 286 uint32_t tirn:24; 287 uint64_t modify_bitmask; 288 struct mlx5_devx_tir_attr tir; 289 }; 290 291 /* RQT attributes structure, used by RQT operations. */ 292 struct mlx5_devx_rqt_attr { 293 uint8_t rq_type; 294 uint32_t rqt_max_size:16; 295 uint32_t rqt_actual_size:16; 296 uint32_t rq_list[]; 297 }; 298 299 /* TIS attributes structure. */ 300 struct mlx5_devx_tis_attr { 301 uint32_t strict_lag_tx_port_affinity:1; 302 uint32_t tls_en:1; 303 uint32_t lag_tx_port_affinity:4; 304 uint32_t prio:4; 305 uint32_t transport_domain:24; 306 }; 307 308 /* SQ attributes structure, used by SQ create operation. */ 309 struct mlx5_devx_create_sq_attr { 310 uint32_t rlky:1; 311 uint32_t cd_master:1; 312 uint32_t fre:1; 313 uint32_t flush_in_error_en:1; 314 uint32_t allow_multi_pkt_send_wqe:1; 315 uint32_t min_wqe_inline_mode:3; 316 uint32_t state:4; 317 uint32_t reg_umr:1; 318 uint32_t allow_swp:1; 319 uint32_t hairpin:1; 320 uint32_t non_wire:1; 321 uint32_t static_sq_wq:1; 322 uint32_t ts_format:2; 323 uint32_t user_index:24; 324 uint32_t cqn:24; 325 uint32_t packet_pacing_rate_limit_index:16; 326 uint32_t tis_lst_sz:16; 327 uint32_t tis_num:24; 328 struct mlx5_devx_wq_attr wq_attr; 329 }; 330 331 /* SQ attributes structure, used by SQ modify operation. */ 332 struct mlx5_devx_modify_sq_attr { 333 uint32_t sq_state:4; 334 uint32_t state:4; 335 uint32_t hairpin_peer_rq:24; 336 uint32_t hairpin_peer_vhca:16; 337 }; 338 339 340 /* CQ attributes structure, used by CQ operations. */ 341 struct mlx5_devx_cq_attr { 342 uint32_t q_umem_valid:1; 343 uint32_t db_umem_valid:1; 344 uint32_t use_first_only:1; 345 uint32_t overrun_ignore:1; 346 uint32_t cqe_comp_en:1; 347 uint32_t mini_cqe_res_format:2; 348 uint32_t mini_cqe_res_format_ext:2; 349 uint32_t log_cq_size:5; 350 uint32_t log_page_size:5; 351 uint32_t uar_page_id; 352 uint32_t q_umem_id; 353 uint64_t q_umem_offset; 354 uint32_t db_umem_id; 355 uint64_t db_umem_offset; 356 uint32_t eqn; 357 uint64_t db_addr; 358 }; 359 360 /* Virtq attributes structure, used by VIRTQ operations. */ 361 struct mlx5_devx_virtq_attr { 362 uint16_t hw_available_index; 363 uint16_t hw_used_index; 364 uint16_t q_size; 365 uint32_t pd:24; 366 uint32_t virtio_version_1_0:1; 367 uint32_t tso_ipv4:1; 368 uint32_t tso_ipv6:1; 369 uint32_t tx_csum:1; 370 uint32_t rx_csum:1; 371 uint32_t event_mode:3; 372 uint32_t state:4; 373 uint32_t hw_latency_mode:2; 374 uint32_t hw_max_latency_us:12; 375 uint32_t hw_max_pending_comp:16; 376 uint32_t dirty_bitmap_dump_enable:1; 377 uint32_t dirty_bitmap_mkey; 378 uint32_t dirty_bitmap_size; 379 uint32_t mkey; 380 uint32_t qp_id; 381 uint32_t queue_index; 382 uint32_t tis_id; 383 uint32_t counters_obj_id; 384 uint64_t dirty_bitmap_addr; 385 uint64_t type; 386 uint64_t desc_addr; 387 uint64_t used_addr; 388 uint64_t available_addr; 389 struct { 390 uint32_t id; 391 uint32_t size; 392 uint64_t offset; 393 } umems[3]; 394 uint8_t error_type; 395 }; 396 397 398 struct mlx5_devx_qp_attr { 399 uint32_t pd:24; 400 uint32_t uar_index:24; 401 uint32_t cqn:24; 402 uint32_t log_page_size:5; 403 uint32_t rq_size:17; /* Must be power of 2. */ 404 uint32_t log_rq_stride:3; 405 uint32_t sq_size:17; /* Must be power of 2. */ 406 uint32_t ts_format:2; 407 uint32_t dbr_umem_valid:1; 408 uint32_t dbr_umem_id; 409 uint64_t dbr_address; 410 uint32_t wq_umem_id; 411 uint64_t wq_umem_offset; 412 uint32_t user_index:24; 413 uint32_t mmo:1; 414 }; 415 416 struct mlx5_devx_virtio_q_couners_attr { 417 uint64_t received_desc; 418 uint64_t completed_desc; 419 uint32_t error_cqes; 420 uint32_t bad_desc_errors; 421 uint32_t exceed_max_chain; 422 uint32_t invalid_buffer; 423 }; 424 425 /* 426 * graph flow match sample attributes structure, 427 * used by flex parser operations. 428 */ 429 struct mlx5_devx_match_sample_attr { 430 uint32_t flow_match_sample_en:1; 431 uint32_t flow_match_sample_field_offset:16; 432 uint32_t flow_match_sample_offset_mode:4; 433 uint32_t flow_match_sample_field_offset_mask; 434 uint32_t flow_match_sample_field_offset_shift:4; 435 uint32_t flow_match_sample_field_base_offset:8; 436 uint32_t flow_match_sample_tunnel_mode:3; 437 uint32_t flow_match_sample_field_id; 438 }; 439 440 /* graph node arc attributes structure, used by flex parser operations. */ 441 struct mlx5_devx_graph_arc_attr { 442 uint32_t compare_condition_value:16; 443 uint32_t start_inner_tunnel:1; 444 uint32_t arc_parse_graph_node:8; 445 uint32_t parse_graph_node_handle; 446 }; 447 448 /* Maximal number of samples per graph node. */ 449 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 450 451 /* Maximal number of input/output arcs per graph node. */ 452 #define MLX5_GRAPH_NODE_ARC_NUM 8 453 454 /* parse graph node attributes structure, used by flex parser operations. */ 455 struct mlx5_devx_graph_node_attr { 456 uint32_t modify_field_select; 457 uint32_t header_length_mode:4; 458 uint32_t header_length_base_value:16; 459 uint32_t header_length_field_shift:4; 460 uint32_t header_length_field_offset:16; 461 uint32_t header_length_field_mask; 462 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 463 uint32_t next_header_field_offset:16; 464 uint32_t next_header_field_size:5; 465 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 466 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 467 }; 468 469 /* Encryption key size is up to 1024 bit, 128 bytes. */ 470 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 471 472 struct mlx5_devx_dek_attr { 473 uint32_t key_size:4; 474 uint32_t has_keytag:1; 475 uint32_t key_purpose:4; 476 uint32_t pd:24; 477 uint64_t opaque; 478 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 479 }; 480 481 struct mlx5_devx_import_kek_attr { 482 uint64_t modify_field_select; 483 uint32_t state:8; 484 uint32_t key_size:4; 485 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 486 }; 487 488 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 489 490 struct mlx5_devx_credential_attr { 491 uint64_t modify_field_select; 492 uint32_t state:8; 493 uint32_t credential_role:8; 494 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 495 }; 496 497 struct mlx5_devx_crypto_login_attr { 498 uint64_t modify_field_select; 499 uint32_t credential_pointer:24; 500 uint32_t session_import_kek_ptr:24; 501 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 502 }; 503 504 /* mlx5_devx_cmds.c */ 505 506 __rte_internal 507 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 508 uint32_t bulk_sz); 509 __rte_internal 510 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 511 __rte_internal 512 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 513 int clear, uint32_t n_counters, 514 uint64_t *pkts, uint64_t *bytes, 515 uint32_t mkey, void *addr, 516 void *cmd_comp, 517 uint64_t async_id); 518 __rte_internal 519 int mlx5_devx_cmd_query_hca_attr(void *ctx, 520 struct mlx5_hca_attr *attr); 521 __rte_internal 522 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 523 struct mlx5_devx_mkey_attr *attr); 524 __rte_internal 525 int mlx5_devx_get_out_command_status(void *out); 526 __rte_internal 527 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 528 uint32_t *tis_td); 529 __rte_internal 530 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 531 struct mlx5_devx_create_rq_attr *rq_attr, 532 int socket); 533 __rte_internal 534 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 535 struct mlx5_devx_modify_rq_attr *rq_attr); 536 __rte_internal 537 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 538 struct mlx5_devx_tir_attr *tir_attr); 539 __rte_internal 540 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 541 struct mlx5_devx_rqt_attr *rqt_attr); 542 __rte_internal 543 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 544 struct mlx5_devx_create_sq_attr *sq_attr); 545 __rte_internal 546 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 547 struct mlx5_devx_modify_sq_attr *sq_attr); 548 __rte_internal 549 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 550 struct mlx5_devx_tis_attr *tis_attr); 551 __rte_internal 552 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 553 __rte_internal 554 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 555 FILE *file); 556 __rte_internal 557 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 558 __rte_internal 559 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 560 struct mlx5_devx_cq_attr *attr); 561 __rte_internal 562 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 563 struct mlx5_devx_virtq_attr *attr); 564 __rte_internal 565 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 566 struct mlx5_devx_virtq_attr *attr); 567 __rte_internal 568 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 569 struct mlx5_devx_virtq_attr *attr); 570 __rte_internal 571 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 572 struct mlx5_devx_qp_attr *attr); 573 __rte_internal 574 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 575 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 576 __rte_internal 577 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 578 struct mlx5_devx_rqt_attr *rqt_attr); 579 __rte_internal 580 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 581 struct mlx5_devx_modify_tir_attr *tir_attr); 582 __rte_internal 583 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 584 uint32_t ids[], uint32_t num); 585 586 __rte_internal 587 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 588 struct mlx5_devx_graph_node_attr *data); 589 590 __rte_internal 591 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 592 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 593 594 __rte_internal 595 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 596 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 597 598 __rte_internal 599 struct mlx5_devx_obj * 600 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 601 uint16_t class, uint8_t type, uint8_t len); 602 603 /** 604 * Create virtio queue counters object DevX API. 605 * 606 * @param[in] ctx 607 * Device context. 608 609 * @return 610 * The DevX object created, NULL otherwise and rte_errno is set. 611 */ 612 __rte_internal 613 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 614 615 /** 616 * Query virtio queue counters object using DevX API. 617 * 618 * @param[in] couners_obj 619 * Pointer to virtq object structure. 620 * @param [in/out] attr 621 * Pointer to virtio queue counters attributes structure. 622 * 623 * @return 624 * 0 on success, a negative errno value otherwise and rte_errno is set. 625 */ 626 __rte_internal 627 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 628 struct mlx5_devx_virtio_q_couners_attr *attr); 629 __rte_internal 630 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 631 uint32_t pd); 632 __rte_internal 633 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 634 635 __rte_internal 636 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 637 638 __rte_internal 639 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 640 __rte_internal 641 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 642 uint32_t *out_of_buffers); 643 __rte_internal 644 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 645 uint32_t pd, uint32_t log_obj_size); 646 647 /** 648 * Create general object of type FLOW_METER_ASO using DevX API.. 649 * 650 * @param[in] ctx 651 * Device context. 652 * @param [in] pd 653 * PD value to associate the FLOW_METER_ASO object with. 654 * @param [in] log_obj_size 655 * log_obj_size define to allocate number of 2 * meters 656 * in one FLOW_METER_ASO object. 657 * 658 * @return 659 * The DevX object created, NULL otherwise and rte_errno is set. 660 */ 661 __rte_internal 662 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 663 uint32_t pd, uint32_t log_obj_size); 664 __rte_internal 665 struct mlx5_devx_obj * 666 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 667 668 __rte_internal 669 struct mlx5_devx_obj * 670 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 671 struct mlx5_devx_import_kek_attr *attr); 672 673 __rte_internal 674 struct mlx5_devx_obj * 675 mlx5_devx_cmd_create_credential_obj(void *ctx, 676 struct mlx5_devx_credential_attr *attr); 677 678 __rte_internal 679 struct mlx5_devx_obj * 680 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 681 struct mlx5_devx_crypto_login_attr *attr); 682 683 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 684