1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 struct mlx5_klm *klm_array; 35 int klm_num; 36 }; 37 38 /* HCA qos attributes. */ 39 struct mlx5_hca_qos_attr { 40 uint32_t sup:1; /* Whether QOS is supported. */ 41 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 42 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 43 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 44 uint32_t flow_meter_reg_share:1; 45 /* Whether reg_c share is supported. */ 46 uint8_t log_max_flow_meter; 47 /* Power of the maximum supported meters. */ 48 uint8_t flow_meter_reg_c_ids; 49 /* Bitmap of the reg_Cs available for flow meter to use. */ 50 51 }; 52 53 struct mlx5_hca_vdpa_attr { 54 uint8_t virtio_queue_type; 55 uint32_t valid:1; 56 uint32_t desc_tunnel_offload_type:1; 57 uint32_t eth_frame_offload_type:1; 58 uint32_t virtio_version_1_0:1; 59 uint32_t tso_ipv4:1; 60 uint32_t tso_ipv6:1; 61 uint32_t tx_csum:1; 62 uint32_t rx_csum:1; 63 uint32_t event_mode:3; 64 uint32_t log_doorbell_stride:5; 65 uint32_t log_doorbell_bar_size:5; 66 uint32_t queue_counters_valid:1; 67 uint32_t max_num_virtio_queues; 68 struct { 69 uint32_t a; 70 uint32_t b; 71 } umems[3]; 72 uint64_t doorbell_bar_offset; 73 }; 74 75 /* HCA supports this number of time periods for LRO. */ 76 #define MLX5_LRO_NUM_SUPP_PERIODS 4 77 78 /* HCA attributes. */ 79 struct mlx5_hca_attr { 80 uint32_t eswitch_manager:1; 81 uint32_t flow_counters_dump:1; 82 uint32_t log_max_rqt_size:5; 83 uint32_t parse_graph_flex_node:1; 84 uint8_t flow_counter_bulk_alloc_bitmap; 85 uint32_t eth_net_offloads:1; 86 uint32_t eth_virt:1; 87 uint32_t wqe_vlan_insert:1; 88 uint32_t wqe_inline_mode:2; 89 uint32_t vport_inline_mode:3; 90 uint32_t tunnel_stateless_geneve_rx:1; 91 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 92 uint32_t tunnel_stateless_gtp:1; 93 uint32_t lro_cap:1; 94 uint32_t tunnel_lro_gre:1; 95 uint32_t tunnel_lro_vxlan:1; 96 uint32_t lro_max_msg_sz_mode:2; 97 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 98 uint16_t lro_min_mss_size; 99 uint32_t flex_parser_protocols; 100 uint32_t max_geneve_tlv_options; 101 uint32_t max_geneve_tlv_option_data_len; 102 uint32_t hairpin:1; 103 uint32_t log_max_hairpin_queues:5; 104 uint32_t log_max_hairpin_wq_data_sz:5; 105 uint32_t log_max_hairpin_num_packets:5; 106 uint32_t vhca_id:16; 107 uint32_t relaxed_ordering_write:1; 108 uint32_t relaxed_ordering_read:1; 109 uint32_t access_register_user:1; 110 uint32_t wqe_index_ignore:1; 111 uint32_t cross_channel:1; 112 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 113 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 114 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 115 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 116 uint32_t scatter_fcs_w_decap_disable:1; 117 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 118 uint32_t regex:1; 119 uint32_t reg_c_preserve:1; 120 uint32_t regexp_num_of_engines; 121 uint32_t log_max_ft_sampler_num:8; 122 uint32_t geneve_tlv_opt; 123 struct mlx5_hca_qos_attr qos; 124 struct mlx5_hca_vdpa_attr vdpa; 125 int log_max_qp_sz; 126 int log_max_cq_sz; 127 int log_max_qp; 128 int log_max_cq; 129 uint32_t log_max_pd; 130 uint32_t log_max_mrw_sz; 131 uint32_t log_max_srq; 132 uint32_t log_max_srq_sz; 133 uint32_t rss_ind_tbl_cap; 134 uint32_t mmo_dma_en:1; 135 uint32_t mmo_compress_en:1; 136 uint32_t mmo_decompress_en:1; 137 uint32_t compress_min_block_size:4; 138 uint32_t log_max_mmo_dma:5; 139 uint32_t log_max_mmo_compress:5; 140 uint32_t log_max_mmo_decompress:5; 141 }; 142 143 struct mlx5_devx_wq_attr { 144 uint32_t wq_type:4; 145 uint32_t wq_signature:1; 146 uint32_t end_padding_mode:2; 147 uint32_t cd_slave:1; 148 uint32_t hds_skip_first_sge:1; 149 uint32_t log2_hds_buf_size:3; 150 uint32_t page_offset:5; 151 uint32_t lwm:16; 152 uint32_t pd:24; 153 uint32_t uar_page:24; 154 uint64_t dbr_addr; 155 uint32_t hw_counter; 156 uint32_t sw_counter; 157 uint32_t log_wq_stride:4; 158 uint32_t log_wq_pg_sz:5; 159 uint32_t log_wq_sz:5; 160 uint32_t dbr_umem_valid:1; 161 uint32_t wq_umem_valid:1; 162 uint32_t log_hairpin_num_packets:5; 163 uint32_t log_hairpin_data_sz:5; 164 uint32_t single_wqe_log_num_of_strides:4; 165 uint32_t two_byte_shift_en:1; 166 uint32_t single_stride_log_num_of_bytes:3; 167 uint32_t dbr_umem_id; 168 uint32_t wq_umem_id; 169 uint64_t wq_umem_offset; 170 }; 171 172 /* Create RQ attributes structure, used by create RQ operation. */ 173 struct mlx5_devx_create_rq_attr { 174 uint32_t rlky:1; 175 uint32_t delay_drop_en:1; 176 uint32_t scatter_fcs:1; 177 uint32_t vsd:1; 178 uint32_t mem_rq_type:4; 179 uint32_t state:4; 180 uint32_t flush_in_error_en:1; 181 uint32_t hairpin:1; 182 uint32_t user_index:24; 183 uint32_t cqn:24; 184 uint32_t counter_set_id:8; 185 uint32_t rmpn:24; 186 struct mlx5_devx_wq_attr wq_attr; 187 }; 188 189 /* Modify RQ attributes structure, used by modify RQ operation. */ 190 struct mlx5_devx_modify_rq_attr { 191 uint32_t rqn:24; 192 uint32_t rq_state:4; /* Current RQ state. */ 193 uint32_t state:4; /* Required RQ state. */ 194 uint32_t scatter_fcs:1; 195 uint32_t vsd:1; 196 uint32_t counter_set_id:8; 197 uint32_t hairpin_peer_sq:24; 198 uint32_t hairpin_peer_vhca:16; 199 uint64_t modify_bitmask; 200 uint32_t lwm:16; /* Contained WQ lwm. */ 201 }; 202 203 struct mlx5_rx_hash_field_select { 204 uint32_t l3_prot_type:1; 205 uint32_t l4_prot_type:1; 206 uint32_t selected_fields:30; 207 }; 208 209 /* TIR attributes structure, used by TIR operations. */ 210 struct mlx5_devx_tir_attr { 211 uint32_t disp_type:4; 212 uint32_t lro_timeout_period_usecs:16; 213 uint32_t lro_enable_mask:4; 214 uint32_t lro_max_msg_sz:8; 215 uint32_t inline_rqn:24; 216 uint32_t rx_hash_symmetric:1; 217 uint32_t tunneled_offload_en:1; 218 uint32_t indirect_table:24; 219 uint32_t rx_hash_fn:4; 220 uint32_t self_lb_block:2; 221 uint32_t transport_domain:24; 222 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 223 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 224 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 225 }; 226 227 /* TIR attributes structure, used by TIR modify. */ 228 struct mlx5_devx_modify_tir_attr { 229 uint32_t tirn:24; 230 uint64_t modify_bitmask; 231 struct mlx5_devx_tir_attr tir; 232 }; 233 234 /* RQT attributes structure, used by RQT operations. */ 235 struct mlx5_devx_rqt_attr { 236 uint8_t rq_type; 237 uint32_t rqt_max_size:16; 238 uint32_t rqt_actual_size:16; 239 uint32_t rq_list[]; 240 }; 241 242 /* TIS attributes structure. */ 243 struct mlx5_devx_tis_attr { 244 uint32_t strict_lag_tx_port_affinity:1; 245 uint32_t tls_en:1; 246 uint32_t lag_tx_port_affinity:4; 247 uint32_t prio:4; 248 uint32_t transport_domain:24; 249 }; 250 251 /* SQ attributes structure, used by SQ create operation. */ 252 struct mlx5_devx_create_sq_attr { 253 uint32_t rlky:1; 254 uint32_t cd_master:1; 255 uint32_t fre:1; 256 uint32_t flush_in_error_en:1; 257 uint32_t allow_multi_pkt_send_wqe:1; 258 uint32_t min_wqe_inline_mode:3; 259 uint32_t state:4; 260 uint32_t reg_umr:1; 261 uint32_t allow_swp:1; 262 uint32_t hairpin:1; 263 uint32_t non_wire:1; 264 uint32_t static_sq_wq:1; 265 uint32_t user_index:24; 266 uint32_t cqn:24; 267 uint32_t packet_pacing_rate_limit_index:16; 268 uint32_t tis_lst_sz:16; 269 uint32_t tis_num:24; 270 struct mlx5_devx_wq_attr wq_attr; 271 }; 272 273 /* SQ attributes structure, used by SQ modify operation. */ 274 struct mlx5_devx_modify_sq_attr { 275 uint32_t sq_state:4; 276 uint32_t state:4; 277 uint32_t hairpin_peer_rq:24; 278 uint32_t hairpin_peer_vhca:16; 279 }; 280 281 282 /* CQ attributes structure, used by CQ operations. */ 283 struct mlx5_devx_cq_attr { 284 uint32_t q_umem_valid:1; 285 uint32_t db_umem_valid:1; 286 uint32_t use_first_only:1; 287 uint32_t overrun_ignore:1; 288 uint32_t cqe_comp_en:1; 289 uint32_t mini_cqe_res_format:2; 290 uint32_t mini_cqe_res_format_ext:2; 291 uint32_t log_cq_size:5; 292 uint32_t log_page_size:5; 293 uint32_t uar_page_id; 294 uint32_t q_umem_id; 295 uint64_t q_umem_offset; 296 uint32_t db_umem_id; 297 uint64_t db_umem_offset; 298 uint32_t eqn; 299 uint64_t db_addr; 300 }; 301 302 /* Virtq attributes structure, used by VIRTQ operations. */ 303 struct mlx5_devx_virtq_attr { 304 uint16_t hw_available_index; 305 uint16_t hw_used_index; 306 uint16_t q_size; 307 uint32_t pd:24; 308 uint32_t virtio_version_1_0:1; 309 uint32_t tso_ipv4:1; 310 uint32_t tso_ipv6:1; 311 uint32_t tx_csum:1; 312 uint32_t rx_csum:1; 313 uint32_t event_mode:3; 314 uint32_t state:4; 315 uint32_t hw_latency_mode:2; 316 uint32_t hw_max_latency_us:12; 317 uint32_t hw_max_pending_comp:16; 318 uint32_t dirty_bitmap_dump_enable:1; 319 uint32_t dirty_bitmap_mkey; 320 uint32_t dirty_bitmap_size; 321 uint32_t mkey; 322 uint32_t qp_id; 323 uint32_t queue_index; 324 uint32_t tis_id; 325 uint32_t counters_obj_id; 326 uint64_t dirty_bitmap_addr; 327 uint64_t type; 328 uint64_t desc_addr; 329 uint64_t used_addr; 330 uint64_t available_addr; 331 struct { 332 uint32_t id; 333 uint32_t size; 334 uint64_t offset; 335 } umems[3]; 336 uint8_t error_type; 337 }; 338 339 340 struct mlx5_devx_qp_attr { 341 uint32_t pd:24; 342 uint32_t uar_index:24; 343 uint32_t cqn:24; 344 uint32_t log_page_size:5; 345 uint32_t rq_size:17; /* Must be power of 2. */ 346 uint32_t log_rq_stride:3; 347 uint32_t sq_size:17; /* Must be power of 2. */ 348 uint32_t dbr_umem_valid:1; 349 uint32_t dbr_umem_id; 350 uint64_t dbr_address; 351 uint32_t wq_umem_id; 352 uint64_t wq_umem_offset; 353 }; 354 355 struct mlx5_devx_virtio_q_couners_attr { 356 uint64_t received_desc; 357 uint64_t completed_desc; 358 uint32_t error_cqes; 359 uint32_t bad_desc_errors; 360 uint32_t exceed_max_chain; 361 uint32_t invalid_buffer; 362 }; 363 364 /* 365 * graph flow match sample attributes structure, 366 * used by flex parser operations. 367 */ 368 struct mlx5_devx_match_sample_attr { 369 uint32_t flow_match_sample_en:1; 370 uint32_t flow_match_sample_field_offset:16; 371 uint32_t flow_match_sample_offset_mode:4; 372 uint32_t flow_match_sample_field_offset_mask; 373 uint32_t flow_match_sample_field_offset_shift:4; 374 uint32_t flow_match_sample_field_base_offset:8; 375 uint32_t flow_match_sample_tunnel_mode:3; 376 uint32_t flow_match_sample_field_id; 377 }; 378 379 /* graph node arc attributes structure, used by flex parser operations. */ 380 struct mlx5_devx_graph_arc_attr { 381 uint32_t compare_condition_value:16; 382 uint32_t start_inner_tunnel:1; 383 uint32_t arc_parse_graph_node:8; 384 uint32_t parse_graph_node_handle; 385 }; 386 387 /* Maximal number of samples per graph node. */ 388 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 389 390 /* Maximal number of input/output arcs per graph node. */ 391 #define MLX5_GRAPH_NODE_ARC_NUM 8 392 393 /* parse graph node attributes structure, used by flex parser operations. */ 394 struct mlx5_devx_graph_node_attr { 395 uint32_t modify_field_select; 396 uint32_t header_length_mode:4; 397 uint32_t header_length_base_value:16; 398 uint32_t header_length_field_shift:4; 399 uint32_t header_length_field_offset:16; 400 uint32_t header_length_field_mask; 401 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 402 uint32_t next_header_field_offset:16; 403 uint32_t next_header_field_size:5; 404 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 405 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 406 }; 407 408 /* mlx5_devx_cmds.c */ 409 410 __rte_internal 411 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 412 uint32_t bulk_sz); 413 __rte_internal 414 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 415 __rte_internal 416 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 417 int clear, uint32_t n_counters, 418 uint64_t *pkts, uint64_t *bytes, 419 uint32_t mkey, void *addr, 420 void *cmd_comp, 421 uint64_t async_id); 422 __rte_internal 423 int mlx5_devx_cmd_query_hca_attr(void *ctx, 424 struct mlx5_hca_attr *attr); 425 __rte_internal 426 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 427 struct mlx5_devx_mkey_attr *attr); 428 __rte_internal 429 int mlx5_devx_get_out_command_status(void *out); 430 __rte_internal 431 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 432 uint32_t *tis_td); 433 __rte_internal 434 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 435 struct mlx5_devx_create_rq_attr *rq_attr, 436 int socket); 437 __rte_internal 438 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 439 struct mlx5_devx_modify_rq_attr *rq_attr); 440 __rte_internal 441 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 442 struct mlx5_devx_tir_attr *tir_attr); 443 __rte_internal 444 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 445 struct mlx5_devx_rqt_attr *rqt_attr); 446 __rte_internal 447 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 448 struct mlx5_devx_create_sq_attr *sq_attr); 449 __rte_internal 450 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 451 struct mlx5_devx_modify_sq_attr *sq_attr); 452 __rte_internal 453 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 454 struct mlx5_devx_tis_attr *tis_attr); 455 __rte_internal 456 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 457 __rte_internal 458 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 459 FILE *file); 460 __rte_internal 461 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 462 struct mlx5_devx_cq_attr *attr); 463 __rte_internal 464 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 465 struct mlx5_devx_virtq_attr *attr); 466 __rte_internal 467 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 468 struct mlx5_devx_virtq_attr *attr); 469 __rte_internal 470 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 471 struct mlx5_devx_virtq_attr *attr); 472 __rte_internal 473 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 474 struct mlx5_devx_qp_attr *attr); 475 __rte_internal 476 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 477 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 478 __rte_internal 479 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 480 struct mlx5_devx_rqt_attr *rqt_attr); 481 __rte_internal 482 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 483 struct mlx5_devx_modify_tir_attr *tir_attr); 484 __rte_internal 485 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 486 uint32_t ids[], uint32_t num); 487 488 __rte_internal 489 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 490 struct mlx5_devx_graph_node_attr *data); 491 492 __rte_internal 493 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 494 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 495 496 __rte_internal 497 struct mlx5_devx_obj * 498 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 499 uint16_t class, uint8_t type, uint8_t len); 500 501 /** 502 * Create virtio queue counters object DevX API. 503 * 504 * @param[in] ctx 505 * Device context. 506 507 * @return 508 * The DevX object created, NULL otherwise and rte_errno is set. 509 */ 510 __rte_internal 511 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 512 513 /** 514 * Query virtio queue counters object using DevX API. 515 * 516 * @param[in] couners_obj 517 * Pointer to virtq object structure. 518 * @param [in/out] attr 519 * Pointer to virtio queue counters attributes structure. 520 * 521 * @return 522 * 0 on success, a negative errno value otherwise and rte_errno is set. 523 */ 524 __rte_internal 525 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 526 struct mlx5_devx_virtio_q_couners_attr *attr); 527 __rte_internal 528 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 529 uint32_t pd); 530 531 __rte_internal 532 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 533 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 534