1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 11 12 /* This is limitation of libibverbs: in length variable type is u16. */ 13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 15 16 struct mlx5_devx_mkey_attr { 17 uint64_t addr; 18 uint64_t size; 19 uint32_t umem_id; 20 uint32_t pd; 21 uint32_t log_entity_size; 22 uint32_t pg_access:1; 23 uint32_t relaxed_ordering:1; 24 struct mlx5_klm *klm_array; 25 int klm_num; 26 }; 27 28 /* HCA qos attributes. */ 29 struct mlx5_hca_qos_attr { 30 uint32_t sup:1; /* Whether QOS is supported. */ 31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 32 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 34 uint32_t flow_meter_reg_share:1; 35 /* Whether reg_c share is supported. */ 36 uint8_t log_max_flow_meter; 37 /* Power of the maximum supported meters. */ 38 uint8_t flow_meter_reg_c_ids; 39 /* Bitmap of the reg_Cs available for flow meter to use. */ 40 41 }; 42 43 struct mlx5_hca_vdpa_attr { 44 uint8_t virtio_queue_type; 45 uint32_t valid:1; 46 uint32_t desc_tunnel_offload_type:1; 47 uint32_t eth_frame_offload_type:1; 48 uint32_t virtio_version_1_0:1; 49 uint32_t tso_ipv4:1; 50 uint32_t tso_ipv6:1; 51 uint32_t tx_csum:1; 52 uint32_t rx_csum:1; 53 uint32_t event_mode:3; 54 uint32_t log_doorbell_stride:5; 55 uint32_t log_doorbell_bar_size:5; 56 uint32_t queue_counters_valid:1; 57 uint32_t max_num_virtio_queues; 58 struct { 59 uint32_t a; 60 uint32_t b; 61 } umems[3]; 62 uint64_t doorbell_bar_offset; 63 }; 64 65 /* HCA supports this number of time periods for LRO. */ 66 #define MLX5_LRO_NUM_SUPP_PERIODS 4 67 68 /* HCA attributes. */ 69 struct mlx5_hca_attr { 70 uint32_t eswitch_manager:1; 71 uint32_t flow_counters_dump:1; 72 uint32_t log_max_rqt_size:5; 73 uint32_t parse_graph_flex_node:1; 74 uint8_t flow_counter_bulk_alloc_bitmap; 75 uint32_t eth_net_offloads:1; 76 uint32_t eth_virt:1; 77 uint32_t wqe_vlan_insert:1; 78 uint32_t wqe_inline_mode:2; 79 uint32_t vport_inline_mode:3; 80 uint32_t tunnel_stateless_geneve_rx:1; 81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 82 uint32_t tunnel_stateless_gtp:1; 83 uint32_t lro_cap:1; 84 uint32_t tunnel_lro_gre:1; 85 uint32_t tunnel_lro_vxlan:1; 86 uint32_t lro_max_msg_sz_mode:2; 87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 88 uint16_t lro_min_mss_size; 89 uint32_t flex_parser_protocols; 90 uint32_t hairpin:1; 91 uint32_t log_max_hairpin_queues:5; 92 uint32_t log_max_hairpin_wq_data_sz:5; 93 uint32_t log_max_hairpin_num_packets:5; 94 uint32_t vhca_id:16; 95 uint32_t relaxed_ordering_write:1; 96 uint32_t relaxed_ordering_read:1; 97 uint32_t access_register_user:1; 98 uint32_t wqe_index_ignore:1; 99 uint32_t cross_channel:1; 100 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 101 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 102 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 103 uint32_t scatter_fcs_w_decap_disable:1; 104 uint32_t regex:1; 105 uint32_t regexp_num_of_engines; 106 uint32_t log_max_ft_sampler_num:8; 107 struct mlx5_hca_qos_attr qos; 108 struct mlx5_hca_vdpa_attr vdpa; 109 }; 110 111 struct mlx5_devx_wq_attr { 112 uint32_t wq_type:4; 113 uint32_t wq_signature:1; 114 uint32_t end_padding_mode:2; 115 uint32_t cd_slave:1; 116 uint32_t hds_skip_first_sge:1; 117 uint32_t log2_hds_buf_size:3; 118 uint32_t page_offset:5; 119 uint32_t lwm:16; 120 uint32_t pd:24; 121 uint32_t uar_page:24; 122 uint64_t dbr_addr; 123 uint32_t hw_counter; 124 uint32_t sw_counter; 125 uint32_t log_wq_stride:4; 126 uint32_t log_wq_pg_sz:5; 127 uint32_t log_wq_sz:5; 128 uint32_t dbr_umem_valid:1; 129 uint32_t wq_umem_valid:1; 130 uint32_t log_hairpin_num_packets:5; 131 uint32_t log_hairpin_data_sz:5; 132 uint32_t single_wqe_log_num_of_strides:4; 133 uint32_t two_byte_shift_en:1; 134 uint32_t single_stride_log_num_of_bytes:3; 135 uint32_t dbr_umem_id; 136 uint32_t wq_umem_id; 137 uint64_t wq_umem_offset; 138 }; 139 140 /* Create RQ attributes structure, used by create RQ operation. */ 141 struct mlx5_devx_create_rq_attr { 142 uint32_t rlky:1; 143 uint32_t delay_drop_en:1; 144 uint32_t scatter_fcs:1; 145 uint32_t vsd:1; 146 uint32_t mem_rq_type:4; 147 uint32_t state:4; 148 uint32_t flush_in_error_en:1; 149 uint32_t hairpin:1; 150 uint32_t user_index:24; 151 uint32_t cqn:24; 152 uint32_t counter_set_id:8; 153 uint32_t rmpn:24; 154 struct mlx5_devx_wq_attr wq_attr; 155 }; 156 157 /* Modify RQ attributes structure, used by modify RQ operation. */ 158 struct mlx5_devx_modify_rq_attr { 159 uint32_t rqn:24; 160 uint32_t rq_state:4; /* Current RQ state. */ 161 uint32_t state:4; /* Required RQ state. */ 162 uint32_t scatter_fcs:1; 163 uint32_t vsd:1; 164 uint32_t counter_set_id:8; 165 uint32_t hairpin_peer_sq:24; 166 uint32_t hairpin_peer_vhca:16; 167 uint64_t modify_bitmask; 168 uint32_t lwm:16; /* Contained WQ lwm. */ 169 }; 170 171 struct mlx5_rx_hash_field_select { 172 uint32_t l3_prot_type:1; 173 uint32_t l4_prot_type:1; 174 uint32_t selected_fields:30; 175 }; 176 177 /* TIR attributes structure, used by TIR operations. */ 178 struct mlx5_devx_tir_attr { 179 uint32_t disp_type:4; 180 uint32_t lro_timeout_period_usecs:16; 181 uint32_t lro_enable_mask:4; 182 uint32_t lro_max_msg_sz:8; 183 uint32_t inline_rqn:24; 184 uint32_t rx_hash_symmetric:1; 185 uint32_t tunneled_offload_en:1; 186 uint32_t indirect_table:24; 187 uint32_t rx_hash_fn:4; 188 uint32_t self_lb_block:2; 189 uint32_t transport_domain:24; 190 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 191 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 192 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 193 }; 194 195 /* TIR attributes structure, used by TIR modify. */ 196 struct mlx5_devx_modify_tir_attr { 197 uint32_t tirn:24; 198 uint64_t modify_bitmask; 199 struct mlx5_devx_tir_attr tir; 200 }; 201 202 /* RQT attributes structure, used by RQT operations. */ 203 struct mlx5_devx_rqt_attr { 204 uint8_t rq_type; 205 uint32_t rqt_max_size:16; 206 uint32_t rqt_actual_size:16; 207 uint32_t rq_list[]; 208 }; 209 210 /* TIS attributes structure. */ 211 struct mlx5_devx_tis_attr { 212 uint32_t strict_lag_tx_port_affinity:1; 213 uint32_t tls_en:1; 214 uint32_t lag_tx_port_affinity:4; 215 uint32_t prio:4; 216 uint32_t transport_domain:24; 217 }; 218 219 /* SQ attributes structure, used by SQ create operation. */ 220 struct mlx5_devx_create_sq_attr { 221 uint32_t rlky:1; 222 uint32_t cd_master:1; 223 uint32_t fre:1; 224 uint32_t flush_in_error_en:1; 225 uint32_t allow_multi_pkt_send_wqe:1; 226 uint32_t min_wqe_inline_mode:3; 227 uint32_t state:4; 228 uint32_t reg_umr:1; 229 uint32_t allow_swp:1; 230 uint32_t hairpin:1; 231 uint32_t non_wire:1; 232 uint32_t static_sq_wq:1; 233 uint32_t user_index:24; 234 uint32_t cqn:24; 235 uint32_t packet_pacing_rate_limit_index:16; 236 uint32_t tis_lst_sz:16; 237 uint32_t tis_num:24; 238 struct mlx5_devx_wq_attr wq_attr; 239 }; 240 241 /* SQ attributes structure, used by SQ modify operation. */ 242 struct mlx5_devx_modify_sq_attr { 243 uint32_t sq_state:4; 244 uint32_t state:4; 245 uint32_t hairpin_peer_rq:24; 246 uint32_t hairpin_peer_vhca:16; 247 }; 248 249 250 /* CQ attributes structure, used by CQ operations. */ 251 struct mlx5_devx_cq_attr { 252 uint32_t q_umem_valid:1; 253 uint32_t db_umem_valid:1; 254 uint32_t use_first_only:1; 255 uint32_t overrun_ignore:1; 256 uint32_t cqe_comp_en:1; 257 uint32_t mini_cqe_res_format:2; 258 uint32_t cqe_size:3; 259 uint32_t log_cq_size:5; 260 uint32_t log_page_size:5; 261 uint32_t uar_page_id; 262 uint32_t q_umem_id; 263 uint64_t q_umem_offset; 264 uint32_t db_umem_id; 265 uint64_t db_umem_offset; 266 uint32_t eqn; 267 uint64_t db_addr; 268 }; 269 270 /* Virtq attributes structure, used by VIRTQ operations. */ 271 struct mlx5_devx_virtq_attr { 272 uint16_t hw_available_index; 273 uint16_t hw_used_index; 274 uint16_t q_size; 275 uint32_t pd:24; 276 uint32_t virtio_version_1_0:1; 277 uint32_t tso_ipv4:1; 278 uint32_t tso_ipv6:1; 279 uint32_t tx_csum:1; 280 uint32_t rx_csum:1; 281 uint32_t event_mode:3; 282 uint32_t state:4; 283 uint32_t dirty_bitmap_dump_enable:1; 284 uint32_t dirty_bitmap_mkey; 285 uint32_t dirty_bitmap_size; 286 uint32_t mkey; 287 uint32_t qp_id; 288 uint32_t queue_index; 289 uint32_t tis_id; 290 uint32_t counters_obj_id; 291 uint64_t dirty_bitmap_addr; 292 uint64_t type; 293 uint64_t desc_addr; 294 uint64_t used_addr; 295 uint64_t available_addr; 296 struct { 297 uint32_t id; 298 uint32_t size; 299 uint64_t offset; 300 } umems[3]; 301 }; 302 303 304 struct mlx5_devx_qp_attr { 305 uint32_t pd:24; 306 uint32_t uar_index:24; 307 uint32_t cqn:24; 308 uint32_t log_page_size:5; 309 uint32_t rq_size:17; /* Must be power of 2. */ 310 uint32_t log_rq_stride:3; 311 uint32_t sq_size:17; /* Must be power of 2. */ 312 uint32_t dbr_umem_valid:1; 313 uint32_t dbr_umem_id; 314 uint64_t dbr_address; 315 uint32_t wq_umem_id; 316 uint64_t wq_umem_offset; 317 }; 318 319 struct mlx5_devx_virtio_q_couners_attr { 320 uint64_t received_desc; 321 uint64_t completed_desc; 322 uint32_t error_cqes; 323 uint32_t bad_desc_errors; 324 uint32_t exceed_max_chain; 325 uint32_t invalid_buffer; 326 }; 327 328 /* 329 * graph flow match sample attributes structure, 330 * used by flex parser operations. 331 */ 332 struct mlx5_devx_match_sample_attr { 333 uint32_t flow_match_sample_en:1; 334 uint32_t flow_match_sample_field_offset:16; 335 uint32_t flow_match_sample_offset_mode:4; 336 uint32_t flow_match_sample_field_offset_mask; 337 uint32_t flow_match_sample_field_offset_shift:4; 338 uint32_t flow_match_sample_field_base_offset:8; 339 uint32_t flow_match_sample_tunnel_mode:3; 340 uint32_t flow_match_sample_field_id; 341 }; 342 343 /* graph node arc attributes structure, used by flex parser operations. */ 344 struct mlx5_devx_graph_arc_attr { 345 uint32_t compare_condition_value:16; 346 uint32_t start_inner_tunnel:1; 347 uint32_t arc_parse_graph_node:8; 348 uint32_t parse_graph_node_handle; 349 }; 350 351 /* Maximal number of samples per graph node. */ 352 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 353 354 /* Maximal number of input/output arcs per graph node. */ 355 #define MLX5_GRAPH_NODE_ARC_NUM 8 356 357 /* parse graph node attributes structure, used by flex parser operations. */ 358 struct mlx5_devx_graph_node_attr { 359 uint32_t modify_field_select; 360 uint32_t header_length_mode:4; 361 uint32_t header_length_base_value:16; 362 uint32_t header_length_field_shift:4; 363 uint32_t header_length_field_offset:16; 364 uint32_t header_length_field_mask; 365 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 366 uint32_t next_header_field_offset:16; 367 uint32_t next_header_field_size:5; 368 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 369 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 370 }; 371 372 /* mlx5_devx_cmds.c */ 373 374 __rte_internal 375 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 376 uint32_t bulk_sz); 377 __rte_internal 378 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 379 __rte_internal 380 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 381 int clear, uint32_t n_counters, 382 uint64_t *pkts, uint64_t *bytes, 383 uint32_t mkey, void *addr, 384 void *cmd_comp, 385 uint64_t async_id); 386 __rte_internal 387 int mlx5_devx_cmd_query_hca_attr(void *ctx, 388 struct mlx5_hca_attr *attr); 389 __rte_internal 390 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 391 struct mlx5_devx_mkey_attr *attr); 392 __rte_internal 393 int mlx5_devx_get_out_command_status(void *out); 394 __rte_internal 395 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 396 uint32_t *tis_td); 397 __rte_internal 398 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 399 struct mlx5_devx_create_rq_attr *rq_attr, 400 int socket); 401 __rte_internal 402 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 403 struct mlx5_devx_modify_rq_attr *rq_attr); 404 __rte_internal 405 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 406 struct mlx5_devx_tir_attr *tir_attr); 407 __rte_internal 408 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 409 struct mlx5_devx_rqt_attr *rqt_attr); 410 __rte_internal 411 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 412 struct mlx5_devx_create_sq_attr *sq_attr); 413 __rte_internal 414 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 415 struct mlx5_devx_modify_sq_attr *sq_attr); 416 __rte_internal 417 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 418 struct mlx5_devx_tis_attr *tis_attr); 419 __rte_internal 420 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 421 __rte_internal 422 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 423 FILE *file); 424 __rte_internal 425 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 426 struct mlx5_devx_cq_attr *attr); 427 __rte_internal 428 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 429 struct mlx5_devx_virtq_attr *attr); 430 __rte_internal 431 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 432 struct mlx5_devx_virtq_attr *attr); 433 __rte_internal 434 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 435 struct mlx5_devx_virtq_attr *attr); 436 __rte_internal 437 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 438 struct mlx5_devx_qp_attr *attr); 439 __rte_internal 440 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 441 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 442 __rte_internal 443 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 444 struct mlx5_devx_rqt_attr *rqt_attr); 445 __rte_internal 446 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 447 struct mlx5_devx_modify_tir_attr *tir_attr); 448 __rte_internal 449 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 450 uint32_t ids[], uint32_t num); 451 452 __rte_internal 453 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 454 struct mlx5_devx_graph_node_attr *data); 455 456 __rte_internal 457 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 458 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 459 /** 460 * Create virtio queue counters object DevX API. 461 * 462 * @param[in] ctx 463 * Device context. 464 465 * @return 466 * The DevX object created, NULL otherwise and rte_errno is set. 467 */ 468 __rte_internal 469 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 470 471 /** 472 * Query virtio queue counters object using DevX API. 473 * 474 * @param[in] couners_obj 475 * Pointer to virtq object structure. 476 * @param [in/out] attr 477 * Pointer to virtio queue counters attributes structure. 478 * 479 * @return 480 * 0 on success, a negative errno value otherwise and rte_errno is set. 481 */ 482 __rte_internal 483 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 484 struct mlx5_devx_virtio_q_couners_attr *attr); 485 486 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 487