1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 static void * 17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 18 int *err, uint32_t flags) 19 { 20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 22 int status, syndrome, rc; 23 24 if (err) 25 *err = 0; 26 memset(in, 0, size_in); 27 memset(out, 0, size_out); 28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 29 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 31 if (rc) { 32 DRV_LOG(ERR, 33 "Failed to query devx HCA capabilities func %#02x", 34 flags >> 1); 35 if (err) 36 *err = rc > 0 ? -rc : rc; 37 return NULL; 38 } 39 status = MLX5_GET(query_hca_cap_out, out, status); 40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 41 if (status) { 42 DRV_LOG(ERR, 43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x", 44 flags >> 1, status, syndrome); 45 if (err) 46 *err = -1; 47 return NULL; 48 } 49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 50 } 51 52 /** 53 * Perform read access to the registers. Reads data from register 54 * and writes ones to the specified buffer. 55 * 56 * @param[in] ctx 57 * Context returned from mlx5 open_device() glue function. 58 * @param[in] reg_id 59 * Register identifier according to the PRM. 60 * @param[in] arg 61 * Register access auxiliary parameter according to the PRM. 62 * @param[out] data 63 * Pointer to the buffer to store read data. 64 * @param[in] dw_cnt 65 * Buffer size in double words. 66 * 67 * @return 68 * 0 on success, a negative value otherwise. 69 */ 70 int 71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 72 uint32_t *data, uint32_t dw_cnt) 73 { 74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 77 int status, rc; 78 79 MLX5_ASSERT(data && dw_cnt); 80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 82 DRV_LOG(ERR, "Not enough buffer for register read data"); 83 return -1; 84 } 85 MLX5_SET(access_register_in, in, opcode, 86 MLX5_CMD_OP_ACCESS_REGISTER_USER); 87 MLX5_SET(access_register_in, in, op_mod, 88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 89 MLX5_SET(access_register_in, in, register_id, reg_id); 90 MLX5_SET(access_register_in, in, argument, arg); 91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 92 MLX5_ST_SZ_BYTES(access_register_out) + 93 sizeof(uint32_t) * dw_cnt); 94 if (rc) 95 goto error; 96 status = MLX5_GET(access_register_out, out, status); 97 if (status) { 98 int syndrome = MLX5_GET(access_register_out, out, syndrome); 99 100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 101 "status %x, syndrome = %x", 102 reg_id, status, syndrome); 103 return -1; 104 } 105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 106 dw_cnt * sizeof(uint32_t)); 107 return 0; 108 error: 109 rc = (rc > 0) ? -rc : rc; 110 return rc; 111 } 112 113 /** 114 * Perform write access to the registers. 115 * 116 * @param[in] ctx 117 * Context returned from mlx5 open_device() glue function. 118 * @param[in] reg_id 119 * Register identifier according to the PRM. 120 * @param[in] arg 121 * Register access auxiliary parameter according to the PRM. 122 * @param[out] data 123 * Pointer to the buffer containing data to write. 124 * @param[in] dw_cnt 125 * Buffer size in double words (32bit units). 126 * 127 * @return 128 * 0 on success, a negative value otherwise. 129 */ 130 int 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 132 uint32_t *data, uint32_t dw_cnt) 133 { 134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 137 int status, rc; 138 void *ptr; 139 140 MLX5_ASSERT(data && dw_cnt); 141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 143 DRV_LOG(ERR, "Data to write exceeds max size"); 144 return -1; 145 } 146 MLX5_SET(access_register_in, in, opcode, 147 MLX5_CMD_OP_ACCESS_REGISTER_USER); 148 MLX5_SET(access_register_in, in, op_mod, 149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 150 MLX5_SET(access_register_in, in, register_id, reg_id); 151 MLX5_SET(access_register_in, in, argument, arg); 152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 155 156 rc = mlx5_glue->devx_general_cmd(ctx, in, 157 MLX5_ST_SZ_BYTES(access_register_in) + 158 dw_cnt * sizeof(uint32_t), 159 out, sizeof(out)); 160 if (rc) 161 goto error; 162 status = MLX5_GET(access_register_out, out, status); 163 if (status) { 164 int syndrome = MLX5_GET(access_register_out, out, syndrome); 165 166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 167 "status %x, syndrome = %x", 168 reg_id, status, syndrome); 169 return -1; 170 } 171 return 0; 172 error: 173 rc = (rc > 0) ? -rc : rc; 174 return rc; 175 } 176 177 /** 178 * Allocate flow counters via devx interface. 179 * 180 * @param[in] ctx 181 * Context returned from mlx5 open_device() glue function. 182 * @param dcs 183 * Pointer to counters properties structure to be filled by the routine. 184 * @param bulk_n_128 185 * Bulk counter numbers in 128 counters units. 186 * 187 * @return 188 * Pointer to counter object on success, a negative value otherwise and 189 * rte_errno is set. 190 */ 191 struct mlx5_devx_obj * 192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 193 { 194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 195 0, SOCKET_ID_ANY); 196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 198 199 if (!dcs) { 200 rte_errno = ENOMEM; 201 return NULL; 202 } 203 MLX5_SET(alloc_flow_counter_in, in, opcode, 204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 207 sizeof(in), out, sizeof(out)); 208 if (!dcs->obj) { 209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 210 rte_errno = errno; 211 mlx5_free(dcs); 212 return NULL; 213 } 214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 215 return dcs; 216 } 217 218 /** 219 * Query flow counters values. 220 * 221 * @param[in] dcs 222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 223 * @param[in] clear 224 * Whether hardware should clear the counters after the query or not. 225 * @param[in] n_counters 226 * 0 in case of 1 counter to read, otherwise the counter number to read. 227 * @param pkts 228 * The number of packets that matched the flow. 229 * @param bytes 230 * The number of bytes that matched the flow. 231 * @param mkey 232 * The mkey key for batch query. 233 * @param addr 234 * The address in the mkey range for batch query. 235 * @param cmd_comp 236 * The completion object for asynchronous batch query. 237 * @param async_id 238 * The ID to be returned in the asynchronous batch query response. 239 * 240 * @return 241 * 0 on success, a negative value otherwise. 242 */ 243 int 244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 245 int clear, uint32_t n_counters, 246 uint64_t *pkts, uint64_t *bytes, 247 uint32_t mkey, void *addr, 248 void *cmd_comp, 249 uint64_t async_id) 250 { 251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 252 MLX5_ST_SZ_BYTES(traffic_counter); 253 uint32_t out[out_len]; 254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 255 void *stats; 256 int rc; 257 258 MLX5_SET(query_flow_counter_in, in, opcode, 259 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 260 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 262 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 263 264 if (n_counters) { 265 MLX5_SET(query_flow_counter_in, in, num_of_counters, 266 n_counters); 267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 268 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 269 MLX5_SET64(query_flow_counter_in, in, address, 270 (uint64_t)(uintptr_t)addr); 271 } 272 if (!cmd_comp) 273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 274 out_len); 275 else 276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 277 out_len, async_id, 278 cmd_comp); 279 if (rc) { 280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 281 rte_errno = rc; 282 return -rc; 283 } 284 if (!n_counters) { 285 stats = MLX5_ADDR_OF(query_flow_counter_out, 286 out, flow_statistics); 287 *pkts = MLX5_GET64(traffic_counter, stats, packets); 288 *bytes = MLX5_GET64(traffic_counter, stats, octets); 289 } 290 return 0; 291 } 292 293 /** 294 * Create a new mkey. 295 * 296 * @param[in] ctx 297 * Context returned from mlx5 open_device() glue function. 298 * @param[in] attr 299 * Attributes of the requested mkey. 300 * 301 * @return 302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 303 * is set. 304 */ 305 struct mlx5_devx_obj * 306 mlx5_devx_cmd_mkey_create(void *ctx, 307 struct mlx5_devx_mkey_attr *attr) 308 { 309 struct mlx5_klm *klm_array = attr->klm_array; 310 int klm_num = attr->klm_num; 311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 313 uint32_t in[in_size_dw]; 314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 315 void *mkc; 316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 317 0, SOCKET_ID_ANY); 318 size_t pgsize; 319 uint32_t translation_size; 320 321 if (!mkey) { 322 rte_errno = ENOMEM; 323 return NULL; 324 } 325 memset(in, 0, in_size_dw * 4); 326 pgsize = rte_mem_page_size(); 327 if (pgsize == (size_t)-1) { 328 mlx5_free(mkey); 329 DRV_LOG(ERR, "Failed to get page size"); 330 rte_errno = ENOMEM; 331 return NULL; 332 } 333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 335 if (klm_num > 0) { 336 int i; 337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 338 klm_pas_mtt); 339 translation_size = RTE_ALIGN(klm_num, 4); 340 for (i = 0; i < klm_num; i++) { 341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 343 MLX5_SET64(klm, klm, address, klm_array[i].address); 344 klm += MLX5_ST_SZ_BYTES(klm); 345 } 346 for (; i < (int)translation_size; i++) { 347 MLX5_SET(klm, klm, mkey, 0x0); 348 MLX5_SET64(klm, klm, address, 0x0); 349 klm += MLX5_ST_SZ_BYTES(klm); 350 } 351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 352 MLX5_MKC_ACCESS_MODE_KLM_FBS : 353 MLX5_MKC_ACCESS_MODE_KLM); 354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 355 } else { 356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 359 } 360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 361 translation_size); 362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 364 MLX5_SET(mkc, mkc, lw, 0x1); 365 MLX5_SET(mkc, mkc, lr, 0x1); 366 if (attr->set_remote_rw) { 367 MLX5_SET(mkc, mkc, rw, 0x1); 368 MLX5_SET(mkc, mkc, rr, 0x1); 369 } 370 MLX5_SET(mkc, mkc, qpn, 0xffffff); 371 MLX5_SET(mkc, mkc, pd, attr->pd); 372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 375 MLX5_SET(mkc, mkc, relaxed_ordering_write, 376 attr->relaxed_ordering_write); 377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 378 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 379 MLX5_SET64(mkc, mkc, len, attr->size); 380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 381 if (attr->crypto_en) { 382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 383 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 384 } 385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 386 sizeof(out)); 387 if (!mkey->obj) { 388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 389 klm_num ? "an in" : "a ", errno); 390 rte_errno = errno; 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int status, syndrome, rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc) 481 goto error; 482 status = MLX5_GET(query_nic_vport_context_out, out, status); 483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 484 if (status) { 485 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 486 "status %x, syndrome = %x", status, syndrome); 487 return -1; 488 } 489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 490 nic_vport_context); 491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 492 min_wqe_inline_mode); 493 return 0; 494 error: 495 rc = (rc > 0) ? -rc : rc; 496 return rc; 497 } 498 499 /** 500 * Query NIC vDPA attributes. 501 * 502 * @param[in] ctx 503 * Context returned from mlx5 open_device() glue function. 504 * @param[out] vdpa_attr 505 * vDPA Attributes structure to fill. 506 */ 507 static void 508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 509 struct mlx5_hca_vdpa_attr *vdpa_attr) 510 { 511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 513 void *hcattr; 514 515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 517 MLX5_HCA_CAP_OPMOD_GET_CUR); 518 if (!hcattr) { 519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 520 vdpa_attr->valid = 0; 521 } else { 522 vdpa_attr->valid = 1; 523 vdpa_attr->desc_tunnel_offload_type = 524 MLX5_GET(virtio_emulation_cap, hcattr, 525 desc_tunnel_offload_type); 526 vdpa_attr->eth_frame_offload_type = 527 MLX5_GET(virtio_emulation_cap, hcattr, 528 eth_frame_offload_type); 529 vdpa_attr->virtio_version_1_0 = 530 MLX5_GET(virtio_emulation_cap, hcattr, 531 virtio_version_1_0); 532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 533 tso_ipv4); 534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 535 tso_ipv6); 536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 537 tx_csum); 538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 539 rx_csum); 540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 541 event_mode); 542 vdpa_attr->virtio_queue_type = 543 MLX5_GET(virtio_emulation_cap, hcattr, 544 virtio_queue_type); 545 vdpa_attr->log_doorbell_stride = 546 MLX5_GET(virtio_emulation_cap, hcattr, 547 log_doorbell_stride); 548 vdpa_attr->log_doorbell_bar_size = 549 MLX5_GET(virtio_emulation_cap, hcattr, 550 log_doorbell_bar_size); 551 vdpa_attr->doorbell_bar_offset = 552 MLX5_GET64(virtio_emulation_cap, hcattr, 553 doorbell_bar_offset); 554 vdpa_attr->max_num_virtio_queues = 555 MLX5_GET(virtio_emulation_cap, hcattr, 556 max_num_virtio_queues); 557 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 558 umem_1_buffer_param_a); 559 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 560 umem_1_buffer_param_b); 561 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 562 umem_2_buffer_param_a); 563 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 564 umem_2_buffer_param_b); 565 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 566 umem_3_buffer_param_a); 567 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 568 umem_3_buffer_param_b); 569 } 570 } 571 572 int 573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 574 uint32_t ids[], uint32_t num) 575 { 576 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 577 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 578 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 579 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 580 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 581 int ret; 582 uint32_t idx = 0; 583 uint32_t i; 584 585 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 588 return -rte_errno; 589 } 590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 591 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 593 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 595 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 596 out, sizeof(out)); 597 if (ret) { 598 rte_errno = ret; 599 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 600 (void *)flex_obj); 601 return -rte_errno; 602 } 603 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 604 void *s_off = (void *)((char *)sample + i * 605 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 606 uint32_t en; 607 608 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 609 flow_match_sample_en); 610 if (!en) 611 continue; 612 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 613 flow_match_sample_field_id); 614 } 615 if (num != idx) { 616 rte_errno = EINVAL; 617 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 618 return -rte_errno; 619 } 620 return ret; 621 } 622 623 struct mlx5_devx_obj * 624 mlx5_devx_cmd_create_flex_parser(void *ctx, 625 struct mlx5_devx_graph_node_attr *data) 626 { 627 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 628 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 629 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 630 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 631 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 632 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 633 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 634 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 635 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 636 uint32_t i; 637 638 if (!parse_flex_obj) { 639 DRV_LOG(ERR, "Failed to allocate flex parser data."); 640 rte_errno = ENOMEM; 641 return NULL; 642 } 643 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 644 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 645 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 646 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 647 MLX5_SET(parse_graph_flex, flex, header_length_mode, 648 data->header_length_mode); 649 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 650 data->modify_field_select); 651 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 652 data->header_length_base_value); 653 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 654 data->header_length_field_offset); 655 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 656 data->header_length_field_shift); 657 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 658 data->next_header_field_offset); 659 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 660 data->next_header_field_size); 661 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 662 data->header_length_field_mask); 663 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 664 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 665 void *s_off = (void *)((char *)sample + i * 666 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 667 668 if (!s->flow_match_sample_en) 669 continue; 670 MLX5_SET(parse_graph_flow_match_sample, s_off, 671 flow_match_sample_en, !!s->flow_match_sample_en); 672 MLX5_SET(parse_graph_flow_match_sample, s_off, 673 flow_match_sample_field_offset, 674 s->flow_match_sample_field_offset); 675 MLX5_SET(parse_graph_flow_match_sample, s_off, 676 flow_match_sample_offset_mode, 677 s->flow_match_sample_offset_mode); 678 MLX5_SET(parse_graph_flow_match_sample, s_off, 679 flow_match_sample_field_offset_mask, 680 s->flow_match_sample_field_offset_mask); 681 MLX5_SET(parse_graph_flow_match_sample, s_off, 682 flow_match_sample_field_offset_shift, 683 s->flow_match_sample_field_offset_shift); 684 MLX5_SET(parse_graph_flow_match_sample, s_off, 685 flow_match_sample_field_base_offset, 686 s->flow_match_sample_field_base_offset); 687 MLX5_SET(parse_graph_flow_match_sample, s_off, 688 flow_match_sample_tunnel_mode, 689 s->flow_match_sample_tunnel_mode); 690 } 691 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 692 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 693 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 694 void *in_off = (void *)((char *)in_arc + i * 695 MLX5_ST_SZ_BYTES(parse_graph_arc)); 696 void *out_off = (void *)((char *)out_arc + i * 697 MLX5_ST_SZ_BYTES(parse_graph_arc)); 698 699 if (ia->arc_parse_graph_node != 0) { 700 MLX5_SET(parse_graph_arc, in_off, 701 compare_condition_value, 702 ia->compare_condition_value); 703 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 704 ia->start_inner_tunnel); 705 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 706 ia->arc_parse_graph_node); 707 MLX5_SET(parse_graph_arc, in_off, 708 parse_graph_node_handle, 709 ia->parse_graph_node_handle); 710 } 711 if (oa->arc_parse_graph_node != 0) { 712 MLX5_SET(parse_graph_arc, out_off, 713 compare_condition_value, 714 oa->compare_condition_value); 715 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 716 oa->start_inner_tunnel); 717 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 718 oa->arc_parse_graph_node); 719 MLX5_SET(parse_graph_arc, out_off, 720 parse_graph_node_handle, 721 oa->parse_graph_node_handle); 722 } 723 } 724 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 725 out, sizeof(out)); 726 if (!parse_flex_obj->obj) { 727 rte_errno = errno; 728 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 729 "by using DevX."); 730 mlx5_free(parse_flex_obj); 731 return NULL; 732 } 733 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 734 return parse_flex_obj; 735 } 736 737 static int 738 mlx5_devx_cmd_query_hca_parse_graph_node_cap 739 (void *ctx, struct mlx5_hca_flex_attr *attr) 740 { 741 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 742 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 743 void *hcattr; 744 int rc; 745 746 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 747 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 748 MLX5_HCA_CAP_OPMOD_GET_CUR); 749 if (!hcattr) 750 return rc; 751 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 752 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 753 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 754 header_length_mode); 755 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 756 sample_offset_mode); 757 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 758 max_num_arc_in); 759 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 760 max_num_arc_out); 761 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 762 max_num_sample); 763 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 764 sample_id_in_out); 765 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 766 max_base_header_length); 767 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 768 max_sample_base_offset); 769 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 770 max_next_header_offset); 771 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 772 header_length_mask_width); 773 /* Get the max supported samples from HCA CAP 2 */ 774 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 775 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 776 MLX5_HCA_CAP_OPMOD_GET_CUR); 777 if (!hcattr) 778 return rc; 779 attr->max_num_prog_sample = 780 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 781 return 0; 782 } 783 784 static int 785 mlx5_devx_query_pkt_integrity_match(void *hcattr) 786 { 787 return MLX5_GET(flow_table_nic_cap, hcattr, 788 ft_field_support_2_nic_receive.inner_l3_ok) && 789 MLX5_GET(flow_table_nic_cap, hcattr, 790 ft_field_support_2_nic_receive.inner_l4_ok) && 791 MLX5_GET(flow_table_nic_cap, hcattr, 792 ft_field_support_2_nic_receive.outer_l3_ok) && 793 MLX5_GET(flow_table_nic_cap, hcattr, 794 ft_field_support_2_nic_receive.outer_l4_ok) && 795 MLX5_GET(flow_table_nic_cap, hcattr, 796 ft_field_support_2_nic_receive 797 .inner_ipv4_checksum_ok) && 798 MLX5_GET(flow_table_nic_cap, hcattr, 799 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 800 MLX5_GET(flow_table_nic_cap, hcattr, 801 ft_field_support_2_nic_receive 802 .outer_ipv4_checksum_ok) && 803 MLX5_GET(flow_table_nic_cap, hcattr, 804 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 805 } 806 807 /** 808 * Query HCA attributes. 809 * Using those attributes we can check on run time if the device 810 * is having the required capabilities. 811 * 812 * @param[in] ctx 813 * Context returned from mlx5 open_device() glue function. 814 * @param[out] attr 815 * Attributes device values. 816 * 817 * @return 818 * 0 on success, a negative value otherwise. 819 */ 820 int 821 mlx5_devx_cmd_query_hca_attr(void *ctx, 822 struct mlx5_hca_attr *attr) 823 { 824 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 825 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 826 uint64_t general_obj_types_supported = 0; 827 void *hcattr; 828 int rc, i; 829 830 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 831 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 832 MLX5_HCA_CAP_OPMOD_GET_CUR); 833 if (!hcattr) 834 return rc; 835 attr->flow_counter_bulk_alloc_bitmap = 836 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 837 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 838 flow_counters_dump); 839 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 840 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 841 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 842 log_max_rqt_size); 843 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 844 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 845 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 846 log_max_hairpin_queues); 847 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 848 log_max_hairpin_wq_data_sz); 849 attr->log_max_hairpin_num_packets = MLX5_GET 850 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 851 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 852 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 853 relaxed_ordering_write); 854 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 855 relaxed_ordering_read); 856 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 857 access_register_user); 858 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 859 eth_net_offloads); 860 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 861 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 862 flex_parser_protocols); 863 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 864 max_geneve_tlv_options); 865 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 866 max_geneve_tlv_option_data_len); 867 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 868 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 869 general_obj_types) & 870 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 871 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 872 general_obj_types) & 873 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 874 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 875 general_obj_types) & 876 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 877 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 878 general_obj_types) & 879 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 880 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 881 wqe_index_ignore_cap); 882 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 883 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 884 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 885 log_max_static_sq_wq); 886 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 887 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 888 device_frequency_khz); 889 attr->scatter_fcs_w_decap_disable = 890 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 891 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 892 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 893 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 894 attr->steering_format_version = 895 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 896 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 897 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 898 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 899 regexp_num_of_engines); 900 /* Read the general_obj_types bitmap and extract the relevant bits. */ 901 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 902 general_obj_types); 903 attr->vdpa.valid = !!(general_obj_types_supported & 904 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 905 attr->vdpa.queue_counters_valid = 906 !!(general_obj_types_supported & 907 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 908 attr->parse_graph_flex_node = 909 !!(general_obj_types_supported & 910 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 911 attr->flow_hit_aso = !!(general_obj_types_supported & 912 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 913 attr->geneve_tlv_opt = !!(general_obj_types_supported & 914 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 915 attr->dek = !!(general_obj_types_supported & 916 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 917 attr->import_kek = !!(general_obj_types_supported & 918 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 919 attr->credential = !!(general_obj_types_supported & 920 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 921 attr->crypto_login = !!(general_obj_types_supported & 922 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 923 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 924 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 925 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 926 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 927 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 928 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 929 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 930 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 931 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 932 attr->reg_c_preserve = 933 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 934 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 935 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 936 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 937 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 938 compress_mmo_sq); 939 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 940 decompress_mmo_sq); 941 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 942 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 943 compress_mmo_qp); 944 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 945 decompress_mmo_qp); 946 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 947 compress_min_block_size); 948 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 949 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 950 log_compress_mmo_size); 951 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 952 log_decompress_mmo_size); 953 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 954 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 955 mini_cqe_resp_flow_tag); 956 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 957 mini_cqe_resp_l3_l4_tag); 958 attr->umr_indirect_mkey_disabled = 959 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 960 attr->umr_modify_entity_size_disabled = 961 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 962 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 963 if (attr->crypto) 964 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 965 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 966 general_obj_types) & 967 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 968 if (attr->qos.sup) { 969 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 970 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 971 MLX5_HCA_CAP_OPMOD_GET_CUR); 972 if (!hcattr) { 973 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 974 return rc; 975 } 976 attr->qos.flow_meter_old = 977 MLX5_GET(qos_cap, hcattr, flow_meter_old); 978 attr->qos.log_max_flow_meter = 979 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 980 attr->qos.flow_meter_reg_c_ids = 981 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 982 attr->qos.flow_meter = 983 MLX5_GET(qos_cap, hcattr, flow_meter); 984 attr->qos.packet_pacing = 985 MLX5_GET(qos_cap, hcattr, packet_pacing); 986 attr->qos.wqe_rate_pp = 987 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 988 if (attr->qos.flow_meter_aso_sup) { 989 attr->qos.log_meter_aso_granularity = 990 MLX5_GET(qos_cap, hcattr, 991 log_meter_aso_granularity); 992 attr->qos.log_meter_aso_max_alloc = 993 MLX5_GET(qos_cap, hcattr, 994 log_meter_aso_max_alloc); 995 attr->qos.log_max_num_meter_aso = 996 MLX5_GET(qos_cap, hcattr, 997 log_max_num_meter_aso); 998 } 999 } 1000 /* 1001 * Flex item support needs max_num_prog_sample_field 1002 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1003 */ 1004 if (attr->parse_graph_flex_node) { 1005 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1006 (ctx, &attr->flex); 1007 if (rc) 1008 return -1; 1009 } 1010 if (attr->vdpa.valid) 1011 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1012 if (!attr->eth_net_offloads) 1013 return 0; 1014 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1015 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1016 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1017 MLX5_HCA_CAP_OPMOD_GET_CUR); 1018 if (!hcattr) { 1019 attr->log_max_ft_sampler_num = 0; 1020 return rc; 1021 } 1022 attr->log_max_ft_sampler_num = MLX5_GET 1023 (flow_table_nic_cap, hcattr, 1024 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1025 attr->flow.tunnel_header_0_1 = MLX5_GET 1026 (flow_table_nic_cap, hcattr, 1027 ft_field_support_2_nic_receive.tunnel_header_0_1); 1028 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1029 attr->inner_ipv4_ihl = MLX5_GET 1030 (flow_table_nic_cap, hcattr, 1031 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1032 attr->outer_ipv4_ihl = MLX5_GET 1033 (flow_table_nic_cap, hcattr, 1034 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1035 /* Query HCA offloads for Ethernet protocol. */ 1036 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1037 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1038 MLX5_HCA_CAP_OPMOD_GET_CUR); 1039 if (!hcattr) { 1040 attr->eth_net_offloads = 0; 1041 return rc; 1042 } 1043 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1044 hcattr, wqe_vlan_insert); 1045 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1046 hcattr, csum_cap); 1047 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1048 hcattr, vlan_cap); 1049 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1050 lro_cap); 1051 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1052 hcattr, max_lso_cap); 1053 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1054 hcattr, scatter_fcs); 1055 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1056 hcattr, tunnel_lro_gre); 1057 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1058 hcattr, tunnel_lro_vxlan); 1059 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1060 hcattr, swp); 1061 attr->tunnel_stateless_gre = 1062 MLX5_GET(per_protocol_networking_offload_caps, 1063 hcattr, tunnel_stateless_gre); 1064 attr->tunnel_stateless_vxlan = 1065 MLX5_GET(per_protocol_networking_offload_caps, 1066 hcattr, tunnel_stateless_vxlan); 1067 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1068 hcattr, swp_csum); 1069 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1070 hcattr, swp_lso); 1071 attr->lro_max_msg_sz_mode = MLX5_GET 1072 (per_protocol_networking_offload_caps, 1073 hcattr, lro_max_msg_sz_mode); 1074 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1075 attr->lro_timer_supported_periods[i] = 1076 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1077 lro_timer_supported_periods[i]); 1078 } 1079 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1080 hcattr, lro_min_mss_size); 1081 attr->tunnel_stateless_geneve_rx = 1082 MLX5_GET(per_protocol_networking_offload_caps, 1083 hcattr, tunnel_stateless_geneve_rx); 1084 attr->geneve_max_opt_len = 1085 MLX5_GET(per_protocol_networking_offload_caps, 1086 hcattr, max_geneve_opt_len); 1087 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1088 hcattr, wqe_inline_mode); 1089 attr->tunnel_stateless_gtp = MLX5_GET 1090 (per_protocol_networking_offload_caps, 1091 hcattr, tunnel_stateless_gtp); 1092 attr->rss_ind_tbl_cap = MLX5_GET 1093 (per_protocol_networking_offload_caps, 1094 hcattr, rss_ind_tbl_cap); 1095 /* Query HCA attribute for ROCE. */ 1096 if (attr->roce) { 1097 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1098 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1099 MLX5_HCA_CAP_OPMOD_GET_CUR); 1100 if (!hcattr) { 1101 DRV_LOG(DEBUG, 1102 "Failed to query devx HCA ROCE capabilities"); 1103 return rc; 1104 } 1105 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1106 } 1107 if (attr->eth_virt && 1108 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1109 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1110 if (rc) { 1111 attr->eth_virt = 0; 1112 goto error; 1113 } 1114 } 1115 return 0; 1116 error: 1117 rc = (rc > 0) ? -rc : rc; 1118 return rc; 1119 } 1120 1121 /** 1122 * Query TIS transport domain from QP verbs object using DevX API. 1123 * 1124 * @param[in] qp 1125 * Pointer to verbs QP returned by ibv_create_qp . 1126 * @param[in] tis_num 1127 * TIS number of TIS to query. 1128 * @param[out] tis_td 1129 * Pointer to TIS transport domain variable, to be set by the routine. 1130 * 1131 * @return 1132 * 0 on success, a negative value otherwise. 1133 */ 1134 int 1135 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1136 uint32_t *tis_td) 1137 { 1138 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1139 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1140 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1141 int rc; 1142 void *tis_ctx; 1143 1144 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1145 MLX5_SET(query_tis_in, in, tisn, tis_num); 1146 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1147 if (rc) { 1148 DRV_LOG(ERR, "Failed to query QP using DevX"); 1149 return -rc; 1150 }; 1151 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1152 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1153 return 0; 1154 #else 1155 (void)qp; 1156 (void)tis_num; 1157 (void)tis_td; 1158 return -ENOTSUP; 1159 #endif 1160 } 1161 1162 /** 1163 * Fill WQ data for DevX API command. 1164 * Utility function for use when creating DevX objects containing a WQ. 1165 * 1166 * @param[in] wq_ctx 1167 * Pointer to WQ context to fill with data. 1168 * @param [in] wq_attr 1169 * Pointer to WQ attributes structure to fill in WQ context. 1170 */ 1171 static void 1172 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1173 { 1174 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1175 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1176 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1177 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1178 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1179 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1180 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1181 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1182 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1183 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1184 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1185 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1186 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1187 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1188 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1189 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1190 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1191 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1192 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1193 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1194 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1195 wq_attr->log_hairpin_num_packets); 1196 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1197 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1198 wq_attr->single_wqe_log_num_of_strides); 1199 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1200 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1201 wq_attr->single_stride_log_num_of_bytes); 1202 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1203 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1204 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1205 } 1206 1207 /** 1208 * Create RQ using DevX API. 1209 * 1210 * @param[in] ctx 1211 * Context returned from mlx5 open_device() glue function. 1212 * @param [in] rq_attr 1213 * Pointer to create RQ attributes structure. 1214 * @param [in] socket 1215 * CPU socket ID for allocations. 1216 * 1217 * @return 1218 * The DevX object created, NULL otherwise and rte_errno is set. 1219 */ 1220 struct mlx5_devx_obj * 1221 mlx5_devx_cmd_create_rq(void *ctx, 1222 struct mlx5_devx_create_rq_attr *rq_attr, 1223 int socket) 1224 { 1225 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1226 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1227 void *rq_ctx, *wq_ctx; 1228 struct mlx5_devx_wq_attr *wq_attr; 1229 struct mlx5_devx_obj *rq = NULL; 1230 1231 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1232 if (!rq) { 1233 DRV_LOG(ERR, "Failed to allocate RQ data"); 1234 rte_errno = ENOMEM; 1235 return NULL; 1236 } 1237 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1238 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1239 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1240 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1241 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1242 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1243 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1244 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1245 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1246 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1247 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1248 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1249 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1250 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1251 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1252 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1253 wq_attr = &rq_attr->wq_attr; 1254 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1255 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1256 out, sizeof(out)); 1257 if (!rq->obj) { 1258 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1259 rte_errno = errno; 1260 mlx5_free(rq); 1261 return NULL; 1262 } 1263 rq->id = MLX5_GET(create_rq_out, out, rqn); 1264 return rq; 1265 } 1266 1267 /** 1268 * Modify RQ using DevX API. 1269 * 1270 * @param[in] rq 1271 * Pointer to RQ object structure. 1272 * @param [in] rq_attr 1273 * Pointer to modify RQ attributes structure. 1274 * 1275 * @return 1276 * 0 on success, a negative errno value otherwise and rte_errno is set. 1277 */ 1278 int 1279 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1280 struct mlx5_devx_modify_rq_attr *rq_attr) 1281 { 1282 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1283 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1284 void *rq_ctx, *wq_ctx; 1285 int ret; 1286 1287 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1288 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1289 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1290 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1291 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1292 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1293 if (rq_attr->modify_bitmask & 1294 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1295 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1296 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1297 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1298 if (rq_attr->modify_bitmask & 1299 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1300 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1301 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1302 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1303 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1304 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1305 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1306 } 1307 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1308 out, sizeof(out)); 1309 if (ret) { 1310 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1311 rte_errno = errno; 1312 return -errno; 1313 } 1314 return ret; 1315 } 1316 1317 /** 1318 * Create RMP using DevX API. 1319 * 1320 * @param[in] ctx 1321 * Context returned from mlx5 open_device() glue function. 1322 * @param [in] rmp_attr 1323 * Pointer to create RMP attributes structure. 1324 * @param [in] socket 1325 * CPU socket ID for allocations. 1326 * 1327 * @return 1328 * The DevX object created, NULL otherwise and rte_errno is set. 1329 */ 1330 struct mlx5_devx_obj * 1331 mlx5_devx_cmd_create_rmp(void *ctx, 1332 struct mlx5_devx_create_rmp_attr *rmp_attr, 1333 int socket) 1334 { 1335 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1336 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1337 void *rmp_ctx, *wq_ctx; 1338 struct mlx5_devx_wq_attr *wq_attr; 1339 struct mlx5_devx_obj *rmp = NULL; 1340 1341 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1342 if (!rmp) { 1343 DRV_LOG(ERR, "Failed to allocate RMP data"); 1344 rte_errno = ENOMEM; 1345 return NULL; 1346 } 1347 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1348 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1349 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1350 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1351 rmp_attr->basic_cyclic_rcv_wqe); 1352 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1353 wq_attr = &rmp_attr->wq_attr; 1354 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1355 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1356 sizeof(out)); 1357 if (!rmp->obj) { 1358 DRV_LOG(ERR, "Failed to create RMP using DevX"); 1359 rte_errno = errno; 1360 mlx5_free(rmp); 1361 return NULL; 1362 } 1363 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1364 return rmp; 1365 } 1366 1367 /* 1368 * Create TIR using DevX API. 1369 * 1370 * @param[in] ctx 1371 * Context returned from mlx5 open_device() glue function. 1372 * @param [in] tir_attr 1373 * Pointer to TIR attributes structure. 1374 * 1375 * @return 1376 * The DevX object created, NULL otherwise and rte_errno is set. 1377 */ 1378 struct mlx5_devx_obj * 1379 mlx5_devx_cmd_create_tir(void *ctx, 1380 struct mlx5_devx_tir_attr *tir_attr) 1381 { 1382 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1383 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1384 void *tir_ctx, *outer, *inner, *rss_key; 1385 struct mlx5_devx_obj *tir = NULL; 1386 1387 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1388 if (!tir) { 1389 DRV_LOG(ERR, "Failed to allocate TIR data"); 1390 rte_errno = ENOMEM; 1391 return NULL; 1392 } 1393 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1394 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1395 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1396 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1397 tir_attr->lro_timeout_period_usecs); 1398 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1399 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1400 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1401 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1402 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1403 tir_attr->tunneled_offload_en); 1404 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1405 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1406 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1407 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1408 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1409 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1410 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1411 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1412 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1413 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1414 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1415 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1416 tir_attr->rx_hash_field_selector_outer.selected_fields); 1417 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1418 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1419 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1420 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1421 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1422 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1423 tir_attr->rx_hash_field_selector_inner.selected_fields); 1424 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1425 out, sizeof(out)); 1426 if (!tir->obj) { 1427 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1428 rte_errno = errno; 1429 mlx5_free(tir); 1430 return NULL; 1431 } 1432 tir->id = MLX5_GET(create_tir_out, out, tirn); 1433 return tir; 1434 } 1435 1436 /** 1437 * Modify TIR using DevX API. 1438 * 1439 * @param[in] tir 1440 * Pointer to TIR DevX object structure. 1441 * @param [in] modify_tir_attr 1442 * Pointer to TIR modification attributes structure. 1443 * 1444 * @return 1445 * 0 on success, a negative errno value otherwise and rte_errno is set. 1446 */ 1447 int 1448 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1449 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1450 { 1451 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1452 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1453 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1454 void *tir_ctx; 1455 int ret; 1456 1457 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1458 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1459 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1460 modify_tir_attr->modify_bitmask); 1461 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1462 if (modify_tir_attr->modify_bitmask & 1463 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1464 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1465 tir_attr->lro_timeout_period_usecs); 1466 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1467 tir_attr->lro_enable_mask); 1468 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1469 tir_attr->lro_max_msg_sz); 1470 } 1471 if (modify_tir_attr->modify_bitmask & 1472 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1473 MLX5_SET(tirc, tir_ctx, indirect_table, 1474 tir_attr->indirect_table); 1475 if (modify_tir_attr->modify_bitmask & 1476 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1477 int i; 1478 void *outer, *inner; 1479 1480 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1481 tir_attr->rx_hash_symmetric); 1482 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1483 for (i = 0; i < 10; i++) { 1484 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1485 tir_attr->rx_hash_toeplitz_key[i]); 1486 } 1487 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1488 rx_hash_field_selector_outer); 1489 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1490 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1491 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1492 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1493 MLX5_SET 1494 (rx_hash_field_select, outer, selected_fields, 1495 tir_attr->rx_hash_field_selector_outer.selected_fields); 1496 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1497 rx_hash_field_selector_inner); 1498 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1499 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1500 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1501 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1502 MLX5_SET 1503 (rx_hash_field_select, inner, selected_fields, 1504 tir_attr->rx_hash_field_selector_inner.selected_fields); 1505 } 1506 if (modify_tir_attr->modify_bitmask & 1507 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1508 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1509 } 1510 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1511 out, sizeof(out)); 1512 if (ret) { 1513 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1514 rte_errno = errno; 1515 return -errno; 1516 } 1517 return ret; 1518 } 1519 1520 /** 1521 * Create RQT using DevX API. 1522 * 1523 * @param[in] ctx 1524 * Context returned from mlx5 open_device() glue function. 1525 * @param [in] rqt_attr 1526 * Pointer to RQT attributes structure. 1527 * 1528 * @return 1529 * The DevX object created, NULL otherwise and rte_errno is set. 1530 */ 1531 struct mlx5_devx_obj * 1532 mlx5_devx_cmd_create_rqt(void *ctx, 1533 struct mlx5_devx_rqt_attr *rqt_attr) 1534 { 1535 uint32_t *in = NULL; 1536 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1537 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1538 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1539 void *rqt_ctx; 1540 struct mlx5_devx_obj *rqt = NULL; 1541 int i; 1542 1543 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1544 if (!in) { 1545 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1546 rte_errno = ENOMEM; 1547 return NULL; 1548 } 1549 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1550 if (!rqt) { 1551 DRV_LOG(ERR, "Failed to allocate RQT data"); 1552 rte_errno = ENOMEM; 1553 mlx5_free(in); 1554 return NULL; 1555 } 1556 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1557 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1558 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1559 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1560 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1561 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1562 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1563 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1564 mlx5_free(in); 1565 if (!rqt->obj) { 1566 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1567 rte_errno = errno; 1568 mlx5_free(rqt); 1569 return NULL; 1570 } 1571 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1572 return rqt; 1573 } 1574 1575 /** 1576 * Modify RQT using DevX API. 1577 * 1578 * @param[in] rqt 1579 * Pointer to RQT DevX object structure. 1580 * @param [in] rqt_attr 1581 * Pointer to RQT attributes structure. 1582 * 1583 * @return 1584 * 0 on success, a negative errno value otherwise and rte_errno is set. 1585 */ 1586 int 1587 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1588 struct mlx5_devx_rqt_attr *rqt_attr) 1589 { 1590 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1591 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1592 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1593 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1594 void *rqt_ctx; 1595 int i; 1596 int ret; 1597 1598 if (!in) { 1599 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1600 rte_errno = ENOMEM; 1601 return -ENOMEM; 1602 } 1603 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1604 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1605 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1606 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1607 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1608 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1609 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1610 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1611 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1612 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1613 mlx5_free(in); 1614 if (ret) { 1615 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1616 rte_errno = errno; 1617 return -rte_errno; 1618 } 1619 return ret; 1620 } 1621 1622 /** 1623 * Create SQ using DevX API. 1624 * 1625 * @param[in] ctx 1626 * Context returned from mlx5 open_device() glue function. 1627 * @param [in] sq_attr 1628 * Pointer to SQ attributes structure. 1629 * @param [in] socket 1630 * CPU socket ID for allocations. 1631 * 1632 * @return 1633 * The DevX object created, NULL otherwise and rte_errno is set. 1634 **/ 1635 struct mlx5_devx_obj * 1636 mlx5_devx_cmd_create_sq(void *ctx, 1637 struct mlx5_devx_create_sq_attr *sq_attr) 1638 { 1639 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1640 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1641 void *sq_ctx; 1642 void *wq_ctx; 1643 struct mlx5_devx_wq_attr *wq_attr; 1644 struct mlx5_devx_obj *sq = NULL; 1645 1646 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1647 if (!sq) { 1648 DRV_LOG(ERR, "Failed to allocate SQ data"); 1649 rte_errno = ENOMEM; 1650 return NULL; 1651 } 1652 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1653 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1654 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1655 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1656 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1657 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1658 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1659 sq_attr->allow_multi_pkt_send_wqe); 1660 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1661 sq_attr->min_wqe_inline_mode); 1662 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1663 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1664 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1665 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1666 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1667 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1668 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1669 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1670 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1671 sq_attr->packet_pacing_rate_limit_index); 1672 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1673 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1674 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1675 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1676 wq_attr = &sq_attr->wq_attr; 1677 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1678 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1679 out, sizeof(out)); 1680 if (!sq->obj) { 1681 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1682 rte_errno = errno; 1683 mlx5_free(sq); 1684 return NULL; 1685 } 1686 sq->id = MLX5_GET(create_sq_out, out, sqn); 1687 return sq; 1688 } 1689 1690 /** 1691 * Modify SQ using DevX API. 1692 * 1693 * @param[in] sq 1694 * Pointer to SQ object structure. 1695 * @param [in] sq_attr 1696 * Pointer to SQ attributes structure. 1697 * 1698 * @return 1699 * 0 on success, a negative errno value otherwise and rte_errno is set. 1700 */ 1701 int 1702 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1703 struct mlx5_devx_modify_sq_attr *sq_attr) 1704 { 1705 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1706 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1707 void *sq_ctx; 1708 int ret; 1709 1710 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1711 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1712 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1713 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1714 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1715 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1716 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1717 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1718 out, sizeof(out)); 1719 if (ret) { 1720 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1721 rte_errno = errno; 1722 return -rte_errno; 1723 } 1724 return ret; 1725 } 1726 1727 /** 1728 * Create TIS using DevX API. 1729 * 1730 * @param[in] ctx 1731 * Context returned from mlx5 open_device() glue function. 1732 * @param [in] tis_attr 1733 * Pointer to TIS attributes structure. 1734 * 1735 * @return 1736 * The DevX object created, NULL otherwise and rte_errno is set. 1737 */ 1738 struct mlx5_devx_obj * 1739 mlx5_devx_cmd_create_tis(void *ctx, 1740 struct mlx5_devx_tis_attr *tis_attr) 1741 { 1742 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1743 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1744 struct mlx5_devx_obj *tis = NULL; 1745 void *tis_ctx; 1746 1747 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1748 if (!tis) { 1749 DRV_LOG(ERR, "Failed to allocate TIS object"); 1750 rte_errno = ENOMEM; 1751 return NULL; 1752 } 1753 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1754 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1755 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1756 tis_attr->strict_lag_tx_port_affinity); 1757 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1758 tis_attr->lag_tx_port_affinity); 1759 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1760 MLX5_SET(tisc, tis_ctx, transport_domain, 1761 tis_attr->transport_domain); 1762 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1763 out, sizeof(out)); 1764 if (!tis->obj) { 1765 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1766 rte_errno = errno; 1767 mlx5_free(tis); 1768 return NULL; 1769 } 1770 tis->id = MLX5_GET(create_tis_out, out, tisn); 1771 return tis; 1772 } 1773 1774 /** 1775 * Create transport domain using DevX API. 1776 * 1777 * @param[in] ctx 1778 * Context returned from mlx5 open_device() glue function. 1779 * @return 1780 * The DevX object created, NULL otherwise and rte_errno is set. 1781 */ 1782 struct mlx5_devx_obj * 1783 mlx5_devx_cmd_create_td(void *ctx) 1784 { 1785 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1786 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1787 struct mlx5_devx_obj *td = NULL; 1788 1789 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1790 if (!td) { 1791 DRV_LOG(ERR, "Failed to allocate TD object"); 1792 rte_errno = ENOMEM; 1793 return NULL; 1794 } 1795 MLX5_SET(alloc_transport_domain_in, in, opcode, 1796 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1797 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1798 out, sizeof(out)); 1799 if (!td->obj) { 1800 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1801 rte_errno = errno; 1802 mlx5_free(td); 1803 return NULL; 1804 } 1805 td->id = MLX5_GET(alloc_transport_domain_out, out, 1806 transport_domain); 1807 return td; 1808 } 1809 1810 /** 1811 * Dump all flows to file. 1812 * 1813 * @param[in] fdb_domain 1814 * FDB domain. 1815 * @param[in] rx_domain 1816 * RX domain. 1817 * @param[in] tx_domain 1818 * TX domain. 1819 * @param[out] file 1820 * Pointer to file stream. 1821 * 1822 * @return 1823 * 0 on success, a nagative value otherwise. 1824 */ 1825 int 1826 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1827 void *rx_domain __rte_unused, 1828 void *tx_domain __rte_unused, FILE *file __rte_unused) 1829 { 1830 int ret = 0; 1831 1832 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1833 if (fdb_domain) { 1834 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1835 if (ret) 1836 return ret; 1837 } 1838 MLX5_ASSERT(rx_domain); 1839 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1840 if (ret) 1841 return ret; 1842 MLX5_ASSERT(tx_domain); 1843 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1844 #else 1845 ret = ENOTSUP; 1846 #endif 1847 return -ret; 1848 } 1849 1850 int 1851 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1852 FILE *file __rte_unused) 1853 { 1854 int ret = 0; 1855 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1856 if (rule_info) 1857 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1858 #else 1859 ret = ENOTSUP; 1860 #endif 1861 return -ret; 1862 } 1863 1864 /* 1865 * Create CQ using DevX API. 1866 * 1867 * @param[in] ctx 1868 * Context returned from mlx5 open_device() glue function. 1869 * @param [in] attr 1870 * Pointer to CQ attributes structure. 1871 * 1872 * @return 1873 * The DevX object created, NULL otherwise and rte_errno is set. 1874 */ 1875 struct mlx5_devx_obj * 1876 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1877 { 1878 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1879 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1880 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1881 sizeof(*cq_obj), 1882 0, SOCKET_ID_ANY); 1883 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1884 1885 if (!cq_obj) { 1886 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1887 rte_errno = ENOMEM; 1888 return NULL; 1889 } 1890 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1891 if (attr->db_umem_valid) { 1892 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1893 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1894 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1895 } else { 1896 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1897 } 1898 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1899 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1900 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1901 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1902 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1903 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1904 MLX5_SET(cqc, cqctx, log_page_size, 1905 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1906 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1907 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1908 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1909 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1910 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1911 attr->mini_cqe_res_format_ext); 1912 if (attr->q_umem_valid) { 1913 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1914 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1915 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1916 attr->q_umem_offset); 1917 } 1918 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1919 sizeof(out)); 1920 if (!cq_obj->obj) { 1921 rte_errno = errno; 1922 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1923 mlx5_free(cq_obj); 1924 return NULL; 1925 } 1926 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1927 return cq_obj; 1928 } 1929 1930 /** 1931 * Create VIRTQ using DevX API. 1932 * 1933 * @param[in] ctx 1934 * Context returned from mlx5 open_device() glue function. 1935 * @param [in] attr 1936 * Pointer to VIRTQ attributes structure. 1937 * 1938 * @return 1939 * The DevX object created, NULL otherwise and rte_errno is set. 1940 */ 1941 struct mlx5_devx_obj * 1942 mlx5_devx_cmd_create_virtq(void *ctx, 1943 struct mlx5_devx_virtq_attr *attr) 1944 { 1945 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1946 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1947 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1948 sizeof(*virtq_obj), 1949 0, SOCKET_ID_ANY); 1950 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1951 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1952 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1953 1954 if (!virtq_obj) { 1955 DRV_LOG(ERR, "Failed to allocate virtq data."); 1956 rte_errno = ENOMEM; 1957 return NULL; 1958 } 1959 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1960 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1961 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1962 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1963 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1964 attr->hw_available_index); 1965 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1966 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1967 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1968 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1969 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1970 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1971 attr->virtio_version_1_0); 1972 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1973 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1974 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1975 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1976 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1977 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1978 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1979 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1980 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1981 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1982 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1983 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1984 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1985 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1986 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1987 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1988 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1989 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1990 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1991 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1992 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1993 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1994 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1995 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1996 sizeof(out)); 1997 if (!virtq_obj->obj) { 1998 rte_errno = errno; 1999 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 2000 mlx5_free(virtq_obj); 2001 return NULL; 2002 } 2003 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2004 return virtq_obj; 2005 } 2006 2007 /** 2008 * Modify VIRTQ using DevX API. 2009 * 2010 * @param[in] virtq_obj 2011 * Pointer to virtq object structure. 2012 * @param [in] attr 2013 * Pointer to modify virtq attributes structure. 2014 * 2015 * @return 2016 * 0 on success, a negative errno value otherwise and rte_errno is set. 2017 */ 2018 int 2019 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2020 struct mlx5_devx_virtq_attr *attr) 2021 { 2022 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2023 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2024 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2025 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2026 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2027 int ret; 2028 2029 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2030 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2031 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2032 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2033 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2034 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 2035 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2036 switch (attr->type) { 2037 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 2038 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2039 break; 2040 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 2041 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2042 attr->dirty_bitmap_mkey); 2043 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2044 attr->dirty_bitmap_addr); 2045 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2046 attr->dirty_bitmap_size); 2047 break; 2048 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 2049 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2050 attr->dirty_bitmap_dump_enable); 2051 break; 2052 default: 2053 rte_errno = EINVAL; 2054 return -rte_errno; 2055 } 2056 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2057 out, sizeof(out)); 2058 if (ret) { 2059 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2060 rte_errno = errno; 2061 return -rte_errno; 2062 } 2063 return ret; 2064 } 2065 2066 /** 2067 * Query VIRTQ using DevX API. 2068 * 2069 * @param[in] virtq_obj 2070 * Pointer to virtq object structure. 2071 * @param [in/out] attr 2072 * Pointer to virtq attributes structure. 2073 * 2074 * @return 2075 * 0 on success, a negative errno value otherwise and rte_errno is set. 2076 */ 2077 int 2078 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2079 struct mlx5_devx_virtq_attr *attr) 2080 { 2081 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2082 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2083 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2084 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2085 int ret; 2086 2087 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2088 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2089 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2090 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2091 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2092 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2093 out, sizeof(out)); 2094 if (ret) { 2095 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2096 rte_errno = errno; 2097 return -errno; 2098 } 2099 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2100 hw_available_index); 2101 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2102 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2103 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2104 virtio_q_context.error_type); 2105 return ret; 2106 } 2107 2108 /** 2109 * Create QP using DevX API. 2110 * 2111 * @param[in] ctx 2112 * Context returned from mlx5 open_device() glue function. 2113 * @param [in] attr 2114 * Pointer to QP attributes structure. 2115 * 2116 * @return 2117 * The DevX object created, NULL otherwise and rte_errno is set. 2118 */ 2119 struct mlx5_devx_obj * 2120 mlx5_devx_cmd_create_qp(void *ctx, 2121 struct mlx5_devx_qp_attr *attr) 2122 { 2123 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2124 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2125 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2126 sizeof(*qp_obj), 2127 0, SOCKET_ID_ANY); 2128 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2129 2130 if (!qp_obj) { 2131 DRV_LOG(ERR, "Failed to allocate QP data."); 2132 rte_errno = ENOMEM; 2133 return NULL; 2134 } 2135 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2136 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2137 MLX5_SET(qpc, qpc, pd, attr->pd); 2138 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2139 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2140 if (attr->uar_index) { 2141 if (attr->mmo) { 2142 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2143 in, qpc_extension_and_pas_list); 2144 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2145 qpc_ext_and_pas_list, qpc_data_extension); 2146 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2147 } 2148 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2149 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2150 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2151 MLX5_SET(qpc, qpc, log_page_size, 2152 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2153 if (attr->sq_size) { 2154 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2155 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2156 MLX5_SET(qpc, qpc, log_sq_size, 2157 rte_log2_u32(attr->sq_size)); 2158 } else { 2159 MLX5_SET(qpc, qpc, no_sq, 1); 2160 } 2161 if (attr->rq_size) { 2162 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2163 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2164 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2165 MLX5_LOG_RQ_STRIDE_SHIFT); 2166 MLX5_SET(qpc, qpc, log_rq_size, 2167 rte_log2_u32(attr->rq_size)); 2168 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2169 } else { 2170 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2171 } 2172 if (attr->dbr_umem_valid) { 2173 MLX5_SET(qpc, qpc, dbr_umem_valid, 2174 attr->dbr_umem_valid); 2175 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2176 } 2177 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2178 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2179 attr->wq_umem_offset); 2180 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2181 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2182 } else { 2183 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2184 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2185 MLX5_SET(qpc, qpc, no_sq, 1); 2186 } 2187 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2188 sizeof(out)); 2189 if (!qp_obj->obj) { 2190 rte_errno = errno; 2191 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2192 mlx5_free(qp_obj); 2193 return NULL; 2194 } 2195 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2196 return qp_obj; 2197 } 2198 2199 /** 2200 * Modify QP using DevX API. 2201 * Currently supports only force loop-back QP. 2202 * 2203 * @param[in] qp 2204 * Pointer to QP object structure. 2205 * @param [in] qp_st_mod_op 2206 * The QP state modification operation. 2207 * @param [in] remote_qp_id 2208 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2209 * 2210 * @return 2211 * 0 on success, a negative errno value otherwise and rte_errno is set. 2212 */ 2213 int 2214 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2215 uint32_t remote_qp_id) 2216 { 2217 union { 2218 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2219 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2220 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2221 } in; 2222 union { 2223 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2224 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2225 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2226 } out; 2227 void *qpc; 2228 int ret; 2229 unsigned int inlen; 2230 unsigned int outlen; 2231 2232 memset(&in, 0, sizeof(in)); 2233 memset(&out, 0, sizeof(out)); 2234 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2235 switch (qp_st_mod_op) { 2236 case MLX5_CMD_OP_RST2INIT_QP: 2237 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2238 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2239 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2240 MLX5_SET(qpc, qpc, rre, 1); 2241 MLX5_SET(qpc, qpc, rwe, 1); 2242 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2243 inlen = sizeof(in.rst2init); 2244 outlen = sizeof(out.rst2init); 2245 break; 2246 case MLX5_CMD_OP_INIT2RTR_QP: 2247 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2248 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2249 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2250 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2251 MLX5_SET(qpc, qpc, mtu, 1); 2252 MLX5_SET(qpc, qpc, log_msg_max, 30); 2253 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2254 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2255 inlen = sizeof(in.init2rtr); 2256 outlen = sizeof(out.init2rtr); 2257 break; 2258 case MLX5_CMD_OP_RTR2RTS_QP: 2259 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2260 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2261 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2262 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2263 MLX5_SET(qpc, qpc, retry_count, 7); 2264 MLX5_SET(qpc, qpc, rnr_retry, 7); 2265 inlen = sizeof(in.rtr2rts); 2266 outlen = sizeof(out.rtr2rts); 2267 break; 2268 default: 2269 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2270 qp_st_mod_op); 2271 rte_errno = EINVAL; 2272 return -rte_errno; 2273 } 2274 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2275 if (ret) { 2276 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2277 rte_errno = errno; 2278 return -rte_errno; 2279 } 2280 return ret; 2281 } 2282 2283 struct mlx5_devx_obj * 2284 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2285 { 2286 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2287 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2288 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2289 sizeof(*couners_obj), 0, 2290 SOCKET_ID_ANY); 2291 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2292 2293 if (!couners_obj) { 2294 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2295 rte_errno = ENOMEM; 2296 return NULL; 2297 } 2298 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2299 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2300 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2301 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2302 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2303 sizeof(out)); 2304 if (!couners_obj->obj) { 2305 rte_errno = errno; 2306 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2307 " DevX."); 2308 mlx5_free(couners_obj); 2309 return NULL; 2310 } 2311 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2312 return couners_obj; 2313 } 2314 2315 int 2316 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2317 struct mlx5_devx_virtio_q_couners_attr *attr) 2318 { 2319 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2320 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2321 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2322 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2323 virtio_q_counters); 2324 int ret; 2325 2326 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2327 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2328 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2329 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2330 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2331 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2332 sizeof(out)); 2333 if (ret) { 2334 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2335 rte_errno = errno; 2336 return -errno; 2337 } 2338 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2339 received_desc); 2340 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2341 completed_desc); 2342 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2343 error_cqes); 2344 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2345 bad_desc_errors); 2346 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2347 exceed_max_chain); 2348 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2349 invalid_buffer); 2350 return ret; 2351 } 2352 2353 /** 2354 * Create general object of type FLOW_HIT_ASO using DevX API. 2355 * 2356 * @param[in] ctx 2357 * Context returned from mlx5 open_device() glue function. 2358 * @param [in] pd 2359 * PD value to associate the FLOW_HIT_ASO object with. 2360 * 2361 * @return 2362 * The DevX object created, NULL otherwise and rte_errno is set. 2363 */ 2364 struct mlx5_devx_obj * 2365 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2366 { 2367 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2368 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2369 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2370 void *ptr = NULL; 2371 2372 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2373 0, SOCKET_ID_ANY); 2374 if (!flow_hit_aso_obj) { 2375 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2376 rte_errno = ENOMEM; 2377 return NULL; 2378 } 2379 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2380 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2381 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2382 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2383 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2384 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2385 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2386 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2387 out, sizeof(out)); 2388 if (!flow_hit_aso_obj->obj) { 2389 rte_errno = errno; 2390 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2391 mlx5_free(flow_hit_aso_obj); 2392 return NULL; 2393 } 2394 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2395 return flow_hit_aso_obj; 2396 } 2397 2398 /* 2399 * Create PD using DevX API. 2400 * 2401 * @param[in] ctx 2402 * Context returned from mlx5 open_device() glue function. 2403 * 2404 * @return 2405 * The DevX object created, NULL otherwise and rte_errno is set. 2406 */ 2407 struct mlx5_devx_obj * 2408 mlx5_devx_cmd_alloc_pd(void *ctx) 2409 { 2410 struct mlx5_devx_obj *ppd = 2411 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2412 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2413 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2414 2415 if (!ppd) { 2416 DRV_LOG(ERR, "Failed to allocate PD data."); 2417 rte_errno = ENOMEM; 2418 return NULL; 2419 } 2420 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2421 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2422 out, sizeof(out)); 2423 if (!ppd->obj) { 2424 mlx5_free(ppd); 2425 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2426 rte_errno = errno; 2427 return NULL; 2428 } 2429 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2430 return ppd; 2431 } 2432 2433 /** 2434 * Create general object of type FLOW_METER_ASO using DevX API. 2435 * 2436 * @param[in] ctx 2437 * Context returned from mlx5 open_device() glue function. 2438 * @param [in] pd 2439 * PD value to associate the FLOW_METER_ASO object with. 2440 * @param [in] log_obj_size 2441 * log_obj_size define to allocate number of 2 * meters 2442 * in one FLOW_METER_ASO object. 2443 * 2444 * @return 2445 * The DevX object created, NULL otherwise and rte_errno is set. 2446 */ 2447 struct mlx5_devx_obj * 2448 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2449 uint32_t log_obj_size) 2450 { 2451 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2452 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2453 struct mlx5_devx_obj *flow_meter_aso_obj; 2454 void *ptr; 2455 2456 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2457 sizeof(*flow_meter_aso_obj), 2458 0, SOCKET_ID_ANY); 2459 if (!flow_meter_aso_obj) { 2460 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2461 rte_errno = ENOMEM; 2462 return NULL; 2463 } 2464 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2465 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2466 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2467 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2468 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2469 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2470 log_obj_size); 2471 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2472 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2473 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2474 ctx, in, sizeof(in), 2475 out, sizeof(out)); 2476 if (!flow_meter_aso_obj->obj) { 2477 rte_errno = errno; 2478 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2479 mlx5_free(flow_meter_aso_obj); 2480 return NULL; 2481 } 2482 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2483 out, obj_id); 2484 return flow_meter_aso_obj; 2485 } 2486 2487 /* 2488 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2489 * 2490 * @param[in] ctx 2491 * Context returned from mlx5 open_device() glue function. 2492 * @param [in] pd 2493 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2494 * @param [in] log_obj_size 2495 * log_obj_size to allocate its power of 2 * objects 2496 * in one CONN_TRACK_OFFLOAD bulk allocation. 2497 * 2498 * @return 2499 * The DevX object created, NULL otherwise and rte_errno is set. 2500 */ 2501 struct mlx5_devx_obj * 2502 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2503 uint32_t log_obj_size) 2504 { 2505 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2506 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2507 struct mlx5_devx_obj *ct_aso_obj; 2508 void *ptr; 2509 2510 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2511 0, SOCKET_ID_ANY); 2512 if (!ct_aso_obj) { 2513 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2514 rte_errno = ENOMEM; 2515 return NULL; 2516 } 2517 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2518 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2519 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2520 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2521 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2522 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2523 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2524 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2525 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2526 out, sizeof(out)); 2527 if (!ct_aso_obj->obj) { 2528 rte_errno = errno; 2529 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2530 mlx5_free(ct_aso_obj); 2531 return NULL; 2532 } 2533 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2534 return ct_aso_obj; 2535 } 2536 2537 /** 2538 * Create general object of type GENEVE TLV option using DevX API. 2539 * 2540 * @param[in] ctx 2541 * Context returned from mlx5 open_device() glue function. 2542 * @param [in] class 2543 * TLV option variable value of class 2544 * @param [in] type 2545 * TLV option variable value of type 2546 * @param [in] len 2547 * TLV option variable value of len 2548 * 2549 * @return 2550 * The DevX object created, NULL otherwise and rte_errno is set. 2551 */ 2552 struct mlx5_devx_obj * 2553 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2554 uint16_t class, uint8_t type, uint8_t len) 2555 { 2556 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2557 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2558 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2559 sizeof(*geneve_tlv_opt_obj), 2560 0, SOCKET_ID_ANY); 2561 2562 if (!geneve_tlv_opt_obj) { 2563 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2564 rte_errno = ENOMEM; 2565 return NULL; 2566 } 2567 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2568 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2569 geneve_tlv_opt); 2570 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2571 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2572 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2573 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2574 MLX5_SET(geneve_tlv_option, opt, option_class, 2575 rte_be_to_cpu_16(class)); 2576 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2577 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2578 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2579 sizeof(in), out, sizeof(out)); 2580 if (!geneve_tlv_opt_obj->obj) { 2581 rte_errno = errno; 2582 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2583 "Obj using DevX."); 2584 mlx5_free(geneve_tlv_opt_obj); 2585 return NULL; 2586 } 2587 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2588 return geneve_tlv_opt_obj; 2589 } 2590 2591 int 2592 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2593 { 2594 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2595 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2596 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2597 int rc; 2598 void *rq_ctx; 2599 2600 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2601 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2602 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2603 if (rc) { 2604 rte_errno = errno; 2605 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2606 "rc = %d, errno = %d.", rc, errno); 2607 return -rc; 2608 }; 2609 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2610 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2611 return 0; 2612 #else 2613 (void)wq; 2614 (void)counter_set_id; 2615 return -ENOTSUP; 2616 #endif 2617 } 2618 2619 /* 2620 * Allocate queue counters via devx interface. 2621 * 2622 * @param[in] ctx 2623 * Context returned from mlx5 open_device() glue function. 2624 * 2625 * @return 2626 * Pointer to counter object on success, a NULL value otherwise and 2627 * rte_errno is set. 2628 */ 2629 struct mlx5_devx_obj * 2630 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2631 { 2632 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2633 SOCKET_ID_ANY); 2634 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2635 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2636 2637 if (!dcs) { 2638 rte_errno = ENOMEM; 2639 return NULL; 2640 } 2641 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2642 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2643 sizeof(out)); 2644 if (!dcs->obj) { 2645 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2646 "%d.", errno); 2647 rte_errno = errno; 2648 mlx5_free(dcs); 2649 return NULL; 2650 } 2651 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2652 return dcs; 2653 } 2654 2655 /** 2656 * Query queue counters values. 2657 * 2658 * @param[in] dcs 2659 * devx object of the queue counter set. 2660 * @param[in] clear 2661 * Whether hardware should clear the counters after the query or not. 2662 * @param[out] out_of_buffers 2663 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2664 * 2665 * @return 2666 * 0 on success, a negative value otherwise. 2667 */ 2668 int 2669 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2670 uint32_t *out_of_buffers) 2671 { 2672 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2673 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2674 int rc; 2675 2676 MLX5_SET(query_q_counter_in, in, opcode, 2677 MLX5_CMD_OP_QUERY_Q_COUNTER); 2678 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2679 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2680 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2681 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2682 sizeof(out)); 2683 if (rc) { 2684 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2685 rte_errno = rc; 2686 return -rc; 2687 } 2688 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2689 return 0; 2690 } 2691 2692 /** 2693 * Create general object of type DEK using DevX API. 2694 * 2695 * @param[in] ctx 2696 * Context returned from mlx5 open_device() glue function. 2697 * @param [in] attr 2698 * Pointer to DEK attributes structure. 2699 * 2700 * @return 2701 * The DevX object created, NULL otherwise and rte_errno is set. 2702 */ 2703 struct mlx5_devx_obj * 2704 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2705 { 2706 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2707 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2708 struct mlx5_devx_obj *dek_obj = NULL; 2709 void *ptr = NULL, *key_addr = NULL; 2710 2711 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2712 0, SOCKET_ID_ANY); 2713 if (dek_obj == NULL) { 2714 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2715 rte_errno = ENOMEM; 2716 return NULL; 2717 } 2718 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2719 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2720 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2721 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2722 MLX5_GENERAL_OBJ_TYPE_DEK); 2723 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2724 MLX5_SET(dek, ptr, key_size, attr->key_size); 2725 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2726 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2727 MLX5_SET(dek, ptr, pd, attr->pd); 2728 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2729 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2730 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2731 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2732 out, sizeof(out)); 2733 if (dek_obj->obj == NULL) { 2734 rte_errno = errno; 2735 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2736 mlx5_free(dek_obj); 2737 return NULL; 2738 } 2739 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2740 return dek_obj; 2741 } 2742 2743 /** 2744 * Create general object of type IMPORT_KEK using DevX API. 2745 * 2746 * @param[in] ctx 2747 * Context returned from mlx5 open_device() glue function. 2748 * @param [in] attr 2749 * Pointer to IMPORT_KEK attributes structure. 2750 * 2751 * @return 2752 * The DevX object created, NULL otherwise and rte_errno is set. 2753 */ 2754 struct mlx5_devx_obj * 2755 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2756 struct mlx5_devx_import_kek_attr *attr) 2757 { 2758 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2759 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2760 struct mlx5_devx_obj *import_kek_obj = NULL; 2761 void *ptr = NULL, *key_addr = NULL; 2762 2763 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2764 0, SOCKET_ID_ANY); 2765 if (import_kek_obj == NULL) { 2766 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2767 rte_errno = ENOMEM; 2768 return NULL; 2769 } 2770 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2771 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2772 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2773 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2774 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2775 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2776 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2777 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2778 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2779 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2780 out, sizeof(out)); 2781 if (import_kek_obj->obj == NULL) { 2782 rte_errno = errno; 2783 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2784 mlx5_free(import_kek_obj); 2785 return NULL; 2786 } 2787 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2788 return import_kek_obj; 2789 } 2790 2791 /** 2792 * Create general object of type CREDENTIAL using DevX API. 2793 * 2794 * @param[in] ctx 2795 * Context returned from mlx5 open_device() glue function. 2796 * @param [in] attr 2797 * Pointer to CREDENTIAL attributes structure. 2798 * 2799 * @return 2800 * The DevX object created, NULL otherwise and rte_errno is set. 2801 */ 2802 struct mlx5_devx_obj * 2803 mlx5_devx_cmd_create_credential_obj(void *ctx, 2804 struct mlx5_devx_credential_attr *attr) 2805 { 2806 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2807 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2808 struct mlx5_devx_obj *credential_obj = NULL; 2809 void *ptr = NULL, *credential_addr = NULL; 2810 2811 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2812 0, SOCKET_ID_ANY); 2813 if (credential_obj == NULL) { 2814 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2815 rte_errno = ENOMEM; 2816 return NULL; 2817 } 2818 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2819 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2820 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2821 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2822 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2823 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2824 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2825 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2826 memcpy(credential_addr, (void *)(attr->credential), 2827 MLX5_CRYPTO_CREDENTIAL_SIZE); 2828 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2829 out, sizeof(out)); 2830 if (credential_obj->obj == NULL) { 2831 rte_errno = errno; 2832 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2833 mlx5_free(credential_obj); 2834 return NULL; 2835 } 2836 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2837 return credential_obj; 2838 } 2839 2840 /** 2841 * Create general object of type CRYPTO_LOGIN using DevX API. 2842 * 2843 * @param[in] ctx 2844 * Context returned from mlx5 open_device() glue function. 2845 * @param [in] attr 2846 * Pointer to CRYPTO_LOGIN attributes structure. 2847 * 2848 * @return 2849 * The DevX object created, NULL otherwise and rte_errno is set. 2850 */ 2851 struct mlx5_devx_obj * 2852 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2853 struct mlx5_devx_crypto_login_attr *attr) 2854 { 2855 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2856 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2857 struct mlx5_devx_obj *crypto_login_obj = NULL; 2858 void *ptr = NULL, *credential_addr = NULL; 2859 2860 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2861 0, SOCKET_ID_ANY); 2862 if (crypto_login_obj == NULL) { 2863 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2864 rte_errno = ENOMEM; 2865 return NULL; 2866 } 2867 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2868 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2869 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2870 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2871 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2872 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2873 MLX5_SET(crypto_login, ptr, credential_pointer, 2874 attr->credential_pointer); 2875 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2876 attr->session_import_kek_ptr); 2877 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2878 memcpy(credential_addr, (void *)(attr->credential), 2879 MLX5_CRYPTO_CREDENTIAL_SIZE); 2880 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2881 out, sizeof(out)); 2882 if (crypto_login_obj->obj == NULL) { 2883 rte_errno = errno; 2884 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2885 mlx5_free(crypto_login_obj); 2886 return NULL; 2887 } 2888 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2889 return crypto_login_obj; 2890 } 2891 2892 /** 2893 * Query LAG context. 2894 * 2895 * @param[in] ctx 2896 * Pointer to ibv_context, returned from mlx5dv_open_device. 2897 * @param[out] lag_ctx 2898 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2899 * 2900 * @return 2901 * 0 on success, a negative value otherwise. 2902 */ 2903 int 2904 mlx5_devx_cmd_query_lag(void *ctx, 2905 struct mlx5_devx_lag_context *lag_ctx) 2906 { 2907 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2908 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2909 void *lctx; 2910 int rc; 2911 2912 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2913 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2914 if (rc) 2915 goto error; 2916 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2917 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2918 fdb_selection_mode); 2919 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2920 port_select_mode); 2921 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2922 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2923 tx_remap_affinity_2); 2924 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2925 tx_remap_affinity_1); 2926 return 0; 2927 error: 2928 rc = (rc > 0) ? -rc : rc; 2929 return rc; 2930 } 2931