1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 /** 703 * Query HCA attributes. 704 * Using those attributes we can check on run time if the device 705 * is having the required capabilities. 706 * 707 * @param[in] ctx 708 * Context returned from mlx5 open_device() glue function. 709 * @param[out] attr 710 * Attributes device values. 711 * 712 * @return 713 * 0 on success, a negative value otherwise. 714 */ 715 int 716 mlx5_devx_cmd_query_hca_attr(void *ctx, 717 struct mlx5_hca_attr *attr) 718 { 719 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 720 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 721 void *hcattr; 722 int status, syndrome, rc, i; 723 uint64_t general_obj_types_supported = 0; 724 725 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 726 MLX5_SET(query_hca_cap_in, in, op_mod, 727 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 728 MLX5_HCA_CAP_OPMOD_GET_CUR); 729 730 rc = mlx5_glue->devx_general_cmd(ctx, 731 in, sizeof(in), out, sizeof(out)); 732 if (rc) 733 goto error; 734 status = MLX5_GET(query_hca_cap_out, out, status); 735 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 736 if (status) { 737 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 738 "status %x, syndrome = %x", status, syndrome); 739 return -1; 740 } 741 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 742 attr->flow_counter_bulk_alloc_bitmap = 743 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 744 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 745 flow_counters_dump); 746 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 747 log_max_rqt_size); 748 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 749 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 750 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 751 log_max_hairpin_queues); 752 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 753 log_max_hairpin_wq_data_sz); 754 attr->log_max_hairpin_num_packets = MLX5_GET 755 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 756 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 757 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 758 relaxed_ordering_write); 759 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 760 relaxed_ordering_read); 761 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 762 access_register_user); 763 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 764 eth_net_offloads); 765 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 766 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 767 flex_parser_protocols); 768 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 769 max_geneve_tlv_options); 770 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 771 max_geneve_tlv_option_data_len); 772 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 773 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 774 general_obj_types) & 775 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 776 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 777 general_obj_types) & 778 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 779 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 780 general_obj_types) & 781 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 782 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 783 general_obj_types) & 784 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 785 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 786 wqe_index_ignore_cap); 787 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 788 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 789 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 790 log_max_static_sq_wq); 791 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 792 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 793 device_frequency_khz); 794 attr->scatter_fcs_w_decap_disable = 795 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 796 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 797 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 798 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 799 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 800 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 801 regexp_num_of_engines); 802 /* Read the general_obj_types bitmap and extract the relevant bits. */ 803 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 804 general_obj_types); 805 attr->vdpa.valid = !!(general_obj_types_supported & 806 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 807 attr->vdpa.queue_counters_valid = 808 !!(general_obj_types_supported & 809 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 810 attr->parse_graph_flex_node = 811 !!(general_obj_types_supported & 812 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 813 attr->flow_hit_aso = !!(general_obj_types_supported & 814 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 815 attr->geneve_tlv_opt = !!(general_obj_types_supported & 816 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 817 attr->dek = !!(general_obj_types_supported & 818 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 819 attr->import_kek = !!(general_obj_types_supported & 820 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 821 attr->credential = !!(general_obj_types_supported & 822 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 823 attr->crypto_login = !!(general_obj_types_supported & 824 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 825 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 826 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 827 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 828 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 829 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 830 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 831 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 832 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 833 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 834 attr->reg_c_preserve = 835 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 836 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 837 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 838 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 839 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 840 compress_min_block_size); 841 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 842 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 843 log_compress_mmo_size); 844 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 845 log_decompress_mmo_size); 846 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 847 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 848 mini_cqe_resp_flow_tag); 849 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 850 mini_cqe_resp_l3_l4_tag); 851 attr->umr_indirect_mkey_disabled = 852 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 853 attr->umr_modify_entity_size_disabled = 854 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 855 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 856 if (attr->crypto) 857 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 858 if (attr->qos.sup) { 859 MLX5_SET(query_hca_cap_in, in, op_mod, 860 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 861 MLX5_HCA_CAP_OPMOD_GET_CUR); 862 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 863 out, sizeof(out)); 864 if (rc) 865 goto error; 866 if (status) { 867 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 868 " status %x, syndrome = %x", status, syndrome); 869 return -1; 870 } 871 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 872 attr->qos.flow_meter_old = 873 MLX5_GET(qos_cap, hcattr, flow_meter_old); 874 attr->qos.log_max_flow_meter = 875 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 876 attr->qos.flow_meter_reg_c_ids = 877 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 878 attr->qos.flow_meter = 879 MLX5_GET(qos_cap, hcattr, flow_meter); 880 attr->qos.packet_pacing = 881 MLX5_GET(qos_cap, hcattr, packet_pacing); 882 attr->qos.wqe_rate_pp = 883 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 884 if (attr->qos.flow_meter_aso_sup) { 885 attr->qos.log_meter_aso_granularity = 886 MLX5_GET(qos_cap, hcattr, 887 log_meter_aso_granularity); 888 attr->qos.log_meter_aso_max_alloc = 889 MLX5_GET(qos_cap, hcattr, 890 log_meter_aso_max_alloc); 891 attr->qos.log_max_num_meter_aso = 892 MLX5_GET(qos_cap, hcattr, 893 log_max_num_meter_aso); 894 } 895 } 896 if (attr->vdpa.valid) 897 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 898 if (!attr->eth_net_offloads) 899 return 0; 900 901 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 902 memset(in, 0, sizeof(in)); 903 memset(out, 0, sizeof(out)); 904 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 905 MLX5_SET(query_hca_cap_in, in, op_mod, 906 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 907 MLX5_HCA_CAP_OPMOD_GET_CUR); 908 909 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 910 if (rc) 911 goto error; 912 status = MLX5_GET(query_hca_cap_out, out, status); 913 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 914 if (status) { 915 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 916 "status %x, syndrome = %x", status, syndrome); 917 attr->log_max_ft_sampler_num = 0; 918 return -1; 919 } 920 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 921 attr->log_max_ft_sampler_num = 922 MLX5_GET(flow_table_nic_cap, 923 hcattr, flow_table_properties.log_max_ft_sampler_num); 924 925 /* Query HCA offloads for Ethernet protocol. */ 926 memset(in, 0, sizeof(in)); 927 memset(out, 0, sizeof(out)); 928 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 929 MLX5_SET(query_hca_cap_in, in, op_mod, 930 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 931 MLX5_HCA_CAP_OPMOD_GET_CUR); 932 933 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 934 if (rc) { 935 attr->eth_net_offloads = 0; 936 goto error; 937 } 938 status = MLX5_GET(query_hca_cap_out, out, status); 939 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 940 if (status) { 941 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 942 "status %x, syndrome = %x", status, syndrome); 943 attr->eth_net_offloads = 0; 944 return -1; 945 } 946 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 947 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 948 hcattr, wqe_vlan_insert); 949 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 950 hcattr, csum_cap); 951 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 952 lro_cap); 953 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 954 hcattr, tunnel_lro_gre); 955 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 956 hcattr, tunnel_lro_vxlan); 957 attr->lro_max_msg_sz_mode = MLX5_GET 958 (per_protocol_networking_offload_caps, 959 hcattr, lro_max_msg_sz_mode); 960 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 961 attr->lro_timer_supported_periods[i] = 962 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 963 lro_timer_supported_periods[i]); 964 } 965 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 966 hcattr, lro_min_mss_size); 967 attr->tunnel_stateless_geneve_rx = 968 MLX5_GET(per_protocol_networking_offload_caps, 969 hcattr, tunnel_stateless_geneve_rx); 970 attr->geneve_max_opt_len = 971 MLX5_GET(per_protocol_networking_offload_caps, 972 hcattr, max_geneve_opt_len); 973 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 974 hcattr, wqe_inline_mode); 975 attr->tunnel_stateless_gtp = MLX5_GET 976 (per_protocol_networking_offload_caps, 977 hcattr, tunnel_stateless_gtp); 978 attr->rss_ind_tbl_cap = MLX5_GET 979 (per_protocol_networking_offload_caps, 980 hcattr, rss_ind_tbl_cap); 981 /* Query HCA attribute for ROCE. */ 982 if (attr->roce) { 983 memset(in, 0, sizeof(in)); 984 memset(out, 0, sizeof(out)); 985 MLX5_SET(query_hca_cap_in, in, opcode, 986 MLX5_CMD_OP_QUERY_HCA_CAP); 987 MLX5_SET(query_hca_cap_in, in, op_mod, 988 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 989 MLX5_HCA_CAP_OPMOD_GET_CUR); 990 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 991 out, sizeof(out)); 992 if (rc) 993 goto error; 994 status = MLX5_GET(query_hca_cap_out, out, status); 995 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 996 if (status) { 997 DRV_LOG(DEBUG, 998 "Failed to query devx HCA ROCE capabilities, " 999 "status %x, syndrome = %x", status, syndrome); 1000 return -1; 1001 } 1002 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1003 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1004 } 1005 if (attr->eth_virt && 1006 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1007 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1008 if (rc) { 1009 attr->eth_virt = 0; 1010 goto error; 1011 } 1012 } 1013 return 0; 1014 error: 1015 rc = (rc > 0) ? -rc : rc; 1016 return rc; 1017 } 1018 1019 /** 1020 * Query TIS transport domain from QP verbs object using DevX API. 1021 * 1022 * @param[in] qp 1023 * Pointer to verbs QP returned by ibv_create_qp . 1024 * @param[in] tis_num 1025 * TIS number of TIS to query. 1026 * @param[out] tis_td 1027 * Pointer to TIS transport domain variable, to be set by the routine. 1028 * 1029 * @return 1030 * 0 on success, a negative value otherwise. 1031 */ 1032 int 1033 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1034 uint32_t *tis_td) 1035 { 1036 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1037 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1038 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1039 int rc; 1040 void *tis_ctx; 1041 1042 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1043 MLX5_SET(query_tis_in, in, tisn, tis_num); 1044 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1045 if (rc) { 1046 DRV_LOG(ERR, "Failed to query QP using DevX"); 1047 return -rc; 1048 }; 1049 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1050 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1051 return 0; 1052 #else 1053 (void)qp; 1054 (void)tis_num; 1055 (void)tis_td; 1056 return -ENOTSUP; 1057 #endif 1058 } 1059 1060 /** 1061 * Fill WQ data for DevX API command. 1062 * Utility function for use when creating DevX objects containing a WQ. 1063 * 1064 * @param[in] wq_ctx 1065 * Pointer to WQ context to fill with data. 1066 * @param [in] wq_attr 1067 * Pointer to WQ attributes structure to fill in WQ context. 1068 */ 1069 static void 1070 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1071 { 1072 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1073 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1074 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1075 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1076 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1077 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1078 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1079 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1080 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1081 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1082 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1083 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1084 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1085 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1086 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1087 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1088 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1089 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1090 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1091 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1092 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1093 wq_attr->log_hairpin_num_packets); 1094 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1095 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1096 wq_attr->single_wqe_log_num_of_strides); 1097 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1098 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1099 wq_attr->single_stride_log_num_of_bytes); 1100 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1101 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1102 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1103 } 1104 1105 /** 1106 * Create RQ using DevX API. 1107 * 1108 * @param[in] ctx 1109 * Context returned from mlx5 open_device() glue function. 1110 * @param [in] rq_attr 1111 * Pointer to create RQ attributes structure. 1112 * @param [in] socket 1113 * CPU socket ID for allocations. 1114 * 1115 * @return 1116 * The DevX object created, NULL otherwise and rte_errno is set. 1117 */ 1118 struct mlx5_devx_obj * 1119 mlx5_devx_cmd_create_rq(void *ctx, 1120 struct mlx5_devx_create_rq_attr *rq_attr, 1121 int socket) 1122 { 1123 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1124 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1125 void *rq_ctx, *wq_ctx; 1126 struct mlx5_devx_wq_attr *wq_attr; 1127 struct mlx5_devx_obj *rq = NULL; 1128 1129 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1130 if (!rq) { 1131 DRV_LOG(ERR, "Failed to allocate RQ data"); 1132 rte_errno = ENOMEM; 1133 return NULL; 1134 } 1135 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1136 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1137 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1138 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1139 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1140 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1141 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1142 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1143 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1144 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1145 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1146 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1147 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1148 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1149 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1150 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1151 wq_attr = &rq_attr->wq_attr; 1152 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1153 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1154 out, sizeof(out)); 1155 if (!rq->obj) { 1156 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1157 rte_errno = errno; 1158 mlx5_free(rq); 1159 return NULL; 1160 } 1161 rq->id = MLX5_GET(create_rq_out, out, rqn); 1162 return rq; 1163 } 1164 1165 /** 1166 * Modify RQ using DevX API. 1167 * 1168 * @param[in] rq 1169 * Pointer to RQ object structure. 1170 * @param [in] rq_attr 1171 * Pointer to modify RQ attributes structure. 1172 * 1173 * @return 1174 * 0 on success, a negative errno value otherwise and rte_errno is set. 1175 */ 1176 int 1177 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1178 struct mlx5_devx_modify_rq_attr *rq_attr) 1179 { 1180 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1181 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1182 void *rq_ctx, *wq_ctx; 1183 int ret; 1184 1185 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1186 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1187 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1188 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1189 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1190 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1191 if (rq_attr->modify_bitmask & 1192 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1193 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1194 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1195 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1196 if (rq_attr->modify_bitmask & 1197 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1198 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1199 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1200 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1201 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1202 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1203 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1204 } 1205 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1206 out, sizeof(out)); 1207 if (ret) { 1208 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1209 rte_errno = errno; 1210 return -errno; 1211 } 1212 return ret; 1213 } 1214 1215 /** 1216 * Create TIR using DevX API. 1217 * 1218 * @param[in] ctx 1219 * Context returned from mlx5 open_device() glue function. 1220 * @param [in] tir_attr 1221 * Pointer to TIR attributes structure. 1222 * 1223 * @return 1224 * The DevX object created, NULL otherwise and rte_errno is set. 1225 */ 1226 struct mlx5_devx_obj * 1227 mlx5_devx_cmd_create_tir(void *ctx, 1228 struct mlx5_devx_tir_attr *tir_attr) 1229 { 1230 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1231 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1232 void *tir_ctx, *outer, *inner, *rss_key; 1233 struct mlx5_devx_obj *tir = NULL; 1234 1235 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1236 if (!tir) { 1237 DRV_LOG(ERR, "Failed to allocate TIR data"); 1238 rte_errno = ENOMEM; 1239 return NULL; 1240 } 1241 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1242 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1243 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1244 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1245 tir_attr->lro_timeout_period_usecs); 1246 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1247 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1248 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1249 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1250 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1251 tir_attr->tunneled_offload_en); 1252 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1253 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1254 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1255 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1256 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1257 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1258 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1259 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1260 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1261 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1262 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1263 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1264 tir_attr->rx_hash_field_selector_outer.selected_fields); 1265 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1266 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1267 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1268 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1269 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1270 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1271 tir_attr->rx_hash_field_selector_inner.selected_fields); 1272 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1273 out, sizeof(out)); 1274 if (!tir->obj) { 1275 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1276 rte_errno = errno; 1277 mlx5_free(tir); 1278 return NULL; 1279 } 1280 tir->id = MLX5_GET(create_tir_out, out, tirn); 1281 return tir; 1282 } 1283 1284 /** 1285 * Modify TIR using DevX API. 1286 * 1287 * @param[in] tir 1288 * Pointer to TIR DevX object structure. 1289 * @param [in] modify_tir_attr 1290 * Pointer to TIR modification attributes structure. 1291 * 1292 * @return 1293 * 0 on success, a negative errno value otherwise and rte_errno is set. 1294 */ 1295 int 1296 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1297 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1298 { 1299 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1300 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1301 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1302 void *tir_ctx; 1303 int ret; 1304 1305 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1306 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1307 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1308 modify_tir_attr->modify_bitmask); 1309 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1310 if (modify_tir_attr->modify_bitmask & 1311 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1312 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1313 tir_attr->lro_timeout_period_usecs); 1314 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1315 tir_attr->lro_enable_mask); 1316 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1317 tir_attr->lro_max_msg_sz); 1318 } 1319 if (modify_tir_attr->modify_bitmask & 1320 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1321 MLX5_SET(tirc, tir_ctx, indirect_table, 1322 tir_attr->indirect_table); 1323 if (modify_tir_attr->modify_bitmask & 1324 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1325 int i; 1326 void *outer, *inner; 1327 1328 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1329 tir_attr->rx_hash_symmetric); 1330 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1331 for (i = 0; i < 10; i++) { 1332 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1333 tir_attr->rx_hash_toeplitz_key[i]); 1334 } 1335 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1336 rx_hash_field_selector_outer); 1337 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1338 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1339 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1340 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1341 MLX5_SET 1342 (rx_hash_field_select, outer, selected_fields, 1343 tir_attr->rx_hash_field_selector_outer.selected_fields); 1344 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1345 rx_hash_field_selector_inner); 1346 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1347 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1348 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1349 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1350 MLX5_SET 1351 (rx_hash_field_select, inner, selected_fields, 1352 tir_attr->rx_hash_field_selector_inner.selected_fields); 1353 } 1354 if (modify_tir_attr->modify_bitmask & 1355 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1356 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1357 } 1358 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1359 out, sizeof(out)); 1360 if (ret) { 1361 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1362 rte_errno = errno; 1363 return -errno; 1364 } 1365 return ret; 1366 } 1367 1368 /** 1369 * Create RQT using DevX API. 1370 * 1371 * @param[in] ctx 1372 * Context returned from mlx5 open_device() glue function. 1373 * @param [in] rqt_attr 1374 * Pointer to RQT attributes structure. 1375 * 1376 * @return 1377 * The DevX object created, NULL otherwise and rte_errno is set. 1378 */ 1379 struct mlx5_devx_obj * 1380 mlx5_devx_cmd_create_rqt(void *ctx, 1381 struct mlx5_devx_rqt_attr *rqt_attr) 1382 { 1383 uint32_t *in = NULL; 1384 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1385 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1386 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1387 void *rqt_ctx; 1388 struct mlx5_devx_obj *rqt = NULL; 1389 int i; 1390 1391 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1392 if (!in) { 1393 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1394 rte_errno = ENOMEM; 1395 return NULL; 1396 } 1397 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1398 if (!rqt) { 1399 DRV_LOG(ERR, "Failed to allocate RQT data"); 1400 rte_errno = ENOMEM; 1401 mlx5_free(in); 1402 return NULL; 1403 } 1404 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1405 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1406 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1407 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1408 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1409 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1410 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1411 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1412 mlx5_free(in); 1413 if (!rqt->obj) { 1414 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1415 rte_errno = errno; 1416 mlx5_free(rqt); 1417 return NULL; 1418 } 1419 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1420 return rqt; 1421 } 1422 1423 /** 1424 * Modify RQT using DevX API. 1425 * 1426 * @param[in] rqt 1427 * Pointer to RQT DevX object structure. 1428 * @param [in] rqt_attr 1429 * Pointer to RQT attributes structure. 1430 * 1431 * @return 1432 * 0 on success, a negative errno value otherwise and rte_errno is set. 1433 */ 1434 int 1435 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1436 struct mlx5_devx_rqt_attr *rqt_attr) 1437 { 1438 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1439 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1440 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1441 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1442 void *rqt_ctx; 1443 int i; 1444 int ret; 1445 1446 if (!in) { 1447 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1448 rte_errno = ENOMEM; 1449 return -ENOMEM; 1450 } 1451 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1452 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1453 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1454 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1455 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1456 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1457 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1458 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1459 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1460 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1461 mlx5_free(in); 1462 if (ret) { 1463 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1464 rte_errno = errno; 1465 return -rte_errno; 1466 } 1467 return ret; 1468 } 1469 1470 /** 1471 * Create SQ using DevX API. 1472 * 1473 * @param[in] ctx 1474 * Context returned from mlx5 open_device() glue function. 1475 * @param [in] sq_attr 1476 * Pointer to SQ attributes structure. 1477 * @param [in] socket 1478 * CPU socket ID for allocations. 1479 * 1480 * @return 1481 * The DevX object created, NULL otherwise and rte_errno is set. 1482 **/ 1483 struct mlx5_devx_obj * 1484 mlx5_devx_cmd_create_sq(void *ctx, 1485 struct mlx5_devx_create_sq_attr *sq_attr) 1486 { 1487 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1488 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1489 void *sq_ctx; 1490 void *wq_ctx; 1491 struct mlx5_devx_wq_attr *wq_attr; 1492 struct mlx5_devx_obj *sq = NULL; 1493 1494 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1495 if (!sq) { 1496 DRV_LOG(ERR, "Failed to allocate SQ data"); 1497 rte_errno = ENOMEM; 1498 return NULL; 1499 } 1500 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1501 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1502 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1503 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1504 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1505 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1506 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1507 sq_attr->allow_multi_pkt_send_wqe); 1508 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1509 sq_attr->min_wqe_inline_mode); 1510 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1511 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1512 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1513 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1514 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1515 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1516 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1517 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1518 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1519 sq_attr->packet_pacing_rate_limit_index); 1520 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1521 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1522 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1523 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1524 wq_attr = &sq_attr->wq_attr; 1525 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1526 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1527 out, sizeof(out)); 1528 if (!sq->obj) { 1529 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1530 rte_errno = errno; 1531 mlx5_free(sq); 1532 return NULL; 1533 } 1534 sq->id = MLX5_GET(create_sq_out, out, sqn); 1535 return sq; 1536 } 1537 1538 /** 1539 * Modify SQ using DevX API. 1540 * 1541 * @param[in] sq 1542 * Pointer to SQ object structure. 1543 * @param [in] sq_attr 1544 * Pointer to SQ attributes structure. 1545 * 1546 * @return 1547 * 0 on success, a negative errno value otherwise and rte_errno is set. 1548 */ 1549 int 1550 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1551 struct mlx5_devx_modify_sq_attr *sq_attr) 1552 { 1553 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1554 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1555 void *sq_ctx; 1556 int ret; 1557 1558 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1559 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1560 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1561 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1562 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1563 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1564 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1565 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1566 out, sizeof(out)); 1567 if (ret) { 1568 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1569 rte_errno = errno; 1570 return -rte_errno; 1571 } 1572 return ret; 1573 } 1574 1575 /** 1576 * Create TIS using DevX API. 1577 * 1578 * @param[in] ctx 1579 * Context returned from mlx5 open_device() glue function. 1580 * @param [in] tis_attr 1581 * Pointer to TIS attributes structure. 1582 * 1583 * @return 1584 * The DevX object created, NULL otherwise and rte_errno is set. 1585 */ 1586 struct mlx5_devx_obj * 1587 mlx5_devx_cmd_create_tis(void *ctx, 1588 struct mlx5_devx_tis_attr *tis_attr) 1589 { 1590 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1591 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1592 struct mlx5_devx_obj *tis = NULL; 1593 void *tis_ctx; 1594 1595 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1596 if (!tis) { 1597 DRV_LOG(ERR, "Failed to allocate TIS object"); 1598 rte_errno = ENOMEM; 1599 return NULL; 1600 } 1601 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1602 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1603 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1604 tis_attr->strict_lag_tx_port_affinity); 1605 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1606 tis_attr->lag_tx_port_affinity); 1607 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1608 MLX5_SET(tisc, tis_ctx, transport_domain, 1609 tis_attr->transport_domain); 1610 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1611 out, sizeof(out)); 1612 if (!tis->obj) { 1613 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1614 rte_errno = errno; 1615 mlx5_free(tis); 1616 return NULL; 1617 } 1618 tis->id = MLX5_GET(create_tis_out, out, tisn); 1619 return tis; 1620 } 1621 1622 /** 1623 * Create transport domain using DevX API. 1624 * 1625 * @param[in] ctx 1626 * Context returned from mlx5 open_device() glue function. 1627 * @return 1628 * The DevX object created, NULL otherwise and rte_errno is set. 1629 */ 1630 struct mlx5_devx_obj * 1631 mlx5_devx_cmd_create_td(void *ctx) 1632 { 1633 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1634 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1635 struct mlx5_devx_obj *td = NULL; 1636 1637 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1638 if (!td) { 1639 DRV_LOG(ERR, "Failed to allocate TD object"); 1640 rte_errno = ENOMEM; 1641 return NULL; 1642 } 1643 MLX5_SET(alloc_transport_domain_in, in, opcode, 1644 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1645 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1646 out, sizeof(out)); 1647 if (!td->obj) { 1648 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1649 rte_errno = errno; 1650 mlx5_free(td); 1651 return NULL; 1652 } 1653 td->id = MLX5_GET(alloc_transport_domain_out, out, 1654 transport_domain); 1655 return td; 1656 } 1657 1658 /** 1659 * Dump all flows to file. 1660 * 1661 * @param[in] fdb_domain 1662 * FDB domain. 1663 * @param[in] rx_domain 1664 * RX domain. 1665 * @param[in] tx_domain 1666 * TX domain. 1667 * @param[out] file 1668 * Pointer to file stream. 1669 * 1670 * @return 1671 * 0 on success, a nagative value otherwise. 1672 */ 1673 int 1674 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1675 void *rx_domain __rte_unused, 1676 void *tx_domain __rte_unused, FILE *file __rte_unused) 1677 { 1678 int ret = 0; 1679 1680 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1681 if (fdb_domain) { 1682 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1683 if (ret) 1684 return ret; 1685 } 1686 MLX5_ASSERT(rx_domain); 1687 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1688 if (ret) 1689 return ret; 1690 MLX5_ASSERT(tx_domain); 1691 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1692 #else 1693 ret = ENOTSUP; 1694 #endif 1695 return -ret; 1696 } 1697 1698 int 1699 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1700 FILE *file __rte_unused) 1701 { 1702 int ret = 0; 1703 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1704 if (rule_info) 1705 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1706 #else 1707 ret = ENOTSUP; 1708 #endif 1709 return -ret; 1710 } 1711 1712 /* 1713 * Create CQ using DevX API. 1714 * 1715 * @param[in] ctx 1716 * Context returned from mlx5 open_device() glue function. 1717 * @param [in] attr 1718 * Pointer to CQ attributes structure. 1719 * 1720 * @return 1721 * The DevX object created, NULL otherwise and rte_errno is set. 1722 */ 1723 struct mlx5_devx_obj * 1724 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1725 { 1726 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1727 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1728 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1729 sizeof(*cq_obj), 1730 0, SOCKET_ID_ANY); 1731 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1732 1733 if (!cq_obj) { 1734 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1735 rte_errno = ENOMEM; 1736 return NULL; 1737 } 1738 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1739 if (attr->db_umem_valid) { 1740 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1741 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1742 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1743 } else { 1744 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1745 } 1746 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1747 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1748 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1749 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1750 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1751 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1752 MLX5_SET(cqc, cqctx, log_page_size, 1753 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1754 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1755 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1756 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1757 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1758 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1759 attr->mini_cqe_res_format_ext); 1760 if (attr->q_umem_valid) { 1761 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1762 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1763 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1764 attr->q_umem_offset); 1765 } 1766 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1767 sizeof(out)); 1768 if (!cq_obj->obj) { 1769 rte_errno = errno; 1770 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1771 mlx5_free(cq_obj); 1772 return NULL; 1773 } 1774 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1775 return cq_obj; 1776 } 1777 1778 /** 1779 * Create VIRTQ using DevX API. 1780 * 1781 * @param[in] ctx 1782 * Context returned from mlx5 open_device() glue function. 1783 * @param [in] attr 1784 * Pointer to VIRTQ attributes structure. 1785 * 1786 * @return 1787 * The DevX object created, NULL otherwise and rte_errno is set. 1788 */ 1789 struct mlx5_devx_obj * 1790 mlx5_devx_cmd_create_virtq(void *ctx, 1791 struct mlx5_devx_virtq_attr *attr) 1792 { 1793 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1794 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1795 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1796 sizeof(*virtq_obj), 1797 0, SOCKET_ID_ANY); 1798 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1799 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1800 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1801 1802 if (!virtq_obj) { 1803 DRV_LOG(ERR, "Failed to allocate virtq data."); 1804 rte_errno = ENOMEM; 1805 return NULL; 1806 } 1807 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1808 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1809 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1810 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1811 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1812 attr->hw_available_index); 1813 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1814 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1815 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1816 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1817 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1818 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1819 attr->virtio_version_1_0); 1820 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1821 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1822 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1823 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1824 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1825 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1826 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1827 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1828 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1829 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1830 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1831 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1832 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1833 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1834 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1835 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1836 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1837 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1838 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1839 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1840 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1841 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1842 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1843 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1844 sizeof(out)); 1845 if (!virtq_obj->obj) { 1846 rte_errno = errno; 1847 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1848 mlx5_free(virtq_obj); 1849 return NULL; 1850 } 1851 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1852 return virtq_obj; 1853 } 1854 1855 /** 1856 * Modify VIRTQ using DevX API. 1857 * 1858 * @param[in] virtq_obj 1859 * Pointer to virtq object structure. 1860 * @param [in] attr 1861 * Pointer to modify virtq attributes structure. 1862 * 1863 * @return 1864 * 0 on success, a negative errno value otherwise and rte_errno is set. 1865 */ 1866 int 1867 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1868 struct mlx5_devx_virtq_attr *attr) 1869 { 1870 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1871 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1872 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1873 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1874 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1875 int ret; 1876 1877 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1878 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1879 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1880 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1881 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1882 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1883 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1884 switch (attr->type) { 1885 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1886 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1887 break; 1888 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1889 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1890 attr->dirty_bitmap_mkey); 1891 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1892 attr->dirty_bitmap_addr); 1893 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1894 attr->dirty_bitmap_size); 1895 break; 1896 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1897 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1898 attr->dirty_bitmap_dump_enable); 1899 break; 1900 default: 1901 rte_errno = EINVAL; 1902 return -rte_errno; 1903 } 1904 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1905 out, sizeof(out)); 1906 if (ret) { 1907 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1908 rte_errno = errno; 1909 return -rte_errno; 1910 } 1911 return ret; 1912 } 1913 1914 /** 1915 * Query VIRTQ using DevX API. 1916 * 1917 * @param[in] virtq_obj 1918 * Pointer to virtq object structure. 1919 * @param [in/out] attr 1920 * Pointer to virtq attributes structure. 1921 * 1922 * @return 1923 * 0 on success, a negative errno value otherwise and rte_errno is set. 1924 */ 1925 int 1926 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1927 struct mlx5_devx_virtq_attr *attr) 1928 { 1929 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1930 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1931 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1932 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1933 int ret; 1934 1935 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1936 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1937 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1938 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1939 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1940 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1941 out, sizeof(out)); 1942 if (ret) { 1943 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1944 rte_errno = errno; 1945 return -errno; 1946 } 1947 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1948 hw_available_index); 1949 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1950 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1951 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1952 virtio_q_context.error_type); 1953 return ret; 1954 } 1955 1956 /** 1957 * Create QP using DevX API. 1958 * 1959 * @param[in] ctx 1960 * Context returned from mlx5 open_device() glue function. 1961 * @param [in] attr 1962 * Pointer to QP attributes structure. 1963 * 1964 * @return 1965 * The DevX object created, NULL otherwise and rte_errno is set. 1966 */ 1967 struct mlx5_devx_obj * 1968 mlx5_devx_cmd_create_qp(void *ctx, 1969 struct mlx5_devx_qp_attr *attr) 1970 { 1971 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1972 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1973 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1974 sizeof(*qp_obj), 1975 0, SOCKET_ID_ANY); 1976 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1977 1978 if (!qp_obj) { 1979 DRV_LOG(ERR, "Failed to allocate QP data."); 1980 rte_errno = ENOMEM; 1981 return NULL; 1982 } 1983 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1984 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1985 MLX5_SET(qpc, qpc, pd, attr->pd); 1986 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 1987 if (attr->uar_index) { 1988 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1989 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1990 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1991 MLX5_SET(qpc, qpc, log_page_size, 1992 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1993 if (attr->sq_size) { 1994 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1995 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1996 MLX5_SET(qpc, qpc, log_sq_size, 1997 rte_log2_u32(attr->sq_size)); 1998 } else { 1999 MLX5_SET(qpc, qpc, no_sq, 1); 2000 } 2001 if (attr->rq_size) { 2002 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2003 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2004 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2005 MLX5_LOG_RQ_STRIDE_SHIFT); 2006 MLX5_SET(qpc, qpc, log_rq_size, 2007 rte_log2_u32(attr->rq_size)); 2008 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2009 } else { 2010 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2011 } 2012 if (attr->dbr_umem_valid) { 2013 MLX5_SET(qpc, qpc, dbr_umem_valid, 2014 attr->dbr_umem_valid); 2015 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2016 } 2017 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2018 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2019 attr->wq_umem_offset); 2020 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2021 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2022 } else { 2023 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2024 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2025 MLX5_SET(qpc, qpc, no_sq, 1); 2026 } 2027 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2028 sizeof(out)); 2029 if (!qp_obj->obj) { 2030 rte_errno = errno; 2031 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2032 mlx5_free(qp_obj); 2033 return NULL; 2034 } 2035 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2036 return qp_obj; 2037 } 2038 2039 /** 2040 * Modify QP using DevX API. 2041 * Currently supports only force loop-back QP. 2042 * 2043 * @param[in] qp 2044 * Pointer to QP object structure. 2045 * @param [in] qp_st_mod_op 2046 * The QP state modification operation. 2047 * @param [in] remote_qp_id 2048 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2049 * 2050 * @return 2051 * 0 on success, a negative errno value otherwise and rte_errno is set. 2052 */ 2053 int 2054 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2055 uint32_t remote_qp_id) 2056 { 2057 union { 2058 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2059 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2060 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2061 } in; 2062 union { 2063 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2064 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2065 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2066 } out; 2067 void *qpc; 2068 int ret; 2069 unsigned int inlen; 2070 unsigned int outlen; 2071 2072 memset(&in, 0, sizeof(in)); 2073 memset(&out, 0, sizeof(out)); 2074 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2075 switch (qp_st_mod_op) { 2076 case MLX5_CMD_OP_RST2INIT_QP: 2077 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2078 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2079 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2080 MLX5_SET(qpc, qpc, rre, 1); 2081 MLX5_SET(qpc, qpc, rwe, 1); 2082 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2083 inlen = sizeof(in.rst2init); 2084 outlen = sizeof(out.rst2init); 2085 break; 2086 case MLX5_CMD_OP_INIT2RTR_QP: 2087 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2088 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2089 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2090 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2091 MLX5_SET(qpc, qpc, mtu, 1); 2092 MLX5_SET(qpc, qpc, log_msg_max, 30); 2093 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2094 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2095 inlen = sizeof(in.init2rtr); 2096 outlen = sizeof(out.init2rtr); 2097 break; 2098 case MLX5_CMD_OP_RTR2RTS_QP: 2099 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2100 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2101 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2102 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2103 MLX5_SET(qpc, qpc, retry_count, 7); 2104 MLX5_SET(qpc, qpc, rnr_retry, 7); 2105 inlen = sizeof(in.rtr2rts); 2106 outlen = sizeof(out.rtr2rts); 2107 break; 2108 default: 2109 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2110 qp_st_mod_op); 2111 rte_errno = EINVAL; 2112 return -rte_errno; 2113 } 2114 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2115 if (ret) { 2116 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2117 rte_errno = errno; 2118 return -rte_errno; 2119 } 2120 return ret; 2121 } 2122 2123 struct mlx5_devx_obj * 2124 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2125 { 2126 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2127 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2128 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2129 sizeof(*couners_obj), 0, 2130 SOCKET_ID_ANY); 2131 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2132 2133 if (!couners_obj) { 2134 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2135 rte_errno = ENOMEM; 2136 return NULL; 2137 } 2138 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2139 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2140 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2141 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2142 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2143 sizeof(out)); 2144 if (!couners_obj->obj) { 2145 rte_errno = errno; 2146 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2147 " DevX."); 2148 mlx5_free(couners_obj); 2149 return NULL; 2150 } 2151 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2152 return couners_obj; 2153 } 2154 2155 int 2156 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2157 struct mlx5_devx_virtio_q_couners_attr *attr) 2158 { 2159 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2160 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2161 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2162 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2163 virtio_q_counters); 2164 int ret; 2165 2166 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2167 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2168 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2169 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2170 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2171 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2172 sizeof(out)); 2173 if (ret) { 2174 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2175 rte_errno = errno; 2176 return -errno; 2177 } 2178 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2179 received_desc); 2180 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2181 completed_desc); 2182 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2183 error_cqes); 2184 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2185 bad_desc_errors); 2186 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2187 exceed_max_chain); 2188 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2189 invalid_buffer); 2190 return ret; 2191 } 2192 2193 /** 2194 * Create general object of type FLOW_HIT_ASO using DevX API. 2195 * 2196 * @param[in] ctx 2197 * Context returned from mlx5 open_device() glue function. 2198 * @param [in] pd 2199 * PD value to associate the FLOW_HIT_ASO object with. 2200 * 2201 * @return 2202 * The DevX object created, NULL otherwise and rte_errno is set. 2203 */ 2204 struct mlx5_devx_obj * 2205 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2206 { 2207 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2208 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2209 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2210 void *ptr = NULL; 2211 2212 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2213 0, SOCKET_ID_ANY); 2214 if (!flow_hit_aso_obj) { 2215 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2216 rte_errno = ENOMEM; 2217 return NULL; 2218 } 2219 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2220 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2221 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2222 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2223 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2224 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2225 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2226 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2227 out, sizeof(out)); 2228 if (!flow_hit_aso_obj->obj) { 2229 rte_errno = errno; 2230 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2231 mlx5_free(flow_hit_aso_obj); 2232 return NULL; 2233 } 2234 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2235 return flow_hit_aso_obj; 2236 } 2237 2238 /* 2239 * Create PD using DevX API. 2240 * 2241 * @param[in] ctx 2242 * Context returned from mlx5 open_device() glue function. 2243 * 2244 * @return 2245 * The DevX object created, NULL otherwise and rte_errno is set. 2246 */ 2247 struct mlx5_devx_obj * 2248 mlx5_devx_cmd_alloc_pd(void *ctx) 2249 { 2250 struct mlx5_devx_obj *ppd = 2251 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2252 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2253 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2254 2255 if (!ppd) { 2256 DRV_LOG(ERR, "Failed to allocate PD data."); 2257 rte_errno = ENOMEM; 2258 return NULL; 2259 } 2260 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2261 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2262 out, sizeof(out)); 2263 if (!ppd->obj) { 2264 mlx5_free(ppd); 2265 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2266 rte_errno = errno; 2267 return NULL; 2268 } 2269 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2270 return ppd; 2271 } 2272 2273 /** 2274 * Create general object of type FLOW_METER_ASO using DevX API. 2275 * 2276 * @param[in] ctx 2277 * Context returned from mlx5 open_device() glue function. 2278 * @param [in] pd 2279 * PD value to associate the FLOW_METER_ASO object with. 2280 * @param [in] log_obj_size 2281 * log_obj_size define to allocate number of 2 * meters 2282 * in one FLOW_METER_ASO object. 2283 * 2284 * @return 2285 * The DevX object created, NULL otherwise and rte_errno is set. 2286 */ 2287 struct mlx5_devx_obj * 2288 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2289 uint32_t log_obj_size) 2290 { 2291 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2292 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2293 struct mlx5_devx_obj *flow_meter_aso_obj; 2294 void *ptr; 2295 2296 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2297 sizeof(*flow_meter_aso_obj), 2298 0, SOCKET_ID_ANY); 2299 if (!flow_meter_aso_obj) { 2300 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2301 rte_errno = ENOMEM; 2302 return NULL; 2303 } 2304 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2305 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2306 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2307 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2308 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2309 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2310 log_obj_size); 2311 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2312 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2313 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2314 ctx, in, sizeof(in), 2315 out, sizeof(out)); 2316 if (!flow_meter_aso_obj->obj) { 2317 rte_errno = errno; 2318 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2319 mlx5_free(flow_meter_aso_obj); 2320 return NULL; 2321 } 2322 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2323 out, obj_id); 2324 return flow_meter_aso_obj; 2325 } 2326 2327 /** 2328 * Create general object of type GENEVE TLV option using DevX API. 2329 * 2330 * @param[in] ctx 2331 * Context returned from mlx5 open_device() glue function. 2332 * @param [in] class 2333 * TLV option variable value of class 2334 * @param [in] type 2335 * TLV option variable value of type 2336 * @param [in] len 2337 * TLV option variable value of len 2338 * 2339 * @return 2340 * The DevX object created, NULL otherwise and rte_errno is set. 2341 */ 2342 struct mlx5_devx_obj * 2343 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2344 uint16_t class, uint8_t type, uint8_t len) 2345 { 2346 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2347 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2348 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2349 sizeof(*geneve_tlv_opt_obj), 2350 0, SOCKET_ID_ANY); 2351 2352 if (!geneve_tlv_opt_obj) { 2353 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2354 rte_errno = ENOMEM; 2355 return NULL; 2356 } 2357 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2358 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2359 geneve_tlv_opt); 2360 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2361 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2362 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2363 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2364 MLX5_SET(geneve_tlv_option, opt, option_class, 2365 rte_be_to_cpu_16(class)); 2366 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2367 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2368 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2369 sizeof(in), out, sizeof(out)); 2370 if (!geneve_tlv_opt_obj->obj) { 2371 rte_errno = errno; 2372 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2373 "Obj using DevX."); 2374 mlx5_free(geneve_tlv_opt_obj); 2375 return NULL; 2376 } 2377 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2378 return geneve_tlv_opt_obj; 2379 } 2380 2381 int 2382 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2383 { 2384 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2385 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2386 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2387 int rc; 2388 void *rq_ctx; 2389 2390 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2391 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2392 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2393 if (rc) { 2394 rte_errno = errno; 2395 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2396 "rc = %d, errno = %d.", rc, errno); 2397 return -rc; 2398 }; 2399 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2400 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2401 return 0; 2402 #else 2403 (void)wq; 2404 (void)counter_set_id; 2405 return -ENOTSUP; 2406 #endif 2407 } 2408 2409 /* 2410 * Allocate queue counters via devx interface. 2411 * 2412 * @param[in] ctx 2413 * Context returned from mlx5 open_device() glue function. 2414 * 2415 * @return 2416 * Pointer to counter object on success, a NULL value otherwise and 2417 * rte_errno is set. 2418 */ 2419 struct mlx5_devx_obj * 2420 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2421 { 2422 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2423 SOCKET_ID_ANY); 2424 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2425 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2426 2427 if (!dcs) { 2428 rte_errno = ENOMEM; 2429 return NULL; 2430 } 2431 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2432 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2433 sizeof(out)); 2434 if (!dcs->obj) { 2435 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2436 "%d.", errno); 2437 rte_errno = errno; 2438 mlx5_free(dcs); 2439 return NULL; 2440 } 2441 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2442 return dcs; 2443 } 2444 2445 /** 2446 * Query queue counters values. 2447 * 2448 * @param[in] dcs 2449 * devx object of the queue counter set. 2450 * @param[in] clear 2451 * Whether hardware should clear the counters after the query or not. 2452 * @param[out] out_of_buffers 2453 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2454 * 2455 * @return 2456 * 0 on success, a negative value otherwise. 2457 */ 2458 int 2459 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2460 uint32_t *out_of_buffers) 2461 { 2462 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2463 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2464 int rc; 2465 2466 MLX5_SET(query_q_counter_in, in, opcode, 2467 MLX5_CMD_OP_QUERY_Q_COUNTER); 2468 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2469 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2470 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2471 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2472 sizeof(out)); 2473 if (rc) { 2474 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2475 rte_errno = rc; 2476 return -rc; 2477 } 2478 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2479 return 0; 2480 } 2481 2482 /** 2483 * Create general object of type DEK using DevX API. 2484 * 2485 * @param[in] ctx 2486 * Context returned from mlx5 open_device() glue function. 2487 * @param [in] attr 2488 * Pointer to DEK attributes structure. 2489 * 2490 * @return 2491 * The DevX object created, NULL otherwise and rte_errno is set. 2492 */ 2493 struct mlx5_devx_obj * 2494 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2495 { 2496 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2497 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2498 struct mlx5_devx_obj *dek_obj = NULL; 2499 void *ptr = NULL, *key_addr = NULL; 2500 2501 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2502 0, SOCKET_ID_ANY); 2503 if (dek_obj == NULL) { 2504 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2505 rte_errno = ENOMEM; 2506 return NULL; 2507 } 2508 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2509 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2510 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2511 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2512 MLX5_GENERAL_OBJ_TYPE_DEK); 2513 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2514 MLX5_SET(dek, ptr, key_size, attr->key_size); 2515 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2516 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2517 MLX5_SET(dek, ptr, pd, attr->pd); 2518 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2519 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2520 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2521 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2522 out, sizeof(out)); 2523 if (dek_obj->obj == NULL) { 2524 rte_errno = errno; 2525 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2526 mlx5_free(dek_obj); 2527 return NULL; 2528 } 2529 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2530 return dek_obj; 2531 } 2532 2533 /** 2534 * Create general object of type IMPORT_KEK using DevX API. 2535 * 2536 * @param[in] ctx 2537 * Context returned from mlx5 open_device() glue function. 2538 * @param [in] attr 2539 * Pointer to IMPORT_KEK attributes structure. 2540 * 2541 * @return 2542 * The DevX object created, NULL otherwise and rte_errno is set. 2543 */ 2544 struct mlx5_devx_obj * 2545 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2546 struct mlx5_devx_import_kek_attr *attr) 2547 { 2548 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2549 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2550 struct mlx5_devx_obj *import_kek_obj = NULL; 2551 void *ptr = NULL, *key_addr = NULL; 2552 2553 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2554 0, SOCKET_ID_ANY); 2555 if (import_kek_obj == NULL) { 2556 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2557 rte_errno = ENOMEM; 2558 return NULL; 2559 } 2560 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2561 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2562 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2563 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2564 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2565 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2566 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2567 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2568 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2569 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2570 out, sizeof(out)); 2571 if (import_kek_obj->obj == NULL) { 2572 rte_errno = errno; 2573 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2574 mlx5_free(import_kek_obj); 2575 return NULL; 2576 } 2577 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2578 return import_kek_obj; 2579 } 2580 2581 /** 2582 * Create general object of type CREDENTIAL using DevX API. 2583 * 2584 * @param[in] ctx 2585 * Context returned from mlx5 open_device() glue function. 2586 * @param [in] attr 2587 * Pointer to CREDENTIAL attributes structure. 2588 * 2589 * @return 2590 * The DevX object created, NULL otherwise and rte_errno is set. 2591 */ 2592 struct mlx5_devx_obj * 2593 mlx5_devx_cmd_create_credential_obj(void *ctx, 2594 struct mlx5_devx_credential_attr *attr) 2595 { 2596 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2597 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2598 struct mlx5_devx_obj *credential_obj = NULL; 2599 void *ptr = NULL, *credential_addr = NULL; 2600 2601 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2602 0, SOCKET_ID_ANY); 2603 if (credential_obj == NULL) { 2604 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2605 rte_errno = ENOMEM; 2606 return NULL; 2607 } 2608 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2609 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2610 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2611 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2612 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2613 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2614 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2615 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2616 memcpy(credential_addr, (void *)(attr->credential), 2617 MLX5_CRYPTO_CREDENTIAL_SIZE); 2618 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2619 out, sizeof(out)); 2620 if (credential_obj->obj == NULL) { 2621 rte_errno = errno; 2622 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2623 mlx5_free(credential_obj); 2624 return NULL; 2625 } 2626 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2627 return credential_obj; 2628 } 2629 2630 /** 2631 * Create general object of type CRYPTO_LOGIN using DevX API. 2632 * 2633 * @param[in] ctx 2634 * Context returned from mlx5 open_device() glue function. 2635 * @param [in] attr 2636 * Pointer to CRYPTO_LOGIN attributes structure. 2637 * 2638 * @return 2639 * The DevX object created, NULL otherwise and rte_errno is set. 2640 */ 2641 struct mlx5_devx_obj * 2642 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2643 struct mlx5_devx_crypto_login_attr *attr) 2644 { 2645 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2646 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2647 struct mlx5_devx_obj *crypto_login_obj = NULL; 2648 void *ptr = NULL, *credential_addr = NULL; 2649 2650 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2651 0, SOCKET_ID_ANY); 2652 if (crypto_login_obj == NULL) { 2653 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2654 rte_errno = ENOMEM; 2655 return NULL; 2656 } 2657 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2658 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2659 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2660 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2661 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2662 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2663 MLX5_SET(crypto_login, ptr, credential_pointer, 2664 attr->credential_pointer); 2665 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2666 attr->session_import_kek_ptr); 2667 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2668 memcpy(credential_addr, (void *)(attr->credential), 2669 MLX5_CRYPTO_CREDENTIAL_SIZE); 2670 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2671 out, sizeof(out)); 2672 if (crypto_login_obj->obj == NULL) { 2673 rte_errno = errno; 2674 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2675 mlx5_free(crypto_login_obj); 2676 return NULL; 2677 } 2678 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2679 return crypto_login_obj; 2680 } 2681