1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Intel Corporation 3 */ 4 5 /** 6 * @file Header file containing DPDK compilation parameters 7 * 8 * Header file containing DPDK compilation parameters. Also include the 9 * meson-generated header file containing the detected parameters that 10 * are variable across builds or build environments. 11 * 12 * NOTE: This file is only used for meson+ninja builds. For builds done 13 * using make/gmake, the rte_config.h file is autogenerated from the 14 * defconfig_* files in the config directory. 15 */ 16 #ifndef _RTE_CONFIG_H_ 17 #define _RTE_CONFIG_H_ 18 19 #include <rte_build_config.h> 20 21 /* legacy defines */ 22 #ifdef RTE_EXEC_ENV_LINUX 23 #define RTE_EXEC_ENV_LINUXAPP 1 24 #endif 25 #ifdef RTE_EXEC_ENV_FREEBSD 26 #define RTE_EXEC_ENV_BSDAPP 1 27 #endif 28 29 /****** library defines ********/ 30 31 /* compat defines */ 32 #define RTE_BUILD_SHARED_LIB 33 34 /* EAL defines */ 35 #define RTE_MAX_HEAPS 32 36 #define RTE_MAX_MEMSEG_LISTS 128 37 #define RTE_MAX_MEMSEG_PER_LIST 8192 38 #define RTE_MAX_MEM_MB_PER_LIST 32768 39 #define RTE_MAX_MEMSEG_PER_TYPE 32768 40 #define RTE_MAX_MEM_MB_PER_TYPE 65536 41 #define RTE_MAX_MEM_MB 524288 42 #define RTE_MAX_MEMZONE 2560 43 #define RTE_MAX_TAILQ 32 44 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO 45 #define RTE_BACKTRACE 1 46 #define RTE_MAX_VFIO_CONTAINERS 64 47 48 /* bsd module defines */ 49 #define RTE_CONTIGMEM_MAX_NUM_BUFS 64 50 #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1 51 #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024) 52 53 /* mempool defines */ 54 #define RTE_MEMPOOL_CACHE_MAX_SIZE 512 55 56 /* mbuf defines */ 57 #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc" 58 #define RTE_MBUF_REFCNT_ATOMIC 1 59 #define RTE_PKTMBUF_HEADROOM 128 60 61 /* ether defines */ 62 #define RTE_MAX_QUEUES_PER_PORT 1024 63 #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 64 #define RTE_ETHDEV_RXTX_CALLBACKS 1 65 66 /* cryptodev defines */ 67 #define RTE_CRYPTO_MAX_DEVS 64 68 #define RTE_CRYPTODEV_NAME_LEN 64 69 70 /* compressdev defines */ 71 #define RTE_COMPRESS_MAX_DEVS 64 72 73 /* eventdev defines */ 74 #define RTE_EVENT_MAX_DEVS 16 75 #define RTE_EVENT_MAX_QUEUES_PER_DEV 64 76 #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32 77 #define RTE_EVENT_ETH_INTR_RING_SIZE 1024 78 #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32 79 #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32 80 81 /* rawdev defines */ 82 #define RTE_RAWDEV_MAX_DEVS 10 83 84 /* ip_fragmentation defines */ 85 #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4 86 #undef RTE_LIBRTE_IP_FRAG_TBL_STAT 87 88 /* rte_power defines */ 89 #define RTE_MAX_LCORE_FREQS 64 90 91 /* rte_sched defines */ 92 #undef RTE_SCHED_RED 93 #undef RTE_SCHED_COLLECT_STATS 94 #undef RTE_SCHED_SUBPORT_TC_OV 95 #define RTE_SCHED_PORT_N_GRINDERS 8 96 #undef RTE_SCHED_VECTOR 97 98 /****** driver defines ********/ 99 100 /* QuickAssist device */ 101 /* Max. number of QuickAssist devices which can be attached */ 102 #define RTE_PMD_QAT_MAX_PCI_DEVICES 48 103 #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16 104 #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536 105 106 /* virtio crypto defines */ 107 #define RTE_MAX_VIRTIO_CRYPTO 32 108 109 /* DPAA SEC max cryptodev devices*/ 110 #define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 111 112 /* fm10k defines */ 113 #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 114 115 /* i40e defines */ 116 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1 117 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC 118 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64 119 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 120 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4 121 122 /* Ring net PMD settings */ 123 #define RTE_PMD_RING_MAX_RX_RINGS 16 124 #define RTE_PMD_RING_MAX_TX_RINGS 16 125 126 /* QEDE PMD defines */ 127 #define RTE_LIBRTE_QEDE_FW "" 128 129 #endif /* _RTE_CONFIG_H_ */ 130