xref: /dpdk/config/arm/meson.build (revision bb07d96d) 
1# SPDX-License-Identifier: BSD-3-Clause
2# Copyright(c) 2017 Intel Corporation.
3# Copyright(c) 2017 Cavium, Inc
4
5# common flags to all aarch64 builds, with lowest priority
6flags_common = [
7	# Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
8	# to determine the best threshold in code. Refer to notes in source file
9	# (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
10	['RTE_ARCH_ARM64_MEMCPY', false],
11	#	['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
12	#	['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
13	# Leave below RTE_ARM64_MEMCPY_xxx options commented out,
14	# unless there are strong reasons.
15	#	['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
16	#	['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
17	#	['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
18
19	['RTE_NET_FM10K', false],
20	['RTE_NET_AVP', false],
21
22	['RTE_SCHED_VECTOR', false],
23	['RTE_ARM_USE_WFE', false],
24	['RTE_ARCH_ARM64', true],
25	['RTE_CACHE_LINE_SIZE', 128]
26]
27
28## Part numbers are specific to Arm implementers
29# implementer specific aarch64 flags have middle priority
30#     (will overwrite common flags)
31# part number specific aarch64 flags have the highest priority
32#     (will overwrite both common and implementer specific flags)
33implementer_generic = {
34	'description': 'Generic armv8',
35	'flags': [
36		['RTE_MACHINE', '"armv8a"'],
37		['RTE_USE_C11_MEM_MODEL', true],
38		['RTE_MAX_LCORE', 256],
39		['RTE_MAX_NUMA_NODES', 4]
40	],
41	'part_number_config': {
42		'generic': {'machine_args': ['-march=armv8-a+crc',
43					     '-moutline-atomics']}
44	}
45}
46
47part_number_config_arm = {
48	'0xd03': {'machine_args':  ['-mcpu=cortex-a53']},
49	'0xd04': {'machine_args':  ['-mcpu=cortex-a35']},
50	'0xd07': {'machine_args':  ['-mcpu=cortex-a57']},
51	'0xd08': {'machine_args':  ['-mcpu=cortex-a72']},
52	'0xd09': {'machine_args':  ['-mcpu=cortex-a73']},
53	'0xd0a': {'machine_args':  ['-mcpu=cortex-a75']},
54	'0xd0b': {'machine_args':  ['-mcpu=cortex-a76']},
55	'0xd0c': {
56		'machine_args':  ['-march=armv8.2-a+crypto',
57				  '-mcpu=neoverse-n1'],
58		'flags': [
59			['RTE_MACHINE', '"neoverse-n1"'],
60			['RTE_ARM_FEATURE_ATOMICS', true],
61			['RTE_MAX_MEM_MB', 1048576],
62			['RTE_MAX_LCORE', 80]
63		]
64	},
65	'0xd49': {
66		'machine_args':  ['-march=armv8.5-a+crypto+sve2'],
67		'flags': [
68			['RTE_MACHINE', '"neoverse-n2"'],
69			['RTE_ARM_FEATURE_ATOMICS', true],
70			['RTE_MAX_LCORE', 64]
71		]
72	}
73}
74implementer_arm = {
75	'description': 'Arm',
76	'flags': [
77		['RTE_MACHINE', '"armv8a"'],
78		['RTE_USE_C11_MEM_MODEL', true],
79		['RTE_CACHE_LINE_SIZE', 64],
80		['RTE_MAX_LCORE', 16],
81		['RTE_MAX_NUMA_NODES', 1]
82	],
83	'part_number_config': part_number_config_arm
84}
85
86flags_part_number_thunderx = [
87	['RTE_MACHINE', '"thunderx"'],
88	['RTE_USE_C11_MEM_MODEL', false]
89]
90implementer_cavium = {
91	'description': 'Cavium',
92	'flags': [
93		['RTE_MAX_VFIO_GROUPS', 128],
94		['RTE_MAX_LCORE', 96],
95		['RTE_MAX_NUMA_NODES', 2]
96	],
97	'part_number_config': {
98		'0xa1': {
99			'machine_args': ['-mcpu=thunderxt88'],
100			'flags': flags_part_number_thunderx
101		},
102		'0xa2': {
103			'machine_args': ['-mcpu=thunderxt81'],
104			'flags': flags_part_number_thunderx
105		},
106		'0xa3': {
107			'machine_args': ['-mcpu=thunderxt83'],
108			'flags': flags_part_number_thunderx
109		},
110		'0xaf': {
111			'machine_args': ['-march=armv8.1-a+crc+crypto',
112					 '-mcpu=thunderx2t99'],
113			'flags': [
114				['RTE_MACHINE', '"thunderx2"'],
115				['RTE_ARM_FEATURE_ATOMICS', true],
116				['RTE_USE_C11_MEM_MODEL', true],
117				['RTE_CACHE_LINE_SIZE', 64],
118				['RTE_MAX_LCORE', 256]
119			]
120		},
121		'0xb2': {
122			'machine_args': ['-march=armv8.2-a+crc+crypto+lse',
123					 '-mcpu=octeontx2'],
124			'flags': [
125				['RTE_MACHINE', '"octeontx2"'],
126				['RTE_ARM_FEATURE_ATOMICS', true],
127				['RTE_USE_C11_MEM_MODEL', true],
128				['RTE_EAL_IGB_UIO', false],
129				['RTE_MAX_LCORE', 36],
130				['RTE_MAX_NUMA_NODES', 1]
131			]
132		}
133	}
134}
135
136implementer_ampere = {
137	'description': 'Ampere Computing',
138	'flags': [
139		['RTE_MACHINE', '"emag"'],
140		['RTE_CACHE_LINE_SIZE', 64],
141		['RTE_MAX_LCORE', 32],
142		['RTE_MAX_NUMA_NODES', 1]
143	],
144	'part_number_config': {
145		'0x0': {'machine_args':  ['-march=armv8-a+crc+crypto',
146					  '-mtune=emag']}
147	}
148}
149
150implementer_qualcomm = {
151	'description': 'Qualcomm',
152	'flags': [
153		['RTE_MACHINE', '"armv8a"'],
154		['RTE_USE_C11_MEM_MODEL', true],
155		['RTE_CACHE_LINE_SIZE', 64],
156		['RTE_MAX_LCORE', 64],
157		['RTE_MAX_NUMA_NODES', 1]
158	],
159	'part_number_config': {
160		'0xc00': {'machine_args':  ['-march=armv8-a+crc']}
161	}
162}
163
164implementer_marvell = {
165	'description': 'Marvell ARMADA',
166	'flags': [
167		['RTE_MACHINE', '"armv8a"'],
168		['RTE_CACHE_LINE_SIZE', 64],
169		['RTE_MAX_LCORE', 16],
170		['RTE_MAX_NUMA_NODES', 1]
171	],
172	'part_number_config': part_number_config_arm
173}
174
175implementer_dpaa = {
176	'description': 'NXP DPAA',
177	'flags': [
178		['RTE_MACHINE', '"dpaa"'],
179		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
180		['RTE_USE_C11_MEM_MODEL', true],
181		['RTE_CACHE_LINE_SIZE', 64],
182		['RTE_MAX_LCORE', 16],
183		['RTE_MAX_NUMA_NODES', 1]
184	],
185	'part_number_config': part_number_config_arm
186}
187
188## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
189implementers = {
190	'generic': implementer_generic,
191	'0x41': implementer_arm,
192	'0x43': implementer_cavium,
193	'0x50': implementer_ampere,
194	'0x51': implementer_qualcomm,
195	'0x56': implementer_marvell,
196	'dpaa': implementer_dpaa
197}
198
199dpdk_conf.set('RTE_ARCH_ARM', 1)
200dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
201
202if dpdk_conf.get('RTE_ARCH_32')
203	# armv7 build
204	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
205	dpdk_conf.set('RTE_ARCH_ARMv7', 1)
206	# the minimum architecture supported, armv7-a, needs the following,
207	machine_args += '-mfpu=neon'
208else
209	# aarch64 build
210	if not meson.is_cross_build()
211		if machine == 'default'
212			# default build
213			implementer_id = 'generic'
214			part_number = 'generic'
215		else
216			# native build
217			# The script returns ['Implementer', 'Variant', 'Architecture',
218			# 'Primary Part number', 'Revision']
219			detect_vendor = find_program(join_paths(
220					meson.current_source_dir(), 'armv8_machine.py'))
221			cmd = run_command(detect_vendor.path())
222			if cmd.returncode() == 0
223				cmd_output = cmd.stdout().to_lower().strip().split(' ')
224				implementer_id = cmd_output[0]
225				part_number = cmd_output[3]
226			else
227				error('Error when getting Arm Implementer ID and part number.')
228			endif
229		endif
230	else
231		# cross build
232		implementer_id = meson.get_cross_property('implementer_id')
233		part_number = meson.get_cross_property('part_number')
234	endif
235
236	if implementers.has_key(implementer_id)
237		implementer_config = implementers[implementer_id]
238	else
239		error('Unsupported Arm implementer: @0@. '.format(implementer_id) +
240		      'Please add support for it or use the generic ' +
241		      '(-Dmachine=generic) build.')
242	endif
243
244	message('Arm implementer: ' + implementer_config['description'])
245	message('Arm part number: ' + part_number)
246
247	part_number_config = implementer_config['part_number_config']
248	if part_number_config.has_key(part_number)
249		# use the specified part_number machine args if found
250		part_number_config = part_number_config[part_number]
251	else
252		# unknown part number
253		error('Unsupported part number @0@ of implementer @1@. '
254		      .format(part_number, implementer_id) +
255		      'Please add support for it or use the generic ' +
256		      '(-Dmachine=generic) build.')
257	endif
258
259	# use default flags with implementer flags
260	dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', [])
261
262	# apply supported machine args
263	machine_args = [] # Clear previous machine args
264	foreach flag: part_number_config['machine_args']
265		if cc.has_argument(flag)
266			machine_args += flag
267		endif
268	endforeach
269
270	# apply flags
271	foreach flag: dpdk_flags
272		if flag.length() > 0
273			dpdk_conf.set(flag[0], flag[1])
274		endif
275	endforeach
276endif
277message('Using machine args: @0@'.format(machine_args))
278
279if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
280    cc.get_define('__aarch64__', args: machine_args) != '')
281	compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
282endif
283
284if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
285	compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
286endif
287
288if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
289	compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
290	'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
291endif
292