1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015 Akamai Technologies. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "test.h" 35 36 #include <stdio.h> 37 #include <unistd.h> 38 #include <inttypes.h> 39 #include <rte_cycles.h> 40 #include <rte_timer.h> 41 #include <rte_common.h> 42 #include <rte_lcore.h> 43 #include <rte_random.h> 44 #include <rte_malloc.h> 45 46 #undef TEST_TIMER_RACECOND_VERBOSE 47 48 #ifdef RTE_EXEC_ENV_LINUXAPP 49 #define usec_delay(us) usleep(us) 50 #else 51 #define usec_delay(us) rte_delay_us(us) 52 #endif 53 54 #define BILLION (1UL << 30) 55 56 #define TEST_DURATION_S 20 /* in seconds */ 57 #define N_TIMERS 50 58 59 static struct rte_timer timer[N_TIMERS]; 60 static unsigned timer_lcore_id[N_TIMERS]; 61 62 static unsigned master; 63 static volatile unsigned stop_slaves; 64 65 static int reload_timer(struct rte_timer *tim); 66 67 static void 68 timer_cb(struct rte_timer *tim, void *arg __rte_unused) 69 { 70 /* Simulate slow callback function, 100 us. */ 71 rte_delay_us(100); 72 73 #ifdef TEST_TIMER_RACECOND_VERBOSE 74 if (tim == &timer[0]) 75 printf("------------------------------------------------\n"); 76 printf("timer_cb: core %u timer %lu\n", 77 rte_lcore_id(), tim - timer); 78 #endif 79 (void)reload_timer(tim); 80 } 81 82 RTE_DEFINE_PER_LCORE(unsigned, n_reset_collisions); 83 84 static int 85 reload_timer(struct rte_timer *tim) 86 { 87 /* Make timer expire roughly when the TSC hits the next BILLION 88 * multiple. Add in timer's index to make them expire in nearly 89 * sorted order. This makes all timers somewhat synchronized, 90 * firing ~2-3 times per second, assuming 2-3 GHz TSCs. 91 */ 92 uint64_t ticks = BILLION - (rte_get_timer_cycles() % BILLION) + 93 (tim - timer); 94 int ret; 95 96 ret = rte_timer_reset(tim, ticks, PERIODICAL, master, timer_cb, NULL); 97 if (ret != 0) { 98 #ifdef TEST_TIMER_RACECOND_VERBOSE 99 printf("- core %u failed to reset timer %lu (OK)\n", 100 rte_lcore_id(), tim - timer); 101 #endif 102 RTE_PER_LCORE(n_reset_collisions) += 1; 103 } 104 return ret; 105 } 106 107 static int 108 slave_main_loop(__attribute__((unused)) void *arg) 109 { 110 unsigned lcore_id = rte_lcore_id(); 111 unsigned i; 112 113 RTE_PER_LCORE(n_reset_collisions) = 0; 114 115 printf("Starting main loop on core %u\n", lcore_id); 116 117 while (!stop_slaves) { 118 /* Wait until the timer manager is running. 119 * We know it's running when we see timer[0] NOT pending. 120 */ 121 if (rte_timer_pending(&timer[0])) { 122 rte_pause(); 123 continue; 124 } 125 126 /* Now, go cause some havoc! 127 * Reload our timers. 128 */ 129 for (i = 0; i < N_TIMERS; i++) { 130 if (timer_lcore_id[i] == lcore_id) 131 (void)reload_timer(&timer[i]); 132 } 133 usec_delay(100*1000); /* sleep 100 ms */ 134 } 135 136 if (RTE_PER_LCORE(n_reset_collisions) != 0) { 137 printf("- core %u, %u reset collisions (OK)\n", 138 lcore_id, RTE_PER_LCORE(n_reset_collisions)); 139 } 140 return 0; 141 } 142 143 static int 144 test_timer_racecond(void) 145 { 146 int ret; 147 uint64_t hz; 148 uint64_t cur_time; 149 uint64_t end_time; 150 int64_t diff = 0; 151 unsigned lcore_id; 152 unsigned i; 153 154 master = lcore_id = rte_lcore_id(); 155 hz = rte_get_timer_hz(); 156 157 /* init and start timers */ 158 for (i = 0; i < N_TIMERS; i++) { 159 rte_timer_init(&timer[i]); 160 ret = reload_timer(&timer[i]); 161 TEST_ASSERT(ret == 0, "reload_timer failed"); 162 163 /* Distribute timers to slaves. 164 * Note that we assign timer[0] to the master. 165 */ 166 timer_lcore_id[i] = lcore_id; 167 lcore_id = rte_get_next_lcore(lcore_id, 1, 1); 168 } 169 170 /* calculate the "end of test" time */ 171 cur_time = rte_get_timer_cycles(); 172 end_time = cur_time + (hz * TEST_DURATION_S); 173 174 /* start slave cores */ 175 stop_slaves = 0; 176 printf("Start timer manage race condition test (%u seconds)\n", 177 TEST_DURATION_S); 178 rte_eal_mp_remote_launch(slave_main_loop, NULL, SKIP_MASTER); 179 180 while (diff >= 0) { 181 /* run the timers */ 182 rte_timer_manage(); 183 184 /* wait 100 ms */ 185 usec_delay(100*1000); 186 187 cur_time = rte_get_timer_cycles(); 188 diff = end_time - cur_time; 189 } 190 191 /* stop slave cores */ 192 printf("Stopping timer manage race condition test\n"); 193 stop_slaves = 1; 194 rte_eal_mp_wait_lcore(); 195 196 /* stop timers */ 197 for (i = 0; i < N_TIMERS; i++) { 198 ret = rte_timer_stop(&timer[i]); 199 TEST_ASSERT(ret == 0, "rte_timer_stop failed"); 200 } 201 202 return TEST_SUCCESS; 203 } 204 205 REGISTER_TEST_COMMAND(timer_racecond_autotest, test_timer_racecond); 206