1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015 Akamai Technologies. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "test.h" 35 36 #include <stdio.h> 37 #include <unistd.h> 38 #include <inttypes.h> 39 #include <rte_cycles.h> 40 #include <rte_timer.h> 41 #include <rte_common.h> 42 #include <rte_lcore.h> 43 #include <rte_random.h> 44 #include <rte_malloc.h> 45 #include <rte_pause.h> 46 47 #undef TEST_TIMER_RACECOND_VERBOSE 48 49 #ifdef RTE_EXEC_ENV_LINUX 50 #define usec_delay(us) usleep(us) 51 #else 52 #define usec_delay(us) rte_delay_us(us) 53 #endif 54 55 #define BILLION (1UL << 30) 56 57 #define TEST_DURATION_S 4 /* in seconds */ 58 #define N_TIMERS 50 59 60 static struct rte_timer timer[N_TIMERS]; 61 static unsigned timer_lcore_id[N_TIMERS]; 62 63 static unsigned master; 64 static volatile unsigned stop_slaves; 65 66 static int reload_timer(struct rte_timer *tim); 67 68 static void 69 timer_cb(struct rte_timer *tim, void *arg __rte_unused) 70 { 71 /* Simulate slow callback function, 100 us. */ 72 rte_delay_us(100); 73 74 #ifdef TEST_TIMER_RACECOND_VERBOSE 75 if (tim == &timer[0]) 76 printf("------------------------------------------------\n"); 77 printf("timer_cb: core %u timer %lu\n", 78 rte_lcore_id(), tim - timer); 79 #endif 80 (void)reload_timer(tim); 81 } 82 83 RTE_DEFINE_PER_LCORE(unsigned, n_reset_collisions); 84 85 static int 86 reload_timer(struct rte_timer *tim) 87 { 88 /* Make timer expire roughly when the TSC hits the next BILLION 89 * multiple. Add in timer's index to make them expire in nearly 90 * sorted order. This makes all timers somewhat synchronized, 91 * firing ~2-3 times per second, assuming 2-3 GHz TSCs. 92 */ 93 uint64_t ticks = BILLION - (rte_get_timer_cycles() % BILLION) + 94 (tim - timer); 95 int ret; 96 97 ret = rte_timer_reset(tim, ticks, PERIODICAL, master, timer_cb, NULL); 98 if (ret != 0) { 99 #ifdef TEST_TIMER_RACECOND_VERBOSE 100 printf("- core %u failed to reset timer %lu (OK)\n", 101 rte_lcore_id(), tim - timer); 102 #endif 103 RTE_PER_LCORE(n_reset_collisions) += 1; 104 } 105 return ret; 106 } 107 108 static int 109 slave_main_loop(__attribute__((unused)) void *arg) 110 { 111 unsigned lcore_id = rte_lcore_id(); 112 unsigned i; 113 114 RTE_PER_LCORE(n_reset_collisions) = 0; 115 116 printf("Starting main loop on core %u\n", lcore_id); 117 118 while (!stop_slaves) { 119 /* Wait until the timer manager is running. 120 * We know it's running when we see timer[0] NOT pending. 121 */ 122 if (rte_timer_pending(&timer[0])) { 123 rte_pause(); 124 continue; 125 } 126 127 /* Now, go cause some havoc! 128 * Reload our timers. 129 */ 130 for (i = 0; i < N_TIMERS; i++) { 131 if (timer_lcore_id[i] == lcore_id) 132 (void)reload_timer(&timer[i]); 133 } 134 usec_delay(100*1000); /* sleep 100 ms */ 135 } 136 137 if (RTE_PER_LCORE(n_reset_collisions) != 0) { 138 printf("- core %u, %u reset collisions (OK)\n", 139 lcore_id, RTE_PER_LCORE(n_reset_collisions)); 140 } 141 return 0; 142 } 143 144 static int 145 test_timer_racecond(void) 146 { 147 int ret; 148 uint64_t hz; 149 uint64_t cur_time; 150 uint64_t end_time; 151 int64_t diff = 0; 152 unsigned lcore_id; 153 unsigned i; 154 155 master = lcore_id = rte_lcore_id(); 156 hz = rte_get_timer_hz(); 157 158 /* init and start timers */ 159 for (i = 0; i < N_TIMERS; i++) { 160 rte_timer_init(&timer[i]); 161 ret = reload_timer(&timer[i]); 162 TEST_ASSERT(ret == 0, "reload_timer failed"); 163 164 /* Distribute timers to slaves. 165 * Note that we assign timer[0] to the master. 166 */ 167 timer_lcore_id[i] = lcore_id; 168 lcore_id = rte_get_next_lcore(lcore_id, 1, 1); 169 } 170 171 /* calculate the "end of test" time */ 172 cur_time = rte_get_timer_cycles(); 173 end_time = cur_time + (hz * TEST_DURATION_S); 174 175 /* start slave cores */ 176 stop_slaves = 0; 177 printf("Start timer manage race condition test (%u seconds)\n", 178 TEST_DURATION_S); 179 rte_eal_mp_remote_launch(slave_main_loop, NULL, SKIP_MASTER); 180 181 while (diff >= 0) { 182 /* run the timers */ 183 rte_timer_manage(); 184 185 /* wait 100 ms */ 186 usec_delay(100*1000); 187 188 cur_time = rte_get_timer_cycles(); 189 diff = end_time - cur_time; 190 } 191 192 /* stop slave cores */ 193 printf("Stopping timer manage race condition test\n"); 194 stop_slaves = 1; 195 rte_eal_mp_wait_lcore(); 196 197 /* stop timers */ 198 for (i = 0; i < N_TIMERS; i++) { 199 ret = rte_timer_stop(&timer[i]); 200 TEST_ASSERT(ret == 0, "rte_timer_stop failed"); 201 } 202 203 return TEST_SUCCESS; 204 } 205 206 REGISTER_TEST_COMMAND(timer_racecond_autotest, test_timer_racecond); 207