1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Timer 37 * ===== 38 * 39 * #. Stress tests. 40 * 41 * The objective of the timer stress tests is to check that there are no 42 * race conditions in list and status management. This test launches, 43 * resets and stops the timer very often on many cores at the same 44 * time. 45 * 46 * - Only one timer is used for this test. 47 * - On each core, the rte_timer_manage() function is called from the main 48 * loop every 3 microseconds. 49 * - In the main loop, the timer may be reset (randomly, with a 50 * probability of 0.5 %) 100 microseconds later on a random core, or 51 * stopped (with a probability of 0.5 % also). 52 * - In callback, the timer is can be reset (randomly, with a 53 * probability of 0.5 %) 100 microseconds later on the same core or 54 * on another core (same probability), or stopped (same 55 * probability). 56 * 57 * 58 * #. Basic test. 59 * 60 * This test performs basic functional checks of the timers. The test 61 * uses four different timers that are loaded and stopped under 62 * specific conditions in specific contexts. 63 * 64 * - Four timers are used for this test. 65 * - On each core, the rte_timer_manage() function is called from main loop 66 * every 3 microseconds. 67 * 68 * The autotest python script checks that the behavior is correct: 69 * 70 * - timer0 71 * 72 * - At initialization, timer0 is loaded by the master core, on master core 73 * in "single" mode (time = 1 second). 74 * - In the first 19 callbacks, timer0 is reloaded on the same core, 75 * then, it is explicitly stopped at the 20th call. 76 * - At t=25s, timer0 is reloaded once by timer2. 77 * 78 * - timer1 79 * 80 * - At initialization, timer1 is loaded by the master core, on the 81 * master core in "single" mode (time = 2 seconds). 82 * - In the first 9 callbacks, timer1 is reloaded on another 83 * core. After the 10th callback, timer1 is not reloaded anymore. 84 * 85 * - timer2 86 * 87 * - At initialization, timer2 is loaded by the master core, on the 88 * master core in "periodical" mode (time = 1 second). 89 * - In the callback, when t=25s, it stops timer3 and reloads timer0 90 * on the current core. 91 * 92 * - timer3 93 * 94 * - At initialization, timer3 is loaded by the master core, on 95 * another core in "periodical" mode (time = 1 second). 96 * - It is stopped at t=25s by timer2. 97 */ 98 99 #include <stdio.h> 100 #include <stdarg.h> 101 #include <string.h> 102 #include <stdlib.h> 103 #include <stdint.h> 104 #include <inttypes.h> 105 #include <sys/queue.h> 106 107 #include <cmdline_parse.h> 108 109 #include <rte_common.h> 110 #include <rte_log.h> 111 #include <rte_memory.h> 112 #include <rte_memzone.h> 113 #include <rte_launch.h> 114 #include <rte_cycles.h> 115 #include <rte_tailq.h> 116 #include <rte_eal.h> 117 #include <rte_per_lcore.h> 118 #include <rte_lcore.h> 119 #include <rte_atomic.h> 120 #include <rte_timer.h> 121 #include <rte_random.h> 122 123 #include "test.h" 124 125 #define TEST_DURATION_S 30 /* in seconds */ 126 #define NB_TIMER 4 127 128 #define RTE_LOGTYPE_TESTTIMER RTE_LOGTYPE_USER3 129 130 static volatile uint64_t end_time; 131 132 struct mytimerinfo { 133 struct rte_timer tim; 134 unsigned id; 135 unsigned count; 136 }; 137 138 static struct mytimerinfo mytiminfo[NB_TIMER]; 139 140 static void timer_basic_cb(struct rte_timer *tim, void *arg); 141 142 static void 143 mytimer_reset(struct mytimerinfo *timinfo, unsigned ticks, 144 enum rte_timer_type type, unsigned tim_lcore, 145 rte_timer_cb_t fct) 146 { 147 rte_timer_reset_sync(&timinfo->tim, ticks, type, tim_lcore, 148 fct, timinfo); 149 } 150 151 /* timer callback for stress tests */ 152 static void 153 timer_stress_cb(__attribute__((unused)) struct rte_timer *tim, 154 __attribute__((unused)) void *arg) 155 { 156 long r; 157 unsigned lcore_id = rte_lcore_id(); 158 uint64_t hz = rte_get_hpet_hz(); 159 160 if (rte_timer_pending(tim)) 161 return; 162 163 r = rte_rand(); 164 if ((r & 0xff) == 0) { 165 mytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id, 166 timer_stress_cb); 167 } 168 else if ((r & 0xff) == 1) { 169 mytimer_reset(&mytiminfo[0], hz, SINGLE, 170 rte_get_next_lcore(lcore_id, 0, 1), 171 timer_stress_cb); 172 } 173 else if ((r & 0xff) == 2) { 174 rte_timer_stop(&mytiminfo[0].tim); 175 } 176 } 177 178 static int 179 timer_stress_main_loop(__attribute__((unused)) void *arg) 180 { 181 uint64_t hz = rte_get_hpet_hz(); 182 unsigned lcore_id = rte_lcore_id(); 183 uint64_t cur_time; 184 int64_t diff = 0; 185 long r; 186 187 while (diff >= 0) { 188 189 /* call the timer handler on each core */ 190 rte_timer_manage(); 191 192 /* simulate the processing of a packet 193 * (3 us = 6000 cycles at 2 Ghz) */ 194 rte_delay_us(3); 195 196 /* randomly stop or reset timer */ 197 r = rte_rand(); 198 lcore_id = rte_get_next_lcore(lcore_id, 0, 1); 199 if ((r & 0xff) == 0) { 200 /* 100 us */ 201 mytimer_reset(&mytiminfo[0], hz/10000, SINGLE, lcore_id, 202 timer_stress_cb); 203 } 204 else if ((r & 0xff) == 1) { 205 rte_timer_stop_sync(&mytiminfo[0].tim); 206 } 207 cur_time = rte_get_hpet_cycles(); 208 diff = end_time - cur_time; 209 } 210 211 lcore_id = rte_lcore_id(); 212 RTE_LOG(INFO, TESTTIMER, "core %u finished\n", lcore_id); 213 214 return 0; 215 } 216 217 /* timer callback for basic tests */ 218 static void 219 timer_basic_cb(struct rte_timer *tim, void *arg) 220 { 221 struct mytimerinfo *timinfo = arg; 222 uint64_t hz = rte_get_hpet_hz(); 223 unsigned lcore_id = rte_lcore_id(); 224 uint64_t cur_time = rte_get_hpet_cycles(); 225 226 if (rte_timer_pending(tim)) 227 return; 228 229 timinfo->count ++; 230 231 RTE_LOG(INFO, TESTTIMER, 232 "%"PRIu64": callback id=%u count=%u on core %u\n", 233 cur_time, timinfo->id, timinfo->count, lcore_id); 234 235 /* reload timer 0 on same core */ 236 if (timinfo->id == 0 && timinfo->count < 20) { 237 mytimer_reset(timinfo, hz, SINGLE, lcore_id, timer_basic_cb); 238 return; 239 } 240 241 /* reload timer 1 on next core */ 242 if (timinfo->id == 1 && timinfo->count < 10) { 243 mytimer_reset(timinfo, hz*2, SINGLE, 244 rte_get_next_lcore(lcore_id, 0, 1), 245 timer_basic_cb); 246 return; 247 } 248 249 /* Explicitelly stop timer 0. Once stop() called, we can even 250 * erase the content of the structure: it is not referenced 251 * anymore by any code (in case of dynamic structure, it can 252 * be freed) */ 253 if (timinfo->id == 0 && timinfo->count == 20) { 254 255 /* stop_sync() is not needed, because we know that the 256 * status of timer is only modified by this core */ 257 rte_timer_stop(tim); 258 memset(tim, 0xAA, sizeof(struct rte_timer)); 259 return; 260 } 261 262 /* stop timer3, and restart a new timer0 (it was removed 5 263 * seconds ago) for a single shot */ 264 if (timinfo->id == 2 && timinfo->count == 25) { 265 rte_timer_stop_sync(&mytiminfo[3].tim); 266 267 /* need to reinit because structure was erased with 0xAA */ 268 rte_timer_init(&mytiminfo[0].tim); 269 mytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id, 270 timer_basic_cb); 271 } 272 } 273 274 static int 275 timer_basic_main_loop(__attribute__((unused)) void *arg) 276 { 277 uint64_t hz = rte_get_hpet_hz(); 278 unsigned lcore_id = rte_lcore_id(); 279 uint64_t cur_time; 280 int64_t diff = 0; 281 282 /* launch all timers on core 0 */ 283 if (lcore_id == rte_get_master_lcore()) { 284 mytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id, 285 timer_basic_cb); 286 mytimer_reset(&mytiminfo[1], hz*2, SINGLE, lcore_id, 287 timer_basic_cb); 288 mytimer_reset(&mytiminfo[2], hz, PERIODICAL, lcore_id, 289 timer_basic_cb); 290 mytimer_reset(&mytiminfo[3], hz, PERIODICAL, 291 rte_get_next_lcore(lcore_id, 0, 1), 292 timer_basic_cb); 293 } 294 295 while (diff >= 0) { 296 297 /* call the timer handler on each core */ 298 rte_timer_manage(); 299 300 /* simulate the processing of a packet 301 * (3 us = 6000 cycles at 2 Ghz) */ 302 rte_delay_us(3); 303 304 cur_time = rte_get_hpet_cycles(); 305 diff = end_time - cur_time; 306 } 307 RTE_LOG(INFO, TESTTIMER, "core %u finished\n", lcore_id); 308 309 return 0; 310 } 311 312 int 313 test_timer(void) 314 { 315 unsigned i; 316 uint64_t cur_time; 317 uint64_t hz; 318 319 if (rte_lcore_count() < 2) { 320 printf("not enough lcores for this test\n"); 321 return -1; 322 } 323 324 /* init timer */ 325 for (i=0; i<NB_TIMER; i++) { 326 memset(&mytiminfo[i], 0, sizeof(struct mytimerinfo)); 327 mytiminfo[i].id = i; 328 rte_timer_init(&mytiminfo[i].tim); 329 } 330 331 /* calculate the "end of test" time */ 332 cur_time = rte_get_hpet_cycles(); 333 hz = rte_get_hpet_hz(); 334 end_time = cur_time + (hz * TEST_DURATION_S); 335 336 /* start other cores */ 337 printf("Start timer stress tests (%d seconds)\n", TEST_DURATION_S); 338 rte_eal_mp_remote_launch(timer_stress_main_loop, NULL, CALL_MASTER); 339 rte_eal_mp_wait_lcore(); 340 341 /* stop timer 0 used for stress test */ 342 rte_timer_stop_sync(&mytiminfo[0].tim); 343 344 /* calculate the "end of test" time */ 345 cur_time = rte_get_hpet_cycles(); 346 hz = rte_get_hpet_hz(); 347 end_time = cur_time + (hz * TEST_DURATION_S); 348 349 /* start other cores */ 350 printf("Start timer basic tests (%d seconds)\n", TEST_DURATION_S); 351 rte_eal_mp_remote_launch(timer_basic_main_loop, NULL, CALL_MASTER); 352 rte_eal_mp_wait_lcore(); 353 354 /* stop all timers */ 355 for (i=0; i<NB_TIMER; i++) { 356 rte_timer_stop_sync(&mytiminfo[i].tim); 357 } 358 359 rte_timer_dump_stats(); 360 361 return 0; 362 } 363