1*d883e6e7SAkhil Goyal /* SPDX-License-Identifier: BSD-3-Clause 2*d883e6e7SAkhil Goyal * Copyright 2019 NXP 3*d883e6e7SAkhil Goyal */ 4*d883e6e7SAkhil Goyal 5*d883e6e7SAkhil Goyal #ifndef SECURITY_PDCP_TEST_FUNC_H_ 6*d883e6e7SAkhil Goyal #define SECURITY_PDCP_TEST_FUNC_H_ 7*d883e6e7SAkhil Goyal 8*d883e6e7SAkhil Goyal #define PDCP_CPLANE_OFFSET 0 9*d883e6e7SAkhil Goyal #define PDCP_CPLANE_LONG_SN_OFFSET 32 10*d883e6e7SAkhil Goyal #define LONG_SEQ_NUM_OFFSET 0 11*d883e6e7SAkhil Goyal #define SHORT_SEQ_NUM_OFFSET 2 12*d883e6e7SAkhil Goyal #define FIFTEEN_BIT_SEQ_NUM_OFFSET 4 13*d883e6e7SAkhil Goyal #define EIGHTEEN_BIT_SEQ_NUM_OFFSET 6 14*d883e6e7SAkhil Goyal #define UPLINK 0 15*d883e6e7SAkhil Goyal #define DOWNLINK 1 16*d883e6e7SAkhil Goyal /* key length(in bytes) for F8 */ 17*d883e6e7SAkhil Goyal #define F8_KEY_LEN 16 18*d883e6e7SAkhil Goyal 19*d883e6e7SAkhil Goyal enum enc_alg_off { 20*d883e6e7SAkhil Goyal NULL_ENC = 0, 21*d883e6e7SAkhil Goyal SNOW_ENC = 8, 22*d883e6e7SAkhil Goyal AES_ENC = 16, 23*d883e6e7SAkhil Goyal ZUC_ENC = 24 24*d883e6e7SAkhil Goyal }; 25*d883e6e7SAkhil Goyal enum auth_alg_off { 26*d883e6e7SAkhil Goyal NULL_AUTH = 0, 27*d883e6e7SAkhil Goyal SNOW_AUTH = 2, 28*d883e6e7SAkhil Goyal AES_AUTH = 4, 29*d883e6e7SAkhil Goyal ZUC_AUTH = 6 30*d883e6e7SAkhil Goyal }; 31*d883e6e7SAkhil Goyal 32*d883e6e7SAkhil Goyal int test_pdcp_proto_cplane_encap(int i); 33*d883e6e7SAkhil Goyal 34*d883e6e7SAkhil Goyal int test_PDCP_PROTO_cplane_encap_all(void); 35*d883e6e7SAkhil Goyal 36*d883e6e7SAkhil Goyal #endif /* SECURITY_PDCP_TEST_FUNC_H_ */ 37