1f714a188SAmr Mokhtar /* SPDX-License-Identifier: BSD-3-Clause 2f714a188SAmr Mokhtar * Copyright(c) 2017 Intel Corporation 3f714a188SAmr Mokhtar */ 4f714a188SAmr Mokhtar 5f714a188SAmr Mokhtar #ifndef TEST_BBDEV_VECTOR_H_ 6f714a188SAmr Mokhtar #define TEST_BBDEV_VECTOR_H_ 7f714a188SAmr Mokhtar 8f714a188SAmr Mokhtar #include <rte_bbdev_op.h> 9f714a188SAmr Mokhtar 10f714a188SAmr Mokhtar /* Flags which are set when specific parameter is define in vector file */ 11f714a188SAmr Mokhtar enum { 12f714a188SAmr Mokhtar TEST_BBDEV_VF_E = (1ULL << 0), 13f714a188SAmr Mokhtar TEST_BBDEV_VF_EA = (1ULL << 1), 14f714a188SAmr Mokhtar TEST_BBDEV_VF_EB = (1ULL << 2), 15f714a188SAmr Mokhtar TEST_BBDEV_VF_K = (1ULL << 3), 16f714a188SAmr Mokhtar TEST_BBDEV_VF_K_NEG = (1ULL << 4), 17f714a188SAmr Mokhtar TEST_BBDEV_VF_K_POS = (1ULL << 5), 18f714a188SAmr Mokhtar TEST_BBDEV_VF_C_NEG = (1ULL << 6), 19f714a188SAmr Mokhtar TEST_BBDEV_VF_C = (1ULL << 7), 20f714a188SAmr Mokhtar TEST_BBDEV_VF_CAB = (1ULL << 8), 21f714a188SAmr Mokhtar TEST_BBDEV_VF_RV_INDEX = (1ULL << 9), 22f714a188SAmr Mokhtar TEST_BBDEV_VF_ITER_MAX = (1ULL << 10), 23f714a188SAmr Mokhtar TEST_BBDEV_VF_ITER_MIN = (1ULL << 11), 24f714a188SAmr Mokhtar TEST_BBDEV_VF_EXPECTED_ITER_COUNT = (1ULL << 12), 25f714a188SAmr Mokhtar TEST_BBDEV_VF_EXT_SCALE = (1ULL << 13), 26f714a188SAmr Mokhtar TEST_BBDEV_VF_NUM_MAPS = (1ULL << 14), 27f714a188SAmr Mokhtar TEST_BBDEV_VF_NCB = (1ULL << 15), 28f714a188SAmr Mokhtar TEST_BBDEV_VF_NCB_NEG = (1ULL << 16), 29f714a188SAmr Mokhtar TEST_BBDEV_VF_NCB_POS = (1ULL << 17), 30f714a188SAmr Mokhtar TEST_BBDEV_VF_R = (1ULL << 18), 31*d819c083SNicolas Chautru TEST_BBDEV_VF_BG = (1ULL << 19), 32*d819c083SNicolas Chautru TEST_BBDEV_VF_ZC = (1ULL << 20), 33*d819c083SNicolas Chautru TEST_BBDEV_VF_F = (1ULL << 21), 34*d819c083SNicolas Chautru TEST_BBDEV_VF_QM = (1ULL << 22), 35*d819c083SNicolas Chautru TEST_BBDEV_VF_CODE_BLOCK_MODE = (1ULL << 23), 36*d819c083SNicolas Chautru TEST_BBDEV_VF_OP_FLAGS = (1ULL << 24), 37*d819c083SNicolas Chautru TEST_BBDEV_VF_EXPECTED_STATUS = (1ULL << 25), 38f714a188SAmr Mokhtar }; 39f714a188SAmr Mokhtar 40f714a188SAmr Mokhtar enum op_data_type { 41f714a188SAmr Mokhtar DATA_INPUT = 0, 42f714a188SAmr Mokhtar DATA_SOFT_OUTPUT, 43f714a188SAmr Mokhtar DATA_HARD_OUTPUT, 44*d819c083SNicolas Chautru DATA_HARQ_INPUT, 45*d819c083SNicolas Chautru DATA_HARQ_OUTPUT, 46f714a188SAmr Mokhtar DATA_NUM_TYPES, 47f714a188SAmr Mokhtar }; 48f714a188SAmr Mokhtar 49f714a188SAmr Mokhtar struct op_data_buf { 50f714a188SAmr Mokhtar uint32_t *addr; 51f714a188SAmr Mokhtar uint32_t length; 52f714a188SAmr Mokhtar }; 53f714a188SAmr Mokhtar 54f714a188SAmr Mokhtar struct op_data_entries { 55c4b0d663SNicolas Chautru struct op_data_buf segments[RTE_BBDEV_TURBO_MAX_CODE_BLOCKS]; 56f714a188SAmr Mokhtar unsigned int nb_segments; 57f714a188SAmr Mokhtar }; 58f714a188SAmr Mokhtar 59f714a188SAmr Mokhtar struct test_bbdev_vector { 60f714a188SAmr Mokhtar enum rte_bbdev_op_type op_type; 61f714a188SAmr Mokhtar int expected_status; 62f714a188SAmr Mokhtar int mask; 63f714a188SAmr Mokhtar union { 64f714a188SAmr Mokhtar struct rte_bbdev_op_turbo_dec turbo_dec; 65f714a188SAmr Mokhtar struct rte_bbdev_op_turbo_enc turbo_enc; 66*d819c083SNicolas Chautru struct rte_bbdev_op_ldpc_dec ldpc_dec; 67*d819c083SNicolas Chautru struct rte_bbdev_op_ldpc_enc ldpc_enc; 68f714a188SAmr Mokhtar }; 69f714a188SAmr Mokhtar /* Additional storage for op data entries */ 70f714a188SAmr Mokhtar struct op_data_entries entries[DATA_NUM_TYPES]; 71f714a188SAmr Mokhtar }; 72f714a188SAmr Mokhtar 73f714a188SAmr Mokhtar /* fills test vector parameters based on test file */ 74f714a188SAmr Mokhtar int 75f714a188SAmr Mokhtar test_bbdev_vector_read(const char *filename, 76f714a188SAmr Mokhtar struct test_bbdev_vector *vector); 77f714a188SAmr Mokhtar 78f714a188SAmr Mokhtar 79f714a188SAmr Mokhtar #endif /* TEST_BBDEV_VECTOR_H_ */ 80