xref: /dpdk/app/test-bbdev/test_bbdev_perf.c (revision b2e2aec3)
1f714a188SAmr Mokhtar /* SPDX-License-Identifier: BSD-3-Clause
2f714a188SAmr Mokhtar  * Copyright(c) 2017 Intel Corporation
3f714a188SAmr Mokhtar  */
4f714a188SAmr Mokhtar 
5f714a188SAmr Mokhtar #include <stdio.h>
6f714a188SAmr Mokhtar #include <inttypes.h>
747d5a049SKamil Chalupnik #include <math.h>
8f714a188SAmr Mokhtar 
9f714a188SAmr Mokhtar #include <rte_eal.h>
10f714a188SAmr Mokhtar #include <rte_common.h>
11f714a188SAmr Mokhtar #include <rte_dev.h>
12f714a188SAmr Mokhtar #include <rte_launch.h>
13f714a188SAmr Mokhtar #include <rte_bbdev.h>
14f714a188SAmr Mokhtar #include <rte_cycles.h>
15f714a188SAmr Mokhtar #include <rte_lcore.h>
16f714a188SAmr Mokhtar #include <rte_malloc.h>
17f714a188SAmr Mokhtar #include <rte_random.h>
18f714a188SAmr Mokhtar #include <rte_hexdump.h>
19f714a188SAmr Mokhtar 
20f714a188SAmr Mokhtar #include "main.h"
21f714a188SAmr Mokhtar #include "test_bbdev_vector.h"
22f714a188SAmr Mokhtar 
23f714a188SAmr Mokhtar #define GET_SOCKET(socket_id) (((socket_id) == SOCKET_ID_ANY) ? 0 : (socket_id))
24f714a188SAmr Mokhtar 
25f714a188SAmr Mokhtar #define MAX_QUEUES RTE_MAX_LCORE
260b98d574SKamil Chalupnik #define TEST_REPETITIONS 1000
27f714a188SAmr Mokhtar 
28f714a188SAmr Mokhtar #define OPS_CACHE_SIZE 256U
29f714a188SAmr Mokhtar #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */
30f714a188SAmr Mokhtar 
31f714a188SAmr Mokhtar #define SYNC_WAIT 0
32f714a188SAmr Mokhtar #define SYNC_START 1
33f714a188SAmr Mokhtar 
34f714a188SAmr Mokhtar #define INVALID_QUEUE_ID -1
35f714a188SAmr Mokhtar 
36f714a188SAmr Mokhtar static struct test_bbdev_vector test_vector;
37f714a188SAmr Mokhtar 
38f714a188SAmr Mokhtar /* Switch between PMD and Interrupt for throughput TC */
39f714a188SAmr Mokhtar static bool intr_enabled;
40f714a188SAmr Mokhtar 
41f714a188SAmr Mokhtar /* Represents tested active devices */
42f714a188SAmr Mokhtar static struct active_device {
43f714a188SAmr Mokhtar 	const char *driver_name;
44f714a188SAmr Mokhtar 	uint8_t dev_id;
45f714a188SAmr Mokhtar 	uint16_t supported_ops;
46f714a188SAmr Mokhtar 	uint16_t queue_ids[MAX_QUEUES];
47f714a188SAmr Mokhtar 	uint16_t nb_queues;
48f714a188SAmr Mokhtar 	struct rte_mempool *ops_mempool;
49f714a188SAmr Mokhtar 	struct rte_mempool *in_mbuf_pool;
50f714a188SAmr Mokhtar 	struct rte_mempool *hard_out_mbuf_pool;
51f714a188SAmr Mokhtar 	struct rte_mempool *soft_out_mbuf_pool;
52f714a188SAmr Mokhtar } active_devs[RTE_BBDEV_MAX_DEVS];
53f714a188SAmr Mokhtar 
54f714a188SAmr Mokhtar static uint8_t nb_active_devs;
55f714a188SAmr Mokhtar 
56f714a188SAmr Mokhtar /* Data buffers used by BBDEV ops */
57f714a188SAmr Mokhtar struct test_buffers {
58f714a188SAmr Mokhtar 	struct rte_bbdev_op_data *inputs;
59f714a188SAmr Mokhtar 	struct rte_bbdev_op_data *hard_outputs;
60f714a188SAmr Mokhtar 	struct rte_bbdev_op_data *soft_outputs;
61f714a188SAmr Mokhtar };
62f714a188SAmr Mokhtar 
63f714a188SAmr Mokhtar /* Operation parameters specific for given test case */
64f714a188SAmr Mokhtar struct test_op_params {
65f714a188SAmr Mokhtar 	struct rte_mempool *mp;
66f714a188SAmr Mokhtar 	struct rte_bbdev_dec_op *ref_dec_op;
67f714a188SAmr Mokhtar 	struct rte_bbdev_enc_op *ref_enc_op;
68f714a188SAmr Mokhtar 	uint16_t burst_sz;
69f714a188SAmr Mokhtar 	uint16_t num_to_process;
70f714a188SAmr Mokhtar 	uint16_t num_lcores;
71f714a188SAmr Mokhtar 	int vector_mask;
72f714a188SAmr Mokhtar 	rte_atomic16_t sync;
73f714a188SAmr Mokhtar 	struct test_buffers q_bufs[RTE_MAX_NUMA_NODES][MAX_QUEUES];
74f714a188SAmr Mokhtar };
75f714a188SAmr Mokhtar 
76f714a188SAmr Mokhtar /* Contains per lcore params */
77f714a188SAmr Mokhtar struct thread_params {
78f714a188SAmr Mokhtar 	uint8_t dev_id;
79f714a188SAmr Mokhtar 	uint16_t queue_id;
80*b2e2aec3SKamil Chalupnik 	uint32_t lcore_id;
81f714a188SAmr Mokhtar 	uint64_t start_time;
820b98d574SKamil Chalupnik 	double ops_per_sec;
83f714a188SAmr Mokhtar 	double mbps;
840b98d574SKamil Chalupnik 	uint8_t iter_count;
85f714a188SAmr Mokhtar 	rte_atomic16_t nb_dequeued;
86f714a188SAmr Mokhtar 	rte_atomic16_t processing_status;
87*b2e2aec3SKamil Chalupnik 	rte_atomic16_t burst_sz;
88f714a188SAmr Mokhtar 	struct test_op_params *op_params;
89*b2e2aec3SKamil Chalupnik 	struct rte_bbdev_dec_op *dec_ops[MAX_BURST];
90*b2e2aec3SKamil Chalupnik 	struct rte_bbdev_enc_op *enc_ops[MAX_BURST];
91f714a188SAmr Mokhtar };
92f714a188SAmr Mokhtar 
93864edd69SKamil Chalupnik #ifdef RTE_BBDEV_OFFLOAD_COST
94864edd69SKamil Chalupnik /* Stores time statistics */
95864edd69SKamil Chalupnik struct test_time_stats {
96864edd69SKamil Chalupnik 	/* Stores software enqueue total working time */
979fa6ebdeSKamil Chalupnik 	uint64_t enq_sw_total_time;
98864edd69SKamil Chalupnik 	/* Stores minimum value of software enqueue working time */
99864edd69SKamil Chalupnik 	uint64_t enq_sw_min_time;
100864edd69SKamil Chalupnik 	/* Stores maximum value of software enqueue working time */
101864edd69SKamil Chalupnik 	uint64_t enq_sw_max_time;
102864edd69SKamil Chalupnik 	/* Stores turbo enqueue total working time */
1039fa6ebdeSKamil Chalupnik 	uint64_t enq_acc_total_time;
1049fa6ebdeSKamil Chalupnik 	/* Stores minimum value of accelerator enqueue working time */
1059fa6ebdeSKamil Chalupnik 	uint64_t enq_acc_min_time;
1069fa6ebdeSKamil Chalupnik 	/* Stores maximum value of accelerator enqueue working time */
1079fa6ebdeSKamil Chalupnik 	uint64_t enq_acc_max_time;
108864edd69SKamil Chalupnik 	/* Stores dequeue total working time */
1099fa6ebdeSKamil Chalupnik 	uint64_t deq_total_time;
110864edd69SKamil Chalupnik 	/* Stores minimum value of dequeue working time */
111864edd69SKamil Chalupnik 	uint64_t deq_min_time;
112864edd69SKamil Chalupnik 	/* Stores maximum value of dequeue working time */
113864edd69SKamil Chalupnik 	uint64_t deq_max_time;
114864edd69SKamil Chalupnik };
115864edd69SKamil Chalupnik #endif
116864edd69SKamil Chalupnik 
117f714a188SAmr Mokhtar typedef int (test_case_function)(struct active_device *ad,
118f714a188SAmr Mokhtar 		struct test_op_params *op_params);
119f714a188SAmr Mokhtar 
120f714a188SAmr Mokhtar static inline void
1219585f8b1SKamil Chalupnik mbuf_reset(struct rte_mbuf *m)
1229585f8b1SKamil Chalupnik {
1239585f8b1SKamil Chalupnik 	m->pkt_len = 0;
1249585f8b1SKamil Chalupnik 
1259585f8b1SKamil Chalupnik 	do {
1269585f8b1SKamil Chalupnik 		m->data_len = 0;
1279585f8b1SKamil Chalupnik 		m = m->next;
1289585f8b1SKamil Chalupnik 	} while (m != NULL);
1299585f8b1SKamil Chalupnik }
1309585f8b1SKamil Chalupnik 
1319585f8b1SKamil Chalupnik static inline void
132f714a188SAmr Mokhtar set_avail_op(struct active_device *ad, enum rte_bbdev_op_type op_type)
133f714a188SAmr Mokhtar {
134f714a188SAmr Mokhtar 	ad->supported_ops |= (1 << op_type);
135f714a188SAmr Mokhtar }
136f714a188SAmr Mokhtar 
137f714a188SAmr Mokhtar static inline bool
138f714a188SAmr Mokhtar is_avail_op(struct active_device *ad, enum rte_bbdev_op_type op_type)
139f714a188SAmr Mokhtar {
140f714a188SAmr Mokhtar 	return ad->supported_ops & (1 << op_type);
141f714a188SAmr Mokhtar }
142f714a188SAmr Mokhtar 
143f714a188SAmr Mokhtar static inline bool
144f714a188SAmr Mokhtar flags_match(uint32_t flags_req, uint32_t flags_present)
145f714a188SAmr Mokhtar {
146f714a188SAmr Mokhtar 	return (flags_req & flags_present) == flags_req;
147f714a188SAmr Mokhtar }
148f714a188SAmr Mokhtar 
149f714a188SAmr Mokhtar static void
150f714a188SAmr Mokhtar clear_soft_out_cap(uint32_t *op_flags)
151f714a188SAmr Mokhtar {
152f714a188SAmr Mokhtar 	*op_flags &= ~RTE_BBDEV_TURBO_SOFT_OUTPUT;
153f714a188SAmr Mokhtar 	*op_flags &= ~RTE_BBDEV_TURBO_POS_LLR_1_BIT_SOFT_OUT;
154f714a188SAmr Mokhtar 	*op_flags &= ~RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT;
155f714a188SAmr Mokhtar }
156f714a188SAmr Mokhtar 
157f714a188SAmr Mokhtar static int
158f714a188SAmr Mokhtar check_dev_cap(const struct rte_bbdev_info *dev_info)
159f714a188SAmr Mokhtar {
160f714a188SAmr Mokhtar 	unsigned int i;
161f714a188SAmr Mokhtar 	unsigned int nb_inputs, nb_soft_outputs, nb_hard_outputs;
162f714a188SAmr Mokhtar 	const struct rte_bbdev_op_cap *op_cap = dev_info->drv.capabilities;
163f714a188SAmr Mokhtar 
164f714a188SAmr Mokhtar 	nb_inputs = test_vector.entries[DATA_INPUT].nb_segments;
165f714a188SAmr Mokhtar 	nb_soft_outputs = test_vector.entries[DATA_SOFT_OUTPUT].nb_segments;
166f714a188SAmr Mokhtar 	nb_hard_outputs = test_vector.entries[DATA_HARD_OUTPUT].nb_segments;
167f714a188SAmr Mokhtar 
168f714a188SAmr Mokhtar 	for (i = 0; op_cap->type != RTE_BBDEV_OP_NONE; ++i, ++op_cap) {
169f714a188SAmr Mokhtar 		if (op_cap->type != test_vector.op_type)
170f714a188SAmr Mokhtar 			continue;
171f714a188SAmr Mokhtar 
172f714a188SAmr Mokhtar 		if (op_cap->type == RTE_BBDEV_OP_TURBO_DEC) {
173f714a188SAmr Mokhtar 			const struct rte_bbdev_op_cap_turbo_dec *cap =
174f714a188SAmr Mokhtar 					&op_cap->cap.turbo_dec;
175f714a188SAmr Mokhtar 			/* Ignore lack of soft output capability, just skip
176f714a188SAmr Mokhtar 			 * checking if soft output is valid.
177f714a188SAmr Mokhtar 			 */
178f714a188SAmr Mokhtar 			if ((test_vector.turbo_dec.op_flags &
179f714a188SAmr Mokhtar 					RTE_BBDEV_TURBO_SOFT_OUTPUT) &&
180f714a188SAmr Mokhtar 					!(cap->capability_flags &
181f714a188SAmr Mokhtar 					RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
182f714a188SAmr Mokhtar 				printf(
183f714a188SAmr Mokhtar 					"WARNING: Device \"%s\" does not support soft output - soft output flags will be ignored.\n",
184f714a188SAmr Mokhtar 					dev_info->dev_name);
185f714a188SAmr Mokhtar 				clear_soft_out_cap(
186f714a188SAmr Mokhtar 					&test_vector.turbo_dec.op_flags);
187f714a188SAmr Mokhtar 			}
188f714a188SAmr Mokhtar 
189f714a188SAmr Mokhtar 			if (!flags_match(test_vector.turbo_dec.op_flags,
190f714a188SAmr Mokhtar 					cap->capability_flags))
191f714a188SAmr Mokhtar 				return TEST_FAILED;
192f714a188SAmr Mokhtar 			if (nb_inputs > cap->num_buffers_src) {
193f714a188SAmr Mokhtar 				printf("Too many inputs defined: %u, max: %u\n",
194f714a188SAmr Mokhtar 					nb_inputs, cap->num_buffers_src);
195f714a188SAmr Mokhtar 				return TEST_FAILED;
196f714a188SAmr Mokhtar 			}
197f714a188SAmr Mokhtar 			if (nb_soft_outputs > cap->num_buffers_soft_out &&
198f714a188SAmr Mokhtar 					(test_vector.turbo_dec.op_flags &
199f714a188SAmr Mokhtar 					RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
200f714a188SAmr Mokhtar 				printf(
201f714a188SAmr Mokhtar 					"Too many soft outputs defined: %u, max: %u\n",
202f714a188SAmr Mokhtar 						nb_soft_outputs,
203f714a188SAmr Mokhtar 						cap->num_buffers_soft_out);
204f714a188SAmr Mokhtar 				return TEST_FAILED;
205f714a188SAmr Mokhtar 			}
206f714a188SAmr Mokhtar 			if (nb_hard_outputs > cap->num_buffers_hard_out) {
207f714a188SAmr Mokhtar 				printf(
208f714a188SAmr Mokhtar 					"Too many hard outputs defined: %u, max: %u\n",
209f714a188SAmr Mokhtar 						nb_hard_outputs,
210f714a188SAmr Mokhtar 						cap->num_buffers_hard_out);
211f714a188SAmr Mokhtar 				return TEST_FAILED;
212f714a188SAmr Mokhtar 			}
213f714a188SAmr Mokhtar 			if (intr_enabled && !(cap->capability_flags &
214f714a188SAmr Mokhtar 					RTE_BBDEV_TURBO_DEC_INTERRUPTS)) {
215f714a188SAmr Mokhtar 				printf(
216f714a188SAmr Mokhtar 					"Dequeue interrupts are not supported!\n");
217f714a188SAmr Mokhtar 				return TEST_FAILED;
218f714a188SAmr Mokhtar 			}
219f714a188SAmr Mokhtar 
220f714a188SAmr Mokhtar 			return TEST_SUCCESS;
221f714a188SAmr Mokhtar 		} else if (op_cap->type == RTE_BBDEV_OP_TURBO_ENC) {
222f714a188SAmr Mokhtar 			const struct rte_bbdev_op_cap_turbo_enc *cap =
223f714a188SAmr Mokhtar 					&op_cap->cap.turbo_enc;
224f714a188SAmr Mokhtar 
225f714a188SAmr Mokhtar 			if (!flags_match(test_vector.turbo_enc.op_flags,
226f714a188SAmr Mokhtar 					cap->capability_flags))
227f714a188SAmr Mokhtar 				return TEST_FAILED;
228f714a188SAmr Mokhtar 			if (nb_inputs > cap->num_buffers_src) {
229f714a188SAmr Mokhtar 				printf("Too many inputs defined: %u, max: %u\n",
230f714a188SAmr Mokhtar 					nb_inputs, cap->num_buffers_src);
231f714a188SAmr Mokhtar 				return TEST_FAILED;
232f714a188SAmr Mokhtar 			}
233f714a188SAmr Mokhtar 			if (nb_hard_outputs > cap->num_buffers_dst) {
234f714a188SAmr Mokhtar 				printf(
235f714a188SAmr Mokhtar 					"Too many hard outputs defined: %u, max: %u\n",
236f714a188SAmr Mokhtar 					nb_hard_outputs, cap->num_buffers_src);
237f714a188SAmr Mokhtar 				return TEST_FAILED;
238f714a188SAmr Mokhtar 			}
239f714a188SAmr Mokhtar 			if (intr_enabled && !(cap->capability_flags &
240f714a188SAmr Mokhtar 					RTE_BBDEV_TURBO_ENC_INTERRUPTS)) {
241f714a188SAmr Mokhtar 				printf(
242f714a188SAmr Mokhtar 					"Dequeue interrupts are not supported!\n");
243f714a188SAmr Mokhtar 				return TEST_FAILED;
244f714a188SAmr Mokhtar 			}
245f714a188SAmr Mokhtar 
246f714a188SAmr Mokhtar 			return TEST_SUCCESS;
247f714a188SAmr Mokhtar 		}
248f714a188SAmr Mokhtar 	}
249f714a188SAmr Mokhtar 
250f714a188SAmr Mokhtar 	if ((i == 0) && (test_vector.op_type == RTE_BBDEV_OP_NONE))
251f714a188SAmr Mokhtar 		return TEST_SUCCESS; /* Special case for NULL device */
252f714a188SAmr Mokhtar 
253f714a188SAmr Mokhtar 	return TEST_FAILED;
254f714a188SAmr Mokhtar }
255f714a188SAmr Mokhtar 
256f714a188SAmr Mokhtar /* calculates optimal mempool size not smaller than the val */
257f714a188SAmr Mokhtar static unsigned int
258f714a188SAmr Mokhtar optimal_mempool_size(unsigned int val)
259f714a188SAmr Mokhtar {
260f714a188SAmr Mokhtar 	return rte_align32pow2(val + 1) - 1;
261f714a188SAmr Mokhtar }
262f714a188SAmr Mokhtar 
263f714a188SAmr Mokhtar /* allocates mbuf mempool for inputs and outputs */
264f714a188SAmr Mokhtar static struct rte_mempool *
265f714a188SAmr Mokhtar create_mbuf_pool(struct op_data_entries *entries, uint8_t dev_id,
266f714a188SAmr Mokhtar 		int socket_id, unsigned int mbuf_pool_size,
267f714a188SAmr Mokhtar 		const char *op_type_str)
268f714a188SAmr Mokhtar {
269f714a188SAmr Mokhtar 	unsigned int i;
270f714a188SAmr Mokhtar 	uint32_t max_seg_sz = 0;
271f714a188SAmr Mokhtar 	char pool_name[RTE_MEMPOOL_NAMESIZE];
272f714a188SAmr Mokhtar 
273f714a188SAmr Mokhtar 	/* find max input segment size */
274f714a188SAmr Mokhtar 	for (i = 0; i < entries->nb_segments; ++i)
275f714a188SAmr Mokhtar 		if (entries->segments[i].length > max_seg_sz)
276f714a188SAmr Mokhtar 			max_seg_sz = entries->segments[i].length;
277f714a188SAmr Mokhtar 
278f714a188SAmr Mokhtar 	snprintf(pool_name, sizeof(pool_name), "%s_pool_%u", op_type_str,
279f714a188SAmr Mokhtar 			dev_id);
280f714a188SAmr Mokhtar 	return rte_pktmbuf_pool_create(pool_name, mbuf_pool_size, 0, 0,
281f714a188SAmr Mokhtar 			RTE_MAX(max_seg_sz + RTE_PKTMBUF_HEADROOM,
282f714a188SAmr Mokhtar 			(unsigned int)RTE_MBUF_DEFAULT_BUF_SIZE), socket_id);
283f714a188SAmr Mokhtar }
284f714a188SAmr Mokhtar 
285f714a188SAmr Mokhtar static int
286f714a188SAmr Mokhtar create_mempools(struct active_device *ad, int socket_id,
287ad458935SKamil Chalupnik 		enum rte_bbdev_op_type org_op_type, uint16_t num_ops)
288f714a188SAmr Mokhtar {
289f714a188SAmr Mokhtar 	struct rte_mempool *mp;
290f714a188SAmr Mokhtar 	unsigned int ops_pool_size, mbuf_pool_size = 0;
291f714a188SAmr Mokhtar 	char pool_name[RTE_MEMPOOL_NAMESIZE];
292f714a188SAmr Mokhtar 	const char *op_type_str;
293ad458935SKamil Chalupnik 	enum rte_bbdev_op_type op_type = org_op_type;
294f714a188SAmr Mokhtar 
295f714a188SAmr Mokhtar 	struct op_data_entries *in = &test_vector.entries[DATA_INPUT];
296f714a188SAmr Mokhtar 	struct op_data_entries *hard_out =
297f714a188SAmr Mokhtar 			&test_vector.entries[DATA_HARD_OUTPUT];
298f714a188SAmr Mokhtar 	struct op_data_entries *soft_out =
299f714a188SAmr Mokhtar 			&test_vector.entries[DATA_SOFT_OUTPUT];
300f714a188SAmr Mokhtar 
301f714a188SAmr Mokhtar 	/* allocate ops mempool */
302f714a188SAmr Mokhtar 	ops_pool_size = optimal_mempool_size(RTE_MAX(
303f714a188SAmr Mokhtar 			/* Ops used plus 1 reference op */
304f714a188SAmr Mokhtar 			RTE_MAX((unsigned int)(ad->nb_queues * num_ops + 1),
305f714a188SAmr Mokhtar 			/* Minimal cache size plus 1 reference op */
306f714a188SAmr Mokhtar 			(unsigned int)(1.5 * rte_lcore_count() *
307f714a188SAmr Mokhtar 					OPS_CACHE_SIZE + 1)),
308f714a188SAmr Mokhtar 			OPS_POOL_SIZE_MIN));
309f714a188SAmr Mokhtar 
310ad458935SKamil Chalupnik 	if (org_op_type == RTE_BBDEV_OP_NONE)
311ad458935SKamil Chalupnik 		op_type = RTE_BBDEV_OP_TURBO_ENC;
312ad458935SKamil Chalupnik 
313f714a188SAmr Mokhtar 	op_type_str = rte_bbdev_op_type_str(op_type);
314f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type);
315f714a188SAmr Mokhtar 
316f714a188SAmr Mokhtar 	snprintf(pool_name, sizeof(pool_name), "%s_pool_%u", op_type_str,
317f714a188SAmr Mokhtar 			ad->dev_id);
318f714a188SAmr Mokhtar 	mp = rte_bbdev_op_pool_create(pool_name, op_type,
319f714a188SAmr Mokhtar 			ops_pool_size, OPS_CACHE_SIZE, socket_id);
320f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(mp,
321f714a188SAmr Mokhtar 			"ERROR Failed to create %u items ops pool for dev %u on socket %u.",
322f714a188SAmr Mokhtar 			ops_pool_size,
323f714a188SAmr Mokhtar 			ad->dev_id,
324f714a188SAmr Mokhtar 			socket_id);
325f714a188SAmr Mokhtar 	ad->ops_mempool = mp;
326f714a188SAmr Mokhtar 
327ad458935SKamil Chalupnik 	/* Do not create inputs and outputs mbufs for BaseBand Null Device */
328ad458935SKamil Chalupnik 	if (org_op_type == RTE_BBDEV_OP_NONE)
329ad458935SKamil Chalupnik 		return TEST_SUCCESS;
330ad458935SKamil Chalupnik 
331f714a188SAmr Mokhtar 	/* Inputs */
332f714a188SAmr Mokhtar 	mbuf_pool_size = optimal_mempool_size(ops_pool_size * in->nb_segments);
333f714a188SAmr Mokhtar 	mp = create_mbuf_pool(in, ad->dev_id, socket_id, mbuf_pool_size, "in");
334f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(mp,
335f714a188SAmr Mokhtar 			"ERROR Failed to create %u items input pktmbuf pool for dev %u on socket %u.",
336f714a188SAmr Mokhtar 			mbuf_pool_size,
337f714a188SAmr Mokhtar 			ad->dev_id,
338f714a188SAmr Mokhtar 			socket_id);
339f714a188SAmr Mokhtar 	ad->in_mbuf_pool = mp;
340f714a188SAmr Mokhtar 
341f714a188SAmr Mokhtar 	/* Hard outputs */
342f714a188SAmr Mokhtar 	mbuf_pool_size = optimal_mempool_size(ops_pool_size *
343f714a188SAmr Mokhtar 			hard_out->nb_segments);
344f714a188SAmr Mokhtar 	mp = create_mbuf_pool(hard_out, ad->dev_id, socket_id, mbuf_pool_size,
345f714a188SAmr Mokhtar 			"hard_out");
346f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(mp,
347f714a188SAmr Mokhtar 			"ERROR Failed to create %u items hard output pktmbuf pool for dev %u on socket %u.",
348f714a188SAmr Mokhtar 			mbuf_pool_size,
349f714a188SAmr Mokhtar 			ad->dev_id,
350f714a188SAmr Mokhtar 			socket_id);
351f714a188SAmr Mokhtar 	ad->hard_out_mbuf_pool = mp;
352f714a188SAmr Mokhtar 
353f714a188SAmr Mokhtar 	if (soft_out->nb_segments == 0)
354f714a188SAmr Mokhtar 		return TEST_SUCCESS;
355f714a188SAmr Mokhtar 
356f714a188SAmr Mokhtar 	/* Soft outputs */
357f714a188SAmr Mokhtar 	mbuf_pool_size = optimal_mempool_size(ops_pool_size *
358f714a188SAmr Mokhtar 			soft_out->nb_segments);
359f714a188SAmr Mokhtar 	mp = create_mbuf_pool(soft_out, ad->dev_id, socket_id, mbuf_pool_size,
360f714a188SAmr Mokhtar 			"soft_out");
361f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(mp,
362f714a188SAmr Mokhtar 			"ERROR Failed to create %uB soft output pktmbuf pool for dev %u on socket %u.",
363f714a188SAmr Mokhtar 			mbuf_pool_size,
364f714a188SAmr Mokhtar 			ad->dev_id,
365f714a188SAmr Mokhtar 			socket_id);
366f714a188SAmr Mokhtar 	ad->soft_out_mbuf_pool = mp;
367f714a188SAmr Mokhtar 
368f714a188SAmr Mokhtar 	return 0;
369f714a188SAmr Mokhtar }
370f714a188SAmr Mokhtar 
371f714a188SAmr Mokhtar static int
372f714a188SAmr Mokhtar add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,
373f714a188SAmr Mokhtar 		struct test_bbdev_vector *vector)
374f714a188SAmr Mokhtar {
375f714a188SAmr Mokhtar 	int ret;
376f714a188SAmr Mokhtar 	unsigned int queue_id;
377f714a188SAmr Mokhtar 	struct rte_bbdev_queue_conf qconf;
378f714a188SAmr Mokhtar 	struct active_device *ad = &active_devs[nb_active_devs];
379f714a188SAmr Mokhtar 	unsigned int nb_queues;
380f714a188SAmr Mokhtar 	enum rte_bbdev_op_type op_type = vector->op_type;
381f714a188SAmr Mokhtar 
382f714a188SAmr Mokhtar 	nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);
383f714a188SAmr Mokhtar 	/* setup device */
384f714a188SAmr Mokhtar 	ret = rte_bbdev_setup_queues(dev_id, nb_queues, info->socket_id);
385f714a188SAmr Mokhtar 	if (ret < 0) {
386f714a188SAmr Mokhtar 		printf("rte_bbdev_setup_queues(%u, %u, %d) ret %i\n",
387f714a188SAmr Mokhtar 				dev_id, nb_queues, info->socket_id, ret);
388f714a188SAmr Mokhtar 		return TEST_FAILED;
389f714a188SAmr Mokhtar 	}
390f714a188SAmr Mokhtar 
391f714a188SAmr Mokhtar 	/* configure interrupts if needed */
392f714a188SAmr Mokhtar 	if (intr_enabled) {
393f714a188SAmr Mokhtar 		ret = rte_bbdev_intr_enable(dev_id);
394f714a188SAmr Mokhtar 		if (ret < 0) {
395f714a188SAmr Mokhtar 			printf("rte_bbdev_intr_enable(%u) ret %i\n", dev_id,
396f714a188SAmr Mokhtar 					ret);
397f714a188SAmr Mokhtar 			return TEST_FAILED;
398f714a188SAmr Mokhtar 		}
399f714a188SAmr Mokhtar 	}
400f714a188SAmr Mokhtar 
401f714a188SAmr Mokhtar 	/* setup device queues */
402f714a188SAmr Mokhtar 	qconf.socket = info->socket_id;
403f714a188SAmr Mokhtar 	qconf.queue_size = info->drv.default_queue_conf.queue_size;
404f714a188SAmr Mokhtar 	qconf.priority = 0;
405f714a188SAmr Mokhtar 	qconf.deferred_start = 0;
406f714a188SAmr Mokhtar 	qconf.op_type = op_type;
407f714a188SAmr Mokhtar 
408f714a188SAmr Mokhtar 	for (queue_id = 0; queue_id < nb_queues; ++queue_id) {
409f714a188SAmr Mokhtar 		ret = rte_bbdev_queue_configure(dev_id, queue_id, &qconf);
410f714a188SAmr Mokhtar 		if (ret != 0) {
411f714a188SAmr Mokhtar 			printf(
412f714a188SAmr Mokhtar 					"Allocated all queues (id=%u) at prio%u on dev%u\n",
413f714a188SAmr Mokhtar 					queue_id, qconf.priority, dev_id);
414f714a188SAmr Mokhtar 			qconf.priority++;
415f714a188SAmr Mokhtar 			ret = rte_bbdev_queue_configure(ad->dev_id, queue_id,
416f714a188SAmr Mokhtar 					&qconf);
417f714a188SAmr Mokhtar 		}
418f714a188SAmr Mokhtar 		if (ret != 0) {
419f714a188SAmr Mokhtar 			printf("All queues on dev %u allocated: %u\n",
420f714a188SAmr Mokhtar 					dev_id, queue_id);
421f714a188SAmr Mokhtar 			break;
422f714a188SAmr Mokhtar 		}
423f714a188SAmr Mokhtar 		ad->queue_ids[queue_id] = queue_id;
424f714a188SAmr Mokhtar 	}
425f714a188SAmr Mokhtar 	TEST_ASSERT(queue_id != 0,
426f714a188SAmr Mokhtar 			"ERROR Failed to configure any queues on dev %u",
427f714a188SAmr Mokhtar 			dev_id);
428f714a188SAmr Mokhtar 	ad->nb_queues = queue_id;
429f714a188SAmr Mokhtar 
430f714a188SAmr Mokhtar 	set_avail_op(ad, op_type);
431f714a188SAmr Mokhtar 
432f714a188SAmr Mokhtar 	return TEST_SUCCESS;
433f714a188SAmr Mokhtar }
434f714a188SAmr Mokhtar 
435f714a188SAmr Mokhtar static int
436f714a188SAmr Mokhtar add_active_device(uint8_t dev_id, struct rte_bbdev_info *info,
437f714a188SAmr Mokhtar 		struct test_bbdev_vector *vector)
438f714a188SAmr Mokhtar {
439f714a188SAmr Mokhtar 	int ret;
440f714a188SAmr Mokhtar 
441f714a188SAmr Mokhtar 	active_devs[nb_active_devs].driver_name = info->drv.driver_name;
442f714a188SAmr Mokhtar 	active_devs[nb_active_devs].dev_id = dev_id;
443f714a188SAmr Mokhtar 
444f714a188SAmr Mokhtar 	ret = add_bbdev_dev(dev_id, info, vector);
445f714a188SAmr Mokhtar 	if (ret == TEST_SUCCESS)
446f714a188SAmr Mokhtar 		++nb_active_devs;
447f714a188SAmr Mokhtar 	return ret;
448f714a188SAmr Mokhtar }
449f714a188SAmr Mokhtar 
450f714a188SAmr Mokhtar static uint8_t
451f714a188SAmr Mokhtar populate_active_devices(void)
452f714a188SAmr Mokhtar {
453f714a188SAmr Mokhtar 	int ret;
454f714a188SAmr Mokhtar 	uint8_t dev_id;
455f714a188SAmr Mokhtar 	uint8_t nb_devs_added = 0;
456f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
457f714a188SAmr Mokhtar 
458f714a188SAmr Mokhtar 	RTE_BBDEV_FOREACH(dev_id) {
459f714a188SAmr Mokhtar 		rte_bbdev_info_get(dev_id, &info);
460f714a188SAmr Mokhtar 
461f714a188SAmr Mokhtar 		if (check_dev_cap(&info)) {
462f714a188SAmr Mokhtar 			printf(
463f714a188SAmr Mokhtar 				"Device %d (%s) does not support specified capabilities\n",
464f714a188SAmr Mokhtar 					dev_id, info.dev_name);
465f714a188SAmr Mokhtar 			continue;
466f714a188SAmr Mokhtar 		}
467f714a188SAmr Mokhtar 
468f714a188SAmr Mokhtar 		ret = add_active_device(dev_id, &info, &test_vector);
469f714a188SAmr Mokhtar 		if (ret != 0) {
470f714a188SAmr Mokhtar 			printf("Adding active bbdev %s skipped\n",
471f714a188SAmr Mokhtar 					info.dev_name);
472f714a188SAmr Mokhtar 			continue;
473f714a188SAmr Mokhtar 		}
474f714a188SAmr Mokhtar 		nb_devs_added++;
475f714a188SAmr Mokhtar 	}
476f714a188SAmr Mokhtar 
477f714a188SAmr Mokhtar 	return nb_devs_added;
478f714a188SAmr Mokhtar }
479f714a188SAmr Mokhtar 
480f714a188SAmr Mokhtar static int
481f714a188SAmr Mokhtar read_test_vector(void)
482f714a188SAmr Mokhtar {
483f714a188SAmr Mokhtar 	int ret;
484f714a188SAmr Mokhtar 
485f714a188SAmr Mokhtar 	memset(&test_vector, 0, sizeof(test_vector));
486f714a188SAmr Mokhtar 	printf("Test vector file = %s\n", get_vector_filename());
487f714a188SAmr Mokhtar 	ret = test_bbdev_vector_read(get_vector_filename(), &test_vector);
488f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS(ret, "Failed to parse file %s\n",
489f714a188SAmr Mokhtar 			get_vector_filename());
490f714a188SAmr Mokhtar 
491f714a188SAmr Mokhtar 	return TEST_SUCCESS;
492f714a188SAmr Mokhtar }
493f714a188SAmr Mokhtar 
494f714a188SAmr Mokhtar static int
495f714a188SAmr Mokhtar testsuite_setup(void)
496f714a188SAmr Mokhtar {
497f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS(read_test_vector(), "Test suite setup failed\n");
498f714a188SAmr Mokhtar 
499f714a188SAmr Mokhtar 	if (populate_active_devices() == 0) {
500f714a188SAmr Mokhtar 		printf("No suitable devices found!\n");
501f714a188SAmr Mokhtar 		return TEST_SKIPPED;
502f714a188SAmr Mokhtar 	}
503f714a188SAmr Mokhtar 
504f714a188SAmr Mokhtar 	return TEST_SUCCESS;
505f714a188SAmr Mokhtar }
506f714a188SAmr Mokhtar 
507f714a188SAmr Mokhtar static int
508f714a188SAmr Mokhtar interrupt_testsuite_setup(void)
509f714a188SAmr Mokhtar {
510f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS(read_test_vector(), "Test suite setup failed\n");
511f714a188SAmr Mokhtar 
512f714a188SAmr Mokhtar 	/* Enable interrupts */
513f714a188SAmr Mokhtar 	intr_enabled = true;
514f714a188SAmr Mokhtar 
515f714a188SAmr Mokhtar 	/* Special case for NULL device (RTE_BBDEV_OP_NONE) */
516f714a188SAmr Mokhtar 	if (populate_active_devices() == 0 ||
517f714a188SAmr Mokhtar 			test_vector.op_type == RTE_BBDEV_OP_NONE) {
518f714a188SAmr Mokhtar 		intr_enabled = false;
519f714a188SAmr Mokhtar 		printf("No suitable devices found!\n");
520f714a188SAmr Mokhtar 		return TEST_SKIPPED;
521f714a188SAmr Mokhtar 	}
522f714a188SAmr Mokhtar 
523f714a188SAmr Mokhtar 	return TEST_SUCCESS;
524f714a188SAmr Mokhtar }
525f714a188SAmr Mokhtar 
526f714a188SAmr Mokhtar static void
527f714a188SAmr Mokhtar testsuite_teardown(void)
528f714a188SAmr Mokhtar {
529f714a188SAmr Mokhtar 	uint8_t dev_id;
530f714a188SAmr Mokhtar 
531f714a188SAmr Mokhtar 	/* Unconfigure devices */
532f714a188SAmr Mokhtar 	RTE_BBDEV_FOREACH(dev_id)
533f714a188SAmr Mokhtar 		rte_bbdev_close(dev_id);
534f714a188SAmr Mokhtar 
535f714a188SAmr Mokhtar 	/* Clear active devices structs. */
536f714a188SAmr Mokhtar 	memset(active_devs, 0, sizeof(active_devs));
537f714a188SAmr Mokhtar 	nb_active_devs = 0;
538f714a188SAmr Mokhtar }
539f714a188SAmr Mokhtar 
540f714a188SAmr Mokhtar static int
541f714a188SAmr Mokhtar ut_setup(void)
542f714a188SAmr Mokhtar {
543f714a188SAmr Mokhtar 	uint8_t i, dev_id;
544f714a188SAmr Mokhtar 
545f714a188SAmr Mokhtar 	for (i = 0; i < nb_active_devs; i++) {
546f714a188SAmr Mokhtar 		dev_id = active_devs[i].dev_id;
547f714a188SAmr Mokhtar 		/* reset bbdev stats */
548f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(rte_bbdev_stats_reset(dev_id),
549f714a188SAmr Mokhtar 				"Failed to reset stats of bbdev %u", dev_id);
550f714a188SAmr Mokhtar 		/* start the device */
551f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(rte_bbdev_start(dev_id),
552f714a188SAmr Mokhtar 				"Failed to start bbdev %u", dev_id);
553f714a188SAmr Mokhtar 	}
554f714a188SAmr Mokhtar 
555f714a188SAmr Mokhtar 	return TEST_SUCCESS;
556f714a188SAmr Mokhtar }
557f714a188SAmr Mokhtar 
558f714a188SAmr Mokhtar static void
559f714a188SAmr Mokhtar ut_teardown(void)
560f714a188SAmr Mokhtar {
561f714a188SAmr Mokhtar 	uint8_t i, dev_id;
562f714a188SAmr Mokhtar 	struct rte_bbdev_stats stats;
563f714a188SAmr Mokhtar 
564f714a188SAmr Mokhtar 	for (i = 0; i < nb_active_devs; i++) {
565f714a188SAmr Mokhtar 		dev_id = active_devs[i].dev_id;
566f714a188SAmr Mokhtar 		/* read stats and print */
567f714a188SAmr Mokhtar 		rte_bbdev_stats_get(dev_id, &stats);
568f714a188SAmr Mokhtar 		/* Stop the device */
569f714a188SAmr Mokhtar 		rte_bbdev_stop(dev_id);
570f714a188SAmr Mokhtar 	}
571f714a188SAmr Mokhtar }
572f714a188SAmr Mokhtar 
573f714a188SAmr Mokhtar static int
574f714a188SAmr Mokhtar init_op_data_objs(struct rte_bbdev_op_data *bufs,
575f714a188SAmr Mokhtar 		struct op_data_entries *ref_entries,
576f714a188SAmr Mokhtar 		struct rte_mempool *mbuf_pool, const uint16_t n,
577f714a188SAmr Mokhtar 		enum op_data_type op_type, uint16_t min_alignment)
578f714a188SAmr Mokhtar {
579f714a188SAmr Mokhtar 	int ret;
580f714a188SAmr Mokhtar 	unsigned int i, j;
581f714a188SAmr Mokhtar 
582f714a188SAmr Mokhtar 	for (i = 0; i < n; ++i) {
583f714a188SAmr Mokhtar 		char *data;
584f714a188SAmr Mokhtar 		struct op_data_buf *seg = &ref_entries->segments[0];
585f714a188SAmr Mokhtar 		struct rte_mbuf *m_head = rte_pktmbuf_alloc(mbuf_pool);
586f714a188SAmr Mokhtar 		TEST_ASSERT_NOT_NULL(m_head,
587f714a188SAmr Mokhtar 				"Not enough mbufs in %d data type mbuf pool (needed %u, available %u)",
588f714a188SAmr Mokhtar 				op_type, n * ref_entries->nb_segments,
589f714a188SAmr Mokhtar 				mbuf_pool->size);
590f714a188SAmr Mokhtar 
5919585f8b1SKamil Chalupnik 		TEST_ASSERT_SUCCESS(((seg->length + RTE_PKTMBUF_HEADROOM) >
5929585f8b1SKamil Chalupnik 				(uint32_t)UINT16_MAX),
5939585f8b1SKamil Chalupnik 				"Given data is bigger than allowed mbuf segment size");
5949585f8b1SKamil Chalupnik 
595f714a188SAmr Mokhtar 		bufs[i].data = m_head;
596f714a188SAmr Mokhtar 		bufs[i].offset = 0;
597f714a188SAmr Mokhtar 		bufs[i].length = 0;
598f714a188SAmr Mokhtar 
599f714a188SAmr Mokhtar 		if (op_type == DATA_INPUT) {
600f714a188SAmr Mokhtar 			data = rte_pktmbuf_append(m_head, seg->length);
601f714a188SAmr Mokhtar 			TEST_ASSERT_NOT_NULL(data,
602f714a188SAmr Mokhtar 					"Couldn't append %u bytes to mbuf from %d data type mbuf pool",
603f714a188SAmr Mokhtar 					seg->length, op_type);
604f714a188SAmr Mokhtar 
605f714a188SAmr Mokhtar 			TEST_ASSERT(data == RTE_PTR_ALIGN(data, min_alignment),
606f714a188SAmr Mokhtar 					"Data addr in mbuf (%p) is not aligned to device min alignment (%u)",
607f714a188SAmr Mokhtar 					data, min_alignment);
608f714a188SAmr Mokhtar 			rte_memcpy(data, seg->addr, seg->length);
609f714a188SAmr Mokhtar 			bufs[i].length += seg->length;
610f714a188SAmr Mokhtar 
611f714a188SAmr Mokhtar 			for (j = 1; j < ref_entries->nb_segments; ++j) {
612f714a188SAmr Mokhtar 				struct rte_mbuf *m_tail =
613f714a188SAmr Mokhtar 						rte_pktmbuf_alloc(mbuf_pool);
614f714a188SAmr Mokhtar 				TEST_ASSERT_NOT_NULL(m_tail,
615f714a188SAmr Mokhtar 						"Not enough mbufs in %d data type mbuf pool (needed %u, available %u)",
616f714a188SAmr Mokhtar 						op_type,
617f714a188SAmr Mokhtar 						n * ref_entries->nb_segments,
618f714a188SAmr Mokhtar 						mbuf_pool->size);
619f714a188SAmr Mokhtar 				seg += 1;
620f714a188SAmr Mokhtar 
621f714a188SAmr Mokhtar 				data = rte_pktmbuf_append(m_tail, seg->length);
622f714a188SAmr Mokhtar 				TEST_ASSERT_NOT_NULL(data,
623f714a188SAmr Mokhtar 						"Couldn't append %u bytes to mbuf from %d data type mbuf pool",
624f714a188SAmr Mokhtar 						seg->length, op_type);
625f714a188SAmr Mokhtar 
626f714a188SAmr Mokhtar 				TEST_ASSERT(data == RTE_PTR_ALIGN(data,
627f714a188SAmr Mokhtar 						min_alignment),
628f714a188SAmr Mokhtar 						"Data addr in mbuf (%p) is not aligned to device min alignment (%u)",
629f714a188SAmr Mokhtar 						data, min_alignment);
630f714a188SAmr Mokhtar 				rte_memcpy(data, seg->addr, seg->length);
631f714a188SAmr Mokhtar 				bufs[i].length += seg->length;
632f714a188SAmr Mokhtar 
633f714a188SAmr Mokhtar 				ret = rte_pktmbuf_chain(m_head, m_tail);
634f714a188SAmr Mokhtar 				TEST_ASSERT_SUCCESS(ret,
635f714a188SAmr Mokhtar 						"Couldn't chain mbufs from %d data type mbuf pool",
636f714a188SAmr Mokhtar 						op_type);
637f714a188SAmr Mokhtar 			}
6389585f8b1SKamil Chalupnik 
6399585f8b1SKamil Chalupnik 		} else {
6409585f8b1SKamil Chalupnik 
6419585f8b1SKamil Chalupnik 			/* allocate chained-mbuf for output buffer */
6429585f8b1SKamil Chalupnik 			for (j = 1; j < ref_entries->nb_segments; ++j) {
6439585f8b1SKamil Chalupnik 				struct rte_mbuf *m_tail =
6449585f8b1SKamil Chalupnik 						rte_pktmbuf_alloc(mbuf_pool);
6459585f8b1SKamil Chalupnik 				TEST_ASSERT_NOT_NULL(m_tail,
6469585f8b1SKamil Chalupnik 						"Not enough mbufs in %d data type mbuf pool (needed %u, available %u)",
6479585f8b1SKamil Chalupnik 						op_type,
6489585f8b1SKamil Chalupnik 						n * ref_entries->nb_segments,
6499585f8b1SKamil Chalupnik 						mbuf_pool->size);
6509585f8b1SKamil Chalupnik 
6519585f8b1SKamil Chalupnik 				ret = rte_pktmbuf_chain(m_head, m_tail);
6529585f8b1SKamil Chalupnik 				TEST_ASSERT_SUCCESS(ret,
6539585f8b1SKamil Chalupnik 						"Couldn't chain mbufs from %d data type mbuf pool",
6549585f8b1SKamil Chalupnik 						op_type);
6559585f8b1SKamil Chalupnik 			}
656f714a188SAmr Mokhtar 		}
657f714a188SAmr Mokhtar 	}
658f714a188SAmr Mokhtar 
659f714a188SAmr Mokhtar 	return 0;
660f714a188SAmr Mokhtar }
661f714a188SAmr Mokhtar 
662f714a188SAmr Mokhtar static int
663f714a188SAmr Mokhtar allocate_buffers_on_socket(struct rte_bbdev_op_data **buffers, const int len,
664f714a188SAmr Mokhtar 		const int socket)
665f714a188SAmr Mokhtar {
666f714a188SAmr Mokhtar 	int i;
667f714a188SAmr Mokhtar 
668f714a188SAmr Mokhtar 	*buffers = rte_zmalloc_socket(NULL, len, 0, socket);
669f714a188SAmr Mokhtar 	if (*buffers == NULL) {
670f714a188SAmr Mokhtar 		printf("WARNING: Failed to allocate op_data on socket %d\n",
671f714a188SAmr Mokhtar 				socket);
672f714a188SAmr Mokhtar 		/* try to allocate memory on other detected sockets */
673f714a188SAmr Mokhtar 		for (i = 0; i < socket; i++) {
674f714a188SAmr Mokhtar 			*buffers = rte_zmalloc_socket(NULL, len, 0, i);
675f714a188SAmr Mokhtar 			if (*buffers != NULL)
676f714a188SAmr Mokhtar 				break;
677f714a188SAmr Mokhtar 		}
678f714a188SAmr Mokhtar 	}
679f714a188SAmr Mokhtar 
680f714a188SAmr Mokhtar 	return (*buffers == NULL) ? TEST_FAILED : TEST_SUCCESS;
681f714a188SAmr Mokhtar }
682f714a188SAmr Mokhtar 
68347d5a049SKamil Chalupnik static void
68447d5a049SKamil Chalupnik limit_input_llr_val_range(struct rte_bbdev_op_data *input_ops,
68547d5a049SKamil Chalupnik 		uint16_t n, int8_t max_llr_modulus)
68647d5a049SKamil Chalupnik {
68747d5a049SKamil Chalupnik 	uint16_t i, byte_idx;
68847d5a049SKamil Chalupnik 
68947d5a049SKamil Chalupnik 	for (i = 0; i < n; ++i) {
69047d5a049SKamil Chalupnik 		struct rte_mbuf *m = input_ops[i].data;
69147d5a049SKamil Chalupnik 		while (m != NULL) {
69247d5a049SKamil Chalupnik 			int8_t *llr = rte_pktmbuf_mtod_offset(m, int8_t *,
69347d5a049SKamil Chalupnik 					input_ops[i].offset);
6949585f8b1SKamil Chalupnik 			for (byte_idx = 0; byte_idx < rte_pktmbuf_data_len(m);
69547d5a049SKamil Chalupnik 					++byte_idx)
69647d5a049SKamil Chalupnik 				llr[byte_idx] = round((double)max_llr_modulus *
69747d5a049SKamil Chalupnik 						llr[byte_idx] / INT8_MAX);
69847d5a049SKamil Chalupnik 
69947d5a049SKamil Chalupnik 			m = m->next;
70047d5a049SKamil Chalupnik 		}
70147d5a049SKamil Chalupnik 	}
70247d5a049SKamil Chalupnik }
70347d5a049SKamil Chalupnik 
704f714a188SAmr Mokhtar static int
705f714a188SAmr Mokhtar fill_queue_buffers(struct test_op_params *op_params,
706f714a188SAmr Mokhtar 		struct rte_mempool *in_mp, struct rte_mempool *hard_out_mp,
707f714a188SAmr Mokhtar 		struct rte_mempool *soft_out_mp, uint16_t queue_id,
70847d5a049SKamil Chalupnik 		const struct rte_bbdev_op_cap *capabilities,
709f714a188SAmr Mokhtar 		uint16_t min_alignment, const int socket_id)
710f714a188SAmr Mokhtar {
711f714a188SAmr Mokhtar 	int ret;
712f714a188SAmr Mokhtar 	enum op_data_type type;
713f714a188SAmr Mokhtar 	const uint16_t n = op_params->num_to_process;
714f714a188SAmr Mokhtar 
715f714a188SAmr Mokhtar 	struct rte_mempool *mbuf_pools[DATA_NUM_TYPES] = {
716f714a188SAmr Mokhtar 		in_mp,
717f714a188SAmr Mokhtar 		soft_out_mp,
718f714a188SAmr Mokhtar 		hard_out_mp,
719f714a188SAmr Mokhtar 	};
720f714a188SAmr Mokhtar 
721f714a188SAmr Mokhtar 	struct rte_bbdev_op_data **queue_ops[DATA_NUM_TYPES] = {
722f714a188SAmr Mokhtar 		&op_params->q_bufs[socket_id][queue_id].inputs,
723f714a188SAmr Mokhtar 		&op_params->q_bufs[socket_id][queue_id].soft_outputs,
724f714a188SAmr Mokhtar 		&op_params->q_bufs[socket_id][queue_id].hard_outputs,
725f714a188SAmr Mokhtar 	};
726f714a188SAmr Mokhtar 
727f714a188SAmr Mokhtar 	for (type = DATA_INPUT; type < DATA_NUM_TYPES; ++type) {
728f714a188SAmr Mokhtar 		struct op_data_entries *ref_entries =
729f714a188SAmr Mokhtar 				&test_vector.entries[type];
730f714a188SAmr Mokhtar 		if (ref_entries->nb_segments == 0)
731f714a188SAmr Mokhtar 			continue;
732f714a188SAmr Mokhtar 
733f714a188SAmr Mokhtar 		ret = allocate_buffers_on_socket(queue_ops[type],
734f714a188SAmr Mokhtar 				n * sizeof(struct rte_bbdev_op_data),
735f714a188SAmr Mokhtar 				socket_id);
736f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(ret,
737f714a188SAmr Mokhtar 				"Couldn't allocate memory for rte_bbdev_op_data structs");
738f714a188SAmr Mokhtar 
739f714a188SAmr Mokhtar 		ret = init_op_data_objs(*queue_ops[type], ref_entries,
740f714a188SAmr Mokhtar 				mbuf_pools[type], n, type, min_alignment);
741f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(ret,
742f714a188SAmr Mokhtar 				"Couldn't init rte_bbdev_op_data structs");
743f714a188SAmr Mokhtar 	}
744f714a188SAmr Mokhtar 
74547d5a049SKamil Chalupnik 	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
74647d5a049SKamil Chalupnik 		limit_input_llr_val_range(*queue_ops[DATA_INPUT], n,
74747d5a049SKamil Chalupnik 			capabilities->cap.turbo_dec.max_llr_modulus);
74847d5a049SKamil Chalupnik 
749f714a188SAmr Mokhtar 	return 0;
750f714a188SAmr Mokhtar }
751f714a188SAmr Mokhtar 
752f714a188SAmr Mokhtar static void
753f714a188SAmr Mokhtar free_buffers(struct active_device *ad, struct test_op_params *op_params)
754f714a188SAmr Mokhtar {
755f714a188SAmr Mokhtar 	unsigned int i, j;
756f714a188SAmr Mokhtar 
757f714a188SAmr Mokhtar 	rte_mempool_free(ad->ops_mempool);
758f714a188SAmr Mokhtar 	rte_mempool_free(ad->in_mbuf_pool);
759f714a188SAmr Mokhtar 	rte_mempool_free(ad->hard_out_mbuf_pool);
760f714a188SAmr Mokhtar 	rte_mempool_free(ad->soft_out_mbuf_pool);
761f714a188SAmr Mokhtar 
762f714a188SAmr Mokhtar 	for (i = 0; i < rte_lcore_count(); ++i) {
763f714a188SAmr Mokhtar 		for (j = 0; j < RTE_MAX_NUMA_NODES; ++j) {
764f714a188SAmr Mokhtar 			rte_free(op_params->q_bufs[j][i].inputs);
765f714a188SAmr Mokhtar 			rte_free(op_params->q_bufs[j][i].hard_outputs);
766f714a188SAmr Mokhtar 			rte_free(op_params->q_bufs[j][i].soft_outputs);
767f714a188SAmr Mokhtar 		}
768f714a188SAmr Mokhtar 	}
769f714a188SAmr Mokhtar }
770f714a188SAmr Mokhtar 
771f714a188SAmr Mokhtar static void
772f714a188SAmr Mokhtar copy_reference_dec_op(struct rte_bbdev_dec_op **ops, unsigned int n,
773f714a188SAmr Mokhtar 		unsigned int start_idx,
774f714a188SAmr Mokhtar 		struct rte_bbdev_op_data *inputs,
775f714a188SAmr Mokhtar 		struct rte_bbdev_op_data *hard_outputs,
776f714a188SAmr Mokhtar 		struct rte_bbdev_op_data *soft_outputs,
777f714a188SAmr Mokhtar 		struct rte_bbdev_dec_op *ref_op)
778f714a188SAmr Mokhtar {
779f714a188SAmr Mokhtar 	unsigned int i;
780f714a188SAmr Mokhtar 	struct rte_bbdev_op_turbo_dec *turbo_dec = &ref_op->turbo_dec;
781f714a188SAmr Mokhtar 
782f714a188SAmr Mokhtar 	for (i = 0; i < n; ++i) {
783f714a188SAmr Mokhtar 		if (turbo_dec->code_block_mode == 0) {
784f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.ea =
785f714a188SAmr Mokhtar 					turbo_dec->tb_params.ea;
786f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.eb =
787f714a188SAmr Mokhtar 					turbo_dec->tb_params.eb;
788f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.k_pos =
789f714a188SAmr Mokhtar 					turbo_dec->tb_params.k_pos;
790f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.k_neg =
791f714a188SAmr Mokhtar 					turbo_dec->tb_params.k_neg;
792f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.c =
793f714a188SAmr Mokhtar 					turbo_dec->tb_params.c;
794f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.c_neg =
795f714a188SAmr Mokhtar 					turbo_dec->tb_params.c_neg;
796f714a188SAmr Mokhtar 			ops[i]->turbo_dec.tb_params.cab =
797f714a188SAmr Mokhtar 					turbo_dec->tb_params.cab;
7980b98d574SKamil Chalupnik 			ops[i]->turbo_dec.tb_params.r =
7990b98d574SKamil Chalupnik 					turbo_dec->tb_params.r;
800f714a188SAmr Mokhtar 		} else {
801f714a188SAmr Mokhtar 			ops[i]->turbo_dec.cb_params.e = turbo_dec->cb_params.e;
802f714a188SAmr Mokhtar 			ops[i]->turbo_dec.cb_params.k = turbo_dec->cb_params.k;
803f714a188SAmr Mokhtar 		}
804f714a188SAmr Mokhtar 
805f714a188SAmr Mokhtar 		ops[i]->turbo_dec.ext_scale = turbo_dec->ext_scale;
806f714a188SAmr Mokhtar 		ops[i]->turbo_dec.iter_max = turbo_dec->iter_max;
807f714a188SAmr Mokhtar 		ops[i]->turbo_dec.iter_min = turbo_dec->iter_min;
808f714a188SAmr Mokhtar 		ops[i]->turbo_dec.op_flags = turbo_dec->op_flags;
809f714a188SAmr Mokhtar 		ops[i]->turbo_dec.rv_index = turbo_dec->rv_index;
810f714a188SAmr Mokhtar 		ops[i]->turbo_dec.num_maps = turbo_dec->num_maps;
811f714a188SAmr Mokhtar 		ops[i]->turbo_dec.code_block_mode = turbo_dec->code_block_mode;
812f714a188SAmr Mokhtar 
813f714a188SAmr Mokhtar 		ops[i]->turbo_dec.hard_output = hard_outputs[start_idx + i];
814f714a188SAmr Mokhtar 		ops[i]->turbo_dec.input = inputs[start_idx + i];
815f714a188SAmr Mokhtar 		if (soft_outputs != NULL)
816f714a188SAmr Mokhtar 			ops[i]->turbo_dec.soft_output =
817f714a188SAmr Mokhtar 				soft_outputs[start_idx + i];
818f714a188SAmr Mokhtar 	}
819f714a188SAmr Mokhtar }
820f714a188SAmr Mokhtar 
821f714a188SAmr Mokhtar static void
822f714a188SAmr Mokhtar copy_reference_enc_op(struct rte_bbdev_enc_op **ops, unsigned int n,
823f714a188SAmr Mokhtar 		unsigned int start_idx,
824f714a188SAmr Mokhtar 		struct rte_bbdev_op_data *inputs,
825f714a188SAmr Mokhtar 		struct rte_bbdev_op_data *outputs,
826f714a188SAmr Mokhtar 		struct rte_bbdev_enc_op *ref_op)
827f714a188SAmr Mokhtar {
828f714a188SAmr Mokhtar 	unsigned int i;
829f714a188SAmr Mokhtar 	struct rte_bbdev_op_turbo_enc *turbo_enc = &ref_op->turbo_enc;
830f714a188SAmr Mokhtar 	for (i = 0; i < n; ++i) {
831f714a188SAmr Mokhtar 		if (turbo_enc->code_block_mode == 0) {
832f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.ea =
833f714a188SAmr Mokhtar 					turbo_enc->tb_params.ea;
834f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.eb =
835f714a188SAmr Mokhtar 					turbo_enc->tb_params.eb;
836f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.k_pos =
837f714a188SAmr Mokhtar 					turbo_enc->tb_params.k_pos;
838f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.k_neg =
839f714a188SAmr Mokhtar 					turbo_enc->tb_params.k_neg;
840f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.c =
841f714a188SAmr Mokhtar 					turbo_enc->tb_params.c;
842f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.c_neg =
843f714a188SAmr Mokhtar 					turbo_enc->tb_params.c_neg;
844f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.cab =
845f714a188SAmr Mokhtar 					turbo_enc->tb_params.cab;
846f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.ncb_pos =
847f714a188SAmr Mokhtar 					turbo_enc->tb_params.ncb_pos;
848f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.ncb_neg =
849f714a188SAmr Mokhtar 					turbo_enc->tb_params.ncb_neg;
850f714a188SAmr Mokhtar 			ops[i]->turbo_enc.tb_params.r = turbo_enc->tb_params.r;
851f714a188SAmr Mokhtar 		} else {
852f714a188SAmr Mokhtar 			ops[i]->turbo_enc.cb_params.e = turbo_enc->cb_params.e;
853f714a188SAmr Mokhtar 			ops[i]->turbo_enc.cb_params.k = turbo_enc->cb_params.k;
854f714a188SAmr Mokhtar 			ops[i]->turbo_enc.cb_params.ncb =
855f714a188SAmr Mokhtar 					turbo_enc->cb_params.ncb;
856f714a188SAmr Mokhtar 		}
857f714a188SAmr Mokhtar 		ops[i]->turbo_enc.rv_index = turbo_enc->rv_index;
858f714a188SAmr Mokhtar 		ops[i]->turbo_enc.op_flags = turbo_enc->op_flags;
859f714a188SAmr Mokhtar 		ops[i]->turbo_enc.code_block_mode = turbo_enc->code_block_mode;
860f714a188SAmr Mokhtar 
861f714a188SAmr Mokhtar 		ops[i]->turbo_enc.output = outputs[start_idx + i];
862f714a188SAmr Mokhtar 		ops[i]->turbo_enc.input = inputs[start_idx + i];
863f714a188SAmr Mokhtar 	}
864f714a188SAmr Mokhtar }
865f714a188SAmr Mokhtar 
866f714a188SAmr Mokhtar static int
867f714a188SAmr Mokhtar check_dec_status_and_ordering(struct rte_bbdev_dec_op *op,
868f714a188SAmr Mokhtar 		unsigned int order_idx, const int expected_status)
869f714a188SAmr Mokhtar {
870f714a188SAmr Mokhtar 	TEST_ASSERT(op->status == expected_status,
871f714a188SAmr Mokhtar 			"op_status (%d) != expected_status (%d)",
872f714a188SAmr Mokhtar 			op->status, expected_status);
873f714a188SAmr Mokhtar 
874f714a188SAmr Mokhtar 	TEST_ASSERT((void *)(uintptr_t)order_idx == op->opaque_data,
875f714a188SAmr Mokhtar 			"Ordering error, expected %p, got %p",
876f714a188SAmr Mokhtar 			(void *)(uintptr_t)order_idx, op->opaque_data);
877f714a188SAmr Mokhtar 
878f714a188SAmr Mokhtar 	return TEST_SUCCESS;
879f714a188SAmr Mokhtar }
880f714a188SAmr Mokhtar 
881f714a188SAmr Mokhtar static int
882f714a188SAmr Mokhtar check_enc_status_and_ordering(struct rte_bbdev_enc_op *op,
883f714a188SAmr Mokhtar 		unsigned int order_idx, const int expected_status)
884f714a188SAmr Mokhtar {
885f714a188SAmr Mokhtar 	TEST_ASSERT(op->status == expected_status,
886f714a188SAmr Mokhtar 			"op_status (%d) != expected_status (%d)",
887f714a188SAmr Mokhtar 			op->status, expected_status);
888f714a188SAmr Mokhtar 
889f714a188SAmr Mokhtar 	TEST_ASSERT((void *)(uintptr_t)order_idx == op->opaque_data,
890f714a188SAmr Mokhtar 			"Ordering error, expected %p, got %p",
891f714a188SAmr Mokhtar 			(void *)(uintptr_t)order_idx, op->opaque_data);
892f714a188SAmr Mokhtar 
893f714a188SAmr Mokhtar 	return TEST_SUCCESS;
894f714a188SAmr Mokhtar }
895f714a188SAmr Mokhtar 
896f714a188SAmr Mokhtar static inline int
897f714a188SAmr Mokhtar validate_op_chain(struct rte_bbdev_op_data *op,
898f714a188SAmr Mokhtar 		struct op_data_entries *orig_op)
899f714a188SAmr Mokhtar {
900f714a188SAmr Mokhtar 	uint8_t i;
901f714a188SAmr Mokhtar 	struct rte_mbuf *m = op->data;
902f714a188SAmr Mokhtar 	uint8_t nb_dst_segments = orig_op->nb_segments;
9039585f8b1SKamil Chalupnik 	uint32_t total_data_size = 0;
904f714a188SAmr Mokhtar 
905f714a188SAmr Mokhtar 	TEST_ASSERT(nb_dst_segments == m->nb_segs,
906f714a188SAmr Mokhtar 			"Number of segments differ in original (%u) and filled (%u) op",
907f714a188SAmr Mokhtar 			nb_dst_segments, m->nb_segs);
908f714a188SAmr Mokhtar 
9099585f8b1SKamil Chalupnik 	/* Validate each mbuf segment length */
910f714a188SAmr Mokhtar 	for (i = 0; i < nb_dst_segments; ++i) {
911f714a188SAmr Mokhtar 		/* Apply offset to the first mbuf segment */
912f714a188SAmr Mokhtar 		uint16_t offset = (i == 0) ? op->offset : 0;
9139585f8b1SKamil Chalupnik 		uint16_t data_len = rte_pktmbuf_data_len(m) - offset;
9149585f8b1SKamil Chalupnik 		total_data_size += orig_op->segments[i].length;
915f714a188SAmr Mokhtar 
916f714a188SAmr Mokhtar 		TEST_ASSERT(orig_op->segments[i].length == data_len,
917f714a188SAmr Mokhtar 				"Length of segment differ in original (%u) and filled (%u) op",
918f714a188SAmr Mokhtar 				orig_op->segments[i].length, data_len);
919f714a188SAmr Mokhtar 		TEST_ASSERT_BUFFERS_ARE_EQUAL(orig_op->segments[i].addr,
920f714a188SAmr Mokhtar 				rte_pktmbuf_mtod_offset(m, uint32_t *, offset),
921f714a188SAmr Mokhtar 				data_len,
922f714a188SAmr Mokhtar 				"Output buffers (CB=%u) are not equal", i);
923f714a188SAmr Mokhtar 		m = m->next;
924f714a188SAmr Mokhtar 	}
925f714a188SAmr Mokhtar 
9269585f8b1SKamil Chalupnik 	/* Validate total mbuf pkt length */
9279585f8b1SKamil Chalupnik 	uint32_t pkt_len = rte_pktmbuf_pkt_len(op->data) - op->offset;
9289585f8b1SKamil Chalupnik 	TEST_ASSERT(total_data_size == pkt_len,
9299585f8b1SKamil Chalupnik 			"Length of data differ in original (%u) and filled (%u) op",
9309585f8b1SKamil Chalupnik 			total_data_size, pkt_len);
9319585f8b1SKamil Chalupnik 
932f714a188SAmr Mokhtar 	return TEST_SUCCESS;
933f714a188SAmr Mokhtar }
934f714a188SAmr Mokhtar 
935f714a188SAmr Mokhtar static int
936f714a188SAmr Mokhtar validate_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
937f714a188SAmr Mokhtar 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
938f714a188SAmr Mokhtar {
939f714a188SAmr Mokhtar 	unsigned int i;
940f714a188SAmr Mokhtar 	int ret;
941f714a188SAmr Mokhtar 	struct op_data_entries *hard_data_orig =
942f714a188SAmr Mokhtar 			&test_vector.entries[DATA_HARD_OUTPUT];
943f714a188SAmr Mokhtar 	struct op_data_entries *soft_data_orig =
944f714a188SAmr Mokhtar 			&test_vector.entries[DATA_SOFT_OUTPUT];
945f714a188SAmr Mokhtar 	struct rte_bbdev_op_turbo_dec *ops_td;
946f714a188SAmr Mokhtar 	struct rte_bbdev_op_data *hard_output;
947f714a188SAmr Mokhtar 	struct rte_bbdev_op_data *soft_output;
948f714a188SAmr Mokhtar 	struct rte_bbdev_op_turbo_dec *ref_td = &ref_op->turbo_dec;
949f714a188SAmr Mokhtar 
950f714a188SAmr Mokhtar 	for (i = 0; i < n; ++i) {
951f714a188SAmr Mokhtar 		ops_td = &ops[i]->turbo_dec;
952f714a188SAmr Mokhtar 		hard_output = &ops_td->hard_output;
953f714a188SAmr Mokhtar 		soft_output = &ops_td->soft_output;
954f714a188SAmr Mokhtar 
955f714a188SAmr Mokhtar 		if (vector_mask & TEST_BBDEV_VF_EXPECTED_ITER_COUNT)
956f714a188SAmr Mokhtar 			TEST_ASSERT(ops_td->iter_count <= ref_td->iter_count,
957f714a188SAmr Mokhtar 					"Returned iter_count (%d) > expected iter_count (%d)",
958f714a188SAmr Mokhtar 					ops_td->iter_count, ref_td->iter_count);
959f714a188SAmr Mokhtar 		ret = check_dec_status_and_ordering(ops[i], i, ref_op->status);
960f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(ret,
961f714a188SAmr Mokhtar 				"Checking status and ordering for decoder failed");
962f714a188SAmr Mokhtar 
963f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(validate_op_chain(hard_output,
964f714a188SAmr Mokhtar 				hard_data_orig),
965f714a188SAmr Mokhtar 				"Hard output buffers (CB=%u) are not equal",
966f714a188SAmr Mokhtar 				i);
967f714a188SAmr Mokhtar 
968f714a188SAmr Mokhtar 		if (ref_op->turbo_dec.op_flags & RTE_BBDEV_TURBO_SOFT_OUTPUT)
969f714a188SAmr Mokhtar 			TEST_ASSERT_SUCCESS(validate_op_chain(soft_output,
970f714a188SAmr Mokhtar 					soft_data_orig),
971f714a188SAmr Mokhtar 					"Soft output buffers (CB=%u) are not equal",
972f714a188SAmr Mokhtar 					i);
973f714a188SAmr Mokhtar 	}
974f714a188SAmr Mokhtar 
975f714a188SAmr Mokhtar 	return TEST_SUCCESS;
976f714a188SAmr Mokhtar }
977f714a188SAmr Mokhtar 
978f714a188SAmr Mokhtar static int
979f714a188SAmr Mokhtar validate_enc_op(struct rte_bbdev_enc_op **ops, const uint16_t n,
980f714a188SAmr Mokhtar 		struct rte_bbdev_enc_op *ref_op)
981f714a188SAmr Mokhtar {
982f714a188SAmr Mokhtar 	unsigned int i;
983f714a188SAmr Mokhtar 	int ret;
984f714a188SAmr Mokhtar 	struct op_data_entries *hard_data_orig =
985f714a188SAmr Mokhtar 			&test_vector.entries[DATA_HARD_OUTPUT];
986f714a188SAmr Mokhtar 
987f714a188SAmr Mokhtar 	for (i = 0; i < n; ++i) {
988f714a188SAmr Mokhtar 		ret = check_enc_status_and_ordering(ops[i], i, ref_op->status);
989f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(ret,
990f714a188SAmr Mokhtar 				"Checking status and ordering for encoder failed");
991f714a188SAmr Mokhtar 		TEST_ASSERT_SUCCESS(validate_op_chain(
992f714a188SAmr Mokhtar 				&ops[i]->turbo_enc.output,
993f714a188SAmr Mokhtar 				hard_data_orig),
994f714a188SAmr Mokhtar 				"Output buffers (CB=%u) are not equal",
995f714a188SAmr Mokhtar 				i);
996f714a188SAmr Mokhtar 	}
997f714a188SAmr Mokhtar 
998f714a188SAmr Mokhtar 	return TEST_SUCCESS;
999f714a188SAmr Mokhtar }
1000f714a188SAmr Mokhtar 
1001f714a188SAmr Mokhtar static void
1002f714a188SAmr Mokhtar create_reference_dec_op(struct rte_bbdev_dec_op *op)
1003f714a188SAmr Mokhtar {
1004f714a188SAmr Mokhtar 	unsigned int i;
1005f714a188SAmr Mokhtar 	struct op_data_entries *entry;
1006f714a188SAmr Mokhtar 
1007f714a188SAmr Mokhtar 	op->turbo_dec = test_vector.turbo_dec;
1008f714a188SAmr Mokhtar 	entry = &test_vector.entries[DATA_INPUT];
1009f714a188SAmr Mokhtar 	for (i = 0; i < entry->nb_segments; ++i)
1010f714a188SAmr Mokhtar 		op->turbo_dec.input.length +=
1011f714a188SAmr Mokhtar 				entry->segments[i].length;
1012f714a188SAmr Mokhtar }
1013f714a188SAmr Mokhtar 
1014f714a188SAmr Mokhtar static void
1015f714a188SAmr Mokhtar create_reference_enc_op(struct rte_bbdev_enc_op *op)
1016f714a188SAmr Mokhtar {
1017f714a188SAmr Mokhtar 	unsigned int i;
1018f714a188SAmr Mokhtar 	struct op_data_entries *entry;
1019f714a188SAmr Mokhtar 
1020f714a188SAmr Mokhtar 	op->turbo_enc = test_vector.turbo_enc;
1021f714a188SAmr Mokhtar 	entry = &test_vector.entries[DATA_INPUT];
1022f714a188SAmr Mokhtar 	for (i = 0; i < entry->nb_segments; ++i)
1023f714a188SAmr Mokhtar 		op->turbo_enc.input.length +=
1024f714a188SAmr Mokhtar 				entry->segments[i].length;
1025f714a188SAmr Mokhtar }
1026f714a188SAmr Mokhtar 
10270b98d574SKamil Chalupnik static uint32_t
10280b98d574SKamil Chalupnik calc_dec_TB_size(struct rte_bbdev_dec_op *op)
10290b98d574SKamil Chalupnik {
10300b98d574SKamil Chalupnik 	uint8_t i;
10310b98d574SKamil Chalupnik 	uint32_t c, r, tb_size = 0;
10320b98d574SKamil Chalupnik 
10330b98d574SKamil Chalupnik 	if (op->turbo_dec.code_block_mode) {
10340b98d574SKamil Chalupnik 		tb_size = op->turbo_dec.tb_params.k_neg;
10350b98d574SKamil Chalupnik 	} else {
10360b98d574SKamil Chalupnik 		c = op->turbo_dec.tb_params.c;
10370b98d574SKamil Chalupnik 		r = op->turbo_dec.tb_params.r;
10380b98d574SKamil Chalupnik 		for (i = 0; i < c-r; i++)
10390b98d574SKamil Chalupnik 			tb_size += (r < op->turbo_dec.tb_params.c_neg) ?
10400b98d574SKamil Chalupnik 				op->turbo_dec.tb_params.k_neg :
10410b98d574SKamil Chalupnik 				op->turbo_dec.tb_params.k_pos;
10420b98d574SKamil Chalupnik 	}
10430b98d574SKamil Chalupnik 	return tb_size;
10440b98d574SKamil Chalupnik }
10450b98d574SKamil Chalupnik 
10460b98d574SKamil Chalupnik static uint32_t
10470b98d574SKamil Chalupnik calc_enc_TB_size(struct rte_bbdev_enc_op *op)
10480b98d574SKamil Chalupnik {
10490b98d574SKamil Chalupnik 	uint8_t i;
10500b98d574SKamil Chalupnik 	uint32_t c, r, tb_size = 0;
10510b98d574SKamil Chalupnik 
10520b98d574SKamil Chalupnik 	if (op->turbo_enc.code_block_mode) {
10530b98d574SKamil Chalupnik 		tb_size = op->turbo_enc.tb_params.k_neg;
10540b98d574SKamil Chalupnik 	} else {
10550b98d574SKamil Chalupnik 		c = op->turbo_enc.tb_params.c;
10560b98d574SKamil Chalupnik 		r = op->turbo_enc.tb_params.r;
10570b98d574SKamil Chalupnik 		for (i = 0; i < c-r; i++)
10580b98d574SKamil Chalupnik 			tb_size += (r < op->turbo_enc.tb_params.c_neg) ?
10590b98d574SKamil Chalupnik 				op->turbo_enc.tb_params.k_neg :
10600b98d574SKamil Chalupnik 				op->turbo_enc.tb_params.k_pos;
10610b98d574SKamil Chalupnik 	}
10620b98d574SKamil Chalupnik 	return tb_size;
10630b98d574SKamil Chalupnik }
10640b98d574SKamil Chalupnik 
1065f714a188SAmr Mokhtar static int
1066f714a188SAmr Mokhtar init_test_op_params(struct test_op_params *op_params,
1067f714a188SAmr Mokhtar 		enum rte_bbdev_op_type op_type, const int expected_status,
1068f714a188SAmr Mokhtar 		const int vector_mask, struct rte_mempool *ops_mp,
1069f714a188SAmr Mokhtar 		uint16_t burst_sz, uint16_t num_to_process, uint16_t num_lcores)
1070f714a188SAmr Mokhtar {
1071f714a188SAmr Mokhtar 	int ret = 0;
1072f714a188SAmr Mokhtar 	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
1073f714a188SAmr Mokhtar 		ret = rte_bbdev_dec_op_alloc_bulk(ops_mp,
1074f714a188SAmr Mokhtar 				&op_params->ref_dec_op, 1);
1075f714a188SAmr Mokhtar 	else
1076f714a188SAmr Mokhtar 		ret = rte_bbdev_enc_op_alloc_bulk(ops_mp,
1077f714a188SAmr Mokhtar 				&op_params->ref_enc_op, 1);
1078f714a188SAmr Mokhtar 
1079f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS(ret, "rte_bbdev_op_alloc_bulk() failed");
1080f714a188SAmr Mokhtar 
1081f714a188SAmr Mokhtar 	op_params->mp = ops_mp;
1082f714a188SAmr Mokhtar 	op_params->burst_sz = burst_sz;
1083f714a188SAmr Mokhtar 	op_params->num_to_process = num_to_process;
1084f714a188SAmr Mokhtar 	op_params->num_lcores = num_lcores;
1085f714a188SAmr Mokhtar 	op_params->vector_mask = vector_mask;
1086f714a188SAmr Mokhtar 	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
1087f714a188SAmr Mokhtar 		op_params->ref_dec_op->status = expected_status;
1088f714a188SAmr Mokhtar 	else if (op_type == RTE_BBDEV_OP_TURBO_ENC)
1089f714a188SAmr Mokhtar 		op_params->ref_enc_op->status = expected_status;
1090f714a188SAmr Mokhtar 
1091f714a188SAmr Mokhtar 	return 0;
1092f714a188SAmr Mokhtar }
1093f714a188SAmr Mokhtar 
1094f714a188SAmr Mokhtar static int
1095f714a188SAmr Mokhtar run_test_case_on_device(test_case_function *test_case_func, uint8_t dev_id,
1096f714a188SAmr Mokhtar 		struct test_op_params *op_params)
1097f714a188SAmr Mokhtar {
1098f714a188SAmr Mokhtar 	int t_ret, f_ret, socket_id = SOCKET_ID_ANY;
1099f714a188SAmr Mokhtar 	unsigned int i;
1100f714a188SAmr Mokhtar 	struct active_device *ad;
1101f714a188SAmr Mokhtar 	unsigned int burst_sz = get_burst_sz();
1102f714a188SAmr Mokhtar 	enum rte_bbdev_op_type op_type = test_vector.op_type;
110347d5a049SKamil Chalupnik 	const struct rte_bbdev_op_cap *capabilities = NULL;
1104f714a188SAmr Mokhtar 
1105f714a188SAmr Mokhtar 	ad = &active_devs[dev_id];
1106f714a188SAmr Mokhtar 
1107f714a188SAmr Mokhtar 	/* Check if device supports op_type */
1108f714a188SAmr Mokhtar 	if (!is_avail_op(ad, test_vector.op_type))
1109f714a188SAmr Mokhtar 		return TEST_SUCCESS;
1110f714a188SAmr Mokhtar 
1111f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
1112f714a188SAmr Mokhtar 	rte_bbdev_info_get(ad->dev_id, &info);
1113f714a188SAmr Mokhtar 	socket_id = GET_SOCKET(info.socket_id);
1114f714a188SAmr Mokhtar 
1115f714a188SAmr Mokhtar 	f_ret = create_mempools(ad, socket_id, op_type,
1116f714a188SAmr Mokhtar 			get_num_ops());
1117f714a188SAmr Mokhtar 	if (f_ret != TEST_SUCCESS) {
1118f714a188SAmr Mokhtar 		printf("Couldn't create mempools");
1119f714a188SAmr Mokhtar 		goto fail;
1120f714a188SAmr Mokhtar 	}
1121ad458935SKamil Chalupnik 	if (op_type == RTE_BBDEV_OP_NONE)
1122ad458935SKamil Chalupnik 		op_type = RTE_BBDEV_OP_TURBO_ENC;
1123f714a188SAmr Mokhtar 
1124f714a188SAmr Mokhtar 	f_ret = init_test_op_params(op_params, test_vector.op_type,
1125f714a188SAmr Mokhtar 			test_vector.expected_status,
1126f714a188SAmr Mokhtar 			test_vector.mask,
1127f714a188SAmr Mokhtar 			ad->ops_mempool,
1128f714a188SAmr Mokhtar 			burst_sz,
1129f714a188SAmr Mokhtar 			get_num_ops(),
1130f714a188SAmr Mokhtar 			get_num_lcores());
1131f714a188SAmr Mokhtar 	if (f_ret != TEST_SUCCESS) {
1132f714a188SAmr Mokhtar 		printf("Couldn't init test op params");
1133f714a188SAmr Mokhtar 		goto fail;
1134f714a188SAmr Mokhtar 	}
1135f714a188SAmr Mokhtar 
113647d5a049SKamil Chalupnik 	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) {
113747d5a049SKamil Chalupnik 		/* Find Decoder capabilities */
113847d5a049SKamil Chalupnik 		const struct rte_bbdev_op_cap *cap = info.drv.capabilities;
113947d5a049SKamil Chalupnik 		while (cap->type != RTE_BBDEV_OP_NONE) {
114047d5a049SKamil Chalupnik 			if (cap->type == RTE_BBDEV_OP_TURBO_DEC) {
114147d5a049SKamil Chalupnik 				capabilities = cap;
114247d5a049SKamil Chalupnik 				break;
114347d5a049SKamil Chalupnik 			}
114447d5a049SKamil Chalupnik 		}
114547d5a049SKamil Chalupnik 		TEST_ASSERT_NOT_NULL(capabilities,
114647d5a049SKamil Chalupnik 				"Couldn't find Decoder capabilities");
114747d5a049SKamil Chalupnik 
1148f714a188SAmr Mokhtar 		create_reference_dec_op(op_params->ref_dec_op);
114947d5a049SKamil Chalupnik 	} else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC)
1150f714a188SAmr Mokhtar 		create_reference_enc_op(op_params->ref_enc_op);
1151f714a188SAmr Mokhtar 
1152f714a188SAmr Mokhtar 	for (i = 0; i < ad->nb_queues; ++i) {
1153f714a188SAmr Mokhtar 		f_ret = fill_queue_buffers(op_params,
1154f714a188SAmr Mokhtar 				ad->in_mbuf_pool,
1155f714a188SAmr Mokhtar 				ad->hard_out_mbuf_pool,
1156f714a188SAmr Mokhtar 				ad->soft_out_mbuf_pool,
1157f714a188SAmr Mokhtar 				ad->queue_ids[i],
115847d5a049SKamil Chalupnik 				capabilities,
1159f714a188SAmr Mokhtar 				info.drv.min_alignment,
1160f714a188SAmr Mokhtar 				socket_id);
1161f714a188SAmr Mokhtar 		if (f_ret != TEST_SUCCESS) {
1162f714a188SAmr Mokhtar 			printf("Couldn't init queue buffers");
1163f714a188SAmr Mokhtar 			goto fail;
1164f714a188SAmr Mokhtar 		}
1165f714a188SAmr Mokhtar 	}
1166f714a188SAmr Mokhtar 
1167f714a188SAmr Mokhtar 	/* Run test case function */
1168f714a188SAmr Mokhtar 	t_ret = test_case_func(ad, op_params);
1169f714a188SAmr Mokhtar 
1170f714a188SAmr Mokhtar 	/* Free active device resources and return */
1171f714a188SAmr Mokhtar 	free_buffers(ad, op_params);
1172f714a188SAmr Mokhtar 	return t_ret;
1173f714a188SAmr Mokhtar 
1174f714a188SAmr Mokhtar fail:
1175f714a188SAmr Mokhtar 	free_buffers(ad, op_params);
1176f714a188SAmr Mokhtar 	return TEST_FAILED;
1177f714a188SAmr Mokhtar }
1178f714a188SAmr Mokhtar 
1179f714a188SAmr Mokhtar /* Run given test function per active device per supported op type
1180f714a188SAmr Mokhtar  * per burst size.
1181f714a188SAmr Mokhtar  */
1182f714a188SAmr Mokhtar static int
1183f714a188SAmr Mokhtar run_test_case(test_case_function *test_case_func)
1184f714a188SAmr Mokhtar {
1185f714a188SAmr Mokhtar 	int ret = 0;
1186f714a188SAmr Mokhtar 	uint8_t dev;
1187f714a188SAmr Mokhtar 
1188f714a188SAmr Mokhtar 	/* Alloc op_params */
1189f714a188SAmr Mokhtar 	struct test_op_params *op_params = rte_zmalloc(NULL,
1190f714a188SAmr Mokhtar 			sizeof(struct test_op_params), RTE_CACHE_LINE_SIZE);
1191f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(op_params, "Failed to alloc %zuB for op_params",
1192f714a188SAmr Mokhtar 			RTE_ALIGN(sizeof(struct test_op_params),
1193f714a188SAmr Mokhtar 				RTE_CACHE_LINE_SIZE));
1194f714a188SAmr Mokhtar 
1195f714a188SAmr Mokhtar 	/* For each device run test case function */
1196f714a188SAmr Mokhtar 	for (dev = 0; dev < nb_active_devs; ++dev)
1197f714a188SAmr Mokhtar 		ret |= run_test_case_on_device(test_case_func, dev, op_params);
1198f714a188SAmr Mokhtar 
1199f714a188SAmr Mokhtar 	rte_free(op_params);
1200f714a188SAmr Mokhtar 
1201f714a188SAmr Mokhtar 	return ret;
1202f714a188SAmr Mokhtar }
1203f714a188SAmr Mokhtar 
1204f714a188SAmr Mokhtar static void
1205f714a188SAmr Mokhtar dequeue_event_callback(uint16_t dev_id,
1206f714a188SAmr Mokhtar 		enum rte_bbdev_event_type event, void *cb_arg,
1207f714a188SAmr Mokhtar 		void *ret_param)
1208f714a188SAmr Mokhtar {
1209f714a188SAmr Mokhtar 	int ret;
1210f714a188SAmr Mokhtar 	uint16_t i;
1211f714a188SAmr Mokhtar 	uint64_t total_time;
12120b98d574SKamil Chalupnik 	uint16_t deq, burst_sz, num_ops;
1213*b2e2aec3SKamil Chalupnik 	uint16_t queue_id = *(uint16_t *) ret_param;
1214f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
1215f714a188SAmr Mokhtar 
12160b98d574SKamil Chalupnik 	double tb_len_bits;
1217f714a188SAmr Mokhtar 
1218f714a188SAmr Mokhtar 	struct thread_params *tp = cb_arg;
1219f714a188SAmr Mokhtar 
1220f714a188SAmr Mokhtar 	/* Find matching thread params using queue_id */
1221f714a188SAmr Mokhtar 	for (i = 0; i < MAX_QUEUES; ++i, ++tp)
1222f714a188SAmr Mokhtar 		if (tp->queue_id == queue_id)
1223f714a188SAmr Mokhtar 			break;
1224f714a188SAmr Mokhtar 
1225f714a188SAmr Mokhtar 	if (i == MAX_QUEUES) {
1226f714a188SAmr Mokhtar 		printf("%s: Queue_id from interrupt details was not found!\n",
1227f714a188SAmr Mokhtar 				__func__);
1228f714a188SAmr Mokhtar 		return;
1229f714a188SAmr Mokhtar 	}
1230f714a188SAmr Mokhtar 
1231f714a188SAmr Mokhtar 	if (unlikely(event != RTE_BBDEV_EVENT_DEQUEUE)) {
1232f714a188SAmr Mokhtar 		rte_atomic16_set(&tp->processing_status, TEST_FAILED);
1233f714a188SAmr Mokhtar 		printf(
1234f714a188SAmr Mokhtar 			"Dequeue interrupt handler called for incorrect event!\n");
1235f714a188SAmr Mokhtar 		return;
1236f714a188SAmr Mokhtar 	}
1237f714a188SAmr Mokhtar 
1238*b2e2aec3SKamil Chalupnik 	burst_sz = rte_atomic16_read(&tp->burst_sz);
12390b98d574SKamil Chalupnik 	num_ops = tp->op_params->num_to_process;
1240f714a188SAmr Mokhtar 
1241*b2e2aec3SKamil Chalupnik 	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
1242*b2e2aec3SKamil Chalupnik 		deq = rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
1243*b2e2aec3SKamil Chalupnik 				&tp->dec_ops[
1244*b2e2aec3SKamil Chalupnik 					rte_atomic16_read(&tp->nb_dequeued)],
1245f714a188SAmr Mokhtar 				burst_sz);
1246*b2e2aec3SKamil Chalupnik 	else
1247*b2e2aec3SKamil Chalupnik 		deq = rte_bbdev_dequeue_enc_ops(dev_id, queue_id,
1248*b2e2aec3SKamil Chalupnik 				&tp->enc_ops[
1249*b2e2aec3SKamil Chalupnik 					rte_atomic16_read(&tp->nb_dequeued)],
1250f714a188SAmr Mokhtar 				burst_sz);
1251f714a188SAmr Mokhtar 
1252f714a188SAmr Mokhtar 	if (deq < burst_sz) {
1253f714a188SAmr Mokhtar 		printf(
1254f714a188SAmr Mokhtar 			"After receiving the interrupt all operations should be dequeued. Expected: %u, got: %u\n",
1255f714a188SAmr Mokhtar 			burst_sz, deq);
1256f714a188SAmr Mokhtar 		rte_atomic16_set(&tp->processing_status, TEST_FAILED);
1257f714a188SAmr Mokhtar 		return;
1258f714a188SAmr Mokhtar 	}
1259f714a188SAmr Mokhtar 
12600b98d574SKamil Chalupnik 	if (rte_atomic16_read(&tp->nb_dequeued) + deq < num_ops) {
1261f714a188SAmr Mokhtar 		rte_atomic16_add(&tp->nb_dequeued, deq);
1262f714a188SAmr Mokhtar 		return;
1263f714a188SAmr Mokhtar 	}
1264f714a188SAmr Mokhtar 
1265f714a188SAmr Mokhtar 	total_time = rte_rdtsc_precise() - tp->start_time;
1266f714a188SAmr Mokhtar 
1267f714a188SAmr Mokhtar 	rte_bbdev_info_get(dev_id, &info);
1268f714a188SAmr Mokhtar 
1269f714a188SAmr Mokhtar 	ret = TEST_SUCCESS;
12700b98d574SKamil Chalupnik 
12710b98d574SKamil Chalupnik 	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) {
12720b98d574SKamil Chalupnik 		struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op;
1273*b2e2aec3SKamil Chalupnik 		ret = validate_dec_op(tp->dec_ops, num_ops, ref_op,
12740b98d574SKamil Chalupnik 				tp->op_params->vector_mask);
1275*b2e2aec3SKamil Chalupnik 		/* get the max of iter_count for all dequeued ops */
1276*b2e2aec3SKamil Chalupnik 		for (i = 0; i < num_ops; ++i)
1277*b2e2aec3SKamil Chalupnik 			tp->iter_count = RTE_MAX(
1278*b2e2aec3SKamil Chalupnik 					tp->dec_ops[i]->turbo_dec.iter_count,
1279*b2e2aec3SKamil Chalupnik 					tp->iter_count);
1280*b2e2aec3SKamil Chalupnik 		rte_bbdev_dec_op_free_bulk(tp->dec_ops, deq);
12810b98d574SKamil Chalupnik 	} else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC) {
12820b98d574SKamil Chalupnik 		struct rte_bbdev_enc_op *ref_op = tp->op_params->ref_enc_op;
1283*b2e2aec3SKamil Chalupnik 		ret = validate_enc_op(tp->enc_ops, num_ops, ref_op);
1284*b2e2aec3SKamil Chalupnik 		rte_bbdev_enc_op_free_bulk(tp->enc_ops, deq);
12850b98d574SKamil Chalupnik 	}
1286f714a188SAmr Mokhtar 
1287f714a188SAmr Mokhtar 	if (ret) {
1288f714a188SAmr Mokhtar 		printf("Buffers validation failed\n");
1289f714a188SAmr Mokhtar 		rte_atomic16_set(&tp->processing_status, TEST_FAILED);
1290f714a188SAmr Mokhtar 	}
1291f714a188SAmr Mokhtar 
1292f714a188SAmr Mokhtar 	switch (test_vector.op_type) {
1293f714a188SAmr Mokhtar 	case RTE_BBDEV_OP_TURBO_DEC:
12940b98d574SKamil Chalupnik 		tb_len_bits = calc_dec_TB_size(tp->op_params->ref_dec_op);
1295f714a188SAmr Mokhtar 		break;
1296f714a188SAmr Mokhtar 	case RTE_BBDEV_OP_TURBO_ENC:
12970b98d574SKamil Chalupnik 		tb_len_bits = calc_enc_TB_size(tp->op_params->ref_enc_op);
1298f714a188SAmr Mokhtar 		break;
1299f714a188SAmr Mokhtar 	case RTE_BBDEV_OP_NONE:
13000b98d574SKamil Chalupnik 		tb_len_bits = 0.0;
1301f714a188SAmr Mokhtar 		break;
1302f714a188SAmr Mokhtar 	default:
1303f714a188SAmr Mokhtar 		printf("Unknown op type: %d\n", test_vector.op_type);
1304f714a188SAmr Mokhtar 		rte_atomic16_set(&tp->processing_status, TEST_FAILED);
1305f714a188SAmr Mokhtar 		return;
1306f714a188SAmr Mokhtar 	}
1307f714a188SAmr Mokhtar 
1308*b2e2aec3SKamil Chalupnik 	tp->ops_per_sec += ((double)num_ops) /
1309f714a188SAmr Mokhtar 			((double)total_time / (double)rte_get_tsc_hz());
1310*b2e2aec3SKamil Chalupnik 	tp->mbps += (((double)(num_ops * tb_len_bits)) / 1000000.0) /
1311f714a188SAmr Mokhtar 			((double)total_time / (double)rte_get_tsc_hz());
1312f714a188SAmr Mokhtar 
1313f714a188SAmr Mokhtar 	rte_atomic16_add(&tp->nb_dequeued, deq);
1314f714a188SAmr Mokhtar }
1315f714a188SAmr Mokhtar 
1316f714a188SAmr Mokhtar static int
1317f714a188SAmr Mokhtar throughput_intr_lcore_dec(void *arg)
1318f714a188SAmr Mokhtar {
1319f714a188SAmr Mokhtar 	struct thread_params *tp = arg;
1320f714a188SAmr Mokhtar 	unsigned int enqueued;
1321f714a188SAmr Mokhtar 	const uint16_t queue_id = tp->queue_id;
1322f714a188SAmr Mokhtar 	const uint16_t burst_sz = tp->op_params->burst_sz;
1323f714a188SAmr Mokhtar 	const uint16_t num_to_process = tp->op_params->num_to_process;
13240b98d574SKamil Chalupnik 	struct rte_bbdev_dec_op *ops[num_to_process];
1325f714a188SAmr Mokhtar 	struct test_buffers *bufs = NULL;
1326f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
1327*b2e2aec3SKamil Chalupnik 	int ret, i, j;
1328*b2e2aec3SKamil Chalupnik 	uint16_t num_to_enq, enq;
1329f714a188SAmr Mokhtar 
1330f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
1331f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
1332f714a188SAmr Mokhtar 
1333f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id),
1334f714a188SAmr Mokhtar 			"Failed to enable interrupts for dev: %u, queue_id: %u",
1335f714a188SAmr Mokhtar 			tp->dev_id, queue_id);
1336f714a188SAmr Mokhtar 
1337f714a188SAmr Mokhtar 	rte_bbdev_info_get(tp->dev_id, &info);
13380b98d574SKamil Chalupnik 
13390b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim),
13400b98d574SKamil Chalupnik 			"NUM_OPS cannot exceed %u for this device",
13410b98d574SKamil Chalupnik 			info.drv.queue_size_lim);
13420b98d574SKamil Chalupnik 
1343f714a188SAmr Mokhtar 	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
1344f714a188SAmr Mokhtar 
1345f714a188SAmr Mokhtar 	rte_atomic16_clear(&tp->processing_status);
1346f714a188SAmr Mokhtar 	rte_atomic16_clear(&tp->nb_dequeued);
1347f714a188SAmr Mokhtar 
1348f714a188SAmr Mokhtar 	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
1349f714a188SAmr Mokhtar 		rte_pause();
1350f714a188SAmr Mokhtar 
13510b98d574SKamil Chalupnik 	ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops,
13520b98d574SKamil Chalupnik 				num_to_process);
13530b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
13540b98d574SKamil Chalupnik 			num_to_process);
13550b98d574SKamil Chalupnik 	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
13560b98d574SKamil Chalupnik 		copy_reference_dec_op(ops, num_to_process, 0, bufs->inputs,
13570b98d574SKamil Chalupnik 				bufs->hard_outputs, bufs->soft_outputs,
13580b98d574SKamil Chalupnik 				tp->op_params->ref_dec_op);
13590b98d574SKamil Chalupnik 
1360*b2e2aec3SKamil Chalupnik 	/* Set counter to validate the ordering */
1361*b2e2aec3SKamil Chalupnik 	for (j = 0; j < num_to_process; ++j)
1362*b2e2aec3SKamil Chalupnik 		ops[j]->opaque_data = (void *)(uintptr_t)j;
1363*b2e2aec3SKamil Chalupnik 
1364*b2e2aec3SKamil Chalupnik 	for (j = 0; j < TEST_REPETITIONS; ++j) {
1365*b2e2aec3SKamil Chalupnik 		for (i = 0; i < num_to_process; ++i)
1366*b2e2aec3SKamil Chalupnik 			rte_pktmbuf_reset(ops[i]->turbo_dec.hard_output.data);
1367*b2e2aec3SKamil Chalupnik 
1368f714a188SAmr Mokhtar 		tp->start_time = rte_rdtsc_precise();
1369f714a188SAmr Mokhtar 		for (enqueued = 0; enqueued < num_to_process;) {
13700b98d574SKamil Chalupnik 			num_to_enq = burst_sz;
1371f714a188SAmr Mokhtar 
1372f714a188SAmr Mokhtar 			if (unlikely(num_to_process - enqueued < num_to_enq))
1373f714a188SAmr Mokhtar 				num_to_enq = num_to_process - enqueued;
1374f714a188SAmr Mokhtar 
1375*b2e2aec3SKamil Chalupnik 			enq = 0;
1376*b2e2aec3SKamil Chalupnik 			do {
1377*b2e2aec3SKamil Chalupnik 				enq += rte_bbdev_enqueue_dec_ops(tp->dev_id,
1378*b2e2aec3SKamil Chalupnik 					queue_id, &ops[enqueued],
1379*b2e2aec3SKamil Chalupnik 					num_to_enq);
1380*b2e2aec3SKamil Chalupnik 			} while (unlikely(num_to_enq != enq));
1381*b2e2aec3SKamil Chalupnik 			enqueued += enq;
1382*b2e2aec3SKamil Chalupnik 
1383*b2e2aec3SKamil Chalupnik 			/* Write to thread burst_sz current number of enqueued
1384*b2e2aec3SKamil Chalupnik 			 * descriptors. It ensures that proper number of
1385*b2e2aec3SKamil Chalupnik 			 * descriptors will be dequeued in callback
1386*b2e2aec3SKamil Chalupnik 			 * function - needed for last batch in case where
1387*b2e2aec3SKamil Chalupnik 			 * the number of operations is not a multiple of
1388*b2e2aec3SKamil Chalupnik 			 * burst size.
1389*b2e2aec3SKamil Chalupnik 			 */
1390*b2e2aec3SKamil Chalupnik 			rte_atomic16_set(&tp->burst_sz, num_to_enq);
1391*b2e2aec3SKamil Chalupnik 
1392*b2e2aec3SKamil Chalupnik 			/* Wait until processing of previous batch is
1393*b2e2aec3SKamil Chalupnik 			 * completed.
1394*b2e2aec3SKamil Chalupnik 			 */
1395*b2e2aec3SKamil Chalupnik 			while (rte_atomic16_read(&tp->nb_dequeued) !=
1396*b2e2aec3SKamil Chalupnik 					(int16_t) enqueued)
1397*b2e2aec3SKamil Chalupnik 				rte_pause();
1398*b2e2aec3SKamil Chalupnik 		}
1399*b2e2aec3SKamil Chalupnik 		if (j != TEST_REPETITIONS - 1)
1400*b2e2aec3SKamil Chalupnik 			rte_atomic16_clear(&tp->nb_dequeued);
1401f714a188SAmr Mokhtar 	}
1402f714a188SAmr Mokhtar 
1403f714a188SAmr Mokhtar 	return TEST_SUCCESS;
1404f714a188SAmr Mokhtar }
1405f714a188SAmr Mokhtar 
1406f714a188SAmr Mokhtar static int
1407f714a188SAmr Mokhtar throughput_intr_lcore_enc(void *arg)
1408f714a188SAmr Mokhtar {
1409f714a188SAmr Mokhtar 	struct thread_params *tp = arg;
1410f714a188SAmr Mokhtar 	unsigned int enqueued;
1411f714a188SAmr Mokhtar 	const uint16_t queue_id = tp->queue_id;
1412f714a188SAmr Mokhtar 	const uint16_t burst_sz = tp->op_params->burst_sz;
1413f714a188SAmr Mokhtar 	const uint16_t num_to_process = tp->op_params->num_to_process;
14140b98d574SKamil Chalupnik 	struct rte_bbdev_enc_op *ops[num_to_process];
1415f714a188SAmr Mokhtar 	struct test_buffers *bufs = NULL;
1416f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
1417*b2e2aec3SKamil Chalupnik 	int ret, i, j;
1418*b2e2aec3SKamil Chalupnik 	uint16_t num_to_enq, enq;
1419f714a188SAmr Mokhtar 
1420f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
1421f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
1422f714a188SAmr Mokhtar 
1423f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id),
1424f714a188SAmr Mokhtar 			"Failed to enable interrupts for dev: %u, queue_id: %u",
1425f714a188SAmr Mokhtar 			tp->dev_id, queue_id);
1426f714a188SAmr Mokhtar 
1427f714a188SAmr Mokhtar 	rte_bbdev_info_get(tp->dev_id, &info);
14280b98d574SKamil Chalupnik 
14290b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim),
14300b98d574SKamil Chalupnik 			"NUM_OPS cannot exceed %u for this device",
14310b98d574SKamil Chalupnik 			info.drv.queue_size_lim);
14320b98d574SKamil Chalupnik 
1433f714a188SAmr Mokhtar 	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
1434f714a188SAmr Mokhtar 
1435f714a188SAmr Mokhtar 	rte_atomic16_clear(&tp->processing_status);
1436f714a188SAmr Mokhtar 	rte_atomic16_clear(&tp->nb_dequeued);
1437f714a188SAmr Mokhtar 
1438f714a188SAmr Mokhtar 	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
1439f714a188SAmr Mokhtar 		rte_pause();
1440f714a188SAmr Mokhtar 
14410b98d574SKamil Chalupnik 	ret = rte_bbdev_enc_op_alloc_bulk(tp->op_params->mp, ops,
14420b98d574SKamil Chalupnik 			num_to_process);
14430b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
14440b98d574SKamil Chalupnik 			num_to_process);
14450b98d574SKamil Chalupnik 	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
14460b98d574SKamil Chalupnik 		copy_reference_enc_op(ops, num_to_process, 0, bufs->inputs,
14470b98d574SKamil Chalupnik 				bufs->hard_outputs, tp->op_params->ref_enc_op);
14480b98d574SKamil Chalupnik 
1449*b2e2aec3SKamil Chalupnik 	/* Set counter to validate the ordering */
1450*b2e2aec3SKamil Chalupnik 	for (j = 0; j < num_to_process; ++j)
1451*b2e2aec3SKamil Chalupnik 		ops[j]->opaque_data = (void *)(uintptr_t)j;
1452*b2e2aec3SKamil Chalupnik 
1453*b2e2aec3SKamil Chalupnik 	for (j = 0; j < TEST_REPETITIONS; ++j) {
1454*b2e2aec3SKamil Chalupnik 		for (i = 0; i < num_to_process; ++i)
1455*b2e2aec3SKamil Chalupnik 			rte_pktmbuf_reset(ops[i]->turbo_enc.output.data);
1456*b2e2aec3SKamil Chalupnik 
1457f714a188SAmr Mokhtar 		tp->start_time = rte_rdtsc_precise();
1458f714a188SAmr Mokhtar 		for (enqueued = 0; enqueued < num_to_process;) {
14590b98d574SKamil Chalupnik 			num_to_enq = burst_sz;
1460f714a188SAmr Mokhtar 
1461f714a188SAmr Mokhtar 			if (unlikely(num_to_process - enqueued < num_to_enq))
1462f714a188SAmr Mokhtar 				num_to_enq = num_to_process - enqueued;
1463f714a188SAmr Mokhtar 
1464*b2e2aec3SKamil Chalupnik 			enq = 0;
1465*b2e2aec3SKamil Chalupnik 			do {
1466*b2e2aec3SKamil Chalupnik 				enq += rte_bbdev_enqueue_enc_ops(tp->dev_id,
1467*b2e2aec3SKamil Chalupnik 						queue_id, &ops[enqueued],
1468*b2e2aec3SKamil Chalupnik 						num_to_enq);
1469*b2e2aec3SKamil Chalupnik 			} while (unlikely(enq != num_to_enq));
1470*b2e2aec3SKamil Chalupnik 			enqueued += enq;
1471*b2e2aec3SKamil Chalupnik 
1472*b2e2aec3SKamil Chalupnik 			/* Write to thread burst_sz current number of enqueued
1473*b2e2aec3SKamil Chalupnik 			 * descriptors. It ensures that proper number of
1474*b2e2aec3SKamil Chalupnik 			 * descriptors will be dequeued in callback
1475*b2e2aec3SKamil Chalupnik 			 * function - needed for last batch in case where
1476*b2e2aec3SKamil Chalupnik 			 * the number of operations is not a multiple of
1477*b2e2aec3SKamil Chalupnik 			 * burst size.
1478*b2e2aec3SKamil Chalupnik 			 */
1479*b2e2aec3SKamil Chalupnik 			rte_atomic16_set(&tp->burst_sz, num_to_enq);
1480*b2e2aec3SKamil Chalupnik 
1481*b2e2aec3SKamil Chalupnik 			/* Wait until processing of previous batch is
1482*b2e2aec3SKamil Chalupnik 			 * completed.
1483*b2e2aec3SKamil Chalupnik 			 */
1484*b2e2aec3SKamil Chalupnik 			while (rte_atomic16_read(&tp->nb_dequeued) !=
1485*b2e2aec3SKamil Chalupnik 					(int16_t) enqueued)
1486*b2e2aec3SKamil Chalupnik 				rte_pause();
1487*b2e2aec3SKamil Chalupnik 		}
1488*b2e2aec3SKamil Chalupnik 		if (j != TEST_REPETITIONS - 1)
1489*b2e2aec3SKamil Chalupnik 			rte_atomic16_clear(&tp->nb_dequeued);
1490f714a188SAmr Mokhtar 	}
1491f714a188SAmr Mokhtar 
1492f714a188SAmr Mokhtar 	return TEST_SUCCESS;
1493f714a188SAmr Mokhtar }
1494f714a188SAmr Mokhtar 
1495f714a188SAmr Mokhtar static int
1496f714a188SAmr Mokhtar throughput_pmd_lcore_dec(void *arg)
1497f714a188SAmr Mokhtar {
1498f714a188SAmr Mokhtar 	struct thread_params *tp = arg;
14990b98d574SKamil Chalupnik 	uint16_t enq, deq;
15000b98d574SKamil Chalupnik 	uint64_t total_time = 0, start_time;
1501f714a188SAmr Mokhtar 	const uint16_t queue_id = tp->queue_id;
1502f714a188SAmr Mokhtar 	const uint16_t burst_sz = tp->op_params->burst_sz;
15030b98d574SKamil Chalupnik 	const uint16_t num_ops = tp->op_params->num_to_process;
15040b98d574SKamil Chalupnik 	struct rte_bbdev_dec_op *ops_enq[num_ops];
15050b98d574SKamil Chalupnik 	struct rte_bbdev_dec_op *ops_deq[num_ops];
1506f714a188SAmr Mokhtar 	struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op;
1507f714a188SAmr Mokhtar 	struct test_buffers *bufs = NULL;
15080b98d574SKamil Chalupnik 	int i, j, ret;
1509f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
15100b98d574SKamil Chalupnik 	uint16_t num_to_enq;
1511f714a188SAmr Mokhtar 
1512f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
1513f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
1514f714a188SAmr Mokhtar 
1515f714a188SAmr Mokhtar 	rte_bbdev_info_get(tp->dev_id, &info);
15160b98d574SKamil Chalupnik 
15170b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim),
15180b98d574SKamil Chalupnik 			"NUM_OPS cannot exceed %u for this device",
15190b98d574SKamil Chalupnik 			info.drv.queue_size_lim);
15200b98d574SKamil Chalupnik 
1521f714a188SAmr Mokhtar 	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
1522f714a188SAmr Mokhtar 
1523f714a188SAmr Mokhtar 	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
1524f714a188SAmr Mokhtar 		rte_pause();
1525f714a188SAmr Mokhtar 
15260b98d574SKamil Chalupnik 	ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops);
15270b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops);
1528f714a188SAmr Mokhtar 
1529f714a188SAmr Mokhtar 	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
15300b98d574SKamil Chalupnik 		copy_reference_dec_op(ops_enq, num_ops, 0, bufs->inputs,
15310b98d574SKamil Chalupnik 				bufs->hard_outputs, bufs->soft_outputs, ref_op);
1532f714a188SAmr Mokhtar 
15330b98d574SKamil Chalupnik 	/* Set counter to validate the ordering */
15340b98d574SKamil Chalupnik 	for (j = 0; j < num_ops; ++j)
15350b98d574SKamil Chalupnik 		ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
15360b98d574SKamil Chalupnik 
15370b98d574SKamil Chalupnik 	for (i = 0; i < TEST_REPETITIONS; ++i) {
15380b98d574SKamil Chalupnik 
15399585f8b1SKamil Chalupnik 		for (j = 0; j < num_ops; ++j)
15409585f8b1SKamil Chalupnik 			mbuf_reset(ops_enq[j]->turbo_dec.hard_output.data);
15410b98d574SKamil Chalupnik 
15420b98d574SKamil Chalupnik 		start_time = rte_rdtsc_precise();
15430b98d574SKamil Chalupnik 
15440b98d574SKamil Chalupnik 		for (enq = 0, deq = 0; enq < num_ops;) {
15450b98d574SKamil Chalupnik 			num_to_enq = burst_sz;
15460b98d574SKamil Chalupnik 
15470b98d574SKamil Chalupnik 			if (unlikely(num_ops - enq < num_to_enq))
15480b98d574SKamil Chalupnik 				num_to_enq = num_ops - enq;
15490b98d574SKamil Chalupnik 
15500b98d574SKamil Chalupnik 			enq += rte_bbdev_enqueue_dec_ops(tp->dev_id,
15510b98d574SKamil Chalupnik 					queue_id, &ops_enq[enq], num_to_enq);
15520b98d574SKamil Chalupnik 
15530b98d574SKamil Chalupnik 			deq += rte_bbdev_dequeue_dec_ops(tp->dev_id,
15540b98d574SKamil Chalupnik 					queue_id, &ops_deq[deq], enq - deq);
1555f714a188SAmr Mokhtar 		}
1556f714a188SAmr Mokhtar 
15570b98d574SKamil Chalupnik 		/* dequeue the remaining */
15580b98d574SKamil Chalupnik 		while (deq < enq) {
15590b98d574SKamil Chalupnik 			deq += rte_bbdev_dequeue_dec_ops(tp->dev_id,
15600b98d574SKamil Chalupnik 					queue_id, &ops_deq[deq], enq - deq);
15610b98d574SKamil Chalupnik 		}
1562f714a188SAmr Mokhtar 
15630b98d574SKamil Chalupnik 		total_time += rte_rdtsc_precise() - start_time;
15640b98d574SKamil Chalupnik 	}
15650b98d574SKamil Chalupnik 
15660b98d574SKamil Chalupnik 	tp->iter_count = 0;
15670b98d574SKamil Chalupnik 	/* get the max of iter_count for all dequeued ops */
15680b98d574SKamil Chalupnik 	for (i = 0; i < num_ops; ++i) {
15690b98d574SKamil Chalupnik 		tp->iter_count = RTE_MAX(ops_enq[i]->turbo_dec.iter_count,
15700b98d574SKamil Chalupnik 				tp->iter_count);
15710b98d574SKamil Chalupnik 	}
1572f714a188SAmr Mokhtar 
1573f714a188SAmr Mokhtar 	if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
15740b98d574SKamil Chalupnik 		ret = validate_dec_op(ops_deq, num_ops, ref_op,
15750b98d574SKamil Chalupnik 				tp->op_params->vector_mask);
15760b98d574SKamil Chalupnik 		TEST_ASSERT_SUCCESS(ret, "Validation failed!");
1577f714a188SAmr Mokhtar 	}
1578f714a188SAmr Mokhtar 
15790b98d574SKamil Chalupnik 	rte_bbdev_dec_op_free_bulk(ops_enq, num_ops);
15800b98d574SKamil Chalupnik 
15810b98d574SKamil Chalupnik 	double tb_len_bits = calc_dec_TB_size(ref_op);
15820b98d574SKamil Chalupnik 
15830b98d574SKamil Chalupnik 	tp->ops_per_sec = ((double)num_ops * TEST_REPETITIONS) /
1584f714a188SAmr Mokhtar 			((double)total_time / (double)rte_get_tsc_hz());
15850b98d574SKamil Chalupnik 	tp->mbps = (((double)(num_ops * TEST_REPETITIONS * tb_len_bits)) /
15860b98d574SKamil Chalupnik 			1000000.0) / ((double)total_time /
15870b98d574SKamil Chalupnik 			(double)rte_get_tsc_hz());
1588f714a188SAmr Mokhtar 
1589f714a188SAmr Mokhtar 	return TEST_SUCCESS;
1590f714a188SAmr Mokhtar }
1591f714a188SAmr Mokhtar 
1592f714a188SAmr Mokhtar static int
1593f714a188SAmr Mokhtar throughput_pmd_lcore_enc(void *arg)
1594f714a188SAmr Mokhtar {
1595f714a188SAmr Mokhtar 	struct thread_params *tp = arg;
15960b98d574SKamil Chalupnik 	uint16_t enq, deq;
15970b98d574SKamil Chalupnik 	uint64_t total_time = 0, start_time;
1598f714a188SAmr Mokhtar 	const uint16_t queue_id = tp->queue_id;
1599f714a188SAmr Mokhtar 	const uint16_t burst_sz = tp->op_params->burst_sz;
16000b98d574SKamil Chalupnik 	const uint16_t num_ops = tp->op_params->num_to_process;
16010b98d574SKamil Chalupnik 	struct rte_bbdev_enc_op *ops_enq[num_ops];
16020b98d574SKamil Chalupnik 	struct rte_bbdev_enc_op *ops_deq[num_ops];
1603f714a188SAmr Mokhtar 	struct rte_bbdev_enc_op *ref_op = tp->op_params->ref_enc_op;
1604f714a188SAmr Mokhtar 	struct test_buffers *bufs = NULL;
16050b98d574SKamil Chalupnik 	int i, j, ret;
1606f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
16070b98d574SKamil Chalupnik 	uint16_t num_to_enq;
1608f714a188SAmr Mokhtar 
1609f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
1610f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
1611f714a188SAmr Mokhtar 
1612f714a188SAmr Mokhtar 	rte_bbdev_info_get(tp->dev_id, &info);
16130b98d574SKamil Chalupnik 
16140b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim),
16150b98d574SKamil Chalupnik 			"NUM_OPS cannot exceed %u for this device",
16160b98d574SKamil Chalupnik 			info.drv.queue_size_lim);
16170b98d574SKamil Chalupnik 
1618f714a188SAmr Mokhtar 	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
1619f714a188SAmr Mokhtar 
1620f714a188SAmr Mokhtar 	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
1621f714a188SAmr Mokhtar 		rte_pause();
1622f714a188SAmr Mokhtar 
16230b98d574SKamil Chalupnik 	ret = rte_bbdev_enc_op_alloc_bulk(tp->op_params->mp, ops_enq,
16240b98d574SKamil Chalupnik 			num_ops);
16250b98d574SKamil Chalupnik 	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
16260b98d574SKamil Chalupnik 			num_ops);
16270b98d574SKamil Chalupnik 	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
16280b98d574SKamil Chalupnik 		copy_reference_enc_op(ops_enq, num_ops, 0, bufs->inputs,
16290b98d574SKamil Chalupnik 				bufs->hard_outputs, ref_op);
1630f714a188SAmr Mokhtar 
16310b98d574SKamil Chalupnik 	/* Set counter to validate the ordering */
16320b98d574SKamil Chalupnik 	for (j = 0; j < num_ops; ++j)
16330b98d574SKamil Chalupnik 		ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
1634f714a188SAmr Mokhtar 
16350b98d574SKamil Chalupnik 	for (i = 0; i < TEST_REPETITIONS; ++i) {
1636f714a188SAmr Mokhtar 
1637f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
16380b98d574SKamil Chalupnik 			for (j = 0; j < num_ops; ++j)
16399585f8b1SKamil Chalupnik 				mbuf_reset(ops_enq[j]->turbo_enc.output.data);
1640f714a188SAmr Mokhtar 
16410b98d574SKamil Chalupnik 		start_time = rte_rdtsc_precise();
16420b98d574SKamil Chalupnik 
16430b98d574SKamil Chalupnik 		for (enq = 0, deq = 0; enq < num_ops;) {
16440b98d574SKamil Chalupnik 			num_to_enq = burst_sz;
16450b98d574SKamil Chalupnik 
16460b98d574SKamil Chalupnik 			if (unlikely(num_ops - enq < num_to_enq))
16470b98d574SKamil Chalupnik 				num_to_enq = num_ops - enq;
16480b98d574SKamil Chalupnik 
16490b98d574SKamil Chalupnik 			enq += rte_bbdev_enqueue_enc_ops(tp->dev_id,
16500b98d574SKamil Chalupnik 					queue_id, &ops_enq[enq], num_to_enq);
16510b98d574SKamil Chalupnik 
16520b98d574SKamil Chalupnik 			deq += rte_bbdev_dequeue_enc_ops(tp->dev_id,
16530b98d574SKamil Chalupnik 					queue_id, &ops_deq[deq], enq - deq);
1654f714a188SAmr Mokhtar 		}
16550b98d574SKamil Chalupnik 
16560b98d574SKamil Chalupnik 		/* dequeue the remaining */
16570b98d574SKamil Chalupnik 		while (deq < enq) {
16580b98d574SKamil Chalupnik 			deq += rte_bbdev_dequeue_enc_ops(tp->dev_id,
16590b98d574SKamil Chalupnik 					queue_id, &ops_deq[deq], enq - deq);
1660f714a188SAmr Mokhtar 		}
1661f714a188SAmr Mokhtar 
16620b98d574SKamil Chalupnik 		total_time += rte_rdtsc_precise() - start_time;
16630b98d574SKamil Chalupnik 	}
1664f714a188SAmr Mokhtar 
1665f714a188SAmr Mokhtar 	if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
16660b98d574SKamil Chalupnik 		ret = validate_enc_op(ops_deq, num_ops, ref_op);
16670b98d574SKamil Chalupnik 		TEST_ASSERT_SUCCESS(ret, "Validation failed!");
1668f714a188SAmr Mokhtar 	}
1669f714a188SAmr Mokhtar 
16700b98d574SKamil Chalupnik 	double tb_len_bits = calc_enc_TB_size(ref_op);
1671f714a188SAmr Mokhtar 
16720b98d574SKamil Chalupnik 	tp->ops_per_sec = ((double)num_ops * TEST_REPETITIONS) /
1673f714a188SAmr Mokhtar 			((double)total_time / (double)rte_get_tsc_hz());
16740b98d574SKamil Chalupnik 	tp->mbps = (((double)(num_ops * TEST_REPETITIONS * tb_len_bits))
16750b98d574SKamil Chalupnik 			/ 1000000.0) / ((double)total_time /
16760b98d574SKamil Chalupnik 			(double)rte_get_tsc_hz());
1677f714a188SAmr Mokhtar 
1678f714a188SAmr Mokhtar 	return TEST_SUCCESS;
1679f714a188SAmr Mokhtar }
16800b98d574SKamil Chalupnik 
1681f714a188SAmr Mokhtar static void
16820b98d574SKamil Chalupnik print_enc_throughput(struct thread_params *t_params, unsigned int used_cores)
1683f714a188SAmr Mokhtar {
1684*b2e2aec3SKamil Chalupnik 	unsigned int iter = 0;
1685f714a188SAmr Mokhtar 	double total_mops = 0, total_mbps = 0;
1686f714a188SAmr Mokhtar 
1687*b2e2aec3SKamil Chalupnik 	for (iter = 0; iter < used_cores; iter++) {
16880b98d574SKamil Chalupnik 		printf(
16890b98d574SKamil Chalupnik 			"Throughput for core (%u): %.8lg Ops/s, %.8lg Mbps\n",
1690*b2e2aec3SKamil Chalupnik 			t_params[iter].lcore_id, t_params[iter].ops_per_sec,
1691*b2e2aec3SKamil Chalupnik 			t_params[iter].mbps);
1692*b2e2aec3SKamil Chalupnik 		total_mops += t_params[iter].ops_per_sec;
1693*b2e2aec3SKamil Chalupnik 		total_mbps += t_params[iter].mbps;
1694f714a188SAmr Mokhtar 	}
1695f714a188SAmr Mokhtar 	printf(
16969fa6ebdeSKamil Chalupnik 		"\nTotal throughput for %u cores: %.8lg MOPS, %.8lg Mbps\n",
1697f714a188SAmr Mokhtar 		used_cores, total_mops, total_mbps);
1698f714a188SAmr Mokhtar }
1699f714a188SAmr Mokhtar 
17000b98d574SKamil Chalupnik static void
17010b98d574SKamil Chalupnik print_dec_throughput(struct thread_params *t_params, unsigned int used_cores)
17020b98d574SKamil Chalupnik {
1703*b2e2aec3SKamil Chalupnik 	unsigned int iter = 0;
17040b98d574SKamil Chalupnik 	double total_mops = 0, total_mbps = 0;
17050b98d574SKamil Chalupnik 	uint8_t iter_count = 0;
17060b98d574SKamil Chalupnik 
1707*b2e2aec3SKamil Chalupnik 	for (iter = 0; iter < used_cores; iter++) {
17080b98d574SKamil Chalupnik 		printf(
17090b98d574SKamil Chalupnik 			"Throughput for core (%u): %.8lg Ops/s, %.8lg Mbps @ max %u iterations\n",
1710*b2e2aec3SKamil Chalupnik 			t_params[iter].lcore_id, t_params[iter].ops_per_sec,
1711*b2e2aec3SKamil Chalupnik 			t_params[iter].mbps, t_params[iter].iter_count);
1712*b2e2aec3SKamil Chalupnik 		total_mops += t_params[iter].ops_per_sec;
1713*b2e2aec3SKamil Chalupnik 		total_mbps += t_params[iter].mbps;
1714*b2e2aec3SKamil Chalupnik 		iter_count = RTE_MAX(iter_count, t_params[iter].iter_count);
17150b98d574SKamil Chalupnik 	}
17160b98d574SKamil Chalupnik 	printf(
17170b98d574SKamil Chalupnik 		"\nTotal throughput for %u cores: %.8lg MOPS, %.8lg Mbps @ max %u iterations\n",
17180b98d574SKamil Chalupnik 		used_cores, total_mops, total_mbps, iter_count);
17190b98d574SKamil Chalupnik }
17200b98d574SKamil Chalupnik 
1721f714a188SAmr Mokhtar /*
1722f714a188SAmr Mokhtar  * Test function that determines how long an enqueue + dequeue of a burst
1723f714a188SAmr Mokhtar  * takes on available lcores.
1724f714a188SAmr Mokhtar  */
1725f714a188SAmr Mokhtar static int
1726f714a188SAmr Mokhtar throughput_test(struct active_device *ad,
1727f714a188SAmr Mokhtar 		struct test_op_params *op_params)
1728f714a188SAmr Mokhtar {
1729f714a188SAmr Mokhtar 	int ret;
1730f714a188SAmr Mokhtar 	unsigned int lcore_id, used_cores = 0;
1731*b2e2aec3SKamil Chalupnik 	struct thread_params *t_params, *tp;
1732f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
1733f714a188SAmr Mokhtar 	lcore_function_t *throughput_function;
1734f714a188SAmr Mokhtar 	uint16_t num_lcores;
1735f714a188SAmr Mokhtar 	const char *op_type_str;
1736f714a188SAmr Mokhtar 
1737f714a188SAmr Mokhtar 	rte_bbdev_info_get(ad->dev_id, &info);
1738f714a188SAmr Mokhtar 
1739f714a188SAmr Mokhtar 	op_type_str = rte_bbdev_op_type_str(test_vector.op_type);
1740f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u",
1741f714a188SAmr Mokhtar 			test_vector.op_type);
1742f714a188SAmr Mokhtar 
1743f714a188SAmr Mokhtar 	printf(
1744f714a188SAmr Mokhtar 		"Throughput test: dev: %s, nb_queues: %u, burst size: %u, num ops: %u, num_lcores: %u, op type: %s, int mode: %s, GHz: %lg\n",
1745f714a188SAmr Mokhtar 			info.dev_name, ad->nb_queues, op_params->burst_sz,
1746f714a188SAmr Mokhtar 			op_params->num_to_process, op_params->num_lcores,
1747f714a188SAmr Mokhtar 			op_type_str,
1748f714a188SAmr Mokhtar 			intr_enabled ? "Interrupt mode" : "PMD mode",
1749f714a188SAmr Mokhtar 			(double)rte_get_tsc_hz() / 1000000000.0);
1750f714a188SAmr Mokhtar 
1751f714a188SAmr Mokhtar 	/* Set number of lcores */
1752f714a188SAmr Mokhtar 	num_lcores = (ad->nb_queues < (op_params->num_lcores))
1753f714a188SAmr Mokhtar 			? ad->nb_queues
1754f714a188SAmr Mokhtar 			: op_params->num_lcores;
1755f714a188SAmr Mokhtar 
1756*b2e2aec3SKamil Chalupnik 	/* Allocate memory for thread parameters structure */
1757*b2e2aec3SKamil Chalupnik 	t_params = rte_zmalloc(NULL, num_lcores * sizeof(struct thread_params),
1758*b2e2aec3SKamil Chalupnik 			RTE_CACHE_LINE_SIZE);
1759*b2e2aec3SKamil Chalupnik 	TEST_ASSERT_NOT_NULL(t_params, "Failed to alloc %zuB for t_params",
1760*b2e2aec3SKamil Chalupnik 			RTE_ALIGN(sizeof(struct thread_params) * num_lcores,
1761*b2e2aec3SKamil Chalupnik 				RTE_CACHE_LINE_SIZE));
1762*b2e2aec3SKamil Chalupnik 
1763f714a188SAmr Mokhtar 	if (intr_enabled) {
1764f714a188SAmr Mokhtar 		if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
1765f714a188SAmr Mokhtar 			throughput_function = throughput_intr_lcore_dec;
1766f714a188SAmr Mokhtar 		else
1767f714a188SAmr Mokhtar 			throughput_function = throughput_intr_lcore_enc;
1768f714a188SAmr Mokhtar 
1769f714a188SAmr Mokhtar 		/* Dequeue interrupt callback registration */
1770d3345d40SAmr Mokhtar 		ret = rte_bbdev_callback_register(ad->dev_id,
1771d3345d40SAmr Mokhtar 				RTE_BBDEV_EVENT_DEQUEUE, dequeue_event_callback,
1772*b2e2aec3SKamil Chalupnik 				t_params);
1773*b2e2aec3SKamil Chalupnik 		if (ret < 0) {
1774*b2e2aec3SKamil Chalupnik 			rte_free(t_params);
1775d3345d40SAmr Mokhtar 			return ret;
1776*b2e2aec3SKamil Chalupnik 		}
1777f714a188SAmr Mokhtar 	} else {
1778f714a188SAmr Mokhtar 		if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
1779f714a188SAmr Mokhtar 			throughput_function = throughput_pmd_lcore_dec;
1780f714a188SAmr Mokhtar 		else
1781f714a188SAmr Mokhtar 			throughput_function = throughput_pmd_lcore_enc;
1782f714a188SAmr Mokhtar 	}
1783f714a188SAmr Mokhtar 
1784f714a188SAmr Mokhtar 	rte_atomic16_set(&op_params->sync, SYNC_WAIT);
1785f714a188SAmr Mokhtar 
1786*b2e2aec3SKamil Chalupnik 	/* Master core is set at first entry */
1787*b2e2aec3SKamil Chalupnik 	t_params[0].dev_id = ad->dev_id;
1788*b2e2aec3SKamil Chalupnik 	t_params[0].lcore_id = rte_lcore_id();
1789*b2e2aec3SKamil Chalupnik 	t_params[0].op_params = op_params;
1790*b2e2aec3SKamil Chalupnik 	t_params[0].queue_id = ad->queue_ids[used_cores++];
1791*b2e2aec3SKamil Chalupnik 	t_params[0].iter_count = 0;
1792f714a188SAmr Mokhtar 
1793f714a188SAmr Mokhtar 	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
1794f714a188SAmr Mokhtar 		if (used_cores >= num_lcores)
1795f714a188SAmr Mokhtar 			break;
1796f714a188SAmr Mokhtar 
1797*b2e2aec3SKamil Chalupnik 		t_params[used_cores].dev_id = ad->dev_id;
1798*b2e2aec3SKamil Chalupnik 		t_params[used_cores].lcore_id = lcore_id;
1799*b2e2aec3SKamil Chalupnik 		t_params[used_cores].op_params = op_params;
1800*b2e2aec3SKamil Chalupnik 		t_params[used_cores].queue_id = ad->queue_ids[used_cores];
1801*b2e2aec3SKamil Chalupnik 		t_params[used_cores].iter_count = 0;
1802f714a188SAmr Mokhtar 
1803*b2e2aec3SKamil Chalupnik 		rte_eal_remote_launch(throughput_function,
1804*b2e2aec3SKamil Chalupnik 				&t_params[used_cores++], lcore_id);
1805f714a188SAmr Mokhtar 	}
1806f714a188SAmr Mokhtar 
1807f714a188SAmr Mokhtar 	rte_atomic16_set(&op_params->sync, SYNC_START);
1808*b2e2aec3SKamil Chalupnik 	ret = throughput_function(&t_params[0]);
1809f714a188SAmr Mokhtar 
1810f714a188SAmr Mokhtar 	/* Master core is always used */
1811*b2e2aec3SKamil Chalupnik 	for (used_cores = 1; used_cores < num_lcores; used_cores++)
1812*b2e2aec3SKamil Chalupnik 		ret |= rte_eal_wait_lcore(t_params[used_cores].lcore_id);
1813f714a188SAmr Mokhtar 
1814f714a188SAmr Mokhtar 	/* Return if test failed */
1815*b2e2aec3SKamil Chalupnik 	if (ret) {
1816*b2e2aec3SKamil Chalupnik 		rte_free(t_params);
1817f714a188SAmr Mokhtar 		return ret;
1818*b2e2aec3SKamil Chalupnik 	}
1819f714a188SAmr Mokhtar 
1820f714a188SAmr Mokhtar 	/* Print throughput if interrupts are disabled and test passed */
1821f714a188SAmr Mokhtar 	if (!intr_enabled) {
18220b98d574SKamil Chalupnik 		if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
18230b98d574SKamil Chalupnik 			print_dec_throughput(t_params, num_lcores);
18240b98d574SKamil Chalupnik 		else
18250b98d574SKamil Chalupnik 			print_enc_throughput(t_params, num_lcores);
1826*b2e2aec3SKamil Chalupnik 		rte_free(t_params);
1827f714a188SAmr Mokhtar 		return ret;
1828f714a188SAmr Mokhtar 	}
1829f714a188SAmr Mokhtar 
1830f714a188SAmr Mokhtar 	/* In interrupt TC we need to wait for the interrupt callback to deqeue
1831f714a188SAmr Mokhtar 	 * all pending operations. Skip waiting for queues which reported an
1832f714a188SAmr Mokhtar 	 * error using processing_status variable.
1833f714a188SAmr Mokhtar 	 * Wait for master lcore operations.
1834f714a188SAmr Mokhtar 	 */
1835*b2e2aec3SKamil Chalupnik 	tp = &t_params[0];
1836f714a188SAmr Mokhtar 	while ((rte_atomic16_read(&tp->nb_dequeued) <
1837f714a188SAmr Mokhtar 			op_params->num_to_process) &&
1838f714a188SAmr Mokhtar 			(rte_atomic16_read(&tp->processing_status) !=
1839f714a188SAmr Mokhtar 			TEST_FAILED))
1840f714a188SAmr Mokhtar 		rte_pause();
1841f714a188SAmr Mokhtar 
1842*b2e2aec3SKamil Chalupnik 	tp->ops_per_sec /= TEST_REPETITIONS;
1843*b2e2aec3SKamil Chalupnik 	tp->mbps /= TEST_REPETITIONS;
1844f714a188SAmr Mokhtar 	ret |= rte_atomic16_read(&tp->processing_status);
1845f714a188SAmr Mokhtar 
1846f714a188SAmr Mokhtar 	/* Wait for slave lcores operations */
1847*b2e2aec3SKamil Chalupnik 	for (used_cores = 1; used_cores < num_lcores; used_cores++) {
1848*b2e2aec3SKamil Chalupnik 		tp = &t_params[used_cores];
1849f714a188SAmr Mokhtar 
1850f714a188SAmr Mokhtar 		while ((rte_atomic16_read(&tp->nb_dequeued) <
1851f714a188SAmr Mokhtar 				op_params->num_to_process) &&
1852f714a188SAmr Mokhtar 				(rte_atomic16_read(&tp->processing_status) !=
1853f714a188SAmr Mokhtar 				TEST_FAILED))
1854f714a188SAmr Mokhtar 			rte_pause();
1855f714a188SAmr Mokhtar 
1856*b2e2aec3SKamil Chalupnik 		tp->ops_per_sec /= TEST_REPETITIONS;
1857*b2e2aec3SKamil Chalupnik 		tp->mbps /= TEST_REPETITIONS;
1858f714a188SAmr Mokhtar 		ret |= rte_atomic16_read(&tp->processing_status);
1859f714a188SAmr Mokhtar 	}
1860f714a188SAmr Mokhtar 
1861f714a188SAmr Mokhtar 	/* Print throughput if test passed */
18620b98d574SKamil Chalupnik 	if (!ret) {
18630b98d574SKamil Chalupnik 		if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
18640b98d574SKamil Chalupnik 			print_dec_throughput(t_params, num_lcores);
18650b98d574SKamil Chalupnik 		else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC)
18660b98d574SKamil Chalupnik 			print_enc_throughput(t_params, num_lcores);
18670b98d574SKamil Chalupnik 	}
1868*b2e2aec3SKamil Chalupnik 
1869*b2e2aec3SKamil Chalupnik 	rte_free(t_params);
1870f714a188SAmr Mokhtar 	return ret;
1871f714a188SAmr Mokhtar }
1872f714a188SAmr Mokhtar 
1873f714a188SAmr Mokhtar static int
1874864edd69SKamil Chalupnik latency_test_dec(struct rte_mempool *mempool,
1875f714a188SAmr Mokhtar 		struct test_buffers *bufs, struct rte_bbdev_dec_op *ref_op,
1876f714a188SAmr Mokhtar 		int vector_mask, uint16_t dev_id, uint16_t queue_id,
1877f714a188SAmr Mokhtar 		const uint16_t num_to_process, uint16_t burst_sz,
1878864edd69SKamil Chalupnik 		uint64_t *total_time, uint64_t *min_time, uint64_t *max_time)
1879f714a188SAmr Mokhtar {
1880f714a188SAmr Mokhtar 	int ret = TEST_SUCCESS;
1881f714a188SAmr Mokhtar 	uint16_t i, j, dequeued;
1882f714a188SAmr Mokhtar 	struct rte_bbdev_dec_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST];
1883864edd69SKamil Chalupnik 	uint64_t start_time = 0, last_time = 0;
1884f714a188SAmr Mokhtar 
1885f714a188SAmr Mokhtar 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
1886f714a188SAmr Mokhtar 		uint16_t enq = 0, deq = 0;
1887f714a188SAmr Mokhtar 		bool first_time = true;
1888864edd69SKamil Chalupnik 		last_time = 0;
1889f714a188SAmr Mokhtar 
1890f714a188SAmr Mokhtar 		if (unlikely(num_to_process - dequeued < burst_sz))
1891f714a188SAmr Mokhtar 			burst_sz = num_to_process - dequeued;
1892f714a188SAmr Mokhtar 
1893b1bc4217SKamil Chalupnik 		ret = rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz);
1894b1bc4217SKamil Chalupnik 		TEST_ASSERT_SUCCESS(ret,
1895b1bc4217SKamil Chalupnik 				"rte_bbdev_dec_op_alloc_bulk() failed");
1896f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
1897f714a188SAmr Mokhtar 			copy_reference_dec_op(ops_enq, burst_sz, dequeued,
1898f714a188SAmr Mokhtar 					bufs->inputs,
1899f714a188SAmr Mokhtar 					bufs->hard_outputs,
1900f714a188SAmr Mokhtar 					bufs->soft_outputs,
1901f714a188SAmr Mokhtar 					ref_op);
1902f714a188SAmr Mokhtar 
1903f714a188SAmr Mokhtar 		/* Set counter to validate the ordering */
1904f714a188SAmr Mokhtar 		for (j = 0; j < burst_sz; ++j)
1905f714a188SAmr Mokhtar 			ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
1906f714a188SAmr Mokhtar 
1907f714a188SAmr Mokhtar 		start_time = rte_rdtsc_precise();
1908f714a188SAmr Mokhtar 
1909f714a188SAmr Mokhtar 		enq = rte_bbdev_enqueue_dec_ops(dev_id, queue_id, &ops_enq[enq],
1910f714a188SAmr Mokhtar 				burst_sz);
1911f714a188SAmr Mokhtar 		TEST_ASSERT(enq == burst_sz,
1912f714a188SAmr Mokhtar 				"Error enqueueing burst, expected %u, got %u",
1913f714a188SAmr Mokhtar 				burst_sz, enq);
1914f714a188SAmr Mokhtar 
1915f714a188SAmr Mokhtar 		/* Dequeue */
1916f714a188SAmr Mokhtar 		do {
1917f714a188SAmr Mokhtar 			deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
1918f714a188SAmr Mokhtar 					&ops_deq[deq], burst_sz - deq);
1919f714a188SAmr Mokhtar 			if (likely(first_time && (deq > 0))) {
1920864edd69SKamil Chalupnik 				last_time = rte_rdtsc_precise() - start_time;
1921f714a188SAmr Mokhtar 				first_time = false;
1922f714a188SAmr Mokhtar 			}
1923f714a188SAmr Mokhtar 		} while (unlikely(burst_sz != deq));
1924f714a188SAmr Mokhtar 
1925864edd69SKamil Chalupnik 		*max_time = RTE_MAX(*max_time, last_time);
1926864edd69SKamil Chalupnik 		*min_time = RTE_MIN(*min_time, last_time);
1927864edd69SKamil Chalupnik 		*total_time += last_time;
1928864edd69SKamil Chalupnik 
1929f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
1930f714a188SAmr Mokhtar 			ret = validate_dec_op(ops_deq, burst_sz, ref_op,
1931f714a188SAmr Mokhtar 					vector_mask);
1932f714a188SAmr Mokhtar 			TEST_ASSERT_SUCCESS(ret, "Validation failed!");
1933f714a188SAmr Mokhtar 		}
1934f714a188SAmr Mokhtar 
1935f714a188SAmr Mokhtar 		rte_bbdev_dec_op_free_bulk(ops_enq, deq);
1936f714a188SAmr Mokhtar 		dequeued += deq;
1937f714a188SAmr Mokhtar 	}
1938f714a188SAmr Mokhtar 
1939f714a188SAmr Mokhtar 	return i;
1940f714a188SAmr Mokhtar }
1941f714a188SAmr Mokhtar 
1942f714a188SAmr Mokhtar static int
1943864edd69SKamil Chalupnik latency_test_enc(struct rte_mempool *mempool,
1944f714a188SAmr Mokhtar 		struct test_buffers *bufs, struct rte_bbdev_enc_op *ref_op,
1945f714a188SAmr Mokhtar 		uint16_t dev_id, uint16_t queue_id,
1946f714a188SAmr Mokhtar 		const uint16_t num_to_process, uint16_t burst_sz,
1947864edd69SKamil Chalupnik 		uint64_t *total_time, uint64_t *min_time, uint64_t *max_time)
1948f714a188SAmr Mokhtar {
1949f714a188SAmr Mokhtar 	int ret = TEST_SUCCESS;
1950f714a188SAmr Mokhtar 	uint16_t i, j, dequeued;
1951f714a188SAmr Mokhtar 	struct rte_bbdev_enc_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST];
1952864edd69SKamil Chalupnik 	uint64_t start_time = 0, last_time = 0;
1953f714a188SAmr Mokhtar 
1954f714a188SAmr Mokhtar 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
1955f714a188SAmr Mokhtar 		uint16_t enq = 0, deq = 0;
1956f714a188SAmr Mokhtar 		bool first_time = true;
1957864edd69SKamil Chalupnik 		last_time = 0;
1958f714a188SAmr Mokhtar 
1959f714a188SAmr Mokhtar 		if (unlikely(num_to_process - dequeued < burst_sz))
1960f714a188SAmr Mokhtar 			burst_sz = num_to_process - dequeued;
1961f714a188SAmr Mokhtar 
1962b1bc4217SKamil Chalupnik 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
1963b1bc4217SKamil Chalupnik 		TEST_ASSERT_SUCCESS(ret,
1964b1bc4217SKamil Chalupnik 				"rte_bbdev_enc_op_alloc_bulk() failed");
1965f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
1966f714a188SAmr Mokhtar 			copy_reference_enc_op(ops_enq, burst_sz, dequeued,
1967f714a188SAmr Mokhtar 					bufs->inputs,
1968f714a188SAmr Mokhtar 					bufs->hard_outputs,
1969f714a188SAmr Mokhtar 					ref_op);
1970f714a188SAmr Mokhtar 
1971f714a188SAmr Mokhtar 		/* Set counter to validate the ordering */
1972f714a188SAmr Mokhtar 		for (j = 0; j < burst_sz; ++j)
1973f714a188SAmr Mokhtar 			ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
1974f714a188SAmr Mokhtar 
1975f714a188SAmr Mokhtar 		start_time = rte_rdtsc_precise();
1976f714a188SAmr Mokhtar 
1977f714a188SAmr Mokhtar 		enq = rte_bbdev_enqueue_enc_ops(dev_id, queue_id, &ops_enq[enq],
1978f714a188SAmr Mokhtar 				burst_sz);
1979f714a188SAmr Mokhtar 		TEST_ASSERT(enq == burst_sz,
1980f714a188SAmr Mokhtar 				"Error enqueueing burst, expected %u, got %u",
1981f714a188SAmr Mokhtar 				burst_sz, enq);
1982f714a188SAmr Mokhtar 
1983f714a188SAmr Mokhtar 		/* Dequeue */
1984f714a188SAmr Mokhtar 		do {
1985f714a188SAmr Mokhtar 			deq += rte_bbdev_dequeue_enc_ops(dev_id, queue_id,
1986f714a188SAmr Mokhtar 					&ops_deq[deq], burst_sz - deq);
1987f714a188SAmr Mokhtar 			if (likely(first_time && (deq > 0))) {
1988864edd69SKamil Chalupnik 				last_time += rte_rdtsc_precise() - start_time;
1989f714a188SAmr Mokhtar 				first_time = false;
1990f714a188SAmr Mokhtar 			}
1991f714a188SAmr Mokhtar 		} while (unlikely(burst_sz != deq));
1992f714a188SAmr Mokhtar 
1993864edd69SKamil Chalupnik 		*max_time = RTE_MAX(*max_time, last_time);
1994864edd69SKamil Chalupnik 		*min_time = RTE_MIN(*min_time, last_time);
1995864edd69SKamil Chalupnik 		*total_time += last_time;
1996864edd69SKamil Chalupnik 
1997f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
1998f714a188SAmr Mokhtar 			ret = validate_enc_op(ops_deq, burst_sz, ref_op);
1999f714a188SAmr Mokhtar 			TEST_ASSERT_SUCCESS(ret, "Validation failed!");
2000f714a188SAmr Mokhtar 		}
2001f714a188SAmr Mokhtar 
2002f714a188SAmr Mokhtar 		rte_bbdev_enc_op_free_bulk(ops_enq, deq);
2003f714a188SAmr Mokhtar 		dequeued += deq;
2004f714a188SAmr Mokhtar 	}
2005f714a188SAmr Mokhtar 
2006f714a188SAmr Mokhtar 	return i;
2007f714a188SAmr Mokhtar }
2008f714a188SAmr Mokhtar 
2009f714a188SAmr Mokhtar static int
2010864edd69SKamil Chalupnik latency_test(struct active_device *ad,
2011f714a188SAmr Mokhtar 		struct test_op_params *op_params)
2012f714a188SAmr Mokhtar {
2013f714a188SAmr Mokhtar 	int iter;
2014f714a188SAmr Mokhtar 	uint16_t burst_sz = op_params->burst_sz;
2015f714a188SAmr Mokhtar 	const uint16_t num_to_process = op_params->num_to_process;
2016f714a188SAmr Mokhtar 	const enum rte_bbdev_op_type op_type = test_vector.op_type;
2017f714a188SAmr Mokhtar 	const uint16_t queue_id = ad->queue_ids[0];
2018f714a188SAmr Mokhtar 	struct test_buffers *bufs = NULL;
2019f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
2020864edd69SKamil Chalupnik 	uint64_t total_time, min_time, max_time;
2021f714a188SAmr Mokhtar 	const char *op_type_str;
2022f714a188SAmr Mokhtar 
2023864edd69SKamil Chalupnik 	total_time = max_time = 0;
2024864edd69SKamil Chalupnik 	min_time = UINT64_MAX;
2025864edd69SKamil Chalupnik 
2026f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
2027f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
2028f714a188SAmr Mokhtar 
2029f714a188SAmr Mokhtar 	rte_bbdev_info_get(ad->dev_id, &info);
2030f714a188SAmr Mokhtar 	bufs = &op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
2031f714a188SAmr Mokhtar 
2032f714a188SAmr Mokhtar 	op_type_str = rte_bbdev_op_type_str(op_type);
2033f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type);
2034f714a188SAmr Mokhtar 
2035f714a188SAmr Mokhtar 	printf(
20369fa6ebdeSKamil Chalupnik 		"\nValidation/Latency test: dev: %s, burst size: %u, num ops: %u, op type: %s\n",
2037f714a188SAmr Mokhtar 			info.dev_name, burst_sz, num_to_process, op_type_str);
2038f714a188SAmr Mokhtar 
2039f714a188SAmr Mokhtar 	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
2040864edd69SKamil Chalupnik 		iter = latency_test_dec(op_params->mp, bufs,
2041f714a188SAmr Mokhtar 				op_params->ref_dec_op, op_params->vector_mask,
2042f714a188SAmr Mokhtar 				ad->dev_id, queue_id, num_to_process,
2043864edd69SKamil Chalupnik 				burst_sz, &total_time, &min_time, &max_time);
2044f714a188SAmr Mokhtar 	else
2045864edd69SKamil Chalupnik 		iter = latency_test_enc(op_params->mp, bufs,
2046f714a188SAmr Mokhtar 				op_params->ref_enc_op, ad->dev_id, queue_id,
2047864edd69SKamil Chalupnik 				num_to_process, burst_sz, &total_time,
2048864edd69SKamil Chalupnik 				&min_time, &max_time);
2049f714a188SAmr Mokhtar 
2050c3aaec26SAmr Mokhtar 	if (iter <= 0)
2051f714a188SAmr Mokhtar 		return TEST_FAILED;
2052f714a188SAmr Mokhtar 
20539fa6ebdeSKamil Chalupnik 	printf("Operation latency:\n"
20549fa6ebdeSKamil Chalupnik 			"\tavg latency: %lg cycles, %lg us\n"
20559fa6ebdeSKamil Chalupnik 			"\tmin latency: %lg cycles, %lg us\n"
20569fa6ebdeSKamil Chalupnik 			"\tmax latency: %lg cycles, %lg us\n",
2057f714a188SAmr Mokhtar 			(double)total_time / (double)iter,
2058f714a188SAmr Mokhtar 			(double)(total_time * 1000000) / (double)iter /
2059864edd69SKamil Chalupnik 			(double)rte_get_tsc_hz(), (double)min_time,
2060864edd69SKamil Chalupnik 			(double)(min_time * 1000000) / (double)rte_get_tsc_hz(),
2061864edd69SKamil Chalupnik 			(double)max_time, (double)(max_time * 1000000) /
2062f714a188SAmr Mokhtar 			(double)rte_get_tsc_hz());
2063f714a188SAmr Mokhtar 
2064f714a188SAmr Mokhtar 	return TEST_SUCCESS;
2065f714a188SAmr Mokhtar }
2066f714a188SAmr Mokhtar 
2067864edd69SKamil Chalupnik #ifdef RTE_BBDEV_OFFLOAD_COST
2068864edd69SKamil Chalupnik static int
2069864edd69SKamil Chalupnik get_bbdev_queue_stats(uint16_t dev_id, uint16_t queue_id,
2070864edd69SKamil Chalupnik 		struct rte_bbdev_stats *stats)
2071864edd69SKamil Chalupnik {
2072864edd69SKamil Chalupnik 	struct rte_bbdev *dev = &rte_bbdev_devices[dev_id];
2073864edd69SKamil Chalupnik 	struct rte_bbdev_stats *q_stats;
2074864edd69SKamil Chalupnik 
2075864edd69SKamil Chalupnik 	if (queue_id >= dev->data->num_queues)
2076864edd69SKamil Chalupnik 		return -1;
2077864edd69SKamil Chalupnik 
2078864edd69SKamil Chalupnik 	q_stats = &dev->data->queues[queue_id].queue_stats;
2079864edd69SKamil Chalupnik 
2080864edd69SKamil Chalupnik 	stats->enqueued_count = q_stats->enqueued_count;
2081864edd69SKamil Chalupnik 	stats->dequeued_count = q_stats->dequeued_count;
2082864edd69SKamil Chalupnik 	stats->enqueue_err_count = q_stats->enqueue_err_count;
2083864edd69SKamil Chalupnik 	stats->dequeue_err_count = q_stats->dequeue_err_count;
20849fa6ebdeSKamil Chalupnik 	stats->acc_offload_cycles = q_stats->acc_offload_cycles;
2085864edd69SKamil Chalupnik 
2086864edd69SKamil Chalupnik 	return 0;
2087864edd69SKamil Chalupnik }
2088864edd69SKamil Chalupnik 
2089f714a188SAmr Mokhtar static int
2090f714a188SAmr Mokhtar offload_latency_test_dec(struct rte_mempool *mempool, struct test_buffers *bufs,
2091f714a188SAmr Mokhtar 		struct rte_bbdev_dec_op *ref_op, uint16_t dev_id,
2092f714a188SAmr Mokhtar 		uint16_t queue_id, const uint16_t num_to_process,
2093864edd69SKamil Chalupnik 		uint16_t burst_sz, struct test_time_stats *time_st)
2094f714a188SAmr Mokhtar {
2095864edd69SKamil Chalupnik 	int i, dequeued, ret;
2096f714a188SAmr Mokhtar 	struct rte_bbdev_dec_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST];
2097f714a188SAmr Mokhtar 	uint64_t enq_start_time, deq_start_time;
2098864edd69SKamil Chalupnik 	uint64_t enq_sw_last_time, deq_last_time;
2099864edd69SKamil Chalupnik 	struct rte_bbdev_stats stats;
2100f714a188SAmr Mokhtar 
2101f714a188SAmr Mokhtar 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
2102f714a188SAmr Mokhtar 		uint16_t enq = 0, deq = 0;
2103f714a188SAmr Mokhtar 
2104f714a188SAmr Mokhtar 		if (unlikely(num_to_process - dequeued < burst_sz))
2105f714a188SAmr Mokhtar 			burst_sz = num_to_process - dequeued;
2106f714a188SAmr Mokhtar 
2107f714a188SAmr Mokhtar 		rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz);
2108f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
2109f714a188SAmr Mokhtar 			copy_reference_dec_op(ops_enq, burst_sz, dequeued,
2110f714a188SAmr Mokhtar 					bufs->inputs,
2111f714a188SAmr Mokhtar 					bufs->hard_outputs,
2112f714a188SAmr Mokhtar 					bufs->soft_outputs,
2113f714a188SAmr Mokhtar 					ref_op);
2114f714a188SAmr Mokhtar 
2115864edd69SKamil Chalupnik 		/* Start time meas for enqueue function offload latency */
2116864edd69SKamil Chalupnik 		enq_start_time = rte_rdtsc_precise();
2117f714a188SAmr Mokhtar 		do {
2118f714a188SAmr Mokhtar 			enq += rte_bbdev_enqueue_dec_ops(dev_id, queue_id,
2119f714a188SAmr Mokhtar 					&ops_enq[enq], burst_sz - enq);
2120f714a188SAmr Mokhtar 		} while (unlikely(burst_sz != enq));
2121864edd69SKamil Chalupnik 
2122864edd69SKamil Chalupnik 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
2123864edd69SKamil Chalupnik 		TEST_ASSERT_SUCCESS(ret,
2124864edd69SKamil Chalupnik 				"Failed to get stats for queue (%u) of device (%u)",
2125864edd69SKamil Chalupnik 				queue_id, dev_id);
2126864edd69SKamil Chalupnik 
2127864edd69SKamil Chalupnik 		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
21289fa6ebdeSKamil Chalupnik 				stats.acc_offload_cycles;
2129864edd69SKamil Chalupnik 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
2130864edd69SKamil Chalupnik 				enq_sw_last_time);
2131864edd69SKamil Chalupnik 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
2132864edd69SKamil Chalupnik 				enq_sw_last_time);
21339fa6ebdeSKamil Chalupnik 		time_st->enq_sw_total_time += enq_sw_last_time;
2134864edd69SKamil Chalupnik 
21359fa6ebdeSKamil Chalupnik 		time_st->enq_acc_max_time = RTE_MAX(time_st->enq_acc_max_time,
21369fa6ebdeSKamil Chalupnik 				stats.acc_offload_cycles);
21379fa6ebdeSKamil Chalupnik 		time_st->enq_acc_min_time = RTE_MIN(time_st->enq_acc_min_time,
21389fa6ebdeSKamil Chalupnik 				stats.acc_offload_cycles);
21399fa6ebdeSKamil Chalupnik 		time_st->enq_acc_total_time += stats.acc_offload_cycles;
2140f714a188SAmr Mokhtar 
2141f714a188SAmr Mokhtar 		/* ensure enqueue has been completed */
21429585f8b1SKamil Chalupnik 		rte_delay_us(200);
2143f714a188SAmr Mokhtar 
2144864edd69SKamil Chalupnik 		/* Start time meas for dequeue function offload latency */
2145864edd69SKamil Chalupnik 		deq_start_time = rte_rdtsc_precise();
2146864edd69SKamil Chalupnik 		/* Dequeue one operation */
2147f714a188SAmr Mokhtar 		do {
2148f714a188SAmr Mokhtar 			deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
2149864edd69SKamil Chalupnik 					&ops_deq[deq], 1);
2150864edd69SKamil Chalupnik 		} while (unlikely(deq != 1));
2151864edd69SKamil Chalupnik 
2152864edd69SKamil Chalupnik 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
2153864edd69SKamil Chalupnik 		time_st->deq_max_time = RTE_MAX(time_st->deq_max_time,
2154864edd69SKamil Chalupnik 				deq_last_time);
2155864edd69SKamil Chalupnik 		time_st->deq_min_time = RTE_MIN(time_st->deq_min_time,
2156864edd69SKamil Chalupnik 				deq_last_time);
21579fa6ebdeSKamil Chalupnik 		time_st->deq_total_time += deq_last_time;
2158864edd69SKamil Chalupnik 
2159864edd69SKamil Chalupnik 		/* Dequeue remaining operations if needed*/
2160864edd69SKamil Chalupnik 		while (burst_sz != deq)
2161864edd69SKamil Chalupnik 			deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
2162f714a188SAmr Mokhtar 					&ops_deq[deq], burst_sz - deq);
2163f714a188SAmr Mokhtar 
2164f714a188SAmr Mokhtar 		rte_bbdev_dec_op_free_bulk(ops_enq, deq);
2165f714a188SAmr Mokhtar 		dequeued += deq;
2166f714a188SAmr Mokhtar 	}
2167f714a188SAmr Mokhtar 
2168f714a188SAmr Mokhtar 	return i;
2169f714a188SAmr Mokhtar }
2170f714a188SAmr Mokhtar 
2171f714a188SAmr Mokhtar static int
2172f714a188SAmr Mokhtar offload_latency_test_enc(struct rte_mempool *mempool, struct test_buffers *bufs,
2173f714a188SAmr Mokhtar 		struct rte_bbdev_enc_op *ref_op, uint16_t dev_id,
2174f714a188SAmr Mokhtar 		uint16_t queue_id, const uint16_t num_to_process,
2175864edd69SKamil Chalupnik 		uint16_t burst_sz, struct test_time_stats *time_st)
2176f714a188SAmr Mokhtar {
2177864edd69SKamil Chalupnik 	int i, dequeued, ret;
2178f714a188SAmr Mokhtar 	struct rte_bbdev_enc_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST];
2179f714a188SAmr Mokhtar 	uint64_t enq_start_time, deq_start_time;
2180864edd69SKamil Chalupnik 	uint64_t enq_sw_last_time, deq_last_time;
2181864edd69SKamil Chalupnik 	struct rte_bbdev_stats stats;
2182f714a188SAmr Mokhtar 
2183f714a188SAmr Mokhtar 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
2184f714a188SAmr Mokhtar 		uint16_t enq = 0, deq = 0;
2185f714a188SAmr Mokhtar 
2186f714a188SAmr Mokhtar 		if (unlikely(num_to_process - dequeued < burst_sz))
2187f714a188SAmr Mokhtar 			burst_sz = num_to_process - dequeued;
2188f714a188SAmr Mokhtar 
2189f714a188SAmr Mokhtar 		rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
2190f714a188SAmr Mokhtar 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
2191f714a188SAmr Mokhtar 			copy_reference_enc_op(ops_enq, burst_sz, dequeued,
2192f714a188SAmr Mokhtar 					bufs->inputs,
2193f714a188SAmr Mokhtar 					bufs->hard_outputs,
2194f714a188SAmr Mokhtar 					ref_op);
2195f714a188SAmr Mokhtar 
2196864edd69SKamil Chalupnik 		/* Start time meas for enqueue function offload latency */
2197864edd69SKamil Chalupnik 		enq_start_time = rte_rdtsc_precise();
2198f714a188SAmr Mokhtar 		do {
2199f714a188SAmr Mokhtar 			enq += rte_bbdev_enqueue_enc_ops(dev_id, queue_id,
2200f714a188SAmr Mokhtar 					&ops_enq[enq], burst_sz - enq);
2201f714a188SAmr Mokhtar 		} while (unlikely(burst_sz != enq));
2202864edd69SKamil Chalupnik 
2203864edd69SKamil Chalupnik 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
2204864edd69SKamil Chalupnik 		TEST_ASSERT_SUCCESS(ret,
2205864edd69SKamil Chalupnik 				"Failed to get stats for queue (%u) of device (%u)",
2206864edd69SKamil Chalupnik 				queue_id, dev_id);
2207864edd69SKamil Chalupnik 
2208864edd69SKamil Chalupnik 		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
22099fa6ebdeSKamil Chalupnik 				stats.acc_offload_cycles;
2210864edd69SKamil Chalupnik 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
2211864edd69SKamil Chalupnik 				enq_sw_last_time);
2212864edd69SKamil Chalupnik 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
2213864edd69SKamil Chalupnik 				enq_sw_last_time);
22149fa6ebdeSKamil Chalupnik 		time_st->enq_sw_total_time += enq_sw_last_time;
2215864edd69SKamil Chalupnik 
22169fa6ebdeSKamil Chalupnik 		time_st->enq_acc_max_time = RTE_MAX(time_st->enq_acc_max_time,
22179fa6ebdeSKamil Chalupnik 				stats.acc_offload_cycles);
22189fa6ebdeSKamil Chalupnik 		time_st->enq_acc_min_time = RTE_MIN(time_st->enq_acc_min_time,
22199fa6ebdeSKamil Chalupnik 				stats.acc_offload_cycles);
22209fa6ebdeSKamil Chalupnik 		time_st->enq_acc_total_time += stats.acc_offload_cycles;
2221f714a188SAmr Mokhtar 
2222f714a188SAmr Mokhtar 		/* ensure enqueue has been completed */
22239585f8b1SKamil Chalupnik 		rte_delay_us(200);
2224f714a188SAmr Mokhtar 
2225864edd69SKamil Chalupnik 		/* Start time meas for dequeue function offload latency */
2226864edd69SKamil Chalupnik 		deq_start_time = rte_rdtsc_precise();
2227864edd69SKamil Chalupnik 		/* Dequeue one operation */
2228f714a188SAmr Mokhtar 		do {
2229f714a188SAmr Mokhtar 			deq += rte_bbdev_dequeue_enc_ops(dev_id, queue_id,
2230864edd69SKamil Chalupnik 					&ops_deq[deq], 1);
2231864edd69SKamil Chalupnik 		} while (unlikely(deq != 1));
2232864edd69SKamil Chalupnik 
2233864edd69SKamil Chalupnik 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
2234864edd69SKamil Chalupnik 		time_st->deq_max_time = RTE_MAX(time_st->deq_max_time,
2235864edd69SKamil Chalupnik 				deq_last_time);
2236864edd69SKamil Chalupnik 		time_st->deq_min_time = RTE_MIN(time_st->deq_min_time,
2237864edd69SKamil Chalupnik 				deq_last_time);
22389fa6ebdeSKamil Chalupnik 		time_st->deq_total_time += deq_last_time;
2239864edd69SKamil Chalupnik 
2240864edd69SKamil Chalupnik 		while (burst_sz != deq)
2241864edd69SKamil Chalupnik 			deq += rte_bbdev_dequeue_enc_ops(dev_id, queue_id,
2242f714a188SAmr Mokhtar 					&ops_deq[deq], burst_sz - deq);
2243f714a188SAmr Mokhtar 
2244f714a188SAmr Mokhtar 		rte_bbdev_enc_op_free_bulk(ops_enq, deq);
2245f714a188SAmr Mokhtar 		dequeued += deq;
2246f714a188SAmr Mokhtar 	}
2247f714a188SAmr Mokhtar 
2248f714a188SAmr Mokhtar 	return i;
2249f714a188SAmr Mokhtar }
2250864edd69SKamil Chalupnik #endif
2251f714a188SAmr Mokhtar 
2252f714a188SAmr Mokhtar static int
2253864edd69SKamil Chalupnik offload_cost_test(struct active_device *ad,
2254f714a188SAmr Mokhtar 		struct test_op_params *op_params)
2255f714a188SAmr Mokhtar {
2256864edd69SKamil Chalupnik #ifndef RTE_BBDEV_OFFLOAD_COST
2257864edd69SKamil Chalupnik 	RTE_SET_USED(ad);
2258864edd69SKamil Chalupnik 	RTE_SET_USED(op_params);
2259864edd69SKamil Chalupnik 	printf("Offload latency test is disabled.\n");
2260864edd69SKamil Chalupnik 	printf("Set RTE_BBDEV_OFFLOAD_COST to 'y' to turn the test on.\n");
2261864edd69SKamil Chalupnik 	return TEST_SKIPPED;
2262864edd69SKamil Chalupnik #else
2263f714a188SAmr Mokhtar 	int iter;
2264f714a188SAmr Mokhtar 	uint16_t burst_sz = op_params->burst_sz;
2265f714a188SAmr Mokhtar 	const uint16_t num_to_process = op_params->num_to_process;
2266f714a188SAmr Mokhtar 	const enum rte_bbdev_op_type op_type = test_vector.op_type;
2267f714a188SAmr Mokhtar 	const uint16_t queue_id = ad->queue_ids[0];
2268f714a188SAmr Mokhtar 	struct test_buffers *bufs = NULL;
2269f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
2270f714a188SAmr Mokhtar 	const char *op_type_str;
2271864edd69SKamil Chalupnik 	struct test_time_stats time_st;
2272864edd69SKamil Chalupnik 
2273864edd69SKamil Chalupnik 	memset(&time_st, 0, sizeof(struct test_time_stats));
2274864edd69SKamil Chalupnik 	time_st.enq_sw_min_time = UINT64_MAX;
22759fa6ebdeSKamil Chalupnik 	time_st.enq_acc_min_time = UINT64_MAX;
2276864edd69SKamil Chalupnik 	time_st.deq_min_time = UINT64_MAX;
2277f714a188SAmr Mokhtar 
2278f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
2279f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
2280f714a188SAmr Mokhtar 
2281f714a188SAmr Mokhtar 	rte_bbdev_info_get(ad->dev_id, &info);
2282f714a188SAmr Mokhtar 	bufs = &op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
2283f714a188SAmr Mokhtar 
2284f714a188SAmr Mokhtar 	op_type_str = rte_bbdev_op_type_str(op_type);
2285f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type);
2286f714a188SAmr Mokhtar 
2287f714a188SAmr Mokhtar 	printf(
22889fa6ebdeSKamil Chalupnik 		"\nOffload latency test: dev: %s, burst size: %u, num ops: %u, op type: %s\n",
2289f714a188SAmr Mokhtar 			info.dev_name, burst_sz, num_to_process, op_type_str);
2290f714a188SAmr Mokhtar 
2291f714a188SAmr Mokhtar 	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
2292f714a188SAmr Mokhtar 		iter = offload_latency_test_dec(op_params->mp, bufs,
2293f714a188SAmr Mokhtar 				op_params->ref_dec_op, ad->dev_id, queue_id,
2294864edd69SKamil Chalupnik 				num_to_process, burst_sz, &time_st);
2295f714a188SAmr Mokhtar 	else
2296f714a188SAmr Mokhtar 		iter = offload_latency_test_enc(op_params->mp, bufs,
2297f714a188SAmr Mokhtar 				op_params->ref_enc_op, ad->dev_id, queue_id,
2298864edd69SKamil Chalupnik 				num_to_process, burst_sz, &time_st);
2299f714a188SAmr Mokhtar 
2300c3aaec26SAmr Mokhtar 	if (iter <= 0)
2301f714a188SAmr Mokhtar 		return TEST_FAILED;
2302f714a188SAmr Mokhtar 
23039fa6ebdeSKamil Chalupnik 	printf("Enqueue offload cost latency:\n"
23049fa6ebdeSKamil Chalupnik 			"\tDriver offload avg %lg cycles, %lg us\n"
23059fa6ebdeSKamil Chalupnik 			"\tDriver offload min %lg cycles, %lg us\n"
23069fa6ebdeSKamil Chalupnik 			"\tDriver offload max %lg cycles, %lg us\n"
23079fa6ebdeSKamil Chalupnik 			"\tAccelerator offload avg %lg cycles, %lg us\n"
23089fa6ebdeSKamil Chalupnik 			"\tAccelerator offload min %lg cycles, %lg us\n"
23099fa6ebdeSKamil Chalupnik 			"\tAccelerator offload max %lg cycles, %lg us\n",
23109fa6ebdeSKamil Chalupnik 			(double)time_st.enq_sw_total_time / (double)iter,
23119fa6ebdeSKamil Chalupnik 			(double)(time_st.enq_sw_total_time * 1000000) /
2312864edd69SKamil Chalupnik 			(double)iter / (double)rte_get_tsc_hz(),
2313864edd69SKamil Chalupnik 			(double)time_st.enq_sw_min_time,
2314864edd69SKamil Chalupnik 			(double)(time_st.enq_sw_min_time * 1000000) /
2315864edd69SKamil Chalupnik 			rte_get_tsc_hz(), (double)time_st.enq_sw_max_time,
2316864edd69SKamil Chalupnik 			(double)(time_st.enq_sw_max_time * 1000000) /
23179fa6ebdeSKamil Chalupnik 			rte_get_tsc_hz(), (double)time_st.enq_acc_total_time /
2318864edd69SKamil Chalupnik 			(double)iter,
23199fa6ebdeSKamil Chalupnik 			(double)(time_st.enq_acc_total_time * 1000000) /
2320864edd69SKamil Chalupnik 			(double)iter / (double)rte_get_tsc_hz(),
23219fa6ebdeSKamil Chalupnik 			(double)time_st.enq_acc_min_time,
23229fa6ebdeSKamil Chalupnik 			(double)(time_st.enq_acc_min_time * 1000000) /
23239fa6ebdeSKamil Chalupnik 			rte_get_tsc_hz(), (double)time_st.enq_acc_max_time,
23249fa6ebdeSKamil Chalupnik 			(double)(time_st.enq_acc_max_time * 1000000) /
2325864edd69SKamil Chalupnik 			rte_get_tsc_hz());
2326f714a188SAmr Mokhtar 
23279fa6ebdeSKamil Chalupnik 	printf("Dequeue offload cost latency - one op:\n"
23289fa6ebdeSKamil Chalupnik 			"\tavg %lg cycles, %lg us\n"
23299fa6ebdeSKamil Chalupnik 			"\tmin %lg cycles, %lg us\n"
23309fa6ebdeSKamil Chalupnik 			"\tmax %lg cycles, %lg us\n",
23319fa6ebdeSKamil Chalupnik 			(double)time_st.deq_total_time / (double)iter,
23329fa6ebdeSKamil Chalupnik 			(double)(time_st.deq_total_time * 1000000) /
2333864edd69SKamil Chalupnik 			(double)iter / (double)rte_get_tsc_hz(),
2334864edd69SKamil Chalupnik 			(double)time_st.deq_min_time,
2335864edd69SKamil Chalupnik 			(double)(time_st.deq_min_time * 1000000) /
2336864edd69SKamil Chalupnik 			rte_get_tsc_hz(), (double)time_st.deq_max_time,
2337864edd69SKamil Chalupnik 			(double)(time_st.deq_max_time * 1000000) /
2338864edd69SKamil Chalupnik 			rte_get_tsc_hz());
2339f714a188SAmr Mokhtar 
2340f714a188SAmr Mokhtar 	return TEST_SUCCESS;
2341864edd69SKamil Chalupnik #endif
2342f714a188SAmr Mokhtar }
2343f714a188SAmr Mokhtar 
2344864edd69SKamil Chalupnik #ifdef RTE_BBDEV_OFFLOAD_COST
2345f714a188SAmr Mokhtar static int
2346f714a188SAmr Mokhtar offload_latency_empty_q_test_dec(uint16_t dev_id, uint16_t queue_id,
2347f714a188SAmr Mokhtar 		const uint16_t num_to_process, uint16_t burst_sz,
23489fa6ebdeSKamil Chalupnik 		uint64_t *deq_total_time, uint64_t *deq_min_time,
2349864edd69SKamil Chalupnik 		uint64_t *deq_max_time)
2350f714a188SAmr Mokhtar {
2351f714a188SAmr Mokhtar 	int i, deq_total;
2352f714a188SAmr Mokhtar 	struct rte_bbdev_dec_op *ops[MAX_BURST];
2353864edd69SKamil Chalupnik 	uint64_t deq_start_time, deq_last_time;
2354f714a188SAmr Mokhtar 
2355f714a188SAmr Mokhtar 	/* Test deq offload latency from an empty queue */
2356864edd69SKamil Chalupnik 
2357f714a188SAmr Mokhtar 	for (i = 0, deq_total = 0; deq_total < num_to_process;
2358f714a188SAmr Mokhtar 			++i, deq_total += burst_sz) {
2359864edd69SKamil Chalupnik 		deq_start_time = rte_rdtsc_precise();
2360864edd69SKamil Chalupnik 
2361f714a188SAmr Mokhtar 		if (unlikely(num_to_process - deq_total < burst_sz))
2362f714a188SAmr Mokhtar 			burst_sz = num_to_process - deq_total;
2363f714a188SAmr Mokhtar 		rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops, burst_sz);
2364864edd69SKamil Chalupnik 
2365864edd69SKamil Chalupnik 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
2366864edd69SKamil Chalupnik 		*deq_max_time = RTE_MAX(*deq_max_time, deq_last_time);
2367864edd69SKamil Chalupnik 		*deq_min_time = RTE_MIN(*deq_min_time, deq_last_time);
23689fa6ebdeSKamil Chalupnik 		*deq_total_time += deq_last_time;
2369f714a188SAmr Mokhtar 	}
2370f714a188SAmr Mokhtar 
2371f714a188SAmr Mokhtar 	return i;
2372f714a188SAmr Mokhtar }
2373f714a188SAmr Mokhtar 
2374f714a188SAmr Mokhtar static int
2375f714a188SAmr Mokhtar offload_latency_empty_q_test_enc(uint16_t dev_id, uint16_t queue_id,
2376f714a188SAmr Mokhtar 		const uint16_t num_to_process, uint16_t burst_sz,
23779fa6ebdeSKamil Chalupnik 		uint64_t *deq_total_time, uint64_t *deq_min_time,
2378864edd69SKamil Chalupnik 		uint64_t *deq_max_time)
2379f714a188SAmr Mokhtar {
2380f714a188SAmr Mokhtar 	int i, deq_total;
2381f714a188SAmr Mokhtar 	struct rte_bbdev_enc_op *ops[MAX_BURST];
2382864edd69SKamil Chalupnik 	uint64_t deq_start_time, deq_last_time;
2383f714a188SAmr Mokhtar 
2384f714a188SAmr Mokhtar 	/* Test deq offload latency from an empty queue */
2385f714a188SAmr Mokhtar 	for (i = 0, deq_total = 0; deq_total < num_to_process;
2386f714a188SAmr Mokhtar 			++i, deq_total += burst_sz) {
2387864edd69SKamil Chalupnik 		deq_start_time = rte_rdtsc_precise();
2388864edd69SKamil Chalupnik 
2389f714a188SAmr Mokhtar 		if (unlikely(num_to_process - deq_total < burst_sz))
2390f714a188SAmr Mokhtar 			burst_sz = num_to_process - deq_total;
2391f714a188SAmr Mokhtar 		rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops, burst_sz);
2392864edd69SKamil Chalupnik 
2393864edd69SKamil Chalupnik 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
2394864edd69SKamil Chalupnik 		*deq_max_time = RTE_MAX(*deq_max_time, deq_last_time);
2395864edd69SKamil Chalupnik 		*deq_min_time = RTE_MIN(*deq_min_time, deq_last_time);
23969fa6ebdeSKamil Chalupnik 		*deq_total_time += deq_last_time;
2397f714a188SAmr Mokhtar 	}
2398f714a188SAmr Mokhtar 
2399f714a188SAmr Mokhtar 	return i;
2400f714a188SAmr Mokhtar }
2401864edd69SKamil Chalupnik #endif
2402f714a188SAmr Mokhtar 
2403f714a188SAmr Mokhtar static int
2404f714a188SAmr Mokhtar offload_latency_empty_q_test(struct active_device *ad,
2405f714a188SAmr Mokhtar 		struct test_op_params *op_params)
2406f714a188SAmr Mokhtar {
2407864edd69SKamil Chalupnik #ifndef RTE_BBDEV_OFFLOAD_COST
2408864edd69SKamil Chalupnik 	RTE_SET_USED(ad);
2409864edd69SKamil Chalupnik 	RTE_SET_USED(op_params);
2410864edd69SKamil Chalupnik 	printf("Offload latency empty dequeue test is disabled.\n");
2411864edd69SKamil Chalupnik 	printf("Set RTE_BBDEV_OFFLOAD_COST to 'y' to turn the test on.\n");
2412864edd69SKamil Chalupnik 	return TEST_SKIPPED;
2413864edd69SKamil Chalupnik #else
2414f714a188SAmr Mokhtar 	int iter;
24159fa6ebdeSKamil Chalupnik 	uint64_t deq_total_time, deq_min_time, deq_max_time;
2416f714a188SAmr Mokhtar 	uint16_t burst_sz = op_params->burst_sz;
2417f714a188SAmr Mokhtar 	const uint16_t num_to_process = op_params->num_to_process;
2418f714a188SAmr Mokhtar 	const enum rte_bbdev_op_type op_type = test_vector.op_type;
2419f714a188SAmr Mokhtar 	const uint16_t queue_id = ad->queue_ids[0];
2420f714a188SAmr Mokhtar 	struct rte_bbdev_info info;
2421f714a188SAmr Mokhtar 	const char *op_type_str;
2422f714a188SAmr Mokhtar 
24239fa6ebdeSKamil Chalupnik 	deq_total_time = deq_max_time = 0;
2424864edd69SKamil Chalupnik 	deq_min_time = UINT64_MAX;
2425864edd69SKamil Chalupnik 
2426f714a188SAmr Mokhtar 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
2427f714a188SAmr Mokhtar 			"BURST_SIZE should be <= %u", MAX_BURST);
2428f714a188SAmr Mokhtar 
2429f714a188SAmr Mokhtar 	rte_bbdev_info_get(ad->dev_id, &info);
2430f714a188SAmr Mokhtar 
2431f714a188SAmr Mokhtar 	op_type_str = rte_bbdev_op_type_str(op_type);
2432f714a188SAmr Mokhtar 	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type);
2433f714a188SAmr Mokhtar 
2434f714a188SAmr Mokhtar 	printf(
24359fa6ebdeSKamil Chalupnik 		"\nOffload latency empty dequeue test: dev: %s, burst size: %u, num ops: %u, op type: %s\n",
2436f714a188SAmr Mokhtar 			info.dev_name, burst_sz, num_to_process, op_type_str);
2437f714a188SAmr Mokhtar 
2438f714a188SAmr Mokhtar 	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
2439f714a188SAmr Mokhtar 		iter = offload_latency_empty_q_test_dec(ad->dev_id, queue_id,
24409fa6ebdeSKamil Chalupnik 				num_to_process, burst_sz, &deq_total_time,
2441864edd69SKamil Chalupnik 				&deq_min_time, &deq_max_time);
2442f714a188SAmr Mokhtar 	else
2443f714a188SAmr Mokhtar 		iter = offload_latency_empty_q_test_enc(ad->dev_id, queue_id,
24449fa6ebdeSKamil Chalupnik 				num_to_process, burst_sz, &deq_total_time,
2445864edd69SKamil Chalupnik 				&deq_min_time, &deq_max_time);
2446f714a188SAmr Mokhtar 
2447c3aaec26SAmr Mokhtar 	if (iter <= 0)
2448f714a188SAmr Mokhtar 		return TEST_FAILED;
2449f714a188SAmr Mokhtar 
24509fa6ebdeSKamil Chalupnik 	printf("Empty dequeue offload\n"
24519fa6ebdeSKamil Chalupnik 			"\tavg. latency: %lg cycles, %lg us\n"
24529fa6ebdeSKamil Chalupnik 			"\tmin. latency: %lg cycles, %lg us\n"
24539fa6ebdeSKamil Chalupnik 			"\tmax. latency: %lg cycles, %lg us\n",
24549fa6ebdeSKamil Chalupnik 			(double)deq_total_time / (double)iter,
24559fa6ebdeSKamil Chalupnik 			(double)(deq_total_time * 1000000) / (double)iter /
2456864edd69SKamil Chalupnik 			(double)rte_get_tsc_hz(), (double)deq_min_time,
2457864edd69SKamil Chalupnik 			(double)(deq_min_time * 1000000) / rte_get_tsc_hz(),
2458864edd69SKamil Chalupnik 			(double)deq_max_time, (double)(deq_max_time * 1000000) /
2459864edd69SKamil Chalupnik 			rte_get_tsc_hz());
2460f714a188SAmr Mokhtar 
2461f714a188SAmr Mokhtar 	return TEST_SUCCESS;
2462864edd69SKamil Chalupnik #endif
2463f714a188SAmr Mokhtar }
2464f714a188SAmr Mokhtar 
2465f714a188SAmr Mokhtar static int
2466f714a188SAmr Mokhtar throughput_tc(void)
2467f714a188SAmr Mokhtar {
2468f714a188SAmr Mokhtar 	return run_test_case(throughput_test);
2469f714a188SAmr Mokhtar }
2470f714a188SAmr Mokhtar 
2471f714a188SAmr Mokhtar static int
2472864edd69SKamil Chalupnik offload_cost_tc(void)
2473f714a188SAmr Mokhtar {
2474864edd69SKamil Chalupnik 	return run_test_case(offload_cost_test);
2475f714a188SAmr Mokhtar }
2476f714a188SAmr Mokhtar 
2477f714a188SAmr Mokhtar static int
2478f714a188SAmr Mokhtar offload_latency_empty_q_tc(void)
2479f714a188SAmr Mokhtar {
2480f714a188SAmr Mokhtar 	return run_test_case(offload_latency_empty_q_test);
2481f714a188SAmr Mokhtar }
2482f714a188SAmr Mokhtar 
2483f714a188SAmr Mokhtar static int
2484864edd69SKamil Chalupnik latency_tc(void)
2485f714a188SAmr Mokhtar {
2486864edd69SKamil Chalupnik 	return run_test_case(latency_test);
2487f714a188SAmr Mokhtar }
2488f714a188SAmr Mokhtar 
2489f714a188SAmr Mokhtar static int
2490f714a188SAmr Mokhtar interrupt_tc(void)
2491f714a188SAmr Mokhtar {
2492f714a188SAmr Mokhtar 	return run_test_case(throughput_test);
2493f714a188SAmr Mokhtar }
2494f714a188SAmr Mokhtar 
2495f714a188SAmr Mokhtar static struct unit_test_suite bbdev_throughput_testsuite = {
2496f714a188SAmr Mokhtar 	.suite_name = "BBdev Throughput Tests",
2497f714a188SAmr Mokhtar 	.setup = testsuite_setup,
2498f714a188SAmr Mokhtar 	.teardown = testsuite_teardown,
2499f714a188SAmr Mokhtar 	.unit_test_cases = {
2500f714a188SAmr Mokhtar 		TEST_CASE_ST(ut_setup, ut_teardown, throughput_tc),
2501f714a188SAmr Mokhtar 		TEST_CASES_END() /**< NULL terminate unit test array */
2502f714a188SAmr Mokhtar 	}
2503f714a188SAmr Mokhtar };
2504f714a188SAmr Mokhtar 
2505f714a188SAmr Mokhtar static struct unit_test_suite bbdev_validation_testsuite = {
2506f714a188SAmr Mokhtar 	.suite_name = "BBdev Validation Tests",
2507f714a188SAmr Mokhtar 	.setup = testsuite_setup,
2508f714a188SAmr Mokhtar 	.teardown = testsuite_teardown,
2509f714a188SAmr Mokhtar 	.unit_test_cases = {
2510864edd69SKamil Chalupnik 		TEST_CASE_ST(ut_setup, ut_teardown, latency_tc),
2511f714a188SAmr Mokhtar 		TEST_CASES_END() /**< NULL terminate unit test array */
2512f714a188SAmr Mokhtar 	}
2513f714a188SAmr Mokhtar };
2514f714a188SAmr Mokhtar 
2515f714a188SAmr Mokhtar static struct unit_test_suite bbdev_latency_testsuite = {
2516f714a188SAmr Mokhtar 	.suite_name = "BBdev Latency Tests",
2517f714a188SAmr Mokhtar 	.setup = testsuite_setup,
2518f714a188SAmr Mokhtar 	.teardown = testsuite_teardown,
2519f714a188SAmr Mokhtar 	.unit_test_cases = {
2520864edd69SKamil Chalupnik 		TEST_CASE_ST(ut_setup, ut_teardown, latency_tc),
2521864edd69SKamil Chalupnik 		TEST_CASES_END() /**< NULL terminate unit test array */
2522864edd69SKamil Chalupnik 	}
2523864edd69SKamil Chalupnik };
2524864edd69SKamil Chalupnik 
2525864edd69SKamil Chalupnik static struct unit_test_suite bbdev_offload_cost_testsuite = {
2526864edd69SKamil Chalupnik 	.suite_name = "BBdev Offload Cost Tests",
2527864edd69SKamil Chalupnik 	.setup = testsuite_setup,
2528864edd69SKamil Chalupnik 	.teardown = testsuite_teardown,
2529864edd69SKamil Chalupnik 	.unit_test_cases = {
2530864edd69SKamil Chalupnik 		TEST_CASE_ST(ut_setup, ut_teardown, offload_cost_tc),
2531f714a188SAmr Mokhtar 		TEST_CASE_ST(ut_setup, ut_teardown, offload_latency_empty_q_tc),
2532f714a188SAmr Mokhtar 		TEST_CASES_END() /**< NULL terminate unit test array */
2533f714a188SAmr Mokhtar 	}
2534f714a188SAmr Mokhtar };
2535f714a188SAmr Mokhtar 
2536f714a188SAmr Mokhtar static struct unit_test_suite bbdev_interrupt_testsuite = {
2537f714a188SAmr Mokhtar 	.suite_name = "BBdev Interrupt Tests",
2538f714a188SAmr Mokhtar 	.setup = interrupt_testsuite_setup,
2539f714a188SAmr Mokhtar 	.teardown = testsuite_teardown,
2540f714a188SAmr Mokhtar 	.unit_test_cases = {
2541f714a188SAmr Mokhtar 		TEST_CASE_ST(ut_setup, ut_teardown, interrupt_tc),
2542f714a188SAmr Mokhtar 		TEST_CASES_END() /**< NULL terminate unit test array */
2543f714a188SAmr Mokhtar 	}
2544f714a188SAmr Mokhtar };
2545f714a188SAmr Mokhtar 
2546f714a188SAmr Mokhtar REGISTER_TEST_COMMAND(throughput, bbdev_throughput_testsuite);
2547f714a188SAmr Mokhtar REGISTER_TEST_COMMAND(validation, bbdev_validation_testsuite);
2548f714a188SAmr Mokhtar REGISTER_TEST_COMMAND(latency, bbdev_latency_testsuite);
2549864edd69SKamil Chalupnik REGISTER_TEST_COMMAND(offload, bbdev_offload_cost_testsuite);
2550f714a188SAmr Mokhtar REGISTER_TEST_COMMAND(interrupt, bbdev_interrupt_testsuite);
2551