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Searched refs:precrq (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/Mips/micromips-dsp/
H A Dvalid.s49 …precrq.ph.w $8, $9, $10 # CHECK: precrq.ph.w $8, $9, $10 # encoding: [0x01,0x49,0x40,0…
50 …precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0…
/llvm-project-15.0.7/llvm/test/MC/Mips/dsp/
H A Dvalid.s94 …precrq.ph.w $17, $18, $19 # CHECK: precrq.ph.w $17, $18, $19 # encoding: [0x7e,0x…
95 …precrq.qb.ph $16, $17, $18 # CHECK: precrq.qb.ph $16, $17, $18 # encoding: [0x7e,0x…
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips-dspr2/
H A Dvalid.s65 …precrq.ph.w $8, $9, $10 # CHECK: precrq.ph.w $8, $9, $10 # encoding: [0x01,0x49,0x40,0…
66 …precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0…
/llvm-project-15.0.7/llvm/test/MC/Mips/dspr2/
H A Dvalid.s127 …precrq.ph.w $17,$18,$19 # CHECK: precrq.ph.w $17, $18, $19 # encoding: [0x7e,0x53,0…
128 …precrq.qb.ph $16,$17,$18 # CHECK: precrq.qb.ph $16, $17, $18 # encoding: [0x7e,0x32,0…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips-dsp/
H A Dvalid.txt48 0x01 0x49 0x40 0xed # CHECK: precrq.ph.w $8, $9, $10
49 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/dsp/
H A Dvalid.txt92 0x7e 0x53 0x8d 0x11 # CHECK: precrq.ph.w $17, $18, $19
93 0x7e 0x32 0x83 0x11 # CHECK: precrq.qb.ph $16, $17, $18
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips-dspr2/
H A Dvalid.txt64 0x01 0x49 0x40 0xed # CHECK: precrq.ph.w $8, $9, $10
65 0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Ddsp-r1.ll603 ; CHECK: precrq.qb.ph
607 %2 = tail call <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16> %0, <2 x i16> %1)
613 declare <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16>, <2 x i16>) nounwind readnone
617 ; CHECK: precrq.ph.w
619 %0 = tail call <2 x i16> @llvm.mips.precrq.ph.w(i32 %a0, i32 %a1)
625 declare <2 x i16> @llvm.mips.precrq.ph.w(i32, i32) nounwind readnone
631 %0 = tail call <2 x i16> @llvm.mips.precrq.rs.ph.w(i32 %a0, i32 %a1)
637 declare <2 x i16> @llvm.mips.precrq.rs.ph.w(i32, i32) nounwind
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/dspr2/
H A Dvalid.txt125 0x7e 0x53 0x8d 0x11 # CHECK: precrq.ph.w $17, $18, $19
126 0x7e 0x32 0x83 0x11 # CHECK: precrq.qb.ph $16, $17, $18
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-dsp.s75 …precrq.ph.w $14,$s8,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
76 …precrq.qb.ph $a2,$12,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
H A Dinvalid-dspr2.s101 …precrq.ph.w $14,$s8,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
102 …precrq.qb.ph $a2,$12,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsDSPInstrInfo.td127 class PRECRQ_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq.ph.w", 0b0011101101>;
128 class PRECRQ_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrq.qb.ph", 0b0010101101>;
H A DMipsDSPInstrInfo.td621 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
625 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",