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Searched refs:load (Results 1 – 25 of 9159) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...367

/llvm-project-15.0.7/polly/test/ScopInfo/
H A D	multiple-types-non-power-of-two.ll	77 %load.i1.val = load i1, i1* %load.i1.ptrcast 83 %load.i16.val = load i16, i16* %load.i16.ptrcast 89 %load.i24.val = load i24, i24* %load.i24.ptrcast 95 %load.i32.val = load i32, i32* %load.i32.ptrcast 101 %load.i40.val = load i40, i40* %load.i40.ptrcast 107 %load.i48.val = load i48, i48* %load.i48.ptrcast 113 %load.i56.val = load i56, i56* %load.i56.ptrcast 119 %load.i64.val = load i64, i64* %load.i64.ptrcast 125 %load.i120.val = load i120, i120* %load.i120.ptrcast 131 %load.i192.val = load i192, i192* %load.i192.ptrcast [all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A D	ra-allocatable.ll	`101 %0 = load i32, i32* @a0, align 4 102 %1 = load i32, i32* @b0, align 4 104 %2 = load i32, i32* @a1, align 4 107 %4 = load i32, i32* @a2, align 4 110 %6 = load i32, i32* @a3, align 4 113 %8 = load i32, i32* @a4, align 4 116 %10 = load i32, i32* @a5, align 4 119 %12 = load i32, i32* @a6, align 4 122 %14 = load i32, i32* @a7, align 4 125 %16 = load i32, i32* @a8, align 4 [all …]`
/llvm-project-15.0.7/lld/test/wasm/Inputs/
H A D	many-funcs.ll	`8 %0 = load i32, i32* @foo, align 4 14 %0 = load i32, i32* @foo, align 4 20 %0 = load i32, i32* @foo, align 4 26 %0 = load i32, i32* @foo, align 4 32 %0 = load i32, i32* @foo, align 4 38 %0 = load i32, i32* @foo, align 4 44 %0 = load i32, i32* @foo, align 4 50 %0 = load i32, i32* @foo, align 4 56 %0 = load i32, i32* @foo, align 4 62 %0 = load i32, i32* @foo, align 4 [all …]`
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A D	load_atomic.ll	14 %load = load atomic i8, i8* %ptr unordered, align 1 15 ret i8 %load 25 %load = load atomic i8, i8* %ptr unordered, align 1 37 %load = load atomic i8, i8* %ptr unordered, align 1 50 %load = load atomic i8, i8* %ptr unordered, align 1 61 %load = load atomic i8, i8* %ptr unordered, align 1 72 %load = load atomic i8, i8* %ptr unordered, align 1 84 %load = load atomic i8, i8* %ptr unordered, align 1 95 %load = load atomic i16, i16* %ptr unordered, align 2 106 %load = load atomic i16, i16* %ptr unordered, align 2 [all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A D	hrc-stack-coloring.ll	`66 %v34 = load %s.11, %s.11* %v1, align 4 69 %v37 = load i64, i64* %v36, align 8 74 %v41 = load %s.11, %s.11* %v1, align 4 77 %v44 = load i64, i64* %v43, align 8 82 %v48 = load %s.11, %s.11* %v1, align 4 85 %v51 = load i64, i64* %v50, align 8 90 %v55 = load %s.11, %s.11* %v1, align 4 93 %v58 = load i64, i64* %v57, align 8 101 %v65 = load i64, i64* %v64, align 8 109 %v72 = load i64, i64* %v71, align 8 [all …]`
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A D	merge-sbuffer-load.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| … 4 # CHECK: S_BUFFER_LOAD_DWORDX2_IMM %0, 0, 0 :: (dereferenceable invariant load (s64), align 4) 13 …_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %0:sgpr_128, 0, 0 :: (dereferenceable invariant load (s32)) 21 # CHECK: S_BUFFER_LOAD_DWORDX4_IMM %0, 0, 0 :: (dereferenceable invariant load (s128), align 4) 39 # CHECK: S_BUFFER_LOAD_DWORDX8_IMM %0, 0, 0 :: (dereferenceable invariant load (s256), align 4) 61 # CHECK: S_BUFFER_LOAD_DWORDX8_IMM %0, 0, 0 :: (dereferenceable invariant load (s256), align 4) 83 # CHECK: S_BUFFER_LOAD_DWORDX8_IMM %0, 0, 0 :: (dereferenceable invariant load (s256), align 8) 92 … %2:sgpr_64 = S_BUFFER_LOAD_DWORDX2_IMM %0:sgpr_128, 8, 0 :: (dereferenceable invariant load (s64)) 93 … %3:sgpr_64 = S_BUFFER_LOAD_DWORDX2_IMM %0:sgpr_128, 0, 0 :: (dereferenceable invariant load (s64)) 101 # CHECK: S_BUFFER_LOAD_DWORDX8_IMM %0, 0, 0 :: (dereferenceable invariant load (s256), align 16) [all …]
H A D	merge-image-load-gfx11.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| … 16 …AD_DWORDX2_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 204 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 205 …BUFFER_LOAD_DWORDX2_OFFSET %2, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 224 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 242 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 260 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 278 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 296 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 314 …BUFFER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) [all …]
H A D	merge-image-load-gfx10.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| … 16 …WORDX2_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 204 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 205 …ER_LOAD_DWORDX2_OFFSET %2, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 224 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 242 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 260 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 278 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 296 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 314 …ER_LOAD_DWORDX2_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) [all …]
H A D	load-constant-i1.ll	13 %load = load i1, i1 addrspace(4)* %in 20 %load = load <2 x i1>, <2 x i1> addrspace(4)* %in 27 %load = load <3 x i1>, <3 x i1> addrspace(4)* %in 34 %load = load <4 x i1>, <4 x i1> addrspace(4)* %in 41 %load = load <8 x i1>, <8 x i1> addrspace(4)* %in 48 %load = load <16 x i1>, <16 x i1> addrspace(4)* %in 55 %load = load <32 x i1>, <32 x i1> addrspace(4)* %in 62 %load = load <64 x i1>, <64 x i1> addrspace(4)* %in 93 %load = load <1 x i1>, <1 x i1> addrspace(4)* %in 101 %load = load <1 x i1>, <1 x i1> addrspace(4)* %in [all …]
H A D	load-global-i1.ll	13 %load = load i1, i1 addrspace(1)* %in 20 %load = load <2 x i1>, <2 x i1> addrspace(1)* %in 27 %load = load <3 x i1>, <3 x i1> addrspace(1)* %in 34 %load = load <4 x i1>, <4 x i1> addrspace(1)* %in 41 %load = load <8 x i1>, <8 x i1> addrspace(1)* %in 48 %load = load <16 x i1>, <16 x i1> addrspace(1)* %in 55 %load = load <32 x i1>, <32 x i1> addrspace(1)* %in 62 %load = load <64 x i1>, <64 x i1> addrspace(1)* %in 93 %load = load <1 x i1>, <1 x i1> addrspace(1)* %in 101 %load = load <1 x i1>, <1 x i1> addrspace(1)* %in [all …]
H A D	merge-image-sample.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| F… 16 …WORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 205 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 206 …ER_LOAD_DWORDX4_OFFSET %2, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 225 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 244 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 262 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 280 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 298 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 316 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) [all …]
H A D	merge-image-load.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| F… 16 …WORDX4_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 205 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 206 …ER_LOAD_DWORDX4_OFFSET %2, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 225 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 243 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 261 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 279 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 297 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 315 …ER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) [all …]
H A D	merge-image-sample-gfx11.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| … 16 …LOAD_DWORD_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 204 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 205 …= BUFFER_LOAD_DWORD_OFFSET %2, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 224 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 243 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 261 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 279 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 297 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) 315 …= BUFFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16) [all …]
H A D	load-local-i1.ll	18 %load = load i1, i1 addrspace(3)* %in 27 %load = load <2 x i1>, <2 x i1> addrspace(3)* %in 36 %load = load <3 x i1>, <3 x i1> addrspace(3)* %in 45 %load = load <4 x i1>, <4 x i1> addrspace(3)* %in 54 %load = load <8 x i1>, <8 x i1> addrspace(3)* %in 63 %load = load <16 x i1>, <16 x i1> addrspace(3)* %in 72 %load = load <32 x i1>, <32 x i1> addrspace(3)* %in 81 %load = load <64 x i1>, <64 x i1> addrspace(3)* %in 120 %load = load <1 x i1>, <1 x i1> addrspace(3)* %in 130 %load = load <1 x i1>, <1 x i1> addrspace(3)* %in [all …]
H A D	merge-image-sample-gfx10.mir	1 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s \| … 16 …_DWORD_OFFSET %2:sgpr_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 204 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 205 …FFER_LOAD_DWORD_OFFSET %2, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 224 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 243 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 261 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 279 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 297 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) 315 …FFER_LOAD_DWORD_OFFSET %2, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) [all …]
H A D	global-extload-i16.ll	32 %load = load <1 x i16>, <1 x i16> addrspace(1)* %in 42 %load = load <1 x i16>, <1 x i16> addrspace(1)* %in 51 %load = load <2 x i16>, <2 x i16> addrspace(1)* %in 60 %load = load <2 x i16>, <2 x i16> addrspace(1)* %in 69 %load = load <4 x i16>, <4 x i16> addrspace(1)* %in 78 %load = load <4 x i16>, <4 x i16> addrspace(1)* %in 87 %load = load <8 x i16>, <8 x i16> addrspace(1)* %in 96 %load = load <8 x i16>, <8 x i16> addrspace(1)* %in 105 %load = load <16 x i16>, <16 x i16> addrspace(1)* %in 181 %load = load <1 x i16>, <1 x i16> addrspace(1)* %in [all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A D	build-vector-float-type.ll	`14 %v1 = load i32, i32* %v0, align 4 16 %v3 = load float, float* %v2, align 4 19 %v6 = load i32, i32* %v5, align 4 21 %v8 = load float, float* %v7, align 4 24 %v11 = load i32, i32* %v10, align 4 29 %v16 = load i32, i32* %v15, align 4 34 %v21 = load i32, i32* %v20, align 4 39 %v26 = load i32, i32* %v25, align 4 44 %v31 = load i32, i32* %v30, align 4 49 %v36 = load i32, i32* %v35, align 4 [all …]`
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A D	jumbled-load.ll	`25 %load.2 = load i32, i32* %gep.1, align 4 27 %load.3 = load i32, i32* %gep.2, align 4 29 %load.4 = load i32, i32* %gep.3, align 4 38 %mul.1 = mul i32 %load.3, %load.5 39 %mul.2 = mul i32 %load.2, %load.8 40 %mul.3 = mul i32 %load.4, %load.7 41 %mul.4 = mul i32 %load.1, %load.6 76 %mul.1 = mul i32 %load.3, %load.4 77 %mul.2 = mul i32 %load.2, %load.2 78 %mul.3 = mul i32 %load.4, %load.1 [all …]`
H A D	arith-add-load.ll	`24 %0 = load i8, ptr %a, align 1 25 %1 = load i8, ptr %r, align 1 29 %2 = load i8, ptr %arrayidx.1, align 1 35 %4 = load i8, ptr %arrayidx.2, align 1 41 %6 = load i8, ptr %arrayidx.3, align 1 59 %0 = load i8, ptr %a, align 1 60 %1 = load i8, ptr %r, align 1 118 %0 = load i8, ptr %a, align 1 119 %1 = load i8, ptr %r, align 1 239 %0 = load i8, ptr %a, align 1 [all …]`
H A D	arith-mul-load.ll	`24 %0 = load i8, ptr %a, align 1 25 %1 = load i8, ptr %r, align 1 29 %2 = load i8, ptr %arrayidx.1, align 1 35 %4 = load i8, ptr %arrayidx.2, align 1 41 %6 = load i8, ptr %arrayidx.3, align 1 59 %0 = load i8, ptr %a, align 1 60 %1 = load i8, ptr %r, align 1 118 %0 = load i8, ptr %a, align 1 119 %1 = load i8, ptr %r, align 1 239 %0 = load i8, ptr %a, align 1 [all …]`
/llvm-project-15.0.7/llvm/test/Analysis/MemorySSA/
H A D	volatile-clobber.ll	`33 load volatile i32, i32* %a 35 ; CHECK-NEXT: load i32, i32* %b 36 load i32, i32* %b 38 ; CHECK-NEXT: load i32, i32* %a 39 load i32, i32* %a 44 load volatile i32, i32* %arg1 47 load i32, i32* %arg2 65 load i32, i32* %b 72 load i32, i32* %b 81 load i32, i32* %a [all …]`
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A D	load-store.ll	`7 %a.load = load i8, i8* %a 13 %b.load = load i16, i16* %b 19 %c.load = load i32, i32* %c 25 %d.load = load i64, i64* %d 36 %a.load = load volatile i8, i8* %a 42 %b.load = load volatile i16, i16* %b 48 %c.load = load volatile i32, i32* %c 54 %d.load = load volatile i64, i64* %d 65 %a.load = load atomic i8, i8* %a monotonic, align 1 71 %b.load = load atomic i16, i16* %b monotonic, align 2 [all …]`
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A D	sve-ld1r.mir	40 … ; CHECK: renamable $z0 = LD1RB_IMM renamable $p0, $sp, 63 :: (load (s8) from %ir.object, align 2) 47 ; CHECK: renamable $z0 = LD1RH_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) 48 ; CHECK: renamable $z0 = LD1RH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) 49 ; CHECK: renamable $z0 = LD1RH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) 50 ; CHECK: renamable $z0 = LD1RSH_S_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) 51 ; CHECK: renamable $z0 = LD1RSH_D_IMM renamable $p0, $sp, 63 :: (load (s16) from %ir.object) 52 ; CHECK: renamable $z0 = LD1RW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) 53 ; CHECK: renamable $z0 = LD1RW_D_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) 54 ; CHECK: renamable $z0 = LD1RSW_IMM renamable $p0, $sp, 63 :: (load (s32) from %ir.object) 55 ; CHECK: renamable $z0 = LD1RD_IMM renamable $p0, $sp, 63 :: (load (s64) from %ir.object) [all …]
H A D	aarch64-minmaxv.ll	`25 %arr.load = load <16 x i8>, <16 x i8>* %arr 33 %arr.load = load <8 x i16>, <8 x i16>* %arr 41 %arr.load = load <4 x i32>, <4 x i32>* %arr 49 %arr.load = load <16 x i8>, <16 x i8>* %arr 57 %arr.load = load <8 x i16>, <8 x i16>* %arr 65 %arr.load = load <4 x i32>, <4 x i32>* %arr 73 %arr.load = load <16 x i8>, <16 x i8>* %arr 81 %arr.load = load <8 x i16>, <8 x i16>* %arr 89 %arr.load = load <4 x i32>, <4 x i32>* %arr 97 %arr.load = load <16 x i8>, <16 x i8>* %arr [all …]`
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/X86/
H A D	subchain-interleaved.ll	`10 ; CHECK: load <2 x i32> 11 ; CHECK: load i32 13 ; CHECK: load i32 30 ; CHECK: load <3 x i32> 32 ; CHECK: load i32 50 ; CHECK: load i32 52 ; CHECK: load <2 x i32> 95 ; CHECK: load i32 97 ; CHECK: load i32 98 ; CHECK: load i32 [all …]`

12 3 4 5 6 7 8 9 10 >>...367

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