| /freebsd-12.1/contrib/gcc/config/arm/ |
| H A D | constraints.md | 169 In ARM state an address valid in ldrsb instructions."
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| H A D | arm.md | 3946 return \"ldrsb\\t%0, %1\";
3961 output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops);
3969 output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
3981 output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
3995 output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
4029 return \"ldrsb\\t%0, %1\";
4044 output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops);
4051 output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
4062 output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
4075 output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb2.td | 1257 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1354 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1360 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
4575 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4586 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4597 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4857 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4868 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
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| H A D | ARMInstrThumb.td | 737 "ldrsb", "\t$Rt, $addr",
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| H A D | ARMInstrInfo.td | 2666 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2785 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 1760 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1761 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
2060 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
2064 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
2313 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
2315 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
2363 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;
2364 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">;
2388 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;
2389 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">;
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| /freebsd-12.1/contrib/binutils/gas/config/ |
| H A D | tc-arm.c | 8355 X(ldrsb, 5600, f9100000), \
15124 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15126 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
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| /freebsd-12.1/contrib/binutils/opcodes/ |
| H A D | ChangeLog-0001 | 1818 instructions changed to ldrsb/ldrsh.
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| /freebsd-12.1/contrib/gdb/ |
| H A D | md5.sum | 3923 bef5c11ab14ef76a4adf86bdb29f3fa7 sim/testsuite/sim/arm/ldrsb.cgs
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| /freebsd-12.1/contrib/gcc/doc/ |
| H A D | md.texi | 1681 A memory reference suitable for the ARMv4 ldrsb instruction.
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| /freebsd-12.1/contrib/gcc/ |
| H A D | ChangeLog-1998 | 11446 * arm.md (*extendqi[sh]i_insn): Split any addresses that ldrsb
|