Home
last modified time | relevance | path

Searched refs:ldrb (Results 1 – 25 of 229) sorted by relevance

12345678910

/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-gather-ind8-unscaled.ll35 ; CHECK-NEXT: ldrb r2, [r1]
69 ; CHECK-NEXT: ldrb r3, [r4]
70 ; CHECK-NEXT: ldrb r2, [r5]
72 ; CHECK-NEXT: ldrb r4, [r4]
73 ; CHECK-NEXT: ldrb r5, [r5]
77 ; CHECK-NEXT: ldrb r5, [r4]
78 ; CHECK-NEXT: ldrb r4, [r6]
82 ; CHECK-NEXT: ldrb r0, [r6]
83 ; CHECK-NEXT: ldrb r7, [r7]
87 ; CHECK-NEXT: ldrb r0, [r0]
[all …]
H A Dthumb2-ldrb.ll6 ; CHECK: ldrb r0, [r0]
14 ; CHECK: ldrb r0, [r0, #-1]
24 ; CHECK: ldrb r0, [r0, r1]
34 ; CHECK: ldrb r0, [r0, #-128]
44 ; CHECK: ldrb r0, [r0, r1]
54 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
66 ; CHECK: ldrb r0, [r0, r1]
H A Dmve-gather-ptrs.ll422 ; CHECK-NEXT: ldrb r5, [r1]
423 ; CHECK-NEXT: ldrb r1, [r2]
424 ; CHECK-NEXT: ldrb r2, [r6]
429 ; CHECK-NEXT: ldrb r4, [r2]
430 ; CHECK-NEXT: ldrb r2, [r3]
431 ; CHECK-NEXT: ldrb r3, [r7]
435 ; CHECK-NEXT: ldrb r3, [r3]
436 ; CHECK-NEXT: ldrb r6, [r6]
440 ; CHECK-NEXT: ldrb r0, [r0]
441 ; CHECK-NEXT: ldrb r3, [r3]
[all …]
H A Dmve-gather-increment.ll118 ; CHECK-NEXT: ldrb r1, [r3]
120 ; CHECK-NEXT: ldrb r3, [r4]
122 ; CHECK-NEXT: ldrb r2, [r2]
123 ; CHECK-NEXT: ldrb r4, [r4]
127 ; CHECK-NEXT: ldrb r4, [r2]
128 ; CHECK-NEXT: ldrb r2, [r6]
130 ; CHECK-NEXT: ldrb r0, [r6]
131 ; CHECK-NEXT: ldrb r7, [r7]
135 ; CHECK-NEXT: ldrb r0, [r0]
136 ; CHECK-NEXT: ldrb r5, [r5]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dstruct_byval_arm_t1_t2.ll62 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
64 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
66 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
71 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
148 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
151 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
171 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
173 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
175 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
180 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
[all …]
H A Dand-load-combine.ll10 ; ARM-NEXT: ldrb r0, [r0]
11 ; ARM-NEXT: ldrb r1, [r1]
28 ; THUMB1-NEXT: ldrb r0, [r0]
29 ; THUMB1-NEXT: ldrb r1, [r1]
37 ; THUMB2-NEXT: ldrb r0, [r0]
38 ; THUMB2-NEXT: ldrb r1, [r1]
55 ; ARM-NEXT: ldrb r0, [r0]
56 ; ARM-NEXT: ldrb r1, [r1]
101 ; ARM-NEXT: ldrb r0, [r0]
102 ; ARM-NEXT: ldrb r1, [r1]
[all …]
H A Dunaligned_load_store.ll16 ; EXPANDED-DAG: ldrb [[R2:r[0-9]+]]
17 ; EXPANDED-DAG: ldrb [[R3:r[0-9]+]]
18 ; EXPANDED-DAG: ldrb [[R12:r[0-9]+]]
19 ; EXPANDED-DAG: ldrb [[R1:r[0-9]+]]
56 ; EXPANDED: ldrb
71 ; EXPANDED: ldrb
75 ; UNALIGNED-NOT: ldrb
H A Dfast-isel-align.ll99 ; ARM-STRICT-ALIGN: ldrb
100 ; ARM-STRICT-ALIGN: ldrb
103 ; THUMB-STRICT-ALIGN: ldrb
104 ; THUMB-STRICT-ALIGN: ldrb
131 ; ARM-STRICT-ALIGN: ldrb
132 ; ARM-STRICT-ALIGN: ldrb
133 ; ARM-STRICT-ALIGN: ldrb
134 ; ARM-STRICT-ALIGN: ldrb
137 ; THUMB-STRICT-ALIGN: ldrb
138 ; THUMB-STRICT-ALIGN: ldrb
[all …]
H A D2013-05-07-ByteLoadSameAddress.ll21 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
22 ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
37 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
38 ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
51 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
52 ; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1]
H A Dload-arm.ll10 ; CHECK: {{ldrb|ldrb.w}} {{r[0-9]+}}, [r0, [[OFFSET]], lsl #3]
20 ; CHECK-NOT: {{ldrb|ldrb.w}} {{r[0-9]+}}, [{{r[0-9]+}}, {{r[0-9]+}}, lsl #3]
H A Dsub-of-not.ll116 ; ARM6-NEXT: ldrb r12, [sp, #52]
142 ; ARM6-NEXT: ldrb r1, [sp, #96]
147 ; ARM6-NEXT: ldrb r1, [sp, #92]
152 ; ARM6-NEXT: ldrb r1, [sp, #88]
157 ; ARM6-NEXT: ldrb r1, [sp, #84]
162 ; ARM6-NEXT: ldrb r1, [sp, #80]
167 ; ARM6-NEXT: ldrb r1, [sp, #76]
169 ; ARM6-NEXT: ldrb r12, [sp, #8]
172 ; ARM6-NEXT: ldrb r1, [sp, #72]
174 ; ARM6-NEXT: ldrb r12, [sp, #4]
[all …]
H A Dinc-of-add.ll117 ; ARM6-NEXT: ldrb r1, [sp, #52]
122 ; ARM6-NEXT: ldrb r1, [sp, #48]
127 ; ARM6-NEXT: ldrb r1, [sp, #44]
132 ; ARM6-NEXT: ldrb r1, [sp, #40]
137 ; ARM6-NEXT: ldrb r1, [sp, #36]
142 ; ARM6-NEXT: ldrb r1, [sp, #32]
147 ; ARM6-NEXT: ldrb r1, [sp, #28]
152 ; ARM6-NEXT: ldrb r1, [sp, #24]
172 ; ARM6-NEXT: ldrb r1, [sp, #8]
177 ; ARM6-NEXT: ldrb r1, [sp, #4]
[all …]
H A Dfast-isel-intrinsic.ll221 ; ARM-MACHO: ldrb [[REG1:r[0-9]+]], [[[REG0]], #16]
250 ; THUMB: ldrb [[REG2:r[0-9]+]], [[[REG0]], #16]
252 ; THUMB: ldrb [[REG3:r[0-9]+]], [[[REG0]], #17]
254 ; THUMB: ldrb [[REG4:r[0-9]+]], [[[REG0]], #18]
256 ; THUMB: ldrb [[REG5:r[0-9]+]], [[[REG0]], #19]
258 ; THUMB: ldrb [[REG6:r[0-9]+]], [[[REG0]], #20]
260 ; THUMB: ldrb [[REG7:r[0-9]+]], [[[REG0]], #21]
262 ; THUMB: ldrb [[REG8:r[0-9]+]], [[[REG0]], #22]
264 ; THUMB: ldrb [[REG9:r[0-9]+]], [[[REG0]], #23]
266 ; THUMB: ldrb [[REG10:r[0-9]+]], [[[REG0]], #24]
[all …]
H A Dload-combine.ll12 ; CHECK-NEXT: ldrb r2, [r0, #1]
13 ; CHECK-NEXT: ldrb r1, [r0]
14 ; CHECK-NEXT: ldrb r3, [r0, #2]
15 ; CHECK-NEXT: ldrb r0, [r0, #3]
24 ; CHECK-ARMv6-NEXT: ldrb r1, [r0]
34 ; CHECK-THUMBv6-NEXT: ldrb r1, [r0]
772 ; CHECK-NEXT: ldrb r1, [r0]
821 ; CHECK-NEXT: ldrb r1, [r0]
870 ; CHECK-NEXT: ldrb r1, [r0]
910 ; CHECK-NEXT: ldrb r1, [r0]
[all …]
H A Dtest-sharedidx.ll23 ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
24 ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
45 ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
46 ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
78 ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]
79 ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dstack-tagging-unchecked-ld-st.ll78 ; ALWAYS: ldrb w0, [sp]
79 ; DEFAULT: ldrb w0, [sp]
80 ; NEVER: ldrb w0, [x{{.*}}]
207 ; NEVER: ldrb [[A:w.*]], [x{{.*}}]
208 ; NEVER: ldrb [[B:w.*]], [x{{.*}}]
210 ; DEFAULT: ldrb [[A:w.*]], [x{{.*}}]
211 ; DEFAULT: ldrb [[B:w.*]], [x{{.*}}]
214 ; ALWAYS-DAG: ldrb [[B:w.*]], [sp]
249 ; ALWAYS-DAG: ldrb w{{.*}}, [sp]
253 ; DEFAULT-DAG: ldrb w{{.*}}, [sp]
[all …]
H A Dtiny-model-pic.ll16 ; CHECK-NEXT: ldrb w8, [x8]
32 ; CHECK-PIC-NEXT: ldrb w8, [x8]
90 ; CHECK-NEXT: ldrb w8, [x8]
108 ; CHECK-PIC-NEXT: ldrb w8, [x8]
136 ; CHECK-NEXT: ldrb w8, [x8]
153 ; CHECK-PIC-NEXT: ldrb w8, [x8]
209 ; CHECK-NEXT: ldrb w8, [x8]
227 ; CHECK-PIC-NEXT: ldrb w8, [x8]
254 ; CHECK-NEXT: ldrb w8, [x8]
271 ; CHECK-PIC-NEXT: ldrb w8, [x8]
[all …]
H A Dbyval-type.ll5 ; CHECK: ldrb w0, [sp, #8]
12 ; CHECK: ldrb [[P1:w[0-9]+]], [x1]
14 ; CHECK: ldrb [[P0:w[0-9]+]], [x0]
23 ; CHECK: ldrb w0, [sp, #24]
H A Dtiny-model-static.ll16 ; CHECK-NEXT: ldrb w8, [x8]
24 ; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
60 ; CHECK-NEXT: ldrb w8, [x8]
69 ; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
89 ; CHECK-NEXT: ldrb w8, [x8]
97 ; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
132 ; CHECK-NEXT: ldrb w8, [x8]
140 ; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
160 ; CHECK-NEXT: ldrb w8, [x8]
168 ; CHECK-GLOBISEL-NEXT: ldrb w8, [x8]
[all …]
H A Dbool-loads.ll10 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
22 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
37 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
51 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
H A Darm64-fast-isel-intrinsic.ll58 ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #16]
75 ; ARM64: ldrb [[REG4:w[0-9]+]], [[[REG1]], #16]
92 ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #8]
111 ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #6]
124 ; ARM64: ldrb w10, [[[REG2]]]
126 ; ARM64: ldrb w10, [[[REG2]], #1]
128 ; ARM64: ldrb w10, [[[REG2]], #2]
130 ; ARM64: ldrb [[REG3:w[0-9]+]], [[[REG2]], #3]
142 ; ARM64: ldrb [[BYTE:w[0-9]+]], [x[[ADDR]]]
H A Darm64-addr-type-promotion.ll20 ; CHECK-NEXT: ldrb w11, [x10, x8]
21 ; CHECK-NEXT: ldrb w12, [x10, x9]
27 ; CHECK-NEXT: ldrb w10, [x8, #1]
28 ; CHECK-NEXT: ldrb w11, [x9, #1]
32 ; CHECK-NEXT: ldrb w8, [x8, #2]
33 ; CHECK-NEXT: ldrb w9, [x9, #2]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-memory-instructions.s26 ldrb r3, [r8]
27 ldrb r1, [sp, #63]
28 ldrb r9, [r3, #4095]!
29 ldrb r8, [r1], #22
30 ldrb r2, [r7], #-19
31 ldrb r9, [r8, r5]
32 ldrb r1, [r5, -r1]
33 ldrb r3, [r5, r2]!
36 ldrb r6, [r9, -r3]!
37 ldrb r2, [r1], r4
[all …]
/llvm-project-15.0.7/libc/AOR_v20.02/string/arm/
H A Dstrcmp-armv6m.S96 ldrb r2, [r0, #0]
97 ldrb r3, [r1, #0]
104 ldrb r2, [r0, #0]
105 ldrb r3, [r1, #0]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmemory-arm-instructions.txt53 # CHECK: ldrb r3, [r8]
54 # CHECK: ldrb r1, [sp, #63]
55 # CHECK: ldrb r9, [r3, #4095]!
56 # CHECK: ldrb r8, [r1], #22
57 # CHECK: ldrb r2, [r7], #-19
69 # CHECK: ldrb r9, [r8, r5]
70 # CHECK: ldrb r1, [r5, -r1]
71 # CHECK: ldrb r3, [r5, r2]!
72 # CHECK: ldrb r6, [r9, -r3]!
73 # CHECK: ldrb r2, [r1], r4
[all …]

12345678910