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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddetect-dead-lanes.mir1 # RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
42 # Check defined lanes transfer; Includes checking for some special cases like
122 # Check used lanes transfer; Includes checking for some special cases like
203 # Check that copies to physregs use all lanes, copies from physregs define all
204 # lanes. So we should not get a dead/undef flag here.
296 ; let's swiffle some lanes around for fun...
308 # for the used lanes. The example reads sub3 lane at the end, however with each
349 ; rotate lanes, but skip sub2 lane...
359 # Similar to loop1 test, but check for fixpoint of defined lanes.
392 ; rotate subreg lanes, skipping sub1
H A Dcombine-add-zext-xor.ll4 ; Test that unused lanes in the s_xor result are masked out with v_cndmask.
35 ; Test that unused lanes in the s_xor result are masked out with v_cndmask.
67 ; Test that unused lanes in the s_or result are masked out with v_cndmask.
100 ; Test that unused lanes in the s_or result are masked out with v_cndmask.
133 ; Test that unused lanes in the s_and result are masked out with v_cndmask.
166 ; Test that unused lanes in the s_and result are masked out with v_cndmask.
H A Ddead-lane.mir1 # RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-schedu…
2 # RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-schedu…
H A Dloop_exit_with_xor.ll3 ; Where the mask of lanes wanting to exit the loop on this iteration is not
35 ; Where the mask of lanes wanting to exit the loop on this iteration is
59 ; Another case where the mask of lanes wanting to exit the loop is not masked
H A Dscalar-branch-missing-and-exec.ll9 ; without ensuring that the resulting mask has bits clear for inactive lanes.
11 ; set bits for inactive lanes.
H A Dsubreg-undef-def-with-other-subreg-defs.mir4 # Deciding which lanes are killed needs to account for other defs in the
8 # current vreg uses because it shared no lanes with %0.sub1 use on the
H A Dat-least-one-def-value-assert.mir13 # used, but not defined. There are also lanes in %0 that are not used
H A Dcall-skip.ll3 ; A call should be skipped if all lanes are zero, since we don't know
H A Dskip-branch-trap.ll5 ; An s_cbranch_execnz is required to avoid trapping if all lanes are 0
H A Dregcoalesce-keep-valid-lanes-implicit-def-bug39602.mir5 # lanes on an implicit_def that later cannot be erased.
H A Dextend-phi-subrange-not-in-parent.mir5 # the rest of the lanes). After %2 is split, after refineSubRanges the
/llvm-project-15.0.7/llvm/test/MachineVerifier/
H A Dtest_g_fcmp.mir18 ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
22 ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
H A Dtest_g_icmp.mir18 ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
22 ; CHECK: Bad machine code: Generic vector icmp/fcmp must preserve number of lanes
/llvm-project-15.0.7/openmp/libomptarget/DeviceRTL/src/
H A DUtils.cpp143 return impl::shuffleDown(lanes::All, Val, Delta, SrcLane); in __kmpc_shuffle_int32()
150 hi = impl::shuffleDown(lanes::All, hi, Delta, Width); in __kmpc_shuffle_int64()
151 lo = impl::shuffleDown(lanes::All, lo, Delta, Width); in __kmpc_shuffle_int64()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dconstant-folding-crash.ll18 define void @constant_folding_crash(i8* %v54, <4 x <4 x i32>*> %lanes.a, <4 x <4 x i32>*> %lanes.b,…
78 %ptrs = select i1 %cmp, <4 x <4 x i32>*> %lanes.a, <4 x <4 x i32>*> %lanes.b
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUModifierSyntax.rst142 all lanes in its group.
157 … Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.
1116 Selects which lanes to pull data from, within a group of 8 lanes. This is a mandatory modifier.
1178 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1218 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1228 lanes in the row.
1256 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1298 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1324 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
1355 Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
[all …]
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_neon_incl.td87 // - "H" - Halve the number of lanes in the type.
88 // - "D" - Double the number of lanes in the type.
104 // all lanes. The type of the vector is the base type of the intrinsic.
109 // the same type by duplicating the scalar value into all lanes.
168 // is a width in bits to reverse. The lanes this maps to is determined
173 // mask0 - The initial sequence of lanes for shuffle ARG0
175 // mask0 - The initial sequence of lanes for shuffle ARG1
/llvm-project-15.0.7/mlir/include/mlir/Dialect/ArmSVE/
H A DArmSVE.td63 op_description # [{ on active lanes. Inactive lanes will keep the value of
86 op_description # [{ on active lanes. Inactive lanes will keep the value of
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dregcoal-subranges-update.mir4 # Check that when we split the live-range with several active lanes
16 # clearing the dead value w.r.t. lanes when doing the splitting. I.e., we were ending
H A Dregcoal-subranges-update-remat.mir5 # only a sub register, it sets the subranges of the unused lanes as being dead
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedAmpere1.td721 // -- Load 1-element structure to one/all lanes
722 // ---- all lanes
728 // -- Load 1-element structure to one/all lanes, 1D size
743 // -- Load 2-element structure to all lanes of 2 registers, 1D size
746 // -- Load 2-element structure to all lanes of 2 registers, other sizes
758 // -- Load 3-element structure to all lanes of 3 registers, 1D size
761 // -- Load 3-element structure to all lanes of 3 registers, other sizes
776 // -- Load 4-element structure to all lanes of 4 registers, 1D size
779 // -- Load 4-element structure to all lanes of 4 registers, other sizes
H A DAArch64SchedThunderX2T99.td1602 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1603 // ASIMD load, 1 element, all lanes, D-form, D
1604 // ASIMD load, 1 element, all lanes, Q-form
1624 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1625 // ASIMD load, 2 element, all lanes, D-form, D
1626 // ASIMD load, 2 element, all lanes, Q-form
1647 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1648 // ASIMD load, 3 element, all lanes, D-form, D
1650 // ASIMD load, 3 element, all lanes, Q-form, D
1672 // ASIMD load, 4 element, all lanes, D-form, D
[all …]
H A DAArch64SchedThunderX3T110.td1727 // ASIMD load, 1 element, all lanes, D-form, B/H/S
1728 // ASIMD load, 1 element, all lanes, D-form, D
1729 // ASIMD load, 1 element, all lanes, Q-form
1750 // ASIMD load, 2 element, all lanes, D-form, B/H/S
1751 // ASIMD load, 2 element, all lanes, D-form, D
1752 // ASIMD load, 2 element, all lanes, Q-form
1774 // ASIMD load, 3 element, all lanes, D-form, B/H/S
1775 // ASIMD load, 3 element, all lanes, D-form, D
1777 // ASIMD load, 3 element, all lanes, Q-form, D
1800 // ASIMD load, 4 element, all lanes, D-form, D
[all …]
/llvm-project-15.0.7/openmp/libomptarget/DeviceRTL/include/
H A DTypes.h139 namespace lanes {
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvector-partial-undef.ll77 ; and undef, C --> 0, so this tests that we are tracking known zero lanes.
96 ; or undef, C --> -1, so this tests that we are tracking known all-ones lanes.

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