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Searched refs:lane1 (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfp16_intrinsic_lane.ll18 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <4 x i32> zeroinitializer
19 %fmla3 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %lane1, <4 x half> %a)
30 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <8 x i32> zeroinitializer
41 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <4 x i32> zeroinitializer
42 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %lane1, <4 x half> %b, <4 x half> %a)
52 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <8 x i32> zeroinitializer
53 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %lane1, <8 x half> %b, <8 x half> %a)
114 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <4 x i32> zeroinitializer
127 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <8 x i32> zeroinitializer
139 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <4 x i32> zeroinitializer
[all …]
H A Darm64-addp.ll10 %lane1.i = extractelement <2 x double> %a, i32 1
11 %vpaddd.i = fadd double %lane0.i, %lane1.i
22 %lane1.i = extractelement <2 x i64> %a, i32 1
23 %vpaddd.i = add i64 %lane0.i, %lane1.i
34 %lane1.i = extractelement <2 x float> %a, i32 1
35 %vpaddd.i = fadd float %lane0.i, %lane1.i
H A Darm64-ld1.ll931 %lane1 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> zeroinitializer
932 %tmp7 = bitcast <2 x i32> %lane1 to <8 x i8>
H A Darm64-neon-2velem.ll3672 %lane1 = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
3673 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane1, <4 x float> %b, <4 x float> %a)
3687 %lane1 = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
3688 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %lane1, <4 x float> %b, <4 x float> %a)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvlddup.ll235 %lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
240 store <8 x i8> %lane1, <8 x i8>* %r11, align 8
253 %lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
259 store <8 x i8> %lane1, <8 x i8>* %r10, align 8
272 %lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
278 store <8 x i8> %lane1, <8 x i8>* %r10, align 8
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dgep-vector-indices.ll132 %lane1 = extractelement <vscale x 2 x i32*> %gep, i32 1
134 store i32* %lane1, i32** %c, align 8
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics.ll2627 define i32 @readlane_idempotent_different_lanes(i32 %arg, i32 %lane0, i32 %lane1) {
2634 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 %lane1)