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Searched refs:lane (Results 1 – 25 of 328) sorted by relevance

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/linux-6.15/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
99 #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) argument
104 #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) argument
153 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
156 ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
517 lane = &priv->lane[i]; in lynx_28g_cdr_lock_check()
521 if (!lane->init || !lane->powered_up) { in lynx_28g_cdr_lock_check()
589 struct lynx_28g_lane *lane = &priv->lane[i]; in lynx_28g_probe() local
[all …]
H A Dphy-fsl-imx8qm-hsio.c128 lane->ctrl_off = 0; in imx_hsio_init()
129 lane->phy_off = 0; in imx_hsio_init()
132 if (lane->idx == 0) in imx_hsio_init()
139 lane->ctrl_off = 0; in imx_hsio_init()
140 lane->phy_off = 0; in imx_hsio_init()
216 if (lane->idx == 1) { in imx_hsio_pcie_phy_resets()
366 if (lane->idx == 1) in imx_hsio_power_on()
580 struct imx_hsio_lane *lane = &priv->lane[i]; in imx_hsio_probe() local
587 lane->priv = priv; in imx_hsio_probe()
588 lane->phy = phy; in imx_hsio_probe()
[all …]
/linux-6.15/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c522 lane->id, lane->mode, old, new); in mvebu_a3700_comphy_set_phy_selector()
527 lane->mode); in mvebu_a3700_comphy_set_phy_selector()
673 lane->submode, lane->id); in mvebu_a3700_comphy_ethernet_power_on()
781 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
806 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
815 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
1123 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_check_mode()
1147 (lane->mode != mode || lane->submode != submode)) in mvebu_a3700_comphy_set_mode()
1161 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, in mvebu_a3700_comphy_power_on()
1172 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
[all …]
H A Dphy-mvebu-cp110-comphy.c182 unsigned lane; member
309 if (conf->lane == lane && in mvebu_comphy_get_mode()
381 lane->id); in mvebu_comphy_ethernet_init_reset()
402 lane->id); in mvebu_comphy_ethernet_init_reset()
729 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
730 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
774 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
775 lane->mode, lane->submode); in mvebu_comphy_power_on()
785 lane->id); in mvebu_comphy_power_on()
790 lane->id); in mvebu_comphy_power_on()
[all …]
H A Dphy-armada38x-comphy.c72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
108 dev_err(lane->priv->dev, in a38x_comphy_poll()
141 a38x_set_conf(lane, false); in a38x_comphy_set_mode()
152 a38x_set_conf(lane, true); in a38x_comphy_set_mode()
177 if (lane->port >= 0) in a38x_comphy_xlate()
180 lane->port = args->args[0]; in a38x_comphy_xlate()
185 if (!gbe_mux[lane->n][lane->port] || in a38x_comphy_xlate()
186 val != gbe_mux[lane->n][lane->port]) { in a38x_comphy_xlate()
187 dev_warn(lane->priv->dev, in a38x_comphy_xlate()
[all …]
/linux-6.15/drivers/net/dsa/b53/
H A Db53_serdes.c44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart() local
106 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_get_state() local
173 switch (lane) { in b53_serdes_phylink_get_caps()
200 if (lane == B53_INVALID_LANE || lane >= B53_N_PCS || in b53_serdes_phylink_mac_select_pcs()
201 !dev->pcs[lane].dev) in b53_serdes_phylink_mac_select_pcs()
238 pcs = &dev->pcs[lane]; in b53_serdes_init()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
80 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
84 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
86 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
106 uint8_t lane = 0; in perform_fixed_vs_pe_nontransparent_training_sequence() local
168 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_fixed_vs_pe_nontransparent_training_sequence()
212 uint8_t lane = 0; in dp_perform_fixed_vs_pe_training_sequence() local
377 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
[all …]
H A Dlink_dp_training.c347 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
361 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_hw_to_dpcd_lane_settings()
466 for (lane = 0; lane < in dp_is_max_vs_reached()
483 for (lane = 0; lane < (uint32_t)(ln_count); lane++) { in dp_is_cr_done()
496 for (lane = 0; lane < (uint32_t)(ln_count); lane++) in dp_is_ch_eq_done()
507 for (lane = 0; lane < (uint32_t)(ln_count); lane++) in dp_is_symbol_locked()
630 for (lane = 0; lane < in dp_get_lane_status_and_lane_adjust()
692 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_lane_settings()
750 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_training_settings()
862 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_decide_lane_settings()
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
163 #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
170 #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
177 #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) argument
290 #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) argument
291 #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) argument
292 #define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
293 #define CHV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
294 #define CHV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
295 #define CHV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) argument
[all …]
H A Dintel_cx0_phy_regs.h47 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
125 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
126 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
127 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
132 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ argument
170 _XELPDP_PORT_MSGBUS_TIMER(port, lane))
188 #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) argument
189 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) argument
190 #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4)) argument
191 #define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4)) argument
[all …]
H A Dbxt_dpio_phy_regs.h28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
241 #define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
256 #define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
H A Dintel_cx0_phy.c85 int lane; in intel_cx0_program_msgbus_timer() local
126 int lane) in intel_clear_response_ready_flag() argument
359 int lane; in intel_cx0_write() local
412 u8 lane; in intel_cx0_rmw() local
2784 int lane = 0; in intel_cx0_get_powerdown_update() local
2795 int lane = 0; in intel_cx0_get_powerdown_state() local
2810 int lane; in intel_cx0_powerdown_change_sequence() local
2858 int lane = 0; in intel_cx0_get_pclk_refclk_request() local
2869 int lane = 0; in intel_cx0_get_pclk_refclk_ack() local
2984 int lane = 0; in intel_cx0_get_pclk_pll_request() local
[all …]
/linux-6.15/drivers/phy/tegra/
H A Dxusb.c143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
331 lane->pad->ops->iddq_enable(lane); in tegra_xusb_lane_program()
340 lane->pad->ops->iddq_disable(lane); in tegra_xusb_lane_program()
394 const char *func = lane->soc->funcs[lane->function]; in tegra_xusb_lane_check()
412 hit = lane; in tegra_xusb_find_lane()
444 match = lane; in tegra_xusb_port_find_lane()
1400 return lane->pad->ops->enable_phy_sleepwalk(lane, speed); in tegra_xusb_padctl_enable_phy_sleepwalk()
1411 return lane->pad->ops->disable_phy_sleepwalk(lane); in tegra_xusb_padctl_disable_phy_sleepwalk()
1422 return lane->pad->ops->enable_phy_wake(lane); in tegra_xusb_padctl_enable_phy_wake()
1433 return lane->pad->ops->disable_phy_wake(lane); in tegra_xusb_padctl_disable_phy_wake()
[all …]
H A Dxusb.h63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
125 to_sata_lane(struct tegra_xusb_lane *lane) in to_sata_lane() argument
134 void (*remove)(struct tegra_xusb_lane *lane);
135 void (*iddq_enable)(struct tegra_xusb_lane *lane);
136 void (*iddq_disable)(struct tegra_xusb_lane *lane);
139 int (*enable_phy_wake)(struct tegra_xusb_lane *lane);
[all …]
H A Dxusb-tegra210.c455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
1699 struct tegra_xusb_lane *lane; in tegra210_usb3_set_lfps_detect() local
1706 lane = port->lane; in tegra210_usb3_set_lfps_detect()
1919 lane->index); in tegra210_usb2_phy_set_mode()
2123 lane->index); in tegra210_usb2_phy_power_off()
2567 if (!lane || !lane->pad || !lane->pad->padctl) in tegra210_lane_to_usb3_port()
3089 struct tegra_xusb_lane *lane; in tegra210_utmi_port_reset() local
3092 lane = phy_get_drvdata(phy); in tegra210_utmi_port_reset()
3093 padctl = lane->pad->padctl; in tegra210_utmi_port_reset()
[all …]
H A Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
486 unsigned int index = lane->index; in tegra124_usb2_phy_power_on()
578 lane->index); in tegra124_usb2_phy_power_off()
869 unsigned int index = lane->index; in tegra124_hsic_phy_power_on()
938 unsigned int index = lane->index; in tegra124_hsic_phy_power_off()
1480 struct tegra_xusb_lane *lane = usb3->base.lane; in tegra124_usb3_port_enable() local
1542 if (lane->pad == padctl->pcie) in tegra124_usb3_port_enable()
1554 if (lane->pad == padctl->pcie) in tegra124_usb3_port_enable()
[all …]
H A Dxusb-tegra186.c335 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
483 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
530 unsigned int index = lane->index; in tegra186_utmi_enable_phy_wake()
555 unsigned int index = lane->index; in tegra186_utmi_disable_phy_wake()
580 unsigned int index = lane->index; in tegra186_utmi_phy_remote_wake_detected()
689 unsigned int index = lane->index; in tegra186_utmi_pad_power_on()
731 unsigned int index = lane->index; in tegra186_utmi_pad_power_down()
820 lane->index); in tegra186_utmi_phy_set_mode()
860 unsigned int index = lane->index; in tegra186_utmi_phy_power_on()
936 unsigned int index = lane->index; in tegra186_utmi_phy_init()
[all …]
/linux-6.15/drivers/phy/
H A Dphy-xgene.c689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
699 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
701 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
944 int lane; in xgene_phy_sata_cfg_lanes() local
946 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
961 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
989 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
992 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
995 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
[all …]
/linux-6.15/drivers/net/dsa/mv88e6xxx/
H A Dserdes.c243 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
254 return lane; in mv88e6341_serdes_get_lane()
260 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
277 return lane; in mv88e6390_serdes_get_lane()
352 return lane; in mv88e6390x_serdes_get_lane()
372 lane = port; in mv88e6393x_serdes_get_lane()
374 return lane; in mv88e6393x_serdes_get_lane()
434 int lane; in mv88e6390_serdes_get_stats() local
438 if (lane < 0) in mv88e6390_serdes_get_stats()
493 int lane; in mv88e6390_serdes_get_regs() local
[all …]
/linux-6.15/sound/soc/tegra/
H A Dtegra186_asrc.c116 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
121 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
230 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
233 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
268 asrc->lane[id].ratio_source, in tegra186_asrc_put_ratio_source()
285 &asrc->lane[id].int_part); in tegra186_asrc_get_ratio_int()
333 &asrc->lane[id].frac_part); in tegra186_asrc_get_ratio_frac()
996 asrc->lane[i].int_part = 1; in tegra186_asrc_platform_probe()
997 asrc->lane[i].frac_part = 0; in tegra186_asrc_platform_probe()
999 asrc->lane[i].input_thresh = in tegra186_asrc_platform_probe()
[all …]
/linux-6.15/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml52 - 0 is RX2 lane
53 - 1 is TX2 lane
54 - 2 is TX1 lane
55 - 3 is RX1 lane
66 - Port A to RX2 lane
67 - Port B to TX2 lane
68 - Port C to TX1 lane
69 - Port D to RX1 lane
77 - Port A to RX1 lane
78 - Port B to TX1 lane
[all …]
/linux-6.15/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c21 unsigned int lane; member
53 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
156 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
184 t_data.lane = params->lane; in sdw_compute_master_ports()
202 if (params[i].lane != l) in _sdw_compute_port_params()
229 params[i].lane = group->lanes[i]; in sdw_compute_group_params()
254 if (rate == params[i].rate && p_rt->lane == params[i].lane) in sdw_compute_group_params()
266 if (params[i].lane != l) in sdw_compute_group_params()
473 lane, i); in is_lane_connected_to_all_peripherals()
615 s_p_rt->lane = l; in sdw_compute_bus_params()
[all …]
/linux-6.15/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
519 writel(0xa410, tcphy->base + RX_PSC_A2(lane)); in tcphy_rx_usb3_cfg_lane()
520 writel(0x2410, tcphy->base + RX_PSC_A3(lane)); in tcphy_rx_usb3_cfg_lane()
534 writel(0x6799, tcphy->base + TX_PSC_A0(lane)); in tcphy_dp_cfg_lane()
536 writel(0x98, tcphy->base + TX_PSC_A2(lane)); in tcphy_dp_cfg_lane()
[all …]
/linux-6.15/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c236 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
267 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
283 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
305 int lane; in analogix_dp_clock_recovery_ok() local
308 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
319 int lane; in analogix_dp_channel_eq_ok() local
325 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_channel_eq_ok()
346 int lane) in analogix_dp_get_adjust_request_pre_emphasis() argument
365 int lane, lane_count; in analogix_dp_get_adjust_training_lane() local
369 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_get_adjust_training_lane()
[all …]
/linux-6.15/Documentation/devicetree/bindings/media/i2c/
H A Dst,st-mipid02.yaml17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18 second input port is a single lane 800Mbps. Both ports support clock
19 and data lane polarity swap. First port also supports data lane swap.
65 Single-lane operation shall be <1> or <2> .
66 Dual-lane operation shall be <1 2> or <2 1> .
70 lane-polarities:
72 Any lane can be inverted or not.
91 Single-lane operation shall be <1> or <2> .
94 lane-polarities:
96 Any lane can be inverted or not.

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