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/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dvectorize-free-extracts-inserts.ll37 %a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
38 %a.lane.1 = fmul double %v1.lane.1, %v2.lane.3
79 %a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
80 %a.lane.1 = fmul double %v3.lane.1, %v2.lane.2
121 %a.lane.0 = fmul double %v1.lane.2, %v2.lane.2
122 %a.lane.1 = fmul double %v1.lane.3, %v2.lane.2
160 %a.lane.0 = fmul double %v1.lane.1, %v2.lane.2
161 %a.lane.1 = fmul double %v1.lane.0, %v2.lane.2
201 %a.lane.0 = fmul double %v1.lane.1, %v2.lane.2
202 %a.lane.1 = fmul double %v1.lane.2, %v2.lane.2
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/RISCV/
H A Dactive_lane_mask.ll62 declare <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64, i64)
73 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
74 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64)
75 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64)
76 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64)
77 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
78 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
79 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
80 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)
81 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A Dactive_lane_mask.ll38 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
39 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64)
40 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64, i64)
41 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64)
42 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
43 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
44 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
45 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)
47 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i16(i16, i16)
48 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i16(i16, i16)
[all …]
H A Dmve-active_lane_mask.ll8 ; lane masks are free.
12 …ound an estimated cost of 0 for instruction: %active.lane.mask = call <4 x i1> @llvm.get.active.la…
15 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
21 …ound an estimated cost of 0 for instruction: %active.lane.mask = call <8 x i1> @llvm.get.active.la…
24 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
30 …und an estimated cost of 0 for instruction: %active.lane.mask = call <16 x i1> @llvm.get.active.la…
33 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
37 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
38 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
39 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dactive_lane_mask.ll11 …%active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 %index, i32…
20 …%active.lane.mask = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 %index, i32 %…
29 …%active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 %index, i32 %…
344 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
355 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
366 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
388 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %TC)
424 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8 %index, i8 %TC)
438 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8 %index, i8 %TC)
456 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC)
[all …]
H A Dsve2-mla-indexed.ll12 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.lane.nxv4i32(<vscale x 4 x i32> %a,
25 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.lane.nxv4i32(<vscale x 4 x i32> %a,
38 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.lane.nxv2i64(<vscale x 2 x i64> %a,
51 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.lane.nxv2i64(<vscale x 2 x i64> %a,
67 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.lane.nxv4i32(<vscale x 4 x i32> %a,
80 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.lane.nxv4i32(<vscale x 4 x i32> %a,
93 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.lane.nxv2i64(<vscale x 2 x i64> %a,
106 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.lane.nxv2i64(<vscale x 2 x i64> %a,
122 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.lane.nxv4i32(<vscale x 4 x i32> %a,
135 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.lane.nxv4i32(<vscale x 4 x i32> %a,
[all …]
H A Dsve2-intrinsics-int-mul-lane.ll14 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64> %a,
25 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32> %a,
36 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16> %a,
51 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64> %a,
63 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32> %a,
75 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16> %a,
91 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64> %a,
103 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32> %a,
115 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16> %a,
122 declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16…
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/Lint/
H A Dget-active-lane-mask.ll6 ; CHECK-NEXT: %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
8 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
15 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask
17 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 1)
24 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask
26 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 -1)
33 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask
35 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 %TC)
39 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
/llvm-project-15.0.7/libc/AOR_v20.02/math/
H A Dv_pow.c18 for (int lane = 0; lane < v_lanes64 (); lane++) in V_NAME() local
20 f64_t sx = v_get_f64 (x, lane); in V_NAME()
21 f64_t sy = v_get_f64 (y, lane); in V_NAME()
23 v_set_f64 (&z, lane, sz); in V_NAME()
H A Dv_powf.c163 for (int lane = 0; lane < v_lanes32 (); lane++) in V_NAME() local
173 si = v_get_u32 (i, lane); in V_NAME()
174 siz = v_get_u32 (iz, lane); in V_NAME()
175 sk = v_get_s32 (k, lane); in V_NAME()
176 sy = v_get_f32 (y, lane); in V_NAME()
202 v_set_u32 (&cmp, lane, in V_NAME()
206 : v_get_u32 (cmp, lane)); in V_NAME()
229 v_set_f32 (&ret, lane, p); in V_NAME()
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A Dactive-lane-mask.ll12 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 0)
22 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 1)
32 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 8)
42 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 15)
104 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 0)
114 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 1)
124 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 4)
134 %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 7)
304 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
305 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dtail-pred-basic.ll32 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
80 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
128 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
175 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
233 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
289 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
350 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
352 %active.lane.mask15 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %v7, i32 %N)
354 %active.lane.mask16 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %v8, i32 %N)
356 %active.lane.mask17 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %v9, i32 %N)
[all …]
H A Dconstbound.ll40 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 500)
44 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
77 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 501)
81 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
114 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 502)
118 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
151 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 503)
155 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
188 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 504)
192 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
[all …]
H A Dtail-pred-intrinsic-round.ll35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
40 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
80 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
85 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
125 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
130 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
170 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
175 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
215 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
264 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
[all …]
H A Dtail-pred-intrinsic-add-sat.ll37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
39 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
41 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
44 …id @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
86 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
88 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
90 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
93 …id @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
102 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
H A Dtail-pred-intrinsic-sub-sat.ll37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
39 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
41 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
44 …id @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
86 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
88 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
90 …6> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> und…
93 …id @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
102 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
H A Dreductions.ll39 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
107 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
178 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
247 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
318 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
387 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
483 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
512 %active.lane.mask61 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index51, i32 %N)
595 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
719 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %4)
[all …]
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dget-active-lane-mask.ll3 declare <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32, i32)
7 ; CHECK-NEXT: %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
9 %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
13 declare i32 @llvm.get.active.lane.mask.i32.i32(i32, i32)
17 ; CHECK-NEXT: ptr @llvm.get.active.lane.mask.i32.i32
19 %res = call i32 @llvm.get.active.lane.mask.i32.i32(i32 %IV, i32 %TC)
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/ARM/
H A Dtail-folding-prefer-flag.ll25 ; PREDFLAG: %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %[[ELEM0]], …
26 …ide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32({{.*}}, <4 x i1> %active.lane.mask
27 …de.masked.load1 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32({{.*}}, <4 x i1> %active.lane.mask
29 ; PREDFLAG: call void @llvm.masked.store.v4i32.p0v4i32({{.*}}, <4 x i1> %active.lane.mask
59 ; PREDFLAG: %[[ALM1:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %…
60 ; PREDFLAG: %[[ALM2:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %…
61 ; PREDFLAG: %[[ALM3:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %…
62 ; PREDFLAG: %[[ALM4:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %…
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dsimd-sext-inreg.ll65 %lane = extractelement <8 x i16> %x, i32 1
66 %a = shl i16 %lane, 8
76 %lane = extractelement <4 x i32> %x, i32 1
77 %a = shl i32 %lane, 24
87 %lane = extractelement <4 x i32> %x, i32 1
88 %a = shl i32 %lane, 16
102 %lane = extractelement <2 x i64> %x, i32 1
103 %a = shl i64 %lane, 56
117 %lane = extractelement <2 x i64> %x, i32 1
118 %a = shl i64 %lane, 48
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vmaxnma-tailpred.ll35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
38 … @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x float> p…
46 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %5, <4 x float>* %7, i32 4, <4 x i1> %active.lane.mask)
85 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
97 …llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %active.lane.mask)
138 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n)
149 … @llvm.masked.store.v8f16.p0v8f16(<8 x half> %5, <8 x half>* %7, i32 2, <8 x i1> %active.lane.mask)
188 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n)
200 … @llvm.masked.store.v8f16.p0v8f16(<8 x half> %6, <8 x half>* %8, i32 2, <8 x i1> %active.lane.mask)
209 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1183 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1256 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1292 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1334 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
2281 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2316 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>,
2353 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2387 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2427 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr47299.ll4 declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
5 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
6 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
7 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64)
8 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
9 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32)
52 %2 = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 0, i64 %0)
66 %2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %0)
83 %2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0)
108 %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0)
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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dactive_lane_mask.ll23 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 %tc)
87 %mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %tc)
99 %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc)
118 %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc)
153 %mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc)
225 declare <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64, i64)
226 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64, i64)
227 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64, i64)
228 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
229 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64)
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.writelane.ll27 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 %vdst.in)
32 define amdgpu_ps float @test_writelane_s_s_imm(i32 inreg %data, i32 inreg %lane) #0 {
52 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 42)
58 define amdgpu_ps float @test_writelane_k_s_v(i32 inreg %lane, i32 %vdst.in) #0 {
78 %writelane = call i32 @llvm.amdgcn.writelane(i32 999, i32 %lane, i32 %vdst.in)
84 define amdgpu_ps float @test_writelane_imm_s_v(i32 inreg %lane, i32 %vdst.in) #0 {
99 %writelane = call i32 @llvm.amdgcn.writelane(i32 42, i32 %lane, i32 %vdst.in)
218 %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 %vdst.in)
252 ; and another SGPR as the lane selector and avoid register swap.
253 define amdgpu_ps float @test_writelane_m0_s_v(i32 inreg %lane, i32 %vdst.in) #0 {
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