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/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dimx27.dtsi114 <&clks IMX27_CLK_PER1_GATE>;
123 <&clks IMX27_CLK_PER1_GATE>;
132 <&clks IMX27_CLK_PER1_GATE>;
142 <&clks IMX27_CLK_PER1_GATE>;
175 <&clks IMX27_CLK_PER1_GATE>;
185 <&clks IMX27_CLK_PER1_GATE>;
195 <&clks IMX27_CLK_PER1_GATE>;
490 <&clks IMX27_CLK_USB_DIV>;
502 <&clks IMX27_CLK_USB_DIV>;
515 <&clks IMX27_CLK_USB_DIV>;
[all …]
H A Dimx6ul.dtsi83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
309 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
324 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
339 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
352 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
353 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
354 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
355 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
356 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
[all …]
H A Dimx6sx.dtsi86 <&clks IMX6SX_CLK_STEP>,
206 <&clks IMX6SX_CLK_GPU>,
268 <&clks 0>, <&clks 0>, <&clks 0>,
270 <&clks 0>, <&clks 0>,
405 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
409 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
1112 <&clks 0>, <&clks 0>;
[all …]
H A Dimx25.dtsi116 clocks = <&clks 75>, <&clks 75>;
125 clocks = <&clks 76>, <&clks 76>;
134 clocks = <&clks 120>, <&clks 57>;
143 clocks = <&clks 121>, <&clks 57>;
174 clocks = <&clks 78>, <&clks 78>;
216 clocks = <&clks 80>, <&clks 80>;
460 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
469 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
478 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
556 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
[all …]
H A Dvfxxx.dtsi94 <&clks VF610_CLK_DMAMUX1>;
192 <&clks 0>, <&clks 0>;
205 <&clks 0>, <&clks 0>;
218 <&clks 0>, <&clks 0>;
231 <&clks 0>, <&clks 0>;
309 <&clks VF610_CLK_QSPI0>;
436 clks: ccm@4006b000 { label
621 <&clks VF610_CLK_FTM3>,
635 <&clks VF610_CLK_QSPI1>;
664 <&clks VF610_CLK_ENET>;
[all …]
H A Dimx6qdl.dtsi313 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
314 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
315 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
316 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
317 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
463 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
464 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
[all …]
H A Dimx53.dtsi56 clocks = <&clks IMX5_CLK_ARM>;
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
244 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_DUMMY>,
309 <&clks IMX5_CLK_DUMMY>,
321 <&clks IMX5_CLK_DUMMY>,
598 clks: ccm@53fd4000{ label
[all …]
H A Dimx51.dtsi138 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
149 <&clks IMX5_CLK_IPU_DI0_GATE>,
196 <&clks IMX5_CLK_DUMMY>,
207 <&clks IMX5_CLK_DUMMY>,
258 <&clks IMX5_CLK_DUMMY>,
270 <&clks IMX5_CLK_DUMMY>,
458 clks: ccm@73fd4000{ label
515 <&clks IMX5_CLK_AHB>;
636 <&clks IMX5_CLK_FEC_GATE>,
637 <&clks IMX5_CLK_FEC_GATE>;
[all …]
H A Dimx7s.dtsi77 clocks = <&clks IMX7D_CLK_ARM>;
461 <&clks IMX7D_GPT1_ROOT_CLK>;
470 <&clks IMX7D_GPT2_ROOT_CLK>;
480 <&clks IMX7D_GPT3_ROOT_CLK>;
805 <&clks IMX7D_CLK_DUMMY>;
948 <&clks IMX7D_CLK_DUMMY>,
949 <&clks IMX7D_CLK_DUMMY>;
963 <&clks IMX7D_CLK_DUMMY>,
964 <&clks IMX7D_CLK_DUMMY>;
978 <&clks IMX7D_CLK_DUMMY>,
[all …]
H A Dimx6sll.dtsi70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
163 <&clks IMX6SLL_CLK_OSC>,
168 <&clks IMX6SLL_CLK_IPG>,
171 <&clks IMX6SLL_CLK_SPBA>;
325 <&clks IMX6SLL_CLK_PWM1>;
335 <&clks IMX6SLL_CLK_PWM2>;
345 <&clks IMX6SLL_CLK_PWM3>;
355 <&clks IMX6SLL_CLK_PWM4>;
[all …]
H A Dimx50.dtsi123 <&clks IMX5_CLK_DUMMY>,
135 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_DUMMY>,
196 <&clks IMX5_CLK_DUMMY>,
274 clocks = <&clks IMX5_CLK_DUMMY>;
282 <&clks IMX5_CLK_GPT_HF_GATE>;
296 <&clks IMX5_CLK_PWM1_HF_GATE>;
338 clks: ccm@53fd4000{ label
429 <&clks IMX5_CLK_AHB>;
492 <&clks IMX5_CLK_FEC_GATE>,
[all …]
H A Dimx35.dtsi101 clocks = <&clks 9>, <&clks 70>;
110 clocks = <&clks 9>, <&clks 71>;
145 clocks = <&clks 35 &clks 35>;
175 clocks = <&clks 9>, <&clks 72>;
187 clocks = <&clks 36 &clks 36>;
195 clocks = <&clks 46>, <&clks 8>;
238 clocks = <&clks 9>, <&clks 8>, <&clks 43>;
247 clocks = <&clks 9>, <&clks 8>, <&clks 44>;
256 clocks = <&clks 9>, <&clks 8>, <&clks 45>;
334 clocks = <&clks 9>, <&clks 73>, <&clks 28>;
[all …]
H A Dimx6sl.dtsi70 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
71 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
72 <&clks IMX6SL_CLK_PLL1_SYS>;
165 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
166 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
167 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
168 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
169 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
346 <&clks IMX6SL_CLK_PWM1>;
356 <&clks IMX6SL_CLK_PWM2>;
[all …]
H A Dimx31.dtsi105 clocks = <&clks 10>, <&clks 30>;
114 clocks = <&clks 10>, <&clks 31>;
133 clocks = <&clks 10>, <&clks 53>;
153 clocks = <&clks 10>, <&clks 49>;
163 clocks = <&clks 10>, <&clks 50>;
180 clocks = <&clks 10>, <&clks 20>;
191 clocks = <&clks 10>, <&clks 21>;
202 clocks = <&clks 10>, <&clks 48>;
211 clocks = <&clks 10>, <&clks 54>;
246 clocks = <&clks 10>, <&clks 28>;
[all …]
H A Dimx6q.dtsi44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
81 <&clks IMX6QDL_CLK_STEP>,
116 <&clks IMX6QDL_CLK_STEP>,
151 <&clks IMX6QDL_CLK_STEP>,
196 <&clks IMX6QDL_CLK_AHB>;
442 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
443 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
444 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
[all …]
H A Dimx6qp.dtsi15 clocks = <&clks IMX6QDL_CLK_OCRAM>;
24 clocks = <&clks IMX6QDL_CLK_OCRAM>;
32 clocks = <&clks IMX6QDL_CLK_PRE0>;
41 clocks = <&clks IMX6QDL_CLK_PRE1>;
50 clocks = <&clks IMX6QDL_CLK_PRE2>;
68 <&clks IMX6QDL_CLK_PRG0_AXI>;
77 <&clks IMX6QDL_CLK_PRG1_AXI>;
105 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
106 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
107 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
[all …]
H A Dimxrt1050.dtsi51 clks: clock-controller@400fc000 { label
59 <&clks IMXRT1050_CLK_PLL1_BYPASS>,
60 <&clks IMXRT1050_CLK_PLL2_BYPASS>,
61 <&clks IMXRT1050_CLK_PLL3_BYPASS>,
65 <&clks IMXRT1050_CLK_PLL1_ARM>,
66 <&clks IMXRT1050_CLK_PLL2_SYS>,
69 <&clks IMXRT1050_CLK_PLL2_SYS>;
81 clocks = <&clks IMXRT1050_CLK_DMA>,
82 <&clks IMXRT1050_CLK_DMA_MUX>;
90 <&clks IMXRT1050_CLK_OSC>,
[all …]
H A Dimx1.dtsi83 <&clks IMX1_CLK_PER1>;
92 <&clks IMX1_CLK_PER1>;
101 <&clks IMX1_CLK_DUMMY>,
102 <&clks IMX1_CLK_PER2>;
112 <&clks IMX1_CLK_PER1>;
122 <&clks IMX1_CLK_PER1>;
133 <&clks IMX1_CLK_PER1>;
152 <&clks IMX1_CLK_PER1>;
172 <&clks IMX1_CLK_PER1>;
194 <&clks IMX1_CLK_PER1>;
[all …]
H A Datlas6.dtsi28 clocks = <&clks 12>;
85 clocks = <&clks 42>;
99 clocks = <&clks 5>;
106 clocks = <&clks 32>;
120 clocks = <&clks 34>;
131 clocks = <&clks 35>;
146 clocks = <&clks 32>;
160 clocks = <&clks 33>;
181 clocks = <&clks 9>;
189 clocks = <&clks 8>;
[all …]
H A Dprima2.dtsi30 clocks = <&clks 12>;
96 clocks = <&clks 42>;
110 clocks = <&clks 5>;
117 clocks = <&clks 32>;
137 clocks = <&clks 35>;
152 clocks = <&clks 32>;
166 clocks = <&clks 33>;
187 clocks = <&clks 9>;
195 clocks = <&clks 8>;
211 clocks = <&clks 11>;
[all …]
H A Dimx6dl.dtsi37 clocks = <&clks IMX6QDL_CLK_ARM>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
70 clocks = <&clks IMX6QDL_CLK_ARM>,
72 <&clks IMX6QDL_CLK_STEP>,
73 <&clks IMX6QDL_CLK_PLL1_SW>,
74 <&clks IMX6QDL_CLK_PLL1_SYS>;
311 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
312 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
[all …]
/freebsd-14.2/sys/contrib/device-tree/src/powerpc/
H A Dmpc5121.dtsi51 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MBX>;
134 clks: clock@f00 { label
160 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512x_CLK_REF>,
172 <&clks MPC512x_CLK_IPS>,
173 <&clks MPC512x_CLK_SYS>,
174 <&clks MPC512x_CLK_REF>,
246 <&clks MPC512x_CLK_IPS>,
[all …]
H A Dmpc5125twr.dts99 clks: clock@f00 { // Clock control label
130 <&clks MPC512x_CLK_IPS>,
131 <&clks MPC512x_CLK_SYS>,
132 <&clks MPC512x_CLK_REF>,
142 <&clks MPC512x_CLK_IPS>,
143 <&clks MPC512x_CLK_SYS>,
144 <&clks MPC512x_CLK_REF>,
153 clocks = <&clks MPC512x_CLK_IPS>,
154 <&clks MPC512x_CLK_SDHC>;
164 clocks = <&clks MPC512x_CLK_I2C>;
[all …]
/freebsd-14.2/sys/dev/fdt/
H A Dfdt_clock.c55 uint32_t *clks; in enable_disable_all() local
59 ncells = OF_getencprop_alloc_multi(cnode, "clocks", sizeof(*clks), in enable_disable_all()
60 (void **)&clks); in enable_disable_all()
68 clockdev = OF_device_from_xref(clks[i]); in enable_disable_all()
69 clocknum = clks[i + 1]; in enable_disable_all()
90 OF_prop_free(clks); in enable_disable_all()
100 uint32_t *clks; in fdt_clock_get_info() local
104 (void **)&clks); in fdt_clock_get_info()
111 clockdev = OF_device_from_xref(clks[n]); in fdt_clock_get_info()
120 clocknum = clks[n + 1]; in fdt_clock_get_info()
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,asrc.txt64 clocks = <&clks 107>, <&clks 107>, <&clks 0>,
65 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
66 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
67 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
68 <&clks 107>, <&clks 0>, <&clks 0>;

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