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Searched refs:cgc1 (Results 1 – 3 of 3) sorted by relevance

/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dimx8ulp.dtsi308 cgc1: clock-controller@292c0000 { label
309 compatible = "fsl,imx8ulp-cgc1";
516 <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
517 <&cgc1 IMX8ULP_CLK_DUMMY>;
531 <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
532 <&cgc1 IMX8ULP_CLK_DUMMY>;
551 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
570 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
589 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
796 <&cgc1 IMX8ULP_CLK_DUMMY>;
[all …]
H A Dimx8ulp-evk.dts196 assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>;
197 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
207 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
266 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
268 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
271 assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dimx8ulp-cgc-clock.yaml20 - fsl,imx8ulp-cgc1
40 compatible = "fsl,imx8ulp-cgc1";