Searched refs:cascade (Results 1 – 25 of 32) sorted by relevance
12
6 to drive the 2 LSBs of the cascade automatically.19 shift register cascade.21 in the shift register cascade.22 - lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit24 - lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.25 - lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
20 shift register cascade.
7 platforms internal interrupt controller cascade.9 Below is an example of a platform describing the cascade inside the devicetree
18 - cascade pattern19 - inversed cascade pattern
65 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */77 interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */89 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
76 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */88 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */100 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
67 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */79 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */91 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
73 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */86 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */98 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
68 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */80 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */85 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
75 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */87 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
74 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */86 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */98 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */81 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
72 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */84 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */96 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
68 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
12 Example for mips when used in cascade mode:
5 This implementation support only cascade mode.
6 This implement only supported cascade mode.