Searched refs:VecAMode (Results 1 – 6 of 6) sorted by relevance
| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/inst/ |
| H A D | vector.rs | 3 VecAMode, VecAluOpRImm5, VecAluOpRR, VecAluOpRRImm5, VecAluOpRRR, VecAluOpRRRImm5, VecAvl,
1061 impl VecAMode { impl
1064 VecAMode::UnitStride { base, .. } => base.get_operands(collector), in get_operands()
1072 VecAMode::UnitStride { .. } => 0b00, in mop()
1080 VecAMode::UnitStride { .. } => 0b00000, in lumop()
1088 VecAMode::UnitStride { .. } => 0b00000, in sumop()
1100 VecAMode::UnitStride { .. } => 0b000, in nf()
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| H A D | mod.rs | 3 use super::lower::isle::generated_code::{VecAMode, VecElementWidth, VecOpMasking};
217 from: VecAMode::UnitStride { base: mem }, in gen_load()
237 to: VecAMode::UnitStride { base: mem }, in gen_store()
921 let format_vec_amode = |amode: &VecAMode| -> String { in print_with_state()
923 VecAMode::UnitStride { base } => base.to_string(), in print_with_state()
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| H A D | emit.rs | 2686 VecAMode::UnitStride { base } => { in emit_uncompressed()
2733 VecAMode::UnitStride { base } => { in emit_uncompressed()
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/ |
| H A D | inst_vector.isle | 305 (type VecAMode (enum
424 (decl vec_load (VecElementWidth VecAMode MemFlags VecOpMasking VState) Reg)
431 (decl vec_store (VecElementWidth VecAMode VReg MemFlags VecOpMasking VState) InstOutput)
1554 (VecAMode.UnitStride (gen_const_amode n))
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| H A D | lower.isle | 2187 (vec_load eew (VecAMode.UnitStride amode) flags (unmasked) ty)))
2201 (loaded VReg (vec_load eew (VecAMode.UnitStride amode) flags (unmasked) load_state)))
2207 (loaded VReg (vec_load eew (VecAMode.UnitStride amode) flags (unmasked) load_state)))
2258 (vec_store eew (VecAMode.UnitStride amode) src flags (unmasked) ty)))
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| H A D | inst.isle | 348 (from VecAMode)
355 (to VecAMode)
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